delay go_st by one cycle, break combinatorial loop

[soc.git] / src / soc / simple / issuer.py

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 5efc0e0ee54ba3e5cc3192774746440b68d46db0..cfc0be4850d1495e2e7673f95281bb46dc9a6b40 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -94,7 +94,6 @@ class TestIssuer(Elaboratable):
         comb += core_sync.clk.eq(ClockSignal())
         # XXX TODO: power-on reset delay (later)
         #comb += core.core_reset_i.eq(delay != 0 | dbg.core_rst_o)
-        comb += core.core_reset_i.eq(dbg.core_rst_o)
 
         # busy/halted signals from core
         comb += self.busy_o.eq(core.busy_o)
@@ -107,7 +106,7 @@ class TestIssuer(Elaboratable):
         l0 = core.l0
         ldst = core.fus.fus['ldst0']
         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
-        m.d.comb += ldst.st.go_i.eq(ldst.st.rel_o) # link store-go direct to rel
+        m.d.sync += ldst.st.go_i.eq(ldst.st.rel_o) # link store-go direct to rel
 
         # PC and instruction from I-Memory
         current_insn = Signal(32) # current fetched instruction (note sync)
@@ -115,19 +114,30 @@ class TestIssuer(Elaboratable):
         comb += self.pc_o.eq(cur_state.pc)
         ilatch = Signal(32)
 
-        # MSR (temp and latched)
+        # MSR
         msr = Signal(64, reset_less=True)
 
         # next instruction (+4 on current)
         nia = Signal(64, reset_less=True)
         comb += nia.eq(cur_state.pc + 4)
 
+        # read the PC
+        pc = Signal(64, reset_less=True)
+        with m.If(self.pc_i.ok):
+            # incoming override (start from pc_i)
+            comb += pc.eq(self.pc_i.data)
+        with m.Else():
+            # otherwise read FastRegs regfile for PC
+            comb += self.fast_r_pc.ren.eq(1<<FastRegs.PC)
+            comb += pc.eq(self.fast_r_pc.data_o)
+
         # connect up debug signals
-        comb += core.core_stopped_i.eq(dbg.core_stop_o)
-        # TODO comb += core.reset_i.eq(dbg.core_rst_o)
         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
+        comb += core.core_stopped_i.eq(dbg.core_stop_o)
+        comb += core.core_reset_i.eq(dbg.core_rst_o)
         comb += dbg.terminate_i.eq(core.core_terminate_o)
-        comb += dbg.state.eq(cur_state)
+        comb += dbg.state.pc.eq(pc)
+        comb += dbg.state.msr.eq(cur_state.msr)
 
         # temporaries
         core_busy_o = core.busy_o         # core is busy
@@ -151,14 +161,6 @@ class TestIssuer(Elaboratable):
                 sync += pc_changed.eq(0)
                 with m.If(~dbg.core_stop_o):
                     # instruction allowed to go: start by reading the PC
-                    pc = Signal(64, reset_less=True)
-                    with m.If(self.pc_i.ok):
-                        # incoming override (start from pc_i)
-                        comb += pc.eq(self.pc_i.data)
-                    with m.Else():
-                        # otherwise read FastRegs regfile for PC
-                        comb += self.fast_r_pc.ren.eq(1<<FastRegs.PC)
-                        comb += pc.eq(self.fast_r_pc.data_o)
                     # capture the PC and also drop it into Insn Memory
                     # we have joined a pair of combinatorial memory
                     # lookups together.  this is Generally Bad.
@@ -242,6 +244,9 @@ class TestIssuer(Elaboratable):
     def external_ports(self):
         return self.pc_i.ports() + [self.pc_o,
                                     self.memerr_o,
+                                    self.core_bigendian_i,
+                                    ClockSignal(),
+                                    ResetSignal(),
                                     self.busy_o,
                                     ] + \
                 list(self.dbg.dmi.ports()) + \
@@ -255,6 +260,7 @@ class TestIssuer(Elaboratable):
 if __name__ == '__main__':
     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
              'spr': 1,
+             'div': 1,
              'mul': 1,
              'shiftrot': 1}
     pspec = TestMemPspec(ldst_ifacetype='bare_wb',