Merge branch 'master' of git.libre-soc.org:soc

[soc.git] / src / soc / simple / issuer.py

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 168f389f0d57c4800e99c07f6218683607ac9011..d93e3782b599dc4b17c98bbdaee0b3198e016f88 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -31,6 +31,8 @@ from soc.decoder.power_enums import MicrOp
 from soc.debug.dmi import CoreDebug, DMIInterface
 from soc.config.state import CoreState
 
+from nmutil.util import rising_edge
+
 
 class TestIssuer(Elaboratable):
     """TestIssuer - reads instructions from TestMemory and issues them
@@ -105,8 +107,9 @@ class TestIssuer(Elaboratable):
         # temporary hack: says "go" immediately for both address gen and ST
         l0 = core.l0
         ldst = core.fus.fus['ldst0']
+        st_go_edge = rising_edge(m, ldst.st.rel_o)
         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
-        m.d.comb += ldst.st.go_i.eq(ldst.st.rel_o) # link store-go direct to rel
+        m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 
         # PC and instruction from I-Memory
         current_insn = Signal(32) # current fetched instruction (note sync)
@@ -114,9 +117,6 @@ class TestIssuer(Elaboratable):
         comb += self.pc_o.eq(cur_state.pc)
         ilatch = Signal(32)
 
-        # MSR
-        msr = Signal(64, reset_less=True)
-
         # next instruction (+4 on current)
         nia = Signal(64, reset_less=True)
         comb += nia.eq(cur_state.pc + 4)
@@ -149,6 +149,9 @@ class TestIssuer(Elaboratable):
         insn_type = core.pdecode2.e.do.insn_type
         insn_state = core.pdecode2.state
 
+        # don't read msr every cycle
+        sync += self.fast_r_msr.ren.eq(0)
+
         # actually use a nmigen FSM for the first time (w00t)
         # this FSM is perhaps unusual in that it detects conditions
         # then "holds" information, combinatorially, for the core
@@ -168,6 +171,11 @@ class TestIssuer(Elaboratable):
                     comb += self.imem.a_valid_i.eq(1)
                     comb += self.imem.f_valid_i.eq(1)
                     sync += cur_state.pc.eq(pc)
+
+                    # read MSR, latch it, and put it in decode "state"
+                    sync += self.fast_r_msr.ren.eq(1<<FastRegs.MSR)
+                    sync += cur_state.msr.eq(self.fast_r_msr.data_o)
+
                     m.next = "INSN_READ" # move to "wait for bus" phase
 
             # waiting for instruction bus (stays there until not busy)
@@ -189,14 +197,8 @@ class TestIssuer(Elaboratable):
                     comb += core_opcode_i.eq(current_insn) # actual opcode
                     sync += ilatch.eq(current_insn) # latch current insn
 
-                    # read MSR, latch it, and put it in decode "state"
-                    comb += self.fast_r_msr.ren.eq(1<<FastRegs.MSR)
-                    comb += msr.eq(self.fast_r_msr.data_o)
-                    comb += insn_state.msr.eq(msr)
-                    sync += cur_state.msr.eq(msr) # latch current MSR
-
-                    # also drop PC into decode "state"
-                    comb += insn_state.pc.eq(cur_state.pc)
+                    # also drop PC and MSR into decode "state"
+                    comb += insn_state.eq(cur_state)
 
                     m.next = "INSN_ACTIVE" # move to "wait completion"