# 64-bit: bit 2 of pc decides which word to select
return f_instr_o.word_select(pc[2], 32)
+# gets state input or reads from state regfile
+def state_get(m, state_i, name, regfile, regnum):
+ comb = m.d.comb
+ sync = m.d.sync
+ # read the PC
+ res = Signal(64, reset_less=True, name=name)
+ res_ok_delay = Signal(name="%s_ok_delay" % name)
+ sync += res_ok_delay.eq(~state_i.ok)
+ with m.If(state_i.ok):
+ # incoming override (start from pc_i)
+ comb += res.eq(state_i.data)
+ with m.Else():
+ # otherwise read StateRegs regfile for PC...
+ comb += regfile.ren.eq(1<<regnum)
+ # ... but on a 1-clock delay
+ with m.If(res_ok_delay):
+ comb += res.eq(regfile.data_o)
+ return res
+
+def get_predint(m, mask):
+ """decode SVP64 predicate integer mask field to reg number and invert
+ this is identical to the equivalent function in ISACaller except that
+ it doesn't read the INT directly, it just decodes "what needs to be done"
+ i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
+ """
+ regread = Signal(5)
+ invert = Signal()
+ unary = Signal()
+ with m.Switch(mask):
+ with m.Case(SVP64PredInt.ALWAYS.value):
+ comb += regread.eq(0)
+ comb += invert.eq(1)
+ with m.Case(SVP64PredInt.R3_UNARY.value):
+ comb += regread.eq(3)
+ comb += unary.eq(1)
+ with m.Case(SVP64PredInt.R3.value):
+ comb += regread.eq(3)
+ with m.Case(SVP64PredInt.R3_N.value):
+ comb += regread.eq(3)
+ comb += invert.eq(1)
+ with m.Case(SVP64PredInt.R10.value):
+ comb += regread.eq(10)
+ with m.Case(SVP64PredInt.R10_N.value):
+ comb += regread.eq(10)
+ comb += invert.eq(1)
+ with m.Case(SVP64PredInt.R30.value):
+ comb += regread.eq(30)
+ with m.Case(SVP64PredInt.R30_N.value):
+ comb += regread.eq(30)
+ comb += invert.eq(1)
+ return regread, invert, unary
+
+def get_predcr(m, mask):
+ """decode SVP64 predicate CR to reg number field and invert status
+ this is identical to _get_predcr in ISACaller
+ """
+ idx = Signal(2)
+ invert = Signal()
+ with m.Switch(mask):
+ with m.Case(SVP64PredCR.LT.value):
+ comb += idx.eq(0)
+ comb += invert.eq(1)
+ with m.Case(SVP64PredCR.GE.value):
+ comb += idx.eq(0)
+ comb += invert.eq(0)
+ with m.Case(SVP64PredCR.GT.value):
+ comb += idx.eq(1)
+ comb += invert.eq(1)
+ with m.Case(SVP64PredCR.LE.value):
+ comb += idx.eq(1)
+ comb += invert.eq(0)
+ with m.Case(SVP64PredCR.EQ.value):
+ comb += idx.eq(2)
+ comb += invert.eq(1)
+ with m.Case(SVP64PredCR.NE.value):
+ comb += idx.eq(1)
+ comb += invert.eq(0)
+ with m.Case(SVP64PredCR.SO.value):
+ comb += idx.eq(3)
+ comb += invert.eq(1)
+ with m.Case(SVP64PredCR.NS.value):
+ comb += idx.eq(3)
+ comb += invert.eq(0)
+ return idx, invert
+
class TestIssuerInternal(Elaboratable):
"""TestIssuer - reads instructions from TestMemory and issues them
self.simple_gpio = SimpleGPIO()
self.gpio_o = self.simple_gpio.gpio_o
- # main instruction core25
+ # main instruction core. suitable for prototyping / demo only
self.core = core = NonProductionCore(pspec)
# instruction decoder. goes into Trap Record
pdecode = create_pdecode()
- self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
+ self.cur_state = CoreState("cur") # current state (MSR/PC/SVSTATE)
self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
opkls=IssuerDecode2ToOperand,
svp64_en=self.svp64_en)
# Test Instruction memory
self.imem = ConfigFetchUnit(pspec).fu
- # one-row cache of instruction read
- self.iline = Signal(64) # one instruction line
- self.iprev_adr = Signal(64) # previous address: if different, do read
# DMI interface
self.dbg = CoreDebug()
self.pc_o = Signal(64, reset_less=True)
self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
self.svstate_i = Data(32, "svstate_i") # ditto
- self.core_bigendian_i = Signal()
+ self.core_bigendian_i = Signal() # TODO: set based on MSR.LE
self.busy_o = Signal(reset_less=True)
self.memerr_o = Signal(reset_less=True)
self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
self.xer_r = xerrf.r_ports['full_xer'] # XER read
+ # for predication
+ self.int_pred = intrf.r_ports['pred'] # INT predicate read
+ self.cr_pred = crrf.r_ports['cr_pred'] # CR predicate read
+
# hack method of keeping an eye on whether branch/trap set the PC
self.state_nia = self.core.regs.rf['state'].w_ports['nia']
self.state_nia.wen.name = 'state_nia_wen'
# pulse to synchronize the simulator at instruction end
self.insn_done = Signal()
+ if self.svp64_en:
+ # store copies of predicate masks
+ self.srcmask = Signal(64)
+ self.dstmask = Signal(64)
+
def fetch_fsm(self, m, core, pc, svstate, nia, is_svp64_mode,
fetch_pc_ready_o, fetch_pc_valid_i,
fetch_insn_valid_o, fetch_insn_ready_i):
insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
sync += dec_opcode_i.eq(insn)
m.next = "INSN_READY"
+ # TODO: probably can start looking at pdecode2.rm_dec
+ # here (or maybe even in INSN_READ state, if svp64_mode
+ # detected, in order to trigger - and wait for - the
+ # predicate reading.
+ pmode = pdecode2.rm_dec.predmode
+ """
+ if pmode != SVP64PredMode.ALWAYS.value:
+ fire predicate loading FSM and wait before
+ moving to INSN_READY
+ else:
+ sync += self.srcmask.eq(-1) # set to all 1s
+ sync += self.dstmask.eq(-1) # set to all 1s
+ m.next = "INSN_READY"
+ """
with m.State("INSN_READY"):
# hand over the instruction, to be decoded
with m.If(fetch_insn_ready_i):
m.next = "IDLE"
- def fetch_predicate_fsm(self, m, core, TODO):
+ def fetch_predicate_fsm(self, m,
+ pred_insn_valid_i, pred_insn_ready_o,
+ pred_mask_valid_o, pred_mask_ready_i):
"""fetch_predicate_fsm - obtains (constructs in the case of CR)
src/dest predicate masks
or CRRegs r_ports['pred']. in the case of CRs it will have to
be done through multiple reads, extracting one relevant at a time.
later, a faster way would be to use the 32-bit-wide CR port but
- this is more complex decoding, here.
+ this is more complex decoding, here. equivalent code used in
+ ISACaller is "from soc.decoder.isa.caller import get_predcr"
"""
comb = m.d.comb
sync = m.d.sync
rm_dec = pdecode2.rm_dec # SVP64RMModeDecode
predmode = rm_dec.predmode
srcpred, dstpred = rm_dec.srcpred, rm_dec.dstpred
+ cr_pred, int_pred = self.cr_pred, self.int_pred # read regfiles
+ # if predmode == INT:
+ # INT-src sregread, sinvert, sunary = get_predint(m, srcpred)
+ # INT-dst dregread, dinvert, dunary = get_predint(m, dstpred)
+ # TODO read INT-src and INT-dst into self.srcmask+dstmask
+ # elif predmode == CR:
+ # CR-src sidx, sinvert = get_predcr(m, srcpred)
+ # CR-dst didx, dinvert = get_predcr(m, dstpred)
+ # TODO read CR-src and CR-dst into self.srcmask+dstmask with loop
+ # else
+ # sync += self.srcmask.eq(-1) # set to all 1s
+ # sync += self.dstmask.eq(-1) # set to all 1s
+ with m.FSM(name="fetch_predicate"):
+
+ with m.State("FETCH_PRED_IDLE"):
+ comb += pred_insn_ready_o.eq(1)
+ with m.If(pred_insn_valid_i):
+ sync += self.srcmask.eq(-1)
+ sync += self.dstmask.eq(-1)
+ m.next = "FETCH_PRED_DONE"
+
+ with m.State("FETCH_PRED_DONE"):
+ comb += pred_mask_valid_o.eq(1)
+ with m.If(pred_mask_ready_i):
+ m.next = "FETCH_PRED_IDLE"
def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
dbg, core_rst, is_svp64_mode,
fetch_pc_ready_o, fetch_pc_valid_i,
fetch_insn_valid_o, fetch_insn_ready_i,
+ pred_insn_valid_i, pred_insn_ready_o,
+ pred_mask_valid_o, pred_mask_ready_i,
exec_insn_valid_i, exec_insn_ready_o,
exec_pc_valid_o, exec_pc_ready_i):
"""issue FSM
new_svstate = SVSTATERec("new_svstate")
comb += new_svstate.eq(cur_state.svstate)
+ # precalculate srcstep+1 and dststep+1
+ cur_srcstep = cur_state.svstate.srcstep
+ cur_dststep = cur_state.svstate.dststep
+ next_srcstep = Signal.like(cur_srcstep)
+ next_dststep = Signal.like(cur_dststep)
+ comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
+ comb += next_dststep.eq(cur_state.svstate.dststep+1)
+
with m.FSM(name="issue_fsm"):
# sync with the "fetch" phase which is reading the instruction
comb += self.insn_done.eq(1)
m.next = "ISSUE_START"
with m.Else():
- m.next = "INSN_EXECUTE" # move to "execute"
+ m.next = "PRED_START" # start fetching the predicate
+
+ with m.State("PRED_START"):
+ comb += pred_insn_valid_i.eq(1) # tell fetch_pred to start
+ with m.If(pred_insn_ready_o): # fetch_pred acknowledged us
+ m.next = "MASK_WAIT"
+
+ with m.State("MASK_WAIT"):
+ comb += pred_mask_ready_i.eq(1) # ready to receive the masks
+ with m.If(pred_mask_valid_o): # predication masks are ready
+ m.next = "INSN_EXECUTE"
# handshake with execution FSM, move to "wait" once acknowledged
with m.State("INSN_EXECUTE"):
+ # with m.If(is_svp64_mode):
+ # TODO advance src/dst step to "skip" over predicated-out
+ # from self.srcmask and self.dstmask
+ # https://bugs.libre-soc.org/show_bug.cgi?id=617#c3
+ # but still without exceeding VL in either case
+ # IMPORTANT: when changing src/dest step, have to
+ # jump to m.next = "DECODE_SV" to deal with the change in
+ # SVSTATE
+
+ with m.If(is_svp64_mode):
+
+ pred_src_zero = pdecode2.rm_dec.pred_sz
+ pred_dst_zero = pdecode2.rm_dec.pred_dz
+
+ """
+ if not pred_src_zero:
+ if (((1<<cur_srcstep) & self.srcmask) == 0) and
+ (cur_srcstep != vl):
+ comb += update_svstate.eq(1)
+ comb += new_svstate.srcstep.eq(next_srcstep)
+ sync += sv_changed.eq(1)
+
+ if not pred_dst_zero:
+ if (((1<<cur_dststep) & self.dstmask) == 0) and
+ (cur_dststep != vl):
+ comb += new_svstate.dststep.eq(next_dststep)
+ comb += update_svstate.eq(1)
+ sync += sv_changed.eq(1)
+
+ if update_svstate:
+ m.next = "DECODE_SV"
+ """
+
comb += exec_insn_valid_i.eq(1) # trigger execute
with m.If(exec_insn_ready_o): # execute acknowledged us
m.next = "EXECUTE_WAIT"
with m.If(~dbg.core_stop_o & ~core_rst):
comb += exec_pc_ready_i.eq(1)
with m.If(exec_pc_valid_o):
- # precalculate srcstep+1 and dststep+1
- # TODO these need to "skip" over predicated-out src/dst
- # https://bugs.libre-soc.org/show_bug.cgi?id=617#c3
- # but still without exceeding VL in either case
- next_srcstep = Signal.like(cur_state.svstate.srcstep)
- next_dststep = Signal.like(cur_state.svstate.dststep)
- comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
- comb += next_dststep.eq(cur_state.svstate.dststep+1)
# was this the last loop iteration?
is_last = Signal()
comb += self.insn_done.eq(1)
m.next = "INSN_START" # back to fetch
- def elaborate(self, platform):
- m = Module()
+ def setup_peripherals(self, m):
comb, sync = m.d.comb, m.d.sync
m.submodules.core = core = DomainRenamer("coresync")(self.core)
m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
+ return core_rst
+
+ def elaborate(self, platform):
+ m = Module()
+ # convenience
+ comb, sync = m.d.comb, m.d.sync
+ cur_state = self.cur_state
+ pdecode2 = self.pdecode2
+ dbg = self.dbg
+ core = self.core
+
+ # set up peripherals and core
+ core_rst = self.setup_peripherals(m)
+
# PC and instruction from I-Memory
comb += self.pc_o.eq(cur_state.pc)
pc_changed = Signal() # note write to PC
sv_changed = Signal() # note write to SVSTATE
- # read the PC
- pc = Signal(64, reset_less=True)
- pc_ok_delay = Signal()
- sync += pc_ok_delay.eq(~self.pc_i.ok)
- with m.If(self.pc_i.ok):
- # incoming override (start from pc_i)
- comb += pc.eq(self.pc_i.data)
- with m.Else():
- # otherwise read StateRegs regfile for PC...
- comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
- # ... but on a 1-clock delay
- with m.If(pc_ok_delay):
- comb += pc.eq(self.state_r_pc.data_o)
-
- # read svstate
- svstate = Signal(64, reset_less=True)
- svstate_ok_delay = Signal()
- sync += svstate_ok_delay.eq(~self.svstate_i.ok)
- with m.If(self.svstate_i.ok):
- # incoming override (start from svstate__i)
- comb += svstate.eq(self.svstate_i.data)
- with m.Else():
- # otherwise read StateRegs regfile for SVSTATE...
- comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
- # ... but on a 1-clock delay
- with m.If(svstate_ok_delay):
- comb += svstate.eq(self.state_r_sv.data_o)
+ # read state either from incoming override or from regfile
+ # TODO: really should be doing MSR in the same way
+ pc = state_get(m, self.pc_i, "pc", # read PC
+ self.state_r_pc, StateRegs.PC)
+ svstate = state_get(m, self.svstate_i, "svstate", # read SVSTATE
+ self.state_r_sv, StateRegs.SVSTATE)
# don't write pc every cycle
comb += self.state_w_pc.wen.eq(0)
fetch_insn_valid_o = Signal()
fetch_insn_ready_i = Signal()
+ # predicate fetch FSM decodes and fetches the predicate
+ pred_insn_valid_i = Signal()
+ pred_insn_ready_o = Signal()
+
+ # predicate fetch FSM delivers the masks
+ pred_mask_valid_o = Signal()
+ pred_mask_ready_i = Signal()
+
# issue FSM delivers the instruction to the be executed
exec_insn_valid_i = Signal()
exec_insn_ready_o = Signal()
dbg, core_rst, is_svp64_mode,
fetch_pc_ready_o, fetch_pc_valid_i,
fetch_insn_valid_o, fetch_insn_ready_i,
+ pred_insn_valid_i, pred_insn_ready_o,
+ pred_mask_valid_o, pred_mask_ready_i,
exec_insn_valid_i, exec_insn_ready_o,
exec_pc_valid_o, exec_pc_ready_i)
+ self.fetch_predicate_fsm(m,
+ pred_insn_valid_i, pred_insn_ready_o,
+ pred_mask_valid_o, pred_mask_ready_i)
+
self.execute_fsm(m, core, pc_changed, sv_changed,
exec_insn_valid_i, exec_insn_ready_o,
exec_pc_valid_o, exec_pc_ready_i)
projects / soc.git / blobdiff