local variable rename in FetchFSM

[soc.git] / src / soc / simple / issuer_verilog.py

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 446b7f419731773df6c6a754174773213cd56613..8c0f8e1f5b8cc6a1a3d3e4f5947350e880c428e5 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -32,6 +32,12 @@ if __name__ == '__main__':
     parser.add_argument("--disable-core", dest='core', action="store_false",
                         help="disable main core",
                         default=False)
+    parser.add_argument("--enable-mmu", dest='mmu', action="store_true",
+                        help="Enable mmu",
+                        default=False)
+    parser.add_argument("--disable-mmu", dest='mmu', action="store_false",
+                        help="Disable mmu",
+                        default=False)
     parser.add_argument("--enable-pll", dest='pll', action="store_true",
                         help="Enable pll",
                         default=False)
@@ -65,9 +71,18 @@ if __name__ == '__main__':
              'mul': 1,
              'shiftrot': 1
             }
+    if args.mmu:
+        units['mmu'] = 1 # enable MMU
+
+    # decide which memory type to configure
+    if args.mmu:
+        ldst_ifacetype = 'mmu_cache_wb'
+    else:
+        ldst_ifacetype = 'bare_wb'
+    imem_ifacetype = 'bare_wb'
 
-    pspec = TestMemPspec(ldst_ifacetype='bare_wb',
-                         imem_ifacetype='bare_wb',
+    pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype,
+                         imem_ifacetype=imem_ifacetype,
                          addr_wid=48,
                          mask_wid=8,
                          # must leave at 64
@@ -84,8 +99,10 @@ if __name__ == '__main__':
                          sram4x4kblock=args.enable_sram4x4kblock, # add SRAMs
                          debug=args.debug,      # set to jtag or dmi
                          svp64=args.svp64,      # enable SVP64
+                         mmu=args.mmu,          # enable MMU
                          units=units)
 
+    print("mmu", pspec.__dict__["mmu"])
     print("nocore", pspec.__dict__["nocore"])
     print("regreduce", pspec.__dict__["regreduce"])
     print("gpio", pspec.__dict__["gpio"])