whoops, combinatorial loop on pending_priority

[soc.git] / src / soc / simple / issuer_verilog.py

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 46d36e99a581d462628083c288fb480e5c46365c..b93d47c2ed3b10d6276ce4c6ab4c98e613dfa193 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -27,7 +27,10 @@ if __name__ == '__main__':
                          imem_reg_wid=64,
                          # set to 32 to make data wishbone bus 32-bit
                          #wb_data_wid=32,
+                         xics=True,
+                         gpio=True, # for test purposes
                          units=units)
+
     dut = TestIssuer(pspec)
 
     vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")