whoops, combinatorial loop on pending_priority

[soc.git] / src / soc / simple / issuer_verilog.py

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index d77464b545d20da905f319e1c4f379cd9ec35d5b..b93d47c2ed3b10d6276ce4c6ab4c98e613dfa193 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -9,10 +9,14 @@ from soc.simple.issuer import TestIssuer
 
 
 if __name__ == '__main__':
-    units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
+    units = {'alu': 1,
+             'cr': 1, 'branch': 1, 'trap': 1,
+            'logical': 1,
              'spr': 1,
+             'div': 1,
              'mul': 1,
-             'shiftrot': 1}
+             'shiftrot': 1
+                }
     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
                          imem_ifacetype='bare_wb',
                          addr_wid=48,
@@ -21,7 +25,12 @@ if __name__ == '__main__':
                          reg_wid=64,
                          # set to 32 for instruction-memory width=32
                          imem_reg_wid=64,
+                         # set to 32 to make data wishbone bus 32-bit
+                         #wb_data_wid=32,
+                         xics=True,
+                         gpio=True, # for test purposes
                          units=units)
+
     dut = TestIssuer(pspec)
 
     vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")