sort out SPR setting in MMU

[soc.git] / src / soc / simple / issuer_verilog.py

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 30ca32b43ce938a356453c615a9938de739fb4bd..f9e655008359902ab8088f31cada5e9d17441d7b 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -12,14 +12,30 @@ if __name__ == '__main__':
     parser = argparse.ArgumentParser(description="Simple core issuer " \
                                      "verilog generator")
     parser.add_argument("output_filename")
-    parser.add_argument("--enable-xics", action="store_true",
+    parser.add_argument("--enable-xics", dest='xics', action="store_true",
+                        help="Enable interrupts",
+                        default=True)
+    parser.add_argument("--disable-xics", dest='xics', action="store_false",
                         help="Disable interrupts",
+                        default=False)
+    parser.add_argument("--enable-core", dest='core', action="store_true",
+                        help="Enable main core",
                         default=True)
-    parser.add_argument("--use-pll", action="store_true", help="Enable pll",
+    parser.add_argument("--disable-core", dest='core', action="store_false",
+                        help="disable main core",
+                        default=False)
+    parser.add_argument("--enable-pll", dest='pll', action="store_true",
+                        help="Enable pll",
+                        default=False)
+    parser.add_argument("--disable-pll", dest='pll', action="store_false",
+                        help="Disable pll",
                         default=False)
     parser.add_argument("--enable-testgpio", action="store_true",
                         help="Disable gpio pins",
                         default=False)
+    parser.add_argument("--enable-sram4x4kblock", action="store_true",
+                        help="Disable sram 4x4k block",
+                        default=False)
     parser.add_argument("--debug", default="jtag", help="Select debug " \
                         "interface [jtag | dmi] [default jtag]")
 
@@ -35,6 +51,7 @@ if __name__ == '__main__':
              'mul': 1,
              'shiftrot': 1
             }
+
     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
                          imem_ifacetype='bare_wb',
                          addr_wid=48,
@@ -45,13 +62,21 @@ if __name__ == '__main__':
                          imem_reg_wid=64,
                          # set to 32 to make data wishbone bus 32-bit
                          #wb_data_wid=32,
-                         xics=args.enable_xics, # XICS interrupt controller
-                         #nocore=True,          # to help test coriolis2 ioring
-                         use_pll=args.use_pll,  # bypass PLL
+                         xics=args.xics, # XICS interrupt controller
+                         nocore=not args.core, # test coriolis2 ioring
+                         use_pll=args.pll,  # bypass PLL
                          gpio=args.enable_testgpio, # for test purposes
+                         sram4x4kblock=args.enable_sram4x4kblock, # add SRAMs
                          debug=args.debug,      # set to jtag or dmi
                          units=units)
 
+    print("nocore", pspec.__dict__["nocore"])
+    print("gpio", pspec.__dict__["gpio"])
+    print("sram4x4kblock", pspec.__dict__["sram4x4kblock"])
+    print("xics", pspec.__dict__["xics"])
+    print("use_pll", pspec.__dict__["use_pll"])
+    print("debug", pspec.__dict__["debug"])
+
     dut = TestIssuer(pspec)
 
     vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")