sort out SPR setting in MMU

[soc.git] / src / soc / simple / issuer_verilog.py

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index f8f52d76949f92f473747f4cb8d8961327517677..f9e655008359902ab8088f31cada5e9d17441d7b 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -1,7 +1,7 @@
 """simple core issuer verilog generator
 """
 
-import sys
+import argparse
 from nmigen.cli import verilog
 
 from soc.config.test.test_loadstore import TestMemPspec
@@ -9,14 +9,49 @@ from soc.simple.issuer import TestIssuer
 
 
 if __name__ == '__main__':
+    parser = argparse.ArgumentParser(description="Simple core issuer " \
+                                     "verilog generator")
+    parser.add_argument("output_filename")
+    parser.add_argument("--enable-xics", dest='xics', action="store_true",
+                        help="Enable interrupts",
+                        default=True)
+    parser.add_argument("--disable-xics", dest='xics', action="store_false",
+                        help="Disable interrupts",
+                        default=False)
+    parser.add_argument("--enable-core", dest='core', action="store_true",
+                        help="Enable main core",
+                        default=True)
+    parser.add_argument("--disable-core", dest='core', action="store_false",
+                        help="disable main core",
+                        default=False)
+    parser.add_argument("--enable-pll", dest='pll', action="store_true",
+                        help="Enable pll",
+                        default=False)
+    parser.add_argument("--disable-pll", dest='pll', action="store_false",
+                        help="Disable pll",
+                        default=False)
+    parser.add_argument("--enable-testgpio", action="store_true",
+                        help="Disable gpio pins",
+                        default=False)
+    parser.add_argument("--enable-sram4x4kblock", action="store_true",
+                        help="Disable sram 4x4k block",
+                        default=False)
+    parser.add_argument("--debug", default="jtag", help="Select debug " \
+                        "interface [jtag | dmi] [default jtag]")
+
+    args = parser.parse_args()
+
+    print(args)
+
     units = {'alu': 1,
              'cr': 1, 'branch': 1, 'trap': 1,
-            'logical': 1,
+             'logical': 1,
              'spr': 1,
              'div': 1,
              'mul': 1,
              'shiftrot': 1
-                }
+            }
+
     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
                          imem_ifacetype='bare_wb',
                          addr_wid=48,
@@ -26,10 +61,24 @@ if __name__ == '__main__':
                          # set to 32 for instruction-memory width=32
                          imem_reg_wid=64,
                          # set to 32 to make data wishbone bus 32-bit
-                         wb_data_wid=32,
+                         #wb_data_wid=32,
+                         xics=args.xics, # XICS interrupt controller
+                         nocore=not args.core, # test coriolis2 ioring
+                         use_pll=args.pll,  # bypass PLL
+                         gpio=args.enable_testgpio, # for test purposes
+                         sram4x4kblock=args.enable_sram4x4kblock, # add SRAMs
+                         debug=args.debug,      # set to jtag or dmi
                          units=units)
+
+    print("nocore", pspec.__dict__["nocore"])
+    print("gpio", pspec.__dict__["gpio"])
+    print("sram4x4kblock", pspec.__dict__["sram4x4kblock"])
+    print("xics", pspec.__dict__["xics"])
+    print("use_pll", pspec.__dict__["use_pll"])
+    print("debug", pspec.__dict__["debug"])
+
     dut = TestIssuer(pspec)
 
     vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")
-    with open(sys.argv[1], "w") as f:
+    with open(args.output_filename, "w") as f:
         f.write(vl)