sort out SPR setting in MMU

[soc.git] / src / soc / simple / test / test_core.py

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 6f7c8ffdc87e3a983c724a06d4a8026131bda575..0bf1ee42d019ef594df0333e025a2bf7b0371030 100644 (file)
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -100,9 +100,9 @@ def setup_regs(pdecode2, core, test):
             # match behaviour of SPRMap in power_decoder2.py
             for i, x in enumerate(SPR):
                 if sprname == x.name:
-                    yield sregs[i].reg.eq(val)
                     print("setting slow SPR %d (%s) to %x" %
                           (i, sprname, val))
+                    yield sregs.memory._array[i].eq(val)
         else:
             yield fregs.regs[fast].reg.eq(val)
             print("setting fast reg %d (%s) to %x" %