adding in ALU test back in, debugging SPR setup

[soc.git] / src / soc / simple / test / test_core.py

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index d3599be807b63a99fb5b1054d11dd23d60046865..aa1845e7846546a047b1a4dadf6b6479523e19ec 100644 (file)
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -14,7 +14,7 @@ from soc.decoder.power_decoder import create_pdecode
 from soc.decoder.power_decoder2 import PowerDecode2
 from soc.decoder.selectable_int import SelectableInt
 from soc.decoder.isa.all import ISA
-from soc.decoder.power_enums import Function, XER_bits
+from soc.decoder.power_enums import SPR, Function, XER_bits
 from soc.config.test.test_loadstore import TestMemPspec
 
 from soc.simple.core import NonProductionCore