from nmutil.formaltest import FHDLTestCase
from nmigen.cli import rtlil
import unittest
-from teststate import SimState, HDLState, TestState
+from openpower.test.state import (SimState, teststate_check_regs,
+ teststate_check_mem)
+from soc.simple.test.teststate import HDLState
from openpower.decoder.isa.caller import special_sprs
from openpower.decoder.power_decoder import create_pdecode
from openpower.decoder.power_decoder2 import PowerDecode2
print("oe:", oe, oe_ok)
-def teststate_check_regs(dut, states, test, code):
- """teststate_check_regs: compares a set of Power ISA objects
- to check if they have the same "state" (registers only, at the moment)
- """
- slist = []
- # create one TestState per "thing"
- for stype, totest in states.items():
- state = yield from TestState(stype, totest, dut, code)
- slist.append(state)
- # compare each "thing" against the next "thing" in the list.
- # (no need to do an O(N^2) comparison here, they *all* have to be the same
- for i in range(len(slist)-1):
- state, against = slist[i], slist[i+1]
- state.compare(against)
-
-
def check_regs(dut, sim, core, test, code):
# create the two states and compare
testdic = {'sim': sim, 'hdl': core}
yield from teststate_check_regs(dut, testdic, test, code)
+def check_mem(dut, sim, core, test, code):
+ # create the two states and compare mem
+ testdic = {'sim': sim, 'hdl': core}
+ yield from teststate_check_mem(dut, testdic, test, code)
+
+
def wait_for_busy_hi(cu):
while True:
busy_o = yield cu.busy_o
for test in self.test_data:
print(test.name)
program = test.program
- self.subTest(test.name)
- sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
- test.msr,
- bigendian=bigendian)
- gen = program.generate_instructions()
- instructions = list(zip(gen, program.assembly.splitlines()))
-
- yield from setup_tst_memory(l0, sim)
- yield from setup_regs(core, test)
-
- index = sim.pc.CIA.value // 4
- while index < len(instructions):
- ins, code = instructions[index]
-
- print("instruction: 0x{:X}".format(ins & 0xffffffff))
- print(code)
-
- # ask the decoder to decode this binary data (endian'd)
- yield core.bigendian_i.eq(bigendian) # little / big?
- yield instruction.eq(ins) # raw binary instr.
- yield ivalid_i.eq(1)
- yield Settle()
- # fn_unit = yield pdecode2.e.fn_unit
- #fuval = self.funit.value
- #self.assertEqual(fn_unit & fuval, fuval)
-
- # set operand and get inputs
- yield from set_issue(core, pdecode2, sim)
- yield Settle()
-
- yield from wait_for_busy_clear(core)
- yield ivalid_i.eq(0)
- yield
-
- print("sim", code)
- # call simulated operation
- opname = code.split(' ')[0]
- yield from sim.call(opname)
- index = sim.pc.CIA.value // 4
+ with self.subTest(test.name):
+ sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
+ test.mem,
+ test.msr,
+ bigendian=bigendian)
+ gen = program.generate_instructions()
+ instructions = list(zip(gen, program.assembly.splitlines()))
- # register check
- yield from check_regs(self, sim, core, test, code)
+ yield from setup_tst_memory(l0, test.mem)
+ yield from setup_regs(core, test)
- # Memory check
- yield from check_sim_memory(self, l0, sim, code)
+ index = sim.pc.CIA.value // 4
+ while index < len(instructions):
+ ins, code = instructions[index]
+
+ print("instruction: 0x{:X}".format(ins & 0xffffffff))
+ print(code)
+
+ # ask the decoder to decode this binary data (endian'd)
+ yield core.bigendian_i.eq(bigendian) # little / big?
+ yield instruction.eq(ins) # raw binary instr.
+ yield ivalid_i.eq(1)
+ yield Settle()
+ # fn_unit = yield pdecode2.e.fn_unit
+ #fuval = self.funit.value
+ #self.assertEqual(fn_unit & fuval, fuval)
+
+ # set operand and get inputs
+ yield from set_issue(core, pdecode2, sim)
+ yield Settle()
+
+ yield from wait_for_busy_clear(core)
+ yield ivalid_i.eq(0)
+ yield
+
+ print("sim", code)
+ # call simulated operation
+ opname = code.split(' ')[0]
+ yield from sim.call(opname)
+ index = sim.pc.CIA.value // 4
+
+ # register check
+ yield from check_regs(self, sim, core, test, code)
+
+ # Memory check
+ yield from check_mem(self, sim, core, test, code)
sim.add_sync_process(process)
with sim.write_vcd("core_simulator.vcd", "core_simulator.gtkw",
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