related bugs:
* https://bugs.libre-soc.org/show_bug.cgi?id=363
+ * https://bugs.libre-soc.org/show_bug.cgi?id=686
"""
+
from nmigen import Module, Signal, Cat
from nmigen.back.pysim import Simulator, Delay, Settle
from nmutil.formaltest import FHDLTestCase
from nmigen.cli import rtlil
import unittest
+from openpower.test.state import (SimState, teststate_check_regs,
+ teststate_check_mem)
+from soc.simple.test.teststate import HDLState
from openpower.decoder.isa.caller import special_sprs
from openpower.decoder.power_decoder import create_pdecode
from openpower.decoder.power_decoder2 import PowerDecode2
# list of SPRs that are controlled and managed by the MMU
mmu_sprs = ["PRTBL", "DSISR", "DAR", "PIDR"]
-def set_mmu_spr(name, i, val, core): #important keep pep8 formatting
- fsm = core.fus.get_fu("mmu0").alu
- yield fsm.mmu.l_in.mtspr.eq(1)
- yield fsm.mmu.l_in.sprn.eq(i)
- yield fsm.mmu.l_in.rs.eq(val)
- yield
- yield fsm.mmu.l_in.mtspr.eq(0)
- print("mmu_spr was updated")
+
+def set_mmu_spr(name, i, val, core): # important keep pep8 formatting
+ fsm = core.fus.get_fu("mmu0").alu
+ yield fsm.mmu.l_in.mtspr.eq(1)
+ yield fsm.mmu.l_in.sprn.eq(i)
+ yield fsm.mmu.l_in.rs.eq(val)
+ yield
+ yield fsm.mmu.l_in.mtspr.eq(0)
+ print("mmu_spr was updated")
+
def setup_regs(pdecode2, core, test):
print("setup cr reg", hex(cr))
for i in range(8):
#j = 7-i
- cri = (cr >> (i*4)) & 0xf
+ cri = (cr >> (i * 4)) & 0xf
#cri = int('{:04b}'.format(cri)[::-1], 2)
print("setup cr reg", hex(cri), i,
crregs.regs[i].reg.shape())
if sprname == x.name:
print("setting slow SPR %d (%s) to %x" %
(i, sprname, val))
- if not sprname in mmu_sprs:
+ if sprname not in mmu_sprs:
yield sregs.memory._array[i].eq(val)
else:
yield from set_mmu_spr(sprname, i, val, core)
def check_regs(dut, sim, core, test, code):
- # int regs
- intregs = []
- for i in range(32):
- if core.regs.int.unary:
- rval = yield core.regs.int.regs[i].reg
- else:
- rval = yield core.regs.int.memory._array[i]
- intregs.append(rval)
- print("int regs", list(map(hex, intregs)))
- for i in range(32):
- simregval = sim.gpr[i].asint()
- dut.assertEqual(simregval, intregs[i],
- "int reg %d not equal %s. got %x expected %x" % \
- (i, repr(code), simregval, intregs[i]))
-
- # CRs
- crregs = []
- for i in range(8):
- rval = yield core.regs.cr.regs[i].reg
- crregs.append(rval)
- print("cr regs", list(map(hex, crregs)))
- for i in range(8):
- rval = crregs[i]
- cri = sim.crl[7-i].get_range().value
- print("cr reg", i, hex(cri), i, hex(rval))
- # XXX https://bugs.libre-soc.org/show_bug.cgi?id=363
- dut.assertEqual(cri, rval,
- "cr reg %d not equal %s" % (i, repr(code)))
-
- # XER
- xregs = core.regs.xer
- so = yield xregs.regs[xregs.SO].reg
- ov = yield xregs.regs[xregs.OV].reg
- ca = yield xregs.regs[xregs.CA].reg
-
- print("sim SO", sim.spr['XER'][XER_bits['SO']])
- e_so = sim.spr['XER'][XER_bits['SO']].value
- e_ov = sim.spr['XER'][XER_bits['OV']].value
- e_ov32 = sim.spr['XER'][XER_bits['OV32']].value
- e_ca = sim.spr['XER'][XER_bits['CA']].value
- e_ca32 = sim.spr['XER'][XER_bits['CA32']].value
-
- e_ov = e_ov | (e_ov32 << 1)
- e_ca = e_ca | (e_ca32 << 1)
+ # create the two states and compare
+ testdic = {'sim': sim, 'hdl': core}
+ yield from teststate_check_regs(dut, testdic, test, code)
- print("after: so/ov-32/ca-32", so, bin(ov), bin(ca))
- dut.assertEqual(e_so, so, "so mismatch %s" % (repr(code)))
- dut.assertEqual(e_ov, ov, "ov mismatch %s" % (repr(code)))
- dut.assertEqual(e_ca, ca, "ca mismatch %s" % (repr(code)))
- # Check the PC as well
- state = core.regs.state
- pc = yield state.r_ports['cia'].o_data
- e_pc = sim.pc.CIA.value
- dut.assertEqual(e_pc, pc)
+def check_mem(dut, sim, core, test, code):
+ # create the two states and compare mem
+ testdic = {'sim': sim, 'hdl': core}
+ yield from teststate_check_mem(dut, testdic, test, code)
def wait_for_busy_hi(cu):
m = Module()
comb = m.d.comb
instruction = Signal(32)
- ii_valid = Signal()
+ ivalid_i = Signal()
pspec = TestMemPspec(ldst_ifacetype='testpi',
imem_ifacetype='',
l0 = core.l0
comb += core.raw_opcode_i.eq(instruction)
- comb += core.ii_valid.eq(ii_valid)
+ comb += core.ivalid_i.eq(ivalid_i)
# temporary hack: says "go" immediately for both address gen and ST
ldst = core.fus.fus['ldst0']
for test in self.test_data:
print(test.name)
program = test.program
- self.subTest(test.name)
- sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
- test.msr,
- bigendian=bigendian)
- gen = program.generate_instructions()
- instructions = list(zip(gen, program.assembly.splitlines()))
-
- yield from setup_tst_memory(l0, sim)
- yield from setup_regs(core, test)
-
- index = sim.pc.CIA.value//4
- while index < len(instructions):
- ins, code = instructions[index]
-
- print("instruction: 0x{:X}".format(ins & 0xffffffff))
- print(code)
-
- # ask the decoder to decode this binary data (endian'd)
- yield core.bigendian_i.eq(bigendian) # little / big?
- yield instruction.eq(ins) # raw binary instr.
- yield ii_valid.eq(1)
- yield Settle()
- # fn_unit = yield pdecode2.e.fn_unit
- #fuval = self.funit.value
- #self.assertEqual(fn_unit & fuval, fuval)
-
- # set operand and get inputs
- yield from set_issue(core, pdecode2, sim)
- yield Settle()
-
- yield from wait_for_busy_clear(core)
- yield ii_valid.eq(0)
- yield
-
- print("sim", code)
- # call simulated operation
- opname = code.split(' ')[0]
- yield from sim.call(opname)
- index = sim.pc.CIA.value//4
-
- # register check
- yield from check_regs(self, sim, core, test, code)
-
- # Memory check
- yield from check_sim_memory(self, l0, sim, code)
+ with self.subTest(test.name):
+ sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
+ test.mem,
+ test.msr,
+ bigendian=bigendian)
+ gen = program.generate_instructions()
+ instructions = list(zip(gen, program.assembly.splitlines()))
+
+ yield from setup_tst_memory(l0, test.mem)
+ yield from setup_regs(core, test)
+
+ index = sim.pc.CIA.value // 4
+ while index < len(instructions):
+ ins, code = instructions[index]
+
+ print("instruction: 0x{:X}".format(ins & 0xffffffff))
+ print(code)
+
+ # ask the decoder to decode this binary data (endian'd)
+ yield core.bigendian_i.eq(bigendian) # little / big?
+ yield instruction.eq(ins) # raw binary instr.
+ yield ivalid_i.eq(1)
+ yield Settle()
+ # fn_unit = yield pdecode2.e.fn_unit
+ #fuval = self.funit.value
+ #self.assertEqual(fn_unit & fuval, fuval)
+
+ # set operand and get inputs
+ yield from set_issue(core, pdecode2, sim)
+ yield Settle()
+
+ yield from wait_for_busy_clear(core)
+ yield ivalid_i.eq(0)
+ yield
+
+ print("sim", code)
+ # call simulated operation
+ opname = code.split(' ')[0]
+ yield from sim.call(opname)
+ index = sim.pc.CIA.value // 4
+
+ # register check
+ yield from check_regs(self, sim, core, test, code)
+
+ # Memory check
+ yield from check_mem(self, sim, core, test, code)
sim.add_sync_process(process)
with sim.write_vcd("core_simulator.vcd", "core_simulator.gtkw",
projects / soc.git / blobdiff