added comment to teststate

[soc.git] / src / soc / simple / test / test_core.py

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index b77ff9425732beb7158847346c32645afc044562..c15732d1b5582e2439ed19d4260c25d0c6d22562 100644 (file)
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -240,7 +240,7 @@ class TestRunner(FHDLTestCase):
                     gen = program.generate_instructions()
                     instructions = list(zip(gen, program.assembly.splitlines()))
 
-                    yield from setup_tst_memory(l0, sim)
+                    yield from setup_tst_memory(l0, test.mem)
                     yield from setup_regs(core, test)
 
                     index = sim.pc.CIA.value // 4