enable all tests again in test_core.py and test_issuer.py

[soc.git] / src / soc / simple / test / test_issuer.py

diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index cd07b500cc0b33338aebcedad81e817e949f1bc2..119c3c7f90cf87723f0dab3dd7dd7d61d1e5cdfa 100644 (file)
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -53,6 +53,7 @@ class TestRunner(FHDLTestCase):
         m = Module()
         comb = m.d.comb
         go_insn_i = Signal()
+        pc_i = Signal(32)
 
         m.submodules.issuer = issuer = TestIssuer()
         imem = issuer.imem.mem
@@ -60,6 +61,7 @@ class TestRunner(FHDLTestCase):
         pdecode2 = core.pdecode2
         l0 = core.l0
 
+        comb += issuer.pc_i.data.eq(pc_i)
         comb += issuer.go_insn_i.eq(go_insn_i)
 
         # nmigen Simulation
@@ -83,7 +85,7 @@ class TestRunner(FHDLTestCase):
                 yield from setup_test_memory(l0, sim)
                 yield from setup_regs(core, test)
 
-                yield issuer.pc_i.data.eq(pc)
+                yield pc_i.eq(pc)
                 yield issuer.pc_i.ok.eq(1)
 
                 index = sim.pc.CIA.value//4
@@ -115,6 +117,8 @@ class TestRunner(FHDLTestCase):
                     # Memory check
                     yield from check_sim_memory(self, l0, sim, code)
 
+                    yield
+
         sim.add_sync_process(process)
         with sim.write_vcd("issuer_simulator.vcd",
                             traces=[]):
@@ -124,12 +128,12 @@ class TestRunner(FHDLTestCase):
 if __name__ == "__main__":
     unittest.main(exit=False)
     suite = unittest.TestSuite()
-    #suite.addTest(TestRunner(LDSTTestCase.test_data))
-    #suite.addTest(TestRunner(CRTestCase.test_data))
-    #suite.addTest(TestRunner(ShiftRotTestCase.test_data))
-    #suite.addTest(TestRunner(LogicalTestCase.test_data))
+    suite.addTest(TestRunner(LDSTTestCase.test_data))
+    suite.addTest(TestRunner(CRTestCase.test_data))
+    suite.addTest(TestRunner(ShiftRotTestCase.test_data))
+    suite.addTest(TestRunner(LogicalTestCase.test_data))
     suite.addTest(TestRunner(ALUTestCase.test_data))
-    #suite.addTest(TestRunner(BranchTestCase.test_data))
+    suite.addTest(TestRunner(BranchTestCase.test_data))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)