src/soc/fu/mmu/fsm.py: add debug outputs for gtkwave

[soc.git] / src / soc / simple / test / test_issuer.py

diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index 3d1359ea004c9faf3bfb82330416a4433f6b280d..2a45ec2d898721b18f7d16c0632b45d6899bfc8b 100644 (file)
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -4,13 +4,14 @@ related bugs:
 
  * https://bugs.libre-soc.org/show_bug.cgi?id=363
 """
-from nmigen import Module, Signal, Cat
+from nmigen import Module, Signal, Cat, ClockSignal
 
 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
 # Also, check out the cxxsim nmigen branch, and latest yosys from git
 from nmutil.sim_tmp_alternative import Simulator, Settle
 
 from nmutil.formaltest import FHDLTestCase
+from nmutil.gtkw import write_gtkw
 from nmigen.cli import rtlil
 import unittest
 from soc.decoder.isa.caller import special_sprs
@@ -132,9 +133,10 @@ def get_dmi(dmi, addr):
 
 
 class TestRunner(FHDLTestCase):
-    def __init__(self, tst_data):
+    def __init__(self, tst_data, microwatt_mmu=False):
         super().__init__("run_all")
         self.test_data = tst_data
+        self.microwatt_mmu = microwatt_mmu
 
     def run_all(self):
         m = Module()
@@ -147,6 +149,11 @@ class TestRunner(FHDLTestCase):
                              mask_wid=8,
                              imem_reg_wid=64,
                              #wb_data_width=32,
+                             use_pll=False,
+                             nocore=False,
+                             xics=False,
+                             gpio=False,
+                             mmu=self.microwatt_mmu,
                              reg_wid=64)
         m.submodules.issuer = issuer = TestIssuerInternal(pspec)
         imem = issuer.imem._get_memory()
@@ -160,6 +167,10 @@ class TestRunner(FHDLTestCase):
         simdec2 = PowerDecode2(simdec)
         m.submodules.simdec2 = simdec2  # pain in the neck
 
+        # run core clock at same rate as test clock
+        intclk = ClockSignal("coresync")
+        comb += intclk.eq(ClockSignal())
+
         comb += issuer.pc_i.data.eq(pc_i)
 
         # nmigen Simulation
@@ -297,9 +308,39 @@ class TestRunner(FHDLTestCase):
                     print ("after test %s reg %2d value %x" % \
                                 (test.name, int_reg, value))
 
+        traces = [
+            'clk',  'fsm_state',
+            {'comment': 'fetch and decode'},
+            'cia[63:0]', 'nia[63:0]', 'pc[63:0]', 'raw_insn_i[31:0]',
+            'raw_opcode_in[31:0]', 'insn_type',
+            {'comment': 'issue and execute'},
+            'core.core_core_insn_type', 'issue_i', 'busy_o',
+            {'comment': 'dmi'},
+            'dbg.dmi_req_i', 'dbg.dmi_ack_o',
+            {'comment': 'instruction memory'},
+            'imem.sram.rdport.memory(0)[63:0]',
+            {'comment': 'registers'},
+            'core.int.rp_src1.memory(0)[63:0]',
+            'core.int.rp_src1.memory(1)[63:0]',
+            'core.int.rp_src1.memory(2)[63:0]',
+            'core.int.rp_src1.memory(3)[63:0]',
+            'core.int.rp_src1.memory(4)[63:0]',
+            'core.int.rp_src1.memory(9)[63:0]',
+        ]
+
+        if(self.microwatt_mmu):
+            traces += [
+                {'comment': 'microwatt_mmu'},
+                'core.fus.mmu0.alu_mmu0.illegal',
+                'core.fus.mmu0.alu_mmu0.debug0[3:0]'
+            ]
+
+        write_gtkw("issuer_simulator.gtkw",
+                   "issuer_simulator.vcd",
+                   traces, module='top.issuer')
+
         sim.add_sync_process(process)
-        with sim.write_vcd("issuer_simulator.vcd",
-                           traces=[]):
+        with sim.write_vcd("issuer_simulator.vcd"):
             sim.run()