alter setup_tst_memory to take a test.mem rather than take a Sim object
[soc.git] / src / soc / simple / test / test_issuer.py
index 3170cfbb423f0af62ddd868a6eb9778c281d5893..2b6fa3e91f5daf0ebdf7bf3d79fc5c585daae5d7 100644 (file)
@@ -10,19 +10,25 @@ related bugs:
 
 import unittest
 import sys
+
+# here is the logic which takes test cases and "executes" them.
+# in this instance (TestRunner) its job is to instantiate both
+# a Libre-SOC nmigen-based HDL instance and an ISACaller python
+# simulator.  it's also responsible for performing the single
+# step and comparison.
 from soc.simple.test.test_runner import TestRunner
 
 # test with ALU data and Logical data
-from soc.fu.alu.test.test_pipe_caller import ALUTestCase
-from soc.fu.div.test.test_pipe_caller import DivTestCases
-from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
-from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
-from soc.fu.cr.test.test_pipe_caller import CRTestCase
-# from soc.fu.branch.test.test_pipe_caller import BranchTestCase
-from soc.fu.spr.test.test_pipe_caller import SPRTestCase
-from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
-from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase)
-# from soc.simulator.test_helloworld_sim import HelloTestCases
+from openpower.test.alu.alu_cases import ALUTestCase
+from openpower.test.div.div_cases import DivTestCases
+from openpower.test.logical.logical_cases import LogicalTestCase
+from openpower.test.shift_rot.shift_rot_cases import ShiftRotTestCase
+from openpower.test.cr.cr_cases import CRTestCase
+from openpower.test.branch.branch_cases import BranchTestCase
+from soc.fu.spr.test.test_pipe_caller import SPRTestCase
+from openpower.test.ldst.ldst_cases import LDSTTestCase
+from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase)
+from openpower.simulator.test_helloworld_sim import HelloTestCases
 
 
 if __name__ == "__main__":
@@ -32,21 +38,37 @@ if __name__ == "__main__":
             svp64 = False
         sys.argv.pop()
 
-    print ("SVP64 test mode enabled", svp64)
+    # allow list of testing to be selected by command-line
+    testing = sys.argv[1:]
+    sys.argv = sys.argv[:1]
+
+    if not testing:
+        testing = ['general', 'ldst', 'cr', 'shiftrot', 'logical', 'alu',
+                   'branch', 'div']
+
+    print ("SVP64 test mode enabled", svp64, testing)
 
     unittest.main(exit=False)
     suite = unittest.TestSuite()
-    # suite.addTest(TestRunner(HelloTestCases.test_data, svp64=svp64))
-    suite.addTest(TestRunner(DivTestCases().test_data, svp64=svp64))
-    # suite.addTest(TestRunner(AttnTestCase.test_data, svp64=svp64))
-    suite.addTest(TestRunner(GeneralTestCases.test_data, svp64=svp64))
-    suite.addTest(TestRunner(LDSTTestCase().test_data, svp64=svp64))
-    suite.addTest(TestRunner(CRTestCase().test_data, svp64=svp64))
-    suite.addTest(TestRunner(ShiftRotTestCase().test_data, svp64=svp64))
-    suite.addTest(TestRunner(LogicalTestCase().test_data, svp64=svp64))
-    suite.addTest(TestRunner(ALUTestCase().test_data, svp64=svp64))
-    # suite.addTest(TestRunner(BranchTestCase.test_data, svp64=svp64))
-    # suite.addTest(TestRunner(SPRTestCase.test_data, svp64=svp64))
+
+    # dictionary  of data for tests
+    tests = {'hello': HelloTestCases.test_data,
+             'div': DivTestCases().test_data,
+             'attn': AttnTestCase.test_data,
+             'general': GeneralTestCases.test_data,
+             'ldst': LDSTTestCase().test_data,
+             'cr': CRTestCase().test_data,
+             'shiftrot': ShiftRotTestCase().test_data,
+             'logical': LogicalTestCase().test_data,
+             'alu': ALUTestCase().test_data,
+             'branch': BranchTestCase().test_data,
+             'spr': SPRTestCase().test_data
+            }
+
+    # walk through all tests, those requested get added
+    for tname, data in tests.items():
+        if tname in testing:
+            suite.addTest(TestRunner(data, svp64=svp64))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)