create dummy PLL block, connect up to core and clock-selector

[soc.git] / src / soc / simple / test / test_issuer.py

diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index 2361ed1a30ce3cfdddfb154c05c80f437fb5a56b..3d1359ea004c9faf3bfb82330416a4433f6b280d 100644 (file)
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -5,7 +5,11 @@ related bugs:
  * https://bugs.libre-soc.org/show_bug.cgi?id=363
 """
 from nmigen import Module, Signal, Cat
-from nmigen.back.pysim import Simulator, Delay, Settle
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
+
 from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 import unittest
@@ -17,7 +21,7 @@ from soc.config.endian import bigendian
 from soc.decoder.power_decoder import create_pdecode
 from soc.decoder.power_decoder2 import PowerDecode2
 
-from soc.simple.issuer import TestIssuer
+from soc.simple.issuer import TestIssuerInternal
 from soc.experiment.compalu_multi import find_ok  # hack
 
 from soc.config.test.test_loadstore import TestMemPspec
@@ -144,7 +148,7 @@ class TestRunner(FHDLTestCase):
                              imem_reg_wid=64,
                              #wb_data_width=32,
                              reg_wid=64)
-        m.submodules.issuer = issuer = TestIssuer(pspec)
+        m.submodules.issuer = issuer = TestIssuerInternal(pspec)
         imem = issuer.imem._get_memory()
         core = issuer.core
         dmi = issuer.dbg.dmi
@@ -281,6 +285,10 @@ class TestRunner(FHDLTestCase):
                 cr = yield from get_dmi(dmi, DBGCore.CR)
                 print ("after test %s cr value %x" % (test.name, cr))
 
+                # get XER
+                xer = yield from get_dmi(dmi, DBGCore.XER)
+                print ("after test %s XER value %x" % (test.name, xer))
+
                 # test of dmi reg get
                 for int_reg in range(32):
                     yield from set_dmi(dmi, DBGCore.GSPR_IDX, int_reg)