* https://bugs.libre-soc.org/show_bug.cgi?id=363
"""
from nmigen import Module, Signal, Cat
-from nmigen.back.pysim import Simulator, Delay, Settle
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
+
from nmutil.formaltest import FHDLTestCase
from nmigen.cli import rtlil
import unittest
from soc.decoder.power_decoder import create_pdecode
from soc.decoder.power_decoder2 import PowerDecode2
-from soc.simple.issuer import TestIssuer
+from soc.simple.issuer import TestIssuerInternal
from soc.experiment.compalu_multi import find_ok # hack
from soc.config.test.test_loadstore import TestMemPspec
imem_reg_wid=64,
#wb_data_width=32,
reg_wid=64)
- m.submodules.issuer = issuer = TestIssuer(pspec)
+ m.submodules.issuer = issuer = TestIssuerInternal(pspec)
imem = issuer.imem._get_memory()
core = issuer.core
dmi = issuer.dbg.dmi
cr = yield from get_dmi(dmi, DBGCore.CR)
print ("after test %s cr value %x" % (test.name, cr))
- # get CR
+ # get XER
xer = yield from get_dmi(dmi, DBGCore.XER)
print ("after test %s XER value %x" % (test.name, xer))