add quick demo/test of reading DMI reg 9

[soc.git] / src / soc / simple / test / test_issuer.py

diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index b1df27dccae250e2b7def5ac59c65ef241831cf6..a8b0f34a77de9fca36467dc0ddd4524241791254 100644 (file)
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -103,6 +103,24 @@ def set_dmi(dmi, addr, data):
     yield dmi.we_i.eq(0)
 
 
+def get_dmi(dmi, addr):
+    yield dmi.req_i.eq(1)
+    yield dmi.addr_i.eq(addr)
+    yield dmi.din.eq(0)
+    yield dmi.we_i.eq(1)
+    while True:
+        ack = yield dmi.ack_o
+        if ack:
+            break
+        yield
+    yield # wait one
+    data = yield dmi.dout # get data after ack valid for 1 cycle
+    yield dmi.req_i.eq(0)
+    yield dmi.addr_i.eq(0)
+    yield dmi.we_i.eq(0)
+    return data
+
+
 class TestRunner(FHDLTestCase):
     def __init__(self, tst_data):
         super().__init__("run_all")
@@ -224,6 +242,14 @@ class TestRunner(FHDLTestCase):
                     if terminated:
                         break
 
+                # test of dmi reg get
+                int_reg = 9
+                yield from set_dmi(dmi, DBGCore.GSPR_IDX, int_reg) # int reg 9
+                value = yield from get_dmi(dmi, DBGCore.GSPR_DATA) # get data
+
+                print ("after test %s reg %x value %s" % \
+                            (test.name, int_reg, value))
+
         sim.add_sync_process(process)
         with sim.write_vcd("issuer_simulator.vcd",
                            traces=[]):