debugging termination / OP_ATTN

[soc.git] / src / soc / simple / test / test_issuer.py

diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index 14a23a8cc51fbdcba758c402937b6a8f6eceb9ca..fd068a65d6dcdcfbd5b9d4add84c16cbcb2ebf7f 100644 (file)
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -17,6 +17,7 @@ from soc.decoder.power_enums import Function, XER_bits
 from soc.simple.issuer import TestIssuer
 from soc.experiment.compalu_multi import find_ok # hack
 
+from soc.config.test.test_loadstore import TestMemPspec
 from soc.simple.test.test_core import (setup_regs, check_regs,
                                        wait_for_busy_clear,
                                        wait_for_busy_hi)
@@ -29,8 +30,9 @@ from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
 from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
 from soc.fu.cr.test.test_pipe_caller import CRTestCase
 from soc.fu.branch.test.test_pipe_caller import BranchTestCase
+from soc.fu.spr.test.test_pipe_caller import SPRTestCase
 from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
-from soc.simulator.test_sim import GeneralTestCases
+from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase)
 
 
 def setup_i_memory(imem, startaddr, instructions):
@@ -66,8 +68,12 @@ class TestRunner(FHDLTestCase):
         go_insn_i = Signal()
         pc_i = Signal(32)
 
-        m.submodules.issuer = issuer = TestIssuer(ifacetype="test_bare_wb",
-                                                  imemtype="test_bare_wb")
+        pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
+                             imem_ifacetype='test_bare_wb',
+                             addr_wid=48,
+                             mask_wid=8,
+                             reg_wid=64)
+        m.submodules.issuer = issuer = TestIssuer(pspec)
         imem = issuer.imem._get_memory()
         core = issuer.core
         pdecode2 = core.pdecode2
@@ -83,6 +89,13 @@ class TestRunner(FHDLTestCase):
         def process():
 
             for test in self.test_data:
+
+                # get core going
+                yield core.core_start_i.eq(1)
+                yield
+                yield core.core_start_i.eq(0)
+                yield Settle()
+
                 print(test.name)
                 program = test.program
                 self.subTest(test.name)
@@ -121,6 +134,7 @@ class TestRunner(FHDLTestCase):
                     yield
                     yield issuer.pc_i.ok.eq(0) # don't change PC from now on
                     yield go_insn_i.eq(0)      # and don't issue a new insn
+                    yield Settle()
 
                     # wait until executed
                     yield from wait_for_busy_hi(core)
@@ -139,6 +153,10 @@ class TestRunner(FHDLTestCase):
                     # Memory check
                     yield from check_sim_memory(self, l0, sim, code)
 
+                    terminated = yield core.core_terminated_o
+                    if terminated:
+                        break
+
         sim.add_sync_process(process)
         with sim.write_vcd("issuer_simulator.vcd",
                             traces=[]):
@@ -148,13 +166,15 @@ class TestRunner(FHDLTestCase):
 if __name__ == "__main__":
     unittest.main(exit=False)
     suite = unittest.TestSuite()
-    suite.addTest(TestRunner(GeneralTestCases.test_data))
-    suite.addTest(TestRunner(LDSTTestCase.test_data))
-    suite.addTest(TestRunner(CRTestCase.test_data))
-    suite.addTest(TestRunner(ShiftRotTestCase.test_data))
-    suite.addTest(TestRunner(LogicalTestCase.test_data))
+    suite.addTest(TestRunner(AttnTestCase.test_data))
+    #suite.addTest(TestRunner(GeneralTestCases.test_data))
+    #suite.addTest(TestRunner(LDSTTestCase.test_data))
+    #suite.addTest(TestRunner(CRTestCase.test_data))
+    #suite.addTest(TestRunner(ShiftRotTestCase.test_data))
+    #suite.addTest(TestRunner(LogicalTestCase.test_data))
     suite.addTest(TestRunner(ALUTestCase.test_data))
-    suite.addTest(TestRunner(BranchTestCase.test_data))
+    #suite.addTest(TestRunner(BranchTestCase.test_data))
+    #suite.addTest(TestRunner(SPRTestCase.test_data))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)