from soc.decoder.power_enums import Function, XER_bits
-from soc.simple.core import TestIssuer
+from soc.simple.issuer import TestIssuer
from soc.experiment.compalu_multi import find_ok # hack
+from soc.config.test.test_loadstore import TestMemPspec
from soc.simple.test.test_core import (setup_regs, check_regs,
wait_for_busy_clear,
wait_for_busy_hi)
from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
from soc.fu.cr.test.test_pipe_caller import CRTestCase
from soc.fu.branch.test.test_pipe_caller import BranchTestCase
+from soc.fu.spr.test.test_pipe_caller import SPRTestCase
from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
+from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase)
def setup_i_memory(imem, startaddr, instructions):
print ("insn before, init mem", mem.depth, mem.width, mem)
for i in range(mem.depth):
yield mem._array[i].eq(0)
- startaddr //= 4 # assume i-mem is 32-bit wide
+ yield Settle()
+ startaddr //= 4 # instructions are 32-bit
+ mask = ((1<<64)-1)
for insn, code in instructions:
- print ("instr: %06x 0x%x %s" % (4*startaddr, insn, code))
- yield mem._array[startaddr].eq(insn)
+ msbs = (startaddr>>1) & mask
+ val = yield mem._array[msbs]
+ print ("before set", hex(startaddr), hex(msbs), hex(val))
+ lsb = 1 if (startaddr & 1) else 0
+ val = (val | (insn << (lsb*32))) & mask
+ yield mem._array[msbs].eq(val)
+ yield Settle()
+ print ("after set", hex(startaddr), hex(msbs), hex(val))
+ print ("instr: %06x 0x%x %s %08x" % (4*startaddr, insn, code, val))
startaddr += 1
+ startaddr = startaddr & mask
class TestRunner(FHDLTestCase):
go_insn_i = Signal()
pc_i = Signal(32)
- m.submodules.issuer = issuer = TestIssuer()
- imem = issuer.imem.mem
+ pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
+ imem_ifacetype='test_bare_wb',
+ addr_wid=48,
+ mask_wid=8,
+ reg_wid=64)
+ m.submodules.issuer = issuer = TestIssuer(pspec)
+ imem = issuer.imem._get_memory()
core = issuer.core
pdecode2 = core.pdecode2
l0 = core.l0
def process():
for test in self.test_data:
+
+ # get core going
+ yield core.core_start_i.eq(1)
+ yield
+ yield core.core_start_i.eq(0)
+ yield Settle()
+
print(test.name)
program = test.program
self.subTest(test.name)
+ print ("regs", test.regs)
+ print ("sprs", test.sprs)
+ print ("cr", test.cr)
+ print ("mem", test.mem)
+ print ("msr", test.msr)
+ print ("assem", program.assembly)
+ gen = list(program.generate_instructions())
+ insncode = program.assembly.splitlines()
+ instructions = list(zip(gen, insncode))
sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
- test.msr)
- gen = program.generate_instructions()
- instructions = list(zip(gen, program.assembly.splitlines()))
+ test.msr,
+ initial_insns=gen, respect_pc=True,
+ disassembly=insncode)
pc = 0 # start address
ins, code = instructions[index]
print("instruction: 0x{:X}".format(ins & 0xffffffff))
- print(code)
+ print(index, code)
# start the instruction
yield go_insn_i.eq(1)
yield
yield issuer.pc_i.ok.eq(0) # don't change PC from now on
yield go_insn_i.eq(0) # and don't issue a new insn
+ yield Settle()
# wait until executed
yield from wait_for_busy_hi(core)
# call simulated operation
opname = code.split(' ')[0]
yield from sim.call(opname)
+ yield Settle()
index = sim.pc.CIA.value//4
# register check
# Memory check
yield from check_sim_memory(self, l0, sim, code)
- yield
+ terminated = yield core.core_terminated_o
+ if terminated:
+ break
sim.add_sync_process(process)
with sim.write_vcd("issuer_simulator.vcd",
if __name__ == "__main__":
unittest.main(exit=False)
suite = unittest.TestSuite()
+ suite.addTest(TestRunner(AttnTestCase.test_data))
+ #suite.addTest(TestRunner(GeneralTestCases.test_data))
#suite.addTest(TestRunner(LDSTTestCase.test_data))
#suite.addTest(TestRunner(CRTestCase.test_data))
#suite.addTest(TestRunner(ShiftRotTestCase.test_data))
#suite.addTest(TestRunner(LogicalTestCase.test_data))
suite.addTest(TestRunner(ALUTestCase.test_data))
#suite.addTest(TestRunner(BranchTestCase.test_data))
+ #suite.addTest(TestRunner(SPRTestCase.test_data))
runner = unittest.TextTestRunner()
runner.run(suite)
projects / soc.git / blobdiff