Merge remote-tracking branch 'upstream/master' into pr

[soc.git] / src / soc / simple / test / test_issuer_mmu.py

diff --git a/src/soc/simple/test/test_issuer_mmu.py b/src/soc/simple/test/test_issuer_mmu.py
index bafcf3b188cea045d4366fbcb48247307dcb79c0..688de4b16490c79be9422879e23f669c68cacbf5 100644 (file)
--- a/src/soc/simple/test/test_issuer_mmu.py
+++ b/src/soc/simple/test/test_issuer_mmu.py
@@ -22,6 +22,7 @@ from soc.simple.test.test_runner import TestRunner
 from openpower.test.mmu.mmu_cases import MMUTestCase
 from openpower.test.mmu.mmu_rom_cases import MMUTestCaseROM, default_mem
 from openpower.test.ldst.ldst_cases import LDSTTestCase
+from openpower.test.ldst.ldst_exc_cases import LDSTExceptionTestCase
 #from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase)
 
 if __name__ == "__main__":
@@ -37,16 +38,20 @@ if __name__ == "__main__":
     suite = unittest.TestSuite()
     #suite.addTest(TestRunner(GeneralTestCases.test_data, svp64=svp64,
     #                          microwatt_mmu=True))
-    suite.addTest(TestRunner(MMUTestCase().test_data, svp64=svp64,
-                              microwatt_mmu=True))
+    #suite.addTest(TestRunner(MMUTestCase().test_data, svp64=svp64,
+    #                          microwatt_mmu=True))
 
     # without ROM set
-    suite.addTest(TestRunner(MMUTestCaseROM().test_data, svp64=svp64,
-                              microwatt_mmu=True))
+    #suite.addTest(TestRunner(MMUTestCaseROM().test_data, svp64=svp64,
+    #                          microwatt_mmu=True))
 
     # LD/ST tests should all still work
     suite.addTest(TestRunner(LDSTTestCase().test_data, svp64=svp64,
                               microwatt_mmu=True))
 
+    # LD/ST exception cases
+    suite.addTest(TestRunner(LDSTExceptionTestCase().test_data, svp64=svp64,
+                              microwatt_mmu=True))
+
     runner = unittest.TextTestRunner()
     runner.run(suite)