from soc.fu.compunits.test.test_compunit import (setup_test_memory,
check_sim_memory)
from soc.debug.dmi import DBGCore, DBGCtrl, DBGStat
+from nmutil.util import wrap
+from soc.experiment.test.test_mmu_dcache import wb_get
def setup_i_memory(imem, startaddr, instructions):
class TestRunner(FHDLTestCase):
- def __init__(self, tst_data, microwatt_mmu=False, rom=None):
+ def __init__(self, tst_data, microwatt_mmu=False, rom=None,
+ svp64=True):
super().__init__("run_all")
self.test_data = tst_data
self.microwatt_mmu = microwatt_mmu
self.rom = rom
+ self.svp64 = svp64
def run_all(self):
m = Module()
comb = m.d.comb
pc_i = Signal(32)
+ svstate_i = Signal(32)
pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
imem_ifacetype='test_bare_wb',
nocore=False,
xics=False,
gpio=False,
+ regreduce=True,
+ svp64=self.svp64,
mmu=self.microwatt_mmu,
reg_wid=64)
m.submodules.issuer = issuer = TestIssuerInternal(pspec)
dmi = issuer.dbg.dmi
pdecode2 = issuer.pdecode2
l0 = core.l0
+ regreduce_en = pspec.regreduce_en == True
# copy of the decoder for simulator
simdec = create_pdecode()
- simdec2 = PowerDecode2(simdec)
+ simdec2 = PowerDecode2(simdec, regreduce_en=regreduce_en)
m.submodules.simdec2 = simdec2 # pain in the neck
# run core clock at same rate as test clock
comb += intclk.eq(ClockSignal())
comb += issuer.pc_i.data.eq(pc_i)
+ comb += issuer.svstate_i.data.eq(svstate_i)
# nmigen Simulation
sim = Simulator(m)
yield from setup_i_memory(imem, pc, instructions)
yield from setup_test_memory(l0, sim)
yield from setup_regs(pdecode2, core, test)
- # TODO, setup svstate here in core.regs.state regfile
- # https://bugs.libre-soc.org/show_bug.cgi?id=583#c35
- # setup of SVSTATE
- initial_svstate = test.svstate
- if isinstance(initial_svstate, int):
- initial_svstate = SVP64State(initial_svstate)
- svstate_reg = core.regs.state.regs[StateRegs.SVSTATE].reg
- yield svstate_reg.eq(initial_svstate.spr.value)
+ # set PC and SVSTATE
yield pc_i.eq(pc)
yield issuer.pc_i.ok.eq(1)
+
+ initial_svstate = test.svstate
+ if isinstance(initial_svstate, int):
+ initial_svstate = SVP64State(initial_svstate)
+ yield svstate_i.eq(initial_svstate.spr.value)
+ yield issuer.svstate_i.ok.eq(1)
yield
print("instructions", instructions)
yield
yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.START)
yield issuer.pc_i.ok.eq(0) # no change PC after this
+ yield issuer.svstate_i.ok.eq(0) # ditto
yield
yield
counter = counter + 1
# wait until executed
- yield from wait_for_busy_hi(core)
- yield from wait_for_busy_clear(core)
+ while not (yield issuer.insn_done):
+ yield
# set up simulated instruction (in simdec2)
try:
yield
yield
- # wait one cycle for registers to settle
- yield
-
# register check
yield from check_regs(self, sim, core, test, code)
traces = [
'clk',
- {'comment': 'state machines'},
- 'fetch_pc_valid_i', 'fetch_pc_ready_o', 'fetch_fsm_state',
- 'fetch_insn_valid_o', 'fetch_insn_ready_i', 'fsm_state',
+ ('state machines', 'closed', [
+ 'fetch_pc_valid_i', 'fetch_pc_ready_o',
+ 'fetch_fsm_state',
+ 'fetch_insn_valid_o', 'fetch_insn_ready_i',
+ 'pred_insn_valid_i', 'pred_insn_ready_o',
+ 'fetch_predicate_state',
+ 'pred_mask_valid_o', 'pred_mask_ready_i',
+ 'issue_fsm_state',
+ 'exec_insn_valid_i', 'exec_insn_ready_o',
+ 'exec_fsm_state',
+ 'exec_pc_valid_o', 'exec_pc_ready_i',
+ 'insn_done', 'core_stop_o', 'pc_i_ok', 'pc_changed',
+ 'is_last', 'dec2.no_out_vec']),
{'comment': 'fetch and decode'},
- 'cia[63:0]', 'nia[63:0]', 'pc[63:0]', 'raw_insn_i[31:0]',
+ (None, 'dec', [
+ 'cia[63:0]', 'nia[63:0]', 'pc[63:0]',
+ 'cur_pc[63:0]', 'core_core_cia[63:0]']),
+ 'raw_insn_i[31:0]',
'raw_opcode_in[31:0]', 'insn_type',
- {'comment': 'svp64 decoding'},
- 'svp64_rm[23:0]',
- ('dec2.extra[8:0]', 'bin'),
+ ('svp64 decoding', 'closed', [
+ 'svp64_rm[23:0]', ('dec2.extra[8:0]', 'bin'),
+ 'dec2.sv_rm_dec.mode', 'dec2.sv_rm_dec.predmode',
+ 'dec2.sv_rm_dec.ptype_in',
+ 'dec2.sv_rm_dec.dstpred[2:0]', 'dec2.sv_rm_dec.srcpred[2:0]',
+ 'dstmask[63:0]', 'srcmask[63:0]',
+ 'dregread[4:0]', 'dinvert',
+ 'sregread[4:0]', 'sinvert',
+ 'core.int.pred__addr[4:0]', 'core.int.pred__data_o[63:0]',
+ 'core.int.pred__ren']),
('register augmentation', 'dec', 'closed', [
{'comment': 'v3.0b registers'},
'dec2.dec_o.RT[4:0]',
]),
{'comment': 'svp64 context'},
'core_core_vl[6:0]', 'core_core_maxvl[6:0]',
- 'core_core_srcstep[6:0]', 'core_core_dststep[6:0]',
+ 'core_core_srcstep[6:0]', 'next_srcstep[6:0]',
+ 'core_core_dststep[6:0]',
{'comment': 'issue and execute'},
'core.core_core_insn_type',
(None, 'dec', [
{'comment': 'instruction memory'},
'imem.sram.rdport.memory(0)[63:0]',
{'comment': 'registers'},
+ # match with soc.regfile.regfiles.IntRegs port names
'core.int.rp_src1.memory(0)[63:0]',
'core.int.rp_src1.memory(1)[63:0]',
'core.int.rp_src1.memory(2)[63:0]',
projects / soc.git / blobdiff