alter setup_tst_memory to take a test.mem rather than take a Sim object

[soc.git] / src / soc / simple / test / test_runner.py

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index 934736ac6584f1cc7ec027661b7db5e860be0835..e1e572be33ece86c8b9b623dc6e2d613de825487 100644 (file)
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -231,7 +231,7 @@ class TestRunner(FHDLTestCase):
                     counter = 0  # test to pause/start
 
                     yield from setup_i_memory(imem, pc, instructions)
-                    yield from setup_tst_memory(l0, sim)
+                    yield from setup_tst_memory(l0, test.mem)
                     yield from setup_regs(pdecode2, core, test)
 
                     # set PC and SVSTATE