local variable rename in FetchFSM

[soc.git] / src / soc / simple / test / teststate.py

diff --git a/src/soc/simple/test/teststate.py b/src/soc/simple/test/teststate.py
index 3a65c9dc7628f27c72963392c72470e003411777..4fd1ab3b7f0e5dd4fa9fe1461ef907a9cb20701d 100644 (file)
--- a/src/soc/simple/test/teststate.py
+++ b/src/soc/simple/test/teststate.py
@@ -12,6 +12,9 @@ from openpower.test.state import (State, state_add, state_factory,
 from soc.fu.compunits.test.test_compunit import get_l0_mem
 
 class HDLState(State):
+    """HDLState: Obtains registers and memory from an nmigen simulator
+    object by implementing State class methods.
+    """
     def __init__(self, core):
         super().__init__()
         self.core = core
@@ -29,7 +32,7 @@ class HDLState(State):
     def get_crregs(self):
         self.crregs = []
         for i in range(8):
-            rval = yield self.core.regs.cr.regs[i].reg
+            rval = yield self.core.regs.cr.regs[7-i].reg
             self.crregs.append(rval)
         log("class hdl cr regs", list(map(hex, self.crregs)))