move DEC and TB into StateRegs, to make room in FastRegs

[soc.git] / src / soc / simple / test / teststate.py

diff --git a/src/soc/simple/test/teststate.py b/src/soc/simple/test/teststate.py
index 7da358ea7af1c51e7ce46e8635d39ff3a2f7a0a9..95650babfa8817f0e6f7e78060c62bf7674d4701 100644 (file)
--- a/src/soc/simple/test/teststate.py
+++ b/src/soc/simple/test/teststate.py
@@ -54,9 +54,12 @@ class HDLState(State):
         log("class hdl pc", hex(self.pc))
 
     def get_mem(self):
+        self.mem = {}
         # get the underlying HDL-simulated memory from the L0CacheBuffer
+        if hasattr(self.core, "icache"):
+            # err temporarily ignore memory
+            return # XXX have to work out how to deal with wb_get
         hdlmem = get_l0_mem(self.core.l0)
-        self.mem = {}
         for i in range(hdlmem.depth):
             value = yield hdlmem._array[i] # should not really do this
             self.mem[i*8] = value