add srcstep and correct PC-advancing during Sub-PC looping in ISACaller

[soc.git] / src / soc / simulator / qemu.py

diff --git a/src/soc/simulator/qemu.py b/src/soc/simulator/qemu.py
index 747e4a941b23100afe22aae65b4439c708bec201..c4511e122eb85d9bb3d8519d9f2175fc6fdba3eb 100644 (file)
--- a/src/soc/simulator/qemu.py
+++ b/src/soc/simulator/qemu.py
@@ -2,14 +2,20 @@ from pygdbmi.gdbcontroller import GdbController
 import subprocess
 
 launch_args_be = ['qemu-system-ppc64',
-               '-machine', 'powernv9',
-               '-nographic',
-               '-s', '-S']
+                  '-machine', 'powernv9',
+                  '-nographic',
+                  '-s', '-S']
 
 launch_args_le = ['qemu-system-ppc64le',
-               '-machine', 'powernv9',
-               '-nographic',
-               '-s', '-S']
+                  '-machine', 'powernv9',
+                  '-nographic',
+                  '-s', '-S']
+
+
+def swap_order(x, nbytes):
+    x = x.to_bytes(nbytes, byteorder='little')
+    x = int.from_bytes(x, byteorder='big', signed=False)
+    return x
 
 
 class QemuController:
@@ -22,6 +28,7 @@ class QemuController:
                                            stdout=subprocess.PIPE,
                                            stdin=subprocess.PIPE)
         self.gdb = GdbController(gdb_path='powerpc64-linux-gnu-gdb')
+        self.bigendian = bigendian
 
     def __enter__(self):
         return self
@@ -50,16 +57,17 @@ class QemuController:
         return self.gdb.write('-break-delete' + breakstring)
 
     def set_byte(self, addr, v):
-        print ("qemu set byte", hex(addr), hex(v))
+        print("qemu set byte", hex(addr), hex(v))
         faddr = '&{int}0x%x' % addr
         res = self.gdb.write('-data-write-memory-bytes %s "%02x"' % (faddr, v))
-        print ("confirm", self.get_mem(addr, 1))
+        print("confirm", self.get_mem(addr, 1))
 
     def get_mem(self, addr, nbytes):
-        res = self.gdb.write("-data-read-memory %d u 1 1 %d" % (addr, 8*nbytes))
+        res = self.gdb.write("-data-read-memory %d u 1 1 %d" %
+                             (addr, 8*nbytes))
         #print ("get_mem", res)
         for x in res:
-            if(x["type"]=="result"):
+            if(x["type"] == "result"):
                 l = list(map(int, x['payload']['memory'][0]['data']))
                 res = []
                 for j in range(0, len(l), 8):
@@ -75,11 +83,13 @@ class QemuController:
 
     def _get_register(self, fmt):
         res = self.gdb.write('-data-list-register-values '+fmt,
-                             timeout_sec=1.0) # increase this timeout if needed
+                             timeout_sec=1.0)  # increase this timeout if needed
         for x in res:
-            if(x["type"]=="result"):
+            if(x["type"] == "result"):
                 assert 'register-values' in x['payload']
-                return int(x['payload']['register-values'][0]['value'], 0)
+                res = int(x['payload']['register-values'][0]['value'], 0)
+                return res
+                # return swap_order(res, 8)
         return None
 
     # TODO: use -data-list-register-names instead of hardcoding the values
@@ -87,10 +97,11 @@ class QemuController:
     def get_msr(self): return self._get_register('x 65')
     def get_cr(self): return self._get_register('x 66')
     def get_lr(self): return self._get_register('x 67')
-    def get_ctr(self): return self._get_register('x 68') # probably
+    def get_ctr(self): return self._get_register('x 68')  # probably
     def get_xer(self): return self._get_register('x 69')
     def get_fpscr(self): return self._get_register('x 70')
     def get_mq(self): return self._get_register('x 71')
+
     def get_register(self, num):
         return self._get_register('x {}'.format(num))
 
@@ -112,30 +123,30 @@ class QemuController:
 
 
 def run_program(program, initial_mem=None, extra_break_addr=None,
-                         bigendian=False):
+                bigendian=False):
     q = QemuController(program.binfile.name, bigendian)
     q.connect()
-    q.set_endian(True) # easier to set variables this way
+    q.set_endian(True)  # easier to set variables this way
 
     # Run to the start of the program
     if initial_mem:
         for addr, (v, wid) in initial_mem.items():
             for i in range(wid):
-                q.set_byte(addr+i, (v>>i*8) & 0xff)
+                q.set_byte(addr+i, (v >> i*8) & 0xff)
 
     # set breakpoint at start
     q.break_address(0x20000000)
     q.gdb_continue()
     # set the MSR bit 63, to set bigendian/littleendian mode
     msr = q.get_msr()
-    print ("msr", bigendian, hex(msr))
+    print("msr", bigendian, hex(msr))
     if bigendian:
-        msr &= ~(1<<0)
-        msr = msr & ((1<<64)-1)
+        msr &= ~(1 << 0)
+        msr = msr & ((1 << 64)-1)
     else:
-        msr |= (1<<0)
+        msr |= (1 << 0)
     q.gdb_eval('$msr=%d' % msr)
-    print ("msr set to", hex(msr))
+    print("msr set to", hex(msr))
     # set the CR to 0, matching the simulator
     q.gdb_eval('$cr=0')
     # delete the previous breakpoint so loops don't screw things up