radix: reading first page table entry

[soc.git] / src / soc / simulator / test_div_sim.py

diff --git a/src/soc/simulator/test_div_sim.py b/src/soc/simulator/test_div_sim.py
index 610f7f86086faf88678d33d3a89029619ccc6879..171af5c1416e127c5376cfa98afb75599f820b90 100644 (file)
--- a/src/soc/simulator/test_div_sim.py
+++ b/src/soc/simulator/test_div_sim.py
@@ -1,9 +1,9 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, InternalOp,
+from soc.decoder.power_enums import (Function, MicrOp,
                                      In1Sel, In2Sel, In3Sel,
                                      OutSel, RC, LdstLen, CryIn,
                                      single_bit_flags, Form, SPR,
@@ -32,6 +32,22 @@ class DivTestCases(FHDLTestCase):
         with Program(lst) as program:
             self.run_tst_program(program, [1, 2, 3])
 
+    def test_1_divw_(self):
+        lst = ["addi 1, 0, 0x5678",
+               "addi 2, 0, 0x1234",
+               "divw.  3, 1, 2",
+               ]
+        with Program(lst) as program:
+            self.run_tst_program(program, [1, 2, 3])
+
+    def test_2_divw_(self):
+        lst = ["addi 1, 0, 0x1234",
+               "addi 2, 0, 0x5678",
+               "divw.  3, 1, 2",
+               ]
+        with Program(lst) as program:
+            self.run_tst_program(program, [1, 2, 3])
+
     def test_1_divwe(self):
         lst = ["addi 1, 0, 0x5678",
                "addi 2, 0, 0x1234",
@@ -56,6 +72,16 @@ class DivTestCases(FHDLTestCase):
         with Program(lst) as program:
             self.run_tst_program(program, [1, 2, 3])
 
+    def test_5_div_regression(self):
+        lst = ["addi 1, 0, 0x4",
+               "addi 2, 0, 0x2",
+               "neg 2, 2",
+               "neg 1, 1",
+               "divwo  3, 1, 2",
+               ]
+        with Program(lst) as program:
+            self.run_tst_program(program, [1, 2, 3])
+
     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
                                     initial_mem=None):
         initial_regs = [0] * 32