add test_0_moduw and correct name to trunc_rem

[soc.git] / src / soc / simulator / test_div_sim.py

diff --git a/src/soc/simulator/test_div_sim.py b/src/soc/simulator/test_div_sim.py
index b84a10c61a941d5835ea298e852c4c209a2354a3..2129de3338f266dfd31d22856b47528161feaab7 100644 (file)
--- a/src/soc/simulator/test_div_sim.py
+++ b/src/soc/simulator/test_div_sim.py
@@ -32,6 +32,14 @@ class DivTestCases(FHDLTestCase):
         with Program(lst) as program:
             self.run_tst_program(program, [1, 2, 3])
 
+    def test_0_moduw(self):
+        lst = ["addi 1, 0, 0x5678",
+               "addi 2, 0, 0x1234",
+               "moduw  3, 1, 2",
+               ]
+        with Program(lst) as program:
+            self.run_tst_program(program, [1, 2, 3])
+
     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
                                     initial_mem=None):
         initial_regs = [0] * 32