add comments to power decoder

[soc.git] / src / soc / simulator / test_sim.py

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index 1c31075a134411ce8a143fe33d12ea244ebc93d3..0a26380cd996d20f4bd65585bc1bbcea257bd5bc 100644 (file)
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -46,7 +46,7 @@ class DecoderTestCase(FHDLTestCase):
 
         sim.add_process(process)
         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
-                           traces=[pdecode2.ports()]):
+                           traces=pdecode2.ports()):
             sim.run()
 
     def test_example(self):
@@ -97,6 +97,31 @@ class DecoderTestCase(FHDLTestCase):
         with Program(lst) as program:
             self.run_tst_program(program, [1, 2, 3, 4, 5])
 
+    def test_add_with_carry(self):
+        lst = ["addi 1, 0, 5",
+               "neg 1, 1",
+               "addi 2, 0, 7",
+               "neg 2, 2",
+               "addc 3, 2, 1",
+               "addi 3, 3, 1"
+               ]
+        with Program(lst) as program:
+            self.run_tst_program(program, [1, 2, 3])
+
+    def test_addis(self):
+        lst = ["addi 1, 0, 0x0FFF",
+               "addis 1, 1, 0x0F"
+               ]
+        with Program(lst) as program:
+            self.run_tst_program(program, [1])
+
+    def test_mulli(self):
+        lst = ["addi 1, 0, 3",
+               "mulli 1, 1, 2"
+               ]
+        with Program(lst) as program:
+            self.run_tst_program(program, [1])
+
     def run_tst_program(self, prog, reglist):
         simulator = InternalOpSimulator()
         self.run_tst(prog, simulator)