Implement load and store of bytes, halfwords, and words

[soc.git] / src / soc / simulator / test_sim.py

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index 94a9f39aa5bf40d85cbe3eda3d6c32b89c8139b1..210141fdbd1262e5e53a3aebbc3768ac01125a26 100644 (file)
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -104,6 +104,26 @@ class DecoderTestCase(FHDLTestCase):
             {1: 0x1234,
              2: 0x5678,
              3: 0x1234})
+    def test_ldst_widths(self):
+        lst = [" lis 1, 0xdead",
+               "ori 1, 1, 0xbeef",
+               "addi 2, 0, 0x1000",
+               "std 1, 0(2)",
+               "lbz 1, 5(2)",
+               "lhz 3, 4(2)",
+               "lwz 4, 4(2)",
+               "ori 5, 0, 0x12",
+               "stb 5, 5(2)",
+               "ld  5, 0(2)"]
+        gen = InstrList(lst)
+        simulator = InternalOpSimulator()
+        self.run_tst(gen, simulator)
+        simulator.regfile.assert_gprs({
+            1: 0xad,
+            3: 0xdead,
+            4: 0xdeadbeef,
+            5: 0xffffffffde12beef})  # checked with qemu
+
 
 if __name__ == "__main__":
     unittest.main()