update test_sim.py to do a simple execution loop: decode-execute-decode-execute

[soc.git] / src / soc / simulator / test_sim.py

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index 95d5c75ff0b2761ae4845f2e3fd1c8e036442e03..cf213f6941073d8795c314d4127d444e708e4fed 100644 (file)
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -24,34 +24,29 @@ class DecoderTestCase(FHDLTestCase):
     def run_tst(self, generator, initial_mem=None):
         m = Module()
         comb = m.d.comb
-        instruction = Signal(32)
 
-        pdecode = create_pdecode()
+        gen = list(generator.generate_instructions())
+        insn_code = generator.assembly.splitlines()
+        instructions = list(zip(gen, insn_code))
 
+        pdecode = create_pdecode()
         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 
-        simulator = ISA(pdecode2, [0] * 32, {}, 0, initial_mem, 0)
-        comb += pdecode2.dec.raw_opcode_in.eq(instruction)
-        comb += pdecode2.dec.bigendian.eq(0)
-        gen = generator.generate_instructions()
-        instructions = list(zip(gen, generator.assembly.splitlines()))
+        simulator = ISA(pdecode2, [0] * 32, {}, 0, initial_mem, 0,
+                        initial_insns=gen, respect_pc=True,
+                        disassembly=insn_code)
 
         sim = Simulator(m)
-        def process():
-
-            index = simulator.pc.CIA.value//4
-            while index < len(instructions):
-                ins, code = instructions[index]
 
-                print("0x{:X}".format(ins & 0xffffffff))
-                print(code)
-
-                yield instruction.eq(ins)
-                yield Delay(1e-6)
-
-                opname = code.split(' ')[0]
-                yield from simulator.call(opname)
-                index = simulator.pc.CIA.value//4
+        def process():
+            while True:
+                try:
+                    yield from simulator.setup_one()
+                except KeyError: # indicates instruction not in imem: stop
+                    break
+                yield Settle()
+                yield from simulator.execute_one()
+                yield Settle()
 
 
         sim.add_process(process)