improve debug for test_sim.py

[soc.git] / src / soc / simulator / test_sim.py

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index a619ba1bd39c533bebfad9b6d7512db5a2be8b3c..e6b09667da10fe77f0eaf49c28ab066b0296f00a 100644 (file)
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -255,7 +255,7 @@ class DecoderBase:
         prog.reset()
         with run_program(prog, initial_mem) as q:
             self.qemu_register_compare(simulator, q, reglist)
-            self.qemu_mem_compare(simulator, q, reglist)
+            self.qemu_mem_compare(simulator, q, True)
         print(simulator.gpr.dump())
 
     def qemu_mem_compare(self, sim, qemu, check=True):
@@ -294,7 +294,8 @@ class DecoderBase:
         for reg in regs:
             qemu_val = qemu.get_register(reg)
             sim_val = sim.gpr(reg).value
-            self.assertEqual(qemu_val, sim_val)
+            self.assertEqual(qemu_val, sim_val,
+                             "expect %x got %x" % (qemu_val, sim_val))
 
 
 class DecoderTestCase(DecoderBase, GeneralTestCases):