improve debug for test_sim.py

[soc.git] / src / soc / simulator / test_sim.py

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index cf213f6941073d8795c314d4127d444e708e4fed..e6b09667da10fe77f0eaf49c28ab066b0296f00a 100644 (file)
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -12,6 +12,7 @@ from soc.decoder.power_decoder2 import (PowerDecode2)
 from soc.simulator.program import Program
 from soc.simulator.qemu import run_program
 from soc.decoder.isa.all import ISA
+from soc.fu.test.common import TestCase
 
 
 class Register:
@@ -19,42 +20,12 @@ class Register:
         self.num = num
 
 
-class DecoderTestCase(FHDLTestCase):
+class GeneralTestCases(FHDLTestCase):
+    test_data = []
 
-    def run_tst(self, generator, initial_mem=None):
-        m = Module()
-        comb = m.d.comb
-
-        gen = list(generator.generate_instructions())
-        insn_code = generator.assembly.splitlines()
-        instructions = list(zip(gen, insn_code))
-
-        pdecode = create_pdecode()
-        m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
-
-        simulator = ISA(pdecode2, [0] * 32, {}, 0, initial_mem, 0,
-                        initial_insns=gen, respect_pc=True,
-                        disassembly=insn_code)
-
-        sim = Simulator(m)
-
-        def process():
-            while True:
-                try:
-                    yield from simulator.setup_one()
-                except KeyError: # indicates instruction not in imem: stop
-                    break
-                yield Settle()
-                yield from simulator.execute_one()
-                yield Settle()
-
-
-        sim.add_process(process)
-        with sim.write_vcd("simulator.vcd", "simulator.gtkw",
-                           traces=[]):
-            sim.run()
-
-        return simulator
+    def __init__(self, name="general"):
+        super().__init__(name)
+        self.test_name = name
 
     @unittest.skip("disable")
     def test_0_cmp(self):
@@ -173,7 +144,8 @@ class DecoderTestCase(FHDLTestCase):
         with Program(lst) as program:
             self.run_tst_program(program, [1])
 
-    def tst_2_load_store(self):
+    @unittest.skip("disable")
+    def test_2_load_store(self):
         lst = ["addi 1, 0, 0x1004",
                "addi 2, 0, 0x1008",
                "addi 3, 0, 0x00ee",
@@ -227,13 +199,63 @@ class DecoderTestCase(FHDLTestCase):
         with Program(lst) as program:
             self.run_tst_program(program, [9], initial_mem={})
 
+    def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
+                                    initial_mem=None):
+        initial_regs = [0] * 32
+        tc = TestCase(prog, self.test_name, initial_regs, initial_sprs, 0,
+                                            initial_mem, 0)
+        self.test_data.append(tc)
+
+
+class DecoderBase:
+
+    def run_tst(self, generator, initial_mem=None, initial_pc=0):
+        m = Module()
+        comb = m.d.comb
+
+        gen = list(generator.generate_instructions())
+        insn_code = generator.assembly.splitlines()
+        instructions = list(zip(gen, insn_code))
+
+        pdecode = create_pdecode()
+        m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
+
+        # place program at requested address
+        gen = (initial_pc, gen)
+
+        simulator = ISA(pdecode2, [0] * 32, {}, 0, initial_mem, 0,
+                        initial_insns=gen, respect_pc=True,
+                        disassembly=insn_code,
+                        initial_pc=initial_pc)
+
+        sim = Simulator(m)
+
+        def process():
+            while True:
+                try:
+                    yield from simulator.setup_one()
+                except KeyError: # indicates instruction not in imem: stop
+                    break
+                yield Settle()
+                yield from simulator.execute_one()
+                yield Settle()
+
+
+        sim.add_process(process)
+        with sim.write_vcd("simulator.vcd", "simulator.gtkw",
+                           traces=[]):
+            sim.run()
+
+        return simulator
+
     def run_tst_program(self, prog, reglist, initial_mem=None):
         import sys
-        simulator = self.run_tst(prog, initial_mem=initial_mem)
+        simulator = self.run_tst(prog, initial_mem=initial_mem,
+                                 initial_pc=0x20000000)
         prog.reset()
         with run_program(prog, initial_mem) as q:
             self.qemu_register_compare(simulator, q, reglist)
-            self.qemu_mem_compare(simulator, q, reglist)
+            self.qemu_mem_compare(simulator, q, True)
         print(simulator.gpr.dump())
 
     def qemu_mem_compare(self, sim, qemu, check=True):
@@ -263,14 +285,21 @@ class DecoderTestCase(FHDLTestCase):
         print("qemu pc", hex(qpc))
         print("qemu cr", hex(qcr))
         print("qemu xer", bin(qxer))
+        print("sim nia", hex(sim.pc.NIA.value))
         print("sim pc", hex(sim.pc.CIA.value))
         print("sim cr", hex(sim_cr))
         print("sim xer", hex(sim_xer))
         self.assertEqual(qcr, sim_cr)
+        self.assertEqual(qpc, sim_pc)
         for reg in regs:
             qemu_val = qemu.get_register(reg)
             sim_val = sim.gpr(reg).value
-            self.assertEqual(qemu_val, sim_val)
+            self.assertEqual(qemu_val, sim_val,
+                             "expect %x got %x" % (qemu_val, sim_val))
+
+
+class DecoderTestCase(DecoderBase, GeneralTestCases):
+    pass
 
 
 if __name__ == "__main__":