rename InternalOp to MicrOp

[soc.git] / src / soc / simulator / test_trap_sim.py

diff --git a/src/soc/simulator/test_trap_sim.py b/src/soc/simulator/test_trap_sim.py
index dfb4faa277281f67018da30e3460f82d5175abc6..d535cf1a76695443d27ccd5fc96c256073b9b887 100644 (file)
--- a/src/soc/simulator/test_trap_sim.py
+++ b/src/soc/simulator/test_trap_sim.py
@@ -3,7 +3,7 @@ from nmigen.back.pysim import Simulator, Delay, Settle
 from nmigen.test.utils import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, InternalOp,
+from soc.decoder.power_enums import (Function, MicrOp,
                                      In1Sel, In2Sel, In3Sel,
                                      OutSel, RC, LdstLen, CryIn,
                                      single_bit_flags, Form, SPR,