move svp64 reg-decode function to more appropriate location

[soc.git] / src / soc / sv / trans / svp64.py

diff --git a/src/soc/sv/trans/svp64.py b/src/soc/sv/trans/svp64.py
index 2e54f708580d6bcfd123c57a6403d14e7249c775..746fa563f9f8d2a9ba24d53a2636d054a1e3f352 100644 (file)
--- a/src/soc/sv/trans/svp64.py
+++ b/src/soc/sv/trans/svp64.py
@@ -18,27 +18,9 @@ import os, sys
 from collections import OrderedDict
 
 from soc.decoder.pseudo.pagereader import ISA
-from soc.decoder.power_svp64 import SVP64RM
+from soc.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
 
 
-# identifies register by type
-def is_CR_3bit(regname):
-    return regname in ['BF', 'BFA']
-
-def is_CR_5bit(regname):
-    return regname in ['BA', 'BB', 'BC', 'BI', 'BT']
-
-def is_GPR(regname):
-    return regname in ['RA', 'RB', 'RC', 'RS', 'RT']
-
-def get_regtype(regname):
-    if is_CR_3bit(regname):
-        return "CR_3bit"
-    if is_CR_5bit(regname):
-        return "CR_5bit"
-    if is_GPR(regname):
-        return "GPR"
-
 # decode GPR into sv extra
 def  get_extra_gpr(etype, regmode, field):
     if regmode == 'scalar':
@@ -129,7 +111,6 @@ def decode_ffirst(encoding):
     return decode_bo(encoding)
 
 
-
 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
 class SVP64:
     def __init__(self, lst):
@@ -189,27 +170,11 @@ class SVP64:
             # which position in the RM EXTRA it goes into
             # also: record if the src or dest was a CR, for sanity-checking
             # (elwidth overrides on CRs are banned)
-            dest_reg_cr, src_reg_cr = False, False
+            decode = decode_extra(rm)
+            dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
             svp64_reg_byname = {}
-            for i in range(4):
-                rfield = rm[str(i)]
-                if not rfield or rfield == '0':
-                    continue
-                print ("EXTRA field", i, rfield)
-                rfield = rfield.split(";") # s:RA;d:CR1 etc.
-                for r in rfield:
-                    rtype = r[0]
-                    # TODO: ignoring s/d makes it impossible to do
-                    # LD/ST-with-update.
-                    r = r[2:] # ignore s: and d:
-                    svp64_reg_byname[r] = i # this reg in EXTRA position 0-3
-                    # check the regtype (if CR, record that)
-                    regtype = get_regtype(r)
-                    if regtype in ['CR_3bit', 'CR_5bit']:
-                        if rtype == 'd':
-                            dest_reg_cr = True
-                        if rtype == 'd':
-                            src_reg_cr = True
+            svp64_reg_byname.update(svp64_src)
+            svp64_reg_byname.update(svp64_dest)
 
             print ("EXTRA field index, by regname", svp64_reg_byname)