pass through MSR.PR through PortInterface, into LoadStore1
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 11 May 2021 10:59:45 +0000 (11:59 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 11 May 2021 10:59:45 +0000 (11:59 +0100)
commit32cd87d73afd7e1f6e68bab5d1efdbe85764e122
tree2278c69a02efca401427e83003eba92f44ee3a46
parenta9b4d828401b6784881143905bc12b727f6ff4a5
pass through MSR.PR through PortInterface, into LoadStore1
src/soc/experiment/pi2ls.py
src/soc/experiment/pimem.py
src/soc/experiment/test/test_l0_cache_buffer2.py
src/soc/experiment/test/test_mmu_dcache_pi.py
src/soc/fu/ldst/loadstore.py