fix some borked imports

diff --git a/src/ieee754/add/test_inputgroup.py b/src/ieee754/add/test_inputgroup.py
index 96de216fc6c8c32bb45c2091f45f5502e96b478b..b487043983d02dc9161c9c2064d3b1d7d101683e 100644 (file)
--- a/src/ieee754/add/test_inputgroup.py
+++ b/src/ieee754/add/test_inputgroup.py
@@ -3,7 +3,7 @@ from nmigen import Module, Signal
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
-from inputgroup import InputGroup
+from ieee754.add.inputgroup import InputGroup
 
 
 def testbench(dut):

diff --git a/src/ieee754/add/test_state_add.py b/src/ieee754/add/test_state_add.py
index e38e3e666d75eaa59514a08d97a28d065fc575db..0d9500929fbe158d27e3f514ec366477255b8ce6 100644 (file)
--- a/src/ieee754/add/test_state_add.py
+++ b/src/ieee754/add/test_state_add.py
@@ -5,12 +5,13 @@ from operator import add
 from nmigen import Module, Signal
 from nmigen.compat.sim import run_simulation
 
-from fadd_state import FPADD
+from ieee754.fpadd.fadd_state import FPADD
 
-from unit_test_single import (get_mantissa, get_exponent, get_sign, is_nan,
-                                is_inf, is_pos_inf, is_neg_inf,
-                                match, get_case, check_case, run_fpunit,
-                                run_edge_cases, run_corner_cases)
+from ieee754.fpcommon.test.unit_test_single import (
+    get_mantissa, get_exponent, get_sign, is_nan,
+    is_inf, is_pos_inf, is_neg_inf,
+    match, get_case, check_case, run_fpunit,
+    run_edge_cases, run_corner_cases)
 
 def testbench(dut):
     yield from check_case(dut, 0xFFFFFFFF, 0xC63B800A, 0xFFC00000)

diff --git a/src/ieee754/add/test_syncops.py b/src/ieee754/add/test_syncops.py
index 484597ca9058cb1998047636b80e003f16fe9f05..2c9bbaa800c48168c50672813d7c9395c5c9ec29 100644 (file)
--- a/src/ieee754/add/test_syncops.py
+++ b/src/ieee754/add/test_syncops.py
@@ -3,7 +3,7 @@ from nmigen import Module, Signal
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog
 
-from inputgroup import FPGetSyncOpsMod
+from ieee754.add.inputgroup import FPGetSyncOpsMod
 
 
 def testbench(dut):

diff --git a/src/ieee754/cordic/test/test_fp_pipe.py b/src/ieee754/cordic/test/test_fp_pipe.py
index db8c7a178c026f1bc77681bbaf133da41fee9344..05c667e717da1cfef37c625dd91ddd60ff2f1f73 100644 (file)
--- a/src/ieee754/cordic/test/test_fp_pipe.py
+++ b/src/ieee754/cordic/test/test_fp_pipe.py
@@ -1,6 +1,6 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Passive
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 from sfpy import Float32
 

diff --git a/src/ieee754/cordic/test/test_fpsin_cos.py b/src/ieee754/cordic/test/test_fpsin_cos.py
index a98db72d3011e53ec4ea23dd9f6d437889c6a618..993e202aaa8acf6493e00104162cf1c69392c5f6 100644 (file)
--- a/src/ieee754/cordic/test/test_fpsin_cos.py
+++ b/src/ieee754/cordic/test/test_fpsin_cos.py
@@ -1,6 +1,6 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 
 from ieee754.cordic.fpsin_cos import CORDIC
 from ieee754.fpcommon.fpbase import FPNumBaseRecord

diff --git a/src/ieee754/cordic/test/test_sincos.py b/src/ieee754/cordic/test/test_sincos.py
index f565b1ce0228b97ad6a678db295b4bc8c88614b6..1fb27f7dcc137b6c24dce0a5606f50be4ce486bc 100644 (file)
--- a/src/ieee754/cordic/test/test_sincos.py
+++ b/src/ieee754/cordic/test/test_sincos.py
@@ -1,6 +1,6 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 
 from ieee754.cordic.sin_cos import CORDIC
 from python_sin_cos import run_cordic

diff --git a/src/ieee754/fpcmp/formal/proof_fpcmp_mod.py b/src/ieee754/fpcmp/formal/proof_fpcmp_mod.py
index 4f3d273ebbff4ea2c5133134383600d14e8c2683..efc2c7b7396921b930a9981ed0ee0d344f0f08d8 100644 (file)
--- a/src/ieee754/fpcmp/formal/proof_fpcmp_mod.py
+++ b/src/ieee754/fpcmp/formal/proof_fpcmp_mod.py
@@ -3,7 +3,7 @@
 
 from nmigen import Module, Signal, Elaboratable, Mux
 from nmigen.asserts import Assert, AnyConst
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 
 from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
 from ieee754.fpcmp.fpcmp import FPCMPPipeMod

diff --git a/src/ieee754/fpmax/formal/proof_fmax_mod.py b/src/ieee754/fpmax/formal/proof_fmax_mod.py
index 700811963a89b4608d87b2d34791d392ddb60d6d..2ca7d407a217b326c7a0bfafdc0b64f0c099f82d 100644 (file)
--- a/src/ieee754/fpmax/formal/proof_fmax_mod.py
+++ b/src/ieee754/fpmax/formal/proof_fmax_mod.py
@@ -3,7 +3,7 @@
 
 from nmigen import Module, Signal, Elaboratable, Mux
 from nmigen.asserts import Assert, AnyConst
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 
 from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
 from ieee754.fpmax.fpmax import FPMAXPipeMod

diff --git a/src/ieee754/fpmul/fmul.py b/src/ieee754/fpmul/fmul.py
index d775671c7f685a7be8d56c240a55f77096611995..dd525b0e17b9ce4c870f3c2773422f52248c9987 100644 (file)
--- a/src/ieee754/fpmul/fmul.py
+++ b/src/ieee754/fpmul/fmul.py
@@ -3,7 +3,7 @@ from nmigen.cli import main, verilog
 
 from ieee754.fpcommon.fpbase import (FPNumIn, FPNumOut, FPOpIn,
                                      FPOpOut, Overflow, FPBase, FPState)
-from ieee754.fpcommon.getop import FPGetOp
+#from ieee754.fpcommon.getop import FPGetOp
 from nmutil.nmoperator import eq
 
 

diff --git a/src/ieee754/fpmul/test/test_mul64.py b/src/ieee754/fpmul/test/test_mul64.py
index 5f8eb305122abef76bbb094f448cf876df83b04e..93d624065eedbeee59ef1951a9d7863499171fde 100644 (file)
--- a/src/ieee754/fpmul/test/test_mul64.py
+++ b/src/ieee754/fpmul/test/test_mul64.py
@@ -2,18 +2,18 @@ from nmigen import Module, Signal
 from nmigen.compat.sim import run_simulation
 from operator import mul
 
-from fmul import FPMUL
+from ieee754.fpmul.fmul import FPMUL
 
 import sys
 import atexit
 from random import randint
 from random import seed
 
-from unit_test_double import (get_mantissa, get_exponent, get_sign, is_nan,
-                                is_inf, is_pos_inf, is_neg_inf,
-                                match, get_case, check_case, run_fpunit,
-                                run_edge_cases, run_corner_cases)
-
+from ieee754.fpcommon.test.unit_test_double import (
+    get_mantissa, get_exponent, get_sign, is_nan,
+    is_inf, is_pos_inf, is_neg_inf,
+    match, get_case, check_case, run_fpunit,
+    run_edge_cases, run_corner_cases)
 
 def testbench(dut):
     yield from check_case(dut, 0, 0, 0)

diff --git a/src/ieee754/fsgnj/formal/proof_fsgnj_mod.py b/src/ieee754/fsgnj/formal/proof_fsgnj_mod.py
index b960a85c111c0caee39b99eded831d86b02903ad..2a744bdfa918096c50c23a23bc0e792d3f411a46 100644 (file)
--- a/src/ieee754/fsgnj/formal/proof_fsgnj_mod.py
+++ b/src/ieee754/fsgnj/formal/proof_fsgnj_mod.py
@@ -3,7 +3,7 @@
 
 from nmigen import Module, Signal, Elaboratable
 from nmigen.asserts import Assert, Assume
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 
 from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
 from ieee754.fsgnj.fsgnj import FSGNJPipeMod

diff --git a/src/ieee754/part_cmp/experiments/formal/proof_eq.py b/src/ieee754/part_cmp/experiments/formal/proof_eq.py
index 80fd7f1d80c5836f1acb61986e0de50756e2abf6..e692956e9c82066e7cb4e32329ffe6d22c7a8fb1 100644 (file)
--- a/src/ieee754/part_cmp/experiments/formal/proof_eq.py
+++ b/src/ieee754/part_cmp/experiments/formal/proof_eq.py
@@ -3,7 +3,7 @@
 
 from nmigen import Module, Signal, Elaboratable, Mux
 from nmigen.asserts import Assert, AnyConst
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 
 from ieee754.part_cmp.experiments.eq_combiner import EQCombiner

diff --git a/src/ieee754/part_cmp/experiments/formal/proof_equal.py b/src/ieee754/part_cmp/experiments/formal/proof_equal.py
index 441a4c7badeae524e7f3663986abf58825ec42a9..e21b1745565dd7d6b313a8fbe0bbaea1ac6c1c73 100644 (file)
--- a/src/ieee754/part_cmp/experiments/formal/proof_equal.py
+++ b/src/ieee754/part_cmp/experiments/formal/proof_equal.py
@@ -3,7 +3,7 @@
 
 from nmigen import Module, Signal, Elaboratable, Mux
 from nmigen.asserts import Assert, AnyConst, Assume
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 
 from ieee754.part_mul_add.partpoints import PartitionPoints

diff --git a/src/ieee754/part_cmp/formal/proof_eq_gt_ge.py b/src/ieee754/part_cmp/formal/proof_eq_gt_ge.py
index 13c42343664b838fd6c6928931733a1c6fcbcdd0..4ad359d5ad5f0b2f2e512ac41243870dc100e0f2 100644 (file)
--- a/src/ieee754/part_cmp/formal/proof_eq_gt_ge.py
+++ b/src/ieee754/part_cmp/formal/proof_eq_gt_ge.py
@@ -3,7 +3,7 @@
 
 from nmigen import Module, Signal, Elaboratable, Mux, Cat
 from nmigen.asserts import Assert, AnyConst, Assume
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 
 from ieee754.part_mul_add.partpoints import PartitionPoints

diff --git a/src/ieee754/part_cmp/formal/proof_gt.py b/src/ieee754/part_cmp/formal/proof_gt.py
index a64eca0faedce56950115961656ac9b2ceab19f2..366f2f87ec99a63d23abacf5636b487f677886bb 100644 (file)
--- a/src/ieee754/part_cmp/formal/proof_gt.py
+++ b/src/ieee754/part_cmp/formal/proof_gt.py
@@ -3,7 +3,7 @@
 
 from nmigen import Module, Signal, Elaboratable, Mux
 from nmigen.asserts import Assert, AnyConst, Assume
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 
 from ieee754.part_cmp.gt_combiner import GTCombiner

diff --git a/src/ieee754/part_shift/formal/proof_shift_dynamic.py b/src/ieee754/part_shift/formal/proof_shift_dynamic.py
index 9c16076227819790c0bc68d275ffcf5af5c46702..f5bdc2564b239bf39fbce79875c60c5e1b47954d 100644 (file)
--- a/src/ieee754/part_shift/formal/proof_shift_dynamic.py
+++ b/src/ieee754/part_shift/formal/proof_shift_dynamic.py
@@ -3,7 +3,7 @@
 
 from nmigen import Module, Signal, Elaboratable, Mux, Cat
 from nmigen.asserts import Assert, AnyConst
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 
 from ieee754.part_mul_add.partpoints import PartitionPoints

diff --git a/src/ieee754/part_shift/formal/proof_shift_scalar.py b/src/ieee754/part_shift/formal/proof_shift_scalar.py
index 7c0d7593d1eb1ac564b08ce328f5659708453321..5f0666f8938339c8e4ea5c5bfd468d6b2fb6c50c 100644 (file)
--- a/src/ieee754/part_shift/formal/proof_shift_scalar.py
+++ b/src/ieee754/part_shift/formal/proof_shift_scalar.py
@@ -3,7 +3,7 @@
 
 from nmigen import Module, Signal, Elaboratable, Mux, Cat
 from nmigen.asserts import Assert, AnyConst, Assume
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 
 from ieee754.part_mul_add.partpoints import PartitionPoints

diff --git a/src/ieee754/part_shift/test/test_shift_dynamic.py b/src/ieee754/part_shift/test/test_shift_dynamic.py
index 86db976cac0bb8977fecbc8bac8ad52bf4b516b9..fac0ff1a5dc390d7f5555c0b9bcebeb852b25c93 100644 (file)
--- a/src/ieee754/part_shift/test/test_shift_dynamic.py
+++ b/src/ieee754/part_shift/test/test_shift_dynamic.py
@@ -1,6 +1,6 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 from ieee754.part_mul_add.partpoints import PartitionPoints
 
 from ieee754.part_shift.part_shift_dynamic import \

diff --git a/src/ieee754/part_shift/test/test_shift_scalar.py b/src/ieee754/part_shift/test/test_shift_scalar.py
index 579e1dc6c4ff5fd59f41a53da2d59e9f971f05b6..6d2640a8854a516a651d6e55a7a2e419d1edfdb4 100644 (file)
--- a/src/ieee754/part_shift/test/test_shift_scalar.py
+++ b/src/ieee754/part_shift/test/test_shift_scalar.py
@@ -1,6 +1,6 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 from ieee754.part_mul_add.partpoints import PartitionPoints
 
 from ieee754.part_shift.part_shift_scalar import \