f565b1ce0228b97ad6a678db295b4bc8c88614b6
[ieee754fpu.git] / src / ieee754 / cordic / test / test_sincos.py
1 from nmigen import Module, Signal
2 from nmigen.back.pysim import Simulator, Delay
3 from nmigen.test.utils import FHDLTestCase
4
5 from ieee754.cordic.sin_cos import CORDIC
6 from python_sin_cos import run_cordic
7 import unittest
8 import math
9 import random
10
11
12 class SinCosTestCase(FHDLTestCase):
13 def run_test(self, zin=0, fracbits=8, expected_sin=0, expected_cos=0):
14
15 m = Module()
16
17 m.submodules.dut = dut = CORDIC(fracbits)
18 z = Signal(dut.z0.shape())
19 start = Signal()
20
21 sin = Signal(dut.sin.shape())
22 cos = Signal(dut.cos.shape())
23 ready = Signal()
24
25 m.d.comb += [
26 dut.z0.eq(z),
27 dut.start.eq(start),
28 sin.eq(dut.sin),
29 cos.eq(dut.cos),
30 ready.eq(dut.ready)]
31
32 sim = Simulator(m)
33 sim.add_clock(1e-6)
34
35 def process():
36 yield z.eq(zin)
37 yield start.eq(1)
38
39 yield
40 yield start.eq(0)
41 yield
42 for i in range(fracbits + 5):
43 rdy = yield ready
44 if rdy == 1:
45 result = yield sin
46 msg = "sin: {}, expected {}".format(result, expected_sin)
47 assert result == expected_sin, msg
48 result = yield cos
49 msg = "cos: {}, expected {}".format(result, expected_cos)
50 assert result == expected_cos, msg
51 else:
52 yield
53
54 sim.add_sync_process(process)
55 with sim.write_vcd("sin_cos.vcd", "sin_cos.gtkw", traces=[
56 z, cos, sin, ready, start]):
57 sim.run()
58
59 def run_test_assert(self, z, fracbits=8):
60 (sin, cos) = run_cordic(z, fracbits=fracbits, log=False)
61 self.run_test(zin=z, fracbits=fracbits,
62 expected_sin=sin, expected_cos=cos)
63
64 def test_0(self):
65 self.run_test_assert(0)
66
67 def test_neg(self):
68 self.run_test_assert(-6)
69
70 def test_rand(self):
71 fracbits = 16
72 M = (1 << fracbits)
73 ZMAX = int(round(M * math.pi/2))
74 for i in range(500):
75 z = random.randrange(-ZMAX, ZMAX-1)
76 self.run_test_assert(z, fracbits=fracbits)
77
78
79 if __name__ == "__main__":
80 unittest.main()