src/ieee754/part_shift/test/test_shift_dynamic.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from ieee754.part_mul_add.partpoints import PartitionPoints
   5
   6 from ieee754.part_shift.part_shift_dynamic import \
   7     PartitionedDynamicShift
   8
   9 import unittest
  10
  11 class DynamicShiftTestCase(FHDLTestCase):
  12     def get_intervals(self, signal, points):
  13         start = 0
  14         interval = []
  15         keys = list(points.keys()) + [signal.width]
  16         for key in keys:
  17             end = key
  18             interval.append(signal[start:end])
  19             start = end
  20         return interval
  21
  22     def test_dynamic(self):
  23         m = Module()
  24         comb = m.d.comb
  25         mwidth = 4
  26         width = 32
  27         step = int(width/mwidth)
  28         gates = Signal(mwidth-1)
  29         points = PartitionPoints()
  30         for i in range(mwidth-1):
  31             points[(i+1)*step] = gates[i]
  32         a = Signal(width)
  33         b = Signal(width)
  34         output = Signal(width)
  35         a_intervals = self.get_intervals(a, points)
  36         b_intervals = self.get_intervals(b, points)
  37         output_intervals = self.get_intervals(output, points)
  38
  39         m.submodules.dut = dut = PartitionedDynamicShift(width, points)
  40         comb += [dut.a.eq(a),
  41                  dut.b.eq(b),
  42                  output.eq(dut.output)]
  43
  44         sim = Simulator(m)
  45         def process():
  46             yield a.eq(0x01010101)
  47             yield b.eq(0x04030201)
  48             for i in range(1<<(mwidth-1)):
  49                 yield gates.eq(i)
  50                 yield Delay(1e-6)
  51                 yield Settle()
  52             yield b.eq(0x0c0b0a09)
  53             for i in range(1<<(mwidth-1)):
  54                 yield gates.eq(i)
  55                 yield Delay(1e-6)
  56                 yield Settle()
  57             yield gates.eq(1)
  58             yield Delay(1e-6)
  59             yield Settle()
  60             yield gates.eq(0)
  61             yield Delay(1e-6)
  62             yield Settle()
  63
  64
  65         sim.add_process(process)
  66         with sim.write_vcd("test.vcd", "test.gtkw", traces=[a,b,output]):
  67             sim.run()
  68
  69 if __name__ == "__main__":
  70     unittest.main()
  71
  72
  73
  74