self.num_rows = num_rows
self.mmax = int(log(self.num_rows) / log(2))
self.rs = []
- self.mid = Signal(self.mmax, reset_less=True) # multiplex id
+ self.muxid = Signal(self.mmax, reset_less=True) # multiplex id
for i in range(num_rows):
self.rs.append(FPGetSyncOpsMod(width, num_ops))
self.rs = Array(self.rs)
# encoder active: ack relevant input, record MID, pass output
with m.If(out_en):
rs = self.rs[pe.o]
- m.d.sync += self.mid.eq(pe.o)
+ m.d.sync += self.muxid.eq(pe.o)
m.d.sync += rs.ack.eq(0)
m.d.sync += self.out_op.stb.eq(0)
for j in range(self.num_ops):
for i in range(self.num_rows):
inop = self.rs[i]
res += inop.in_op + [inop.stb]
- return self.out_op.ports() + res + [self.mid]
+ return self.out_op.ports() + res + [self.muxid]
# output strobe should be active, MID should be 0 until "ack" is set...
out_stb = yield dut.out_op.stb
assert out_stb == 1
- out_mid = yield dut.mid
- assert out_mid == 0
+ out_muxid = yield dut.muxid
+ assert out_muxid == 0
# ... and output should not yet be passed through either
op0 = yield dut.out_op.v[0]
op0 = yield dut.out_op.v[0]
op1 = yield dut.out_op.v[1]
assert op0 == 3 and op1 == 4, "op0 %d op1 %d" % (op0, op1)
- out_mid = yield dut.mid
- assert out_mid == 2
+ out_muxid = yield dut.muxid
+ assert out_muxid == 2
# set row 0 and 3 input
yield dut.rs[0].in_op[0].eq(9)
yield
yield dut.rs[0].stb.eq(0) # clear row 1 strobe
yield
- out_mid = yield dut.mid
- assert out_mid == 0, "out mid %d" % out_mid
+ out_muxid = yield dut.muxid
+ assert out_muxid == 0, "out muxid %d" % out_muxid
yield
yield dut.rs[3].stb.eq(0) # clear row 1 strobe
yield dut.out_op.ack.eq(0) # clear ack on output
yield
- out_mid = yield dut.mid
- assert out_mid == 3, "out mid %d" % out_mid
+ out_muxid = yield dut.muxid
+ assert out_muxid == 3, "out muxid %d" % out_muxid
class InputTest:
self.di = {}
self.do = {}
self.tlen = 10
- for mid in range(dut.num_rows):
- self.di[mid] = {}
- self.do[mid] = {}
+ for muxid in range(dut.num_rows):
+ self.di[muxid] = {}
+ self.do[muxid] = {}
for i in range(self.tlen):
- self.di[mid][i] = randint(0, 100)
- self.do[mid][i] = self.di[mid][i]
+ self.di[muxid][i] = randint(0, 100)
+ self.do[muxid][i] = self.di[muxid][i]
- def send(self, mid):
+ def send(self, muxid):
for i in range(self.tlen):
- op2 = self.di[mid][i]
- rs = dut.rs[mid]
+ op2 = self.di[muxid][i]
+ rs = dut.rs[muxid]
ack = yield rs.ack
while not ack:
yield
while stb:
yield
stb = yield dut.out_op.stb
- mid = yield dut.mid
+ muxid = yield dut.muxid
out_i = yield dut.out_op.v[0]
out_v = yield dut.out_op.v[1]
# see if this output has occurred already, delete it if it has
- assert out_i in self.do[mid]
- assert self.do[mid][out_i] == out_v
- del self.do[mid][out_i]
+ assert out_i in self.do[muxid]
+ assert self.do[muxid][out_i] == out_v
+ del self.do[muxid][out_i]
# check if there's any more outputs
zerolen = True
self.oz = Signal(width, reset_less=True)
self.tot = Signal(self.z.m_width + 4, reset_less=True)
self.ctx = FPBaseData(width, pspec)
- self.mid = self.ctx.mid
+ self.muxid = self.ctx.muxid
def eq(self, i):
return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
self.out_do_z = Signal(reset_less=True)
self.oz = Signal(width, reset_less=True)
self.ctx = FPBaseData(width, pspec)
- self.mid = self.ctx.mid
+ self.muxid = self.ctx.muxid
def eq(self, i):
return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
def __init__(self, width, id_wid):
self.z = FPOpOut(width)
self.z.data_o = Signal(width)
- self.mid = Signal(id_wid, reset_less=True)
+ self.muxid = Signal(id_wid, reset_less=True)
def __iter__(self):
yield self.z
- yield self.mid
+ yield self.muxid
def eq(self, i):
- return [self.z.eq(i.z), self.mid.eq(i.mid)]
+ return [self.z.eq(i.z), self.muxid.eq(i.mid)]
def ports(self):
return list(self)
self.oz = Signal(width, reset_less=True) # "finished" (bypass) result
self.out_do_z = Signal(reset_less=True) # "bypass" enabled
self.ctx = FPBaseData(width, pspec)
- self.mid = self.ctx.mid
+ self.muxid = self.ctx.muxid
def __iter__(self):
yield from self.a
def __init__(self, width, id_wid, m_extra=True):
self.a = FPNumBase(width, m_extra)
self.b = FPNumBase(width, m_extra)
- self.mid = Signal(id_wid, reset_less=True)
+ self.muxid = Signal(id_wid, reset_less=True)
def eq(self, i):
- return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
+ return [self.a.eq(i.a), self.b.eq(i.b), self.muxid.eq(i.muxid)]
def ports(self):
- return [self.a, self.b, self.mid]
+ return [self.a, self.b, self.muxid]
class FPBaseData:
print (pspec)
self.id_wid = pspec['id_wid']
self.op_wid = pspec.get('op_wid', 0)
- self.mid = Signal(self.id_wid, reset_less=True) # RS multiplex ID
+ self.muxid = Signal(self.id_wid, reset_less=True) # RS multiplex ID
self.op = Signal(self.op_wid, reset_less=True)
def eq(self, i):
- ret = [self.mid.eq(i.mid)]
+ ret = [self.muxid.eq(i.muxid)]
if self.op_wid:
ret.append(self.op.eq(i.op))
return ret
def __iter__(self):
- yield self.mid
+ yield self.muxid
if self.op_wid:
yield self.op
operand = Signal(width, name=name)
setattr(self, name, operand)
ops.append(operand)
- self.mid = self.ctx.mid # make muxid available here: complicated
+ self.muxid = self.ctx.muxid # make muxid available here: complicated
self.ops = ops
def eq(self, i):
Object.__init__(self)
self.z = Signal(width, reset_less=True) # result
self.ctx = FPBaseData(width, pspec)
- self.mid = self.ctx.mid
+ self.muxid = self.ctx.muxid
class FPPackMod(Elaboratable):
self.oz = Signal(width, reset_less=True)
self.of = Overflow()
self.ctx = FPBaseData(width, pspec)
- self.mid = self.ctx.mid
+ self.muxid = self.ctx.muxid
def __iter__(self):
yield from self.z
self.out_do_z = Signal(reset_less=True)
self.oz = Signal(width, reset_less=True)
self.ctx = FPBaseData(width, pspec)
- self.mid = self.ctx.mid
+ self.muxid = self.ctx.muxid
def eq(self, i):
ret = [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
def __init__(self, width, pspec):
self.z = FPNumBaseRecord(width, False)
self.ctx = FPBaseData(width, pspec)
- self.mid = self.ctx.mid
+ self.muxid = self.ctx.muxid
# pipeline bypass [data comes from specialcases]
self.out_do_z = Signal(reset_less=True)
self.oz = Signal(width, reset_less=True)
self.do = {}
self.tlen = 10
self.width = width
- for mid in range(dut.num_rows):
- self.di[mid] = {}
- self.do[mid] = []
+ for muxid in range(dut.num_rows):
+ self.di[muxid] = {}
+ self.do[muxid] = []
for i in range(self.tlen):
op1 = randint(0, (1<<self.width)-1)
op2 = randint(0, (1<<self.width)-1)
#op1 = 0x40900000
#op2 = 0x40200000
res = self.fpop(self.fpkls(op1), self.fpkls(op2))
- self.di[mid][i] = (op1, op2)
- self.do[mid].append(res.bits)
+ self.di[muxid][i] = (op1, op2)
+ self.do[muxid].append(res.bits)
- def send(self, mid):
+ def send(self, muxid):
for i in range(self.tlen):
- op1, op2 = self.di[mid][i]
- rs = self.dut.p[mid]
+ op1, op2 = self.di[muxid][i]
+ rs = self.dut.p[muxid]
yield rs.valid_i.eq(1)
yield rs.data_i.a.eq(op1)
yield rs.data_i.b.eq(op2)
- yield rs.data_i.mid.eq(mid)
+ yield rs.data_i.muxid.eq(muxid)
yield
o_p_ready = yield rs.ready_o
while not o_p_ready:
fop1 = self.fpkls(op1)
fop2 = self.fpkls(op2)
res = self.fpop(fop1, fop2)
- print ("send", mid, i, hex(op1), hex(op2), hex(res.bits),
+ print ("send", muxid, i, hex(op1), hex(op2), hex(res.bits),
fop1, fop2, res)
yield rs.valid_i.eq(0)
yield rs.valid_i.eq(0)
yield
- print ("send ended", mid)
+ print ("send ended", muxid)
## wait random period of time before queueing another value
#for i in range(randint(0, 3)):
#else:
# send = randint(0, send_range) != 0
- def rcv(self, mid):
+ def rcv(self, muxid):
while True:
#stall_range = randint(0, 3)
#for j in range(randint(1,10)):
# stall = randint(0, stall_range) != 0
# yield self.dut.n[0].ready_i.eq(stall)
# yield
- n = self.dut.n[mid]
+ n = self.dut.n[muxid]
yield n.ready_i.eq(1)
yield
o_n_valid = yield n.valid_o
if not o_n_valid or not i_n_ready:
continue
- out_mid = yield n.data_o.mid
+ out_muxid = yield n.data_o.muxid
out_z = yield n.data_o.z
out_i = 0
- print ("recv", out_mid, hex(out_z), "expected",
- hex(self.do[mid][out_i] ))
+ print ("recv", out_muxid, hex(out_z), "expected",
+ hex(self.do[muxid][out_i] ))
# see if this output has occurred already, delete it if it has
- assert mid == out_mid, "out_mid %d not correct %d" % (out_mid, mid)
- assert self.do[mid][out_i] == out_z
- del self.do[mid][out_i]
+ assert muxid == out_muxid, "out_muxid %d not correct %d" % \
+ (out_muxid, muxid)
+ assert self.do[muxid][out_i] == out_z
+ del self.do[muxid][out_i]
# check if there's any more outputs
- if len(self.do[mid]) == 0:
+ if len(self.do[muxid]) == 0:
break
- print ("recv ended", mid)
+ print ("recv ended", muxid)
def runfp(dut, width, name, fpkls, fpop):
self.of = Overflow()
self.ctx = FPBaseData(width, pspec) # context: muxid, operator etc.
- self.mid = self.ctx.mid # annoying. complicated.
+ self.muxid = self.ctx.muxid # annoying. complicated.
# TODO: here is where Q and R would be put, and passed
# down to Stage1 processing.
mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
self.product = Signal(mw, reset_less=True)
self.ctx = FPBaseData(width, pspec)
- self.mid = self.ctx.mid
+ self.muxid = self.ctx.muxid
def eq(self, i):
return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
self.stage.setup(m, r_data)
# multiplexer id taken from n_mux
- mid = self.n_mux.m_id
+ muxid = self.n_mux.m_id
print ("self.n_mux", self.n_mux)
print ("self.n_mux.m_id", self.n_mux.m_id)
# the only output "active" is then selected by the muxid
for i in range(len(self.n)):
m.d.comb += self.n[i].valid_o.eq(0)
- data_valid = self.n[mid].valid_o
- m.d.comb += self.p.ready_o.eq(~data_valid | self.n[mid].ready_i)
+ data_valid = self.n[muxid].valid_o
+ m.d.comb += self.p.ready_o.eq(~data_valid | self.n[muxid].ready_i)
m.d.comb += data_valid.eq(p_valid_i | \
- (~self.n[mid].ready_i & data_valid))
+ (~self.n[muxid].ready_i & data_valid))
with m.If(pv):
m.d.comb += eq(r_data, self.p.data_i)
- m.d.comb += eq(self.n[mid].data_o, self.process(r_data))
+ m.d.comb += eq(self.n[muxid].data_o, self.process(r_data))
return m
# HACK: stage is also the n-way multiplexer
CombMultiOutPipeline.__init__(self, stage, n_len=n_len, n_mux=stage)
- # HACK: n-mux is also the stage... so set the muxid equal to input mid
- print ("combmuxout", self.p.data_i.mid)
- stage.m_id = self.p.data_i.mid
+ # HACK: n-mux is also the stage... so set the muxid equal to input muxid
+ print ("combmuxout", self.p.data_i.muxid)
+ stage.m_id = self.p.data_i.muxid
class PassData2(RecordObject):
def __init__(self):
RecordObject.__init__(self)
- self.mid = Signal(2, reset_less=True)
+ self.muxid = Signal(2, reset_less=True)
self.idx = Signal(8, reset_less=True)
self.data = Signal(16, reset_less=True)
class PassData(Object):
def __init__(self):
Object.__init__(self)
- self.mid = Signal(2, reset_less=True)
+ self.muxid = Signal(2, reset_less=True)
self.idx = Signal(8, reset_less=True)
self.data = Signal(16, reset_less=True)
self.di = {}
self.do = {}
self.tlen = 100
- for mid in range(dut.num_rows):
- self.di[mid] = {}
- self.do[mid] = {}
+ for muxid in range(dut.num_rows):
+ self.di[muxid] = {}
+ self.do[muxid] = {}
for i in range(self.tlen):
- self.di[mid][i] = randint(0, 255) + (mid<<8)
- self.do[mid][i] = self.di[mid][i]
+ self.di[muxid][i] = randint(0, 255) + (muxid<<8)
+ self.do[muxid][i] = self.di[muxid][i]
- def send(self, mid):
+ def send(self, muxid):
for i in range(self.tlen):
- op2 = self.di[mid][i]
- rs = self.dut.p[mid]
+ op2 = self.di[muxid][i]
+ rs = self.dut.p[muxid]
yield rs.valid_i.eq(1)
yield rs.data_i.data.eq(op2)
yield rs.data_i.idx.eq(i)
- yield rs.data_i.mid.eq(mid)
+ yield rs.data_i.muxid.eq(muxid)
yield
o_p_ready = yield rs.ready_o
while not o_p_ready:
yield
o_p_ready = yield rs.ready_o
- print ("send", mid, i, hex(op2))
+ print ("send", muxid, i, hex(op2))
yield rs.valid_i.eq(0)
# wait random period of time before queueing another value
yield rs.valid_i.eq(0)
yield
- print ("send ended", mid)
+ print ("send ended", muxid)
## wait random period of time before queueing another value
#for i in range(randint(0, 3)):
#else:
# send = randint(0, send_range) != 0
- def rcv(self, mid):
+ def rcv(self, muxid):
while True:
#stall_range = randint(0, 3)
#for j in range(randint(1,10)):
# stall = randint(0, stall_range) != 0
# yield self.dut.n[0].ready_i.eq(stall)
# yield
- n = self.dut.n[mid]
+ n = self.dut.n[muxid]
yield n.ready_i.eq(1)
yield
o_n_valid = yield n.valid_o
if not o_n_valid or not i_n_ready:
continue
- out_mid = yield n.data_o.mid
+ out_muxid = yield n.data_o.muxid
out_i = yield n.data_o.idx
out_v = yield n.data_o.data
- print ("recv", out_mid, out_i, hex(out_v))
+ print ("recv", out_muxid, out_i, hex(out_v))
# see if this output has occurred already, delete it if it has
- assert mid == out_mid, "out_mid %d not correct %d" % (out_mid, mid)
- assert out_i in self.do[mid], "out_i %d not in array %s" % \
- (out_i, repr(self.do[mid]))
- assert self.do[mid][out_i] == out_v # pass-through data
- del self.do[mid][out_i]
+ assert muxid == out_muxid, "out_muxid %d not correct %d" % (out_muxid, muxid)
+ assert out_i in self.do[muxid], "out_i %d not in array %s" % \
+ (out_i, repr(self.do[muxid]))
+ assert self.do[muxid][out_i] == out_v # pass-through data
+ del self.do[muxid][out_i]
# check if there's any more outputs
- if len(self.do[mid]) == 0:
+ if len(self.do[muxid]) == 0:
break
- print ("recv ended", mid)
+ print ("recv ended", muxid)
class TestPriorityMuxPipe(PriorityCombMuxInPipe):
self.tlen = 100
for i in range(self.tlen * dut.num_rows):
if i < dut.num_rows:
- mid = i
+ muxid = i
else:
- mid = randint(0, dut.num_rows-1)
- data = randint(0, 255) + (mid<<8)
+ muxid = randint(0, dut.num_rows-1)
+ data = randint(0, 255) + (muxid<<8)
def send(self):
for i in range(self.tlen * dut.num_rows):
op2 = self.di[i][0]
- mid = self.di[i][1]
+ muxid = self.di[i][1]
rs = dut.p
yield rs.valid_i.eq(1)
yield rs.data_i.data.eq(op2)
- yield rs.data_i.mid.eq(mid)
+ yield rs.data_i.muxid.eq(muxid)
yield
o_p_ready = yield rs.ready_o
while not o_p_ready:
yield
o_p_ready = yield rs.ready_o
- print ("send", mid, i, hex(op2))
+ print ("send", muxid, i, hex(op2))
yield rs.valid_i.eq(0)
# wait random period of time before queueing another value
class PassInData(RecordObject):
def __init__(self):
RecordObject.__init__(self)
- self.mid = Signal(2, reset_less=True)
+ self.muxid = Signal(2, reset_less=True)
self.data = Signal(16, reset_less=True)
self.tlen = 10
for i in range(self.tlen * dut.num_rows):
if i < dut.num_rows:
- mid = i
+ muxid = i
else:
- mid = randint(0, dut.num_rows-1)
- data = randint(0, 255) + (mid<<8)
- if mid not in self.do:
- self.do[mid] = []
- self.di.append((data, mid))
- self.do[mid].append(data)
+ muxid = randint(0, dut.num_rows-1)
+ data = randint(0, 255) + (muxid<<8)
+ if muxid not in self.do:
+ self.do[muxid] = []
+ self.di.append((data, muxid))
+ self.do[muxid].append(data)
def send(self):
for i in range(self.tlen * self.dut.num_rows):
op2 = self.di[i][0]
- mid = self.di[i][1]
+ muxid = self.di[i][1]
rs = self.dut.p
yield rs.valid_i.eq(1)
yield rs.data_i.data.eq(op2)
- yield rs.data_i.mid.eq(mid)
+ yield rs.data_i.muxid.eq(muxid)
yield
o_p_ready = yield rs.ready_o
while not o_p_ready:
yield
o_p_ready = yield rs.ready_o
- print ("send", mid, i, hex(op2))
+ print ("send", muxid, i, hex(op2))
yield rs.valid_i.eq(0)
# wait random period of time before queueing another value
yield rs.valid_i.eq(0)
- def rcv(self, mid):
+ def rcv(self, muxid):
out_i = 0
count = 0
stall_range = randint(0, 3)
- while out_i != len(self.do[mid]):
+ while out_i != len(self.do[muxid]):
count += 1
assert count != 2000, "timeout: too long"
- n = self.dut.n[mid]
+ n = self.dut.n[muxid]
yield n.ready_i.eq(1)
yield
o_n_valid = yield n.valid_o
out_v = yield n.data_o
- print ("recv", mid, out_i, hex(out_v))
+ print ("recv", muxid, out_i, hex(out_v))
- assert self.do[mid][out_i] == out_v # pass-through data
+ assert self.do[muxid][out_i] == out_v # pass-through data
out_i += 1
class PassData:
def __init__(self):
- self.mid = Signal(2, reset_less=True)
+ self.muxid = Signal(2, reset_less=True)
self.idx = Signal(6, reset_less=True)
self.data = Signal(16, reset_less=True)
def eq(self, i):
- return [self.mid.eq(i.mid), self.idx.eq(i.idx), self.data.eq(i.data)]
+ return [self.muxid.eq(i.muxid), self.idx.eq(i.idx), self.data.eq(i.data)]
def ports(self):
- return [self.mid, self.idx, self.data]
+ return [self.muxid, self.idx, self.data]
def tbench(dut):
# output strobe should be active, MID should be 0 until "ack" is set...
out_stb = yield dut.out_op.stb
assert out_stb == 1
- out_mid = yield dut.mid
- assert out_mid == 0
+ out_muxid = yield dut.muxid
+ assert out_muxid == 0
# ... and output should not yet be passed through either
op0 = yield dut.out_op.v[0]
op0 = yield dut.out_op.v[0]
op1 = yield dut.out_op.v[1]
assert op0 == 3 and op1 == 4, "op0 %d op1 %d" % (op0, op1)
- out_mid = yield dut.mid
- assert out_mid == 2
+ out_muxid = yield dut.muxid
+ assert out_muxid == 2
# set row 0 and 3 input
yield dut.rs[0].in_op[0].eq(9)
yield
yield dut.rs[0].stb.eq(0) # clear row 1 strobe
yield
- out_mid = yield dut.mid
- assert out_mid == 0, "out mid %d" % out_mid
+ out_muxid = yield dut.muxid
+ assert out_muxid == 0, "out muxid %d" % out_muxid
yield
yield dut.rs[3].stb.eq(0) # clear row 1 strobe
yield dut.out_op.ack.eq(0) # clear ack on output
yield
- out_mid = yield dut.mid
- assert out_mid == 3, "out mid %d" % out_mid
+ out_muxid = yield dut.muxid
+ assert out_muxid == 3, "out muxid %d" % out_muxid
class InputTest:
self.di = {}
self.do = {}
self.tlen = 10
- for mid in range(dut.num_rows):
- self.di[mid] = {}
- self.do[mid] = {}
+ for muxid in range(dut.num_rows):
+ self.di[muxid] = {}
+ self.do[muxid] = {}
for i in range(self.tlen):
- self.di[mid][i] = randint(0, 100) + (mid<<8)
- self.do[mid][i] = self.di[mid][i]
+ self.di[muxid][i] = randint(0, 100) + (muxid<<8)
+ self.do[muxid][i] = self.di[muxid][i]
- def send(self, mid):
+ def send(self, muxid):
for i in range(self.tlen):
- op2 = self.di[mid][i]
- rs = self.dut.p[mid]
+ op2 = self.di[muxid][i]
+ rs = self.dut.p[muxid]
yield rs.valid_i.eq(1)
yield rs.data_i.data.eq(op2)
yield rs.data_i.idx.eq(i)
- yield rs.data_i.mid.eq(mid)
+ yield rs.data_i.muxid.eq(muxid)
yield
o_p_ready = yield rs.ready_o
while not o_p_ready:
yield
o_p_ready = yield rs.ready_o
- print ("send", mid, i, hex(op2))
+ print ("send", muxid, i, hex(op2))
yield rs.valid_i.eq(0)
# wait random period of time before queueing another value
if not o_n_valid or not i_n_ready:
continue
- mid = yield n.data_o.mid
+ muxid = yield n.data_o.muxid
out_i = yield n.data_o.idx
out_v = yield n.data_o.data
- print ("recv", mid, out_i, hex(out_v))
+ print ("recv", muxid, out_i, hex(out_v))
# see if this output has occurred already, delete it if it has
- assert out_i in self.do[mid], "out_i %d not in array %s" % \
- (out_i, repr(self.do[mid]))
- assert self.do[mid][out_i] == out_v # pass-through data
- del self.do[mid][out_i]
+ assert out_i in self.do[muxid], "out_i %d not in array %s" % \
+ (out_i, repr(self.do[muxid]))
+ assert self.do[muxid][out_i] == out_v # pass-through data
+ del self.do[muxid][out_i]
# check if there's any more outputs
zerolen = True
projects / ieee754fpu.git / commitdiff