Make all ports the same size, on the test ALU

The old regspec API can't cope with different port sizes.
The CR port is now changed from 3 to "width" bits (16).
The problem was that cr.ok went into the fourth bit, messing with
the results.

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index a780dd86357e4c5cb1fc75148d38911b509bf380..76d8e22126d21e06c2da58e774a6befb7504bc34 100644 (file)
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -198,7 +198,7 @@ class ALU(Elaboratable):
         self.a, self.b = i[0], i[1]
         out = []
         out.append(Data(width, name="alu_o"))
-        out.append(Data(3, name="alu_cr"))
+        out.append(Data(width, name="alu_cr"))
         self.out = Array(out)
         self.o = self.out[0]
         self.cr = self.out[1]

diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py
index f6635c320fc213b68bdacdc9669d531b0e14362e..ae4f819983e37ee1bfe048c4a5de734e202730ec 100644 (file)
--- a/src/soc/experiment/test/test_compalu_multi.py
+++ b/src/soc/experiment/test/test_compalu_multi.py
@@ -724,7 +724,7 @@ def test_compunit_regspec1():
     inspec = [('INT', 'a', '0:15'),
               ('INT', 'b', '0:15')]
     outspec = [('INT', 'o', '0:15'),
-               ('INT', 'cr', '0:2')]
+               ('INT', 'cr', '0:15')]
 
     regspec = (inspec, outspec)