Update to new privileged ISA

diff --git a/env b/env
index f3545105d54ab746efac58b96e998a252cafd16b..9c4e0839779f302720173ad063fa25366cef21f7 160000 (submodule)
--- a/env
+++ b/env
@@ -1 +1 @@
-Subproject commit f3545105d54ab746efac58b96e998a252cafd16b
+Subproject commit 9c4e0839779f302720173ad063fa25366cef21f7

diff --git a/isa/macros/scalar/test_macros.h b/isa/macros/scalar/test_macros.h
index b856701824d0de37e20d9ada602bb2be22ff52f6..10680d47b9fd64be17a7b358e4b0216af4fc8551 100644 (file)
--- a/isa/macros/scalar/test_macros.h
+++ b/isa/macros/scalar/test_macros.h
@@ -46,23 +46,25 @@ pass_ ## testnum: \
 # Tests for instructions with immediate operand
 #-----------------------------------------------------------------------
 
+#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
+
 #define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
     TEST_CASE( testnum, x3, result, \
       li  x1, val1; \
-      inst x3, x1, imm; \
+      inst x3, x1, SEXT_IMM(imm); \
     )
 
 #define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
     TEST_CASE( testnum, x1, result, \
       li  x1, val1; \
-      inst x1, x1, imm; \
+      inst x1, x1, SEXT_IMM(imm); \
     )
 
 #define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
     TEST_CASE( testnum, x6, result, \
       li  x4, 0; \
 1:    li  x1, val1; \
-      inst x3, x1, imm; \
+      inst x3, x1, SEXT_IMM(imm); \
       TEST_INSERT_NOPS_ ## nop_cycles \
       addi  x6, x3, 0; \
       addi  x4, x4, 1; \
@@ -75,7 +77,7 @@ pass_ ## testnum: \
       li  x4, 0; \
 1:    li  x1, val1; \
       TEST_INSERT_NOPS_ ## nop_cycles \
-      inst x3, x1, imm; \
+      inst x3, x1, SEXT_IMM(imm); \
       addi  x4, x4, 1; \
       li  x5, 2; \
       bne x4, x5, 1b \
@@ -83,13 +85,13 @@ pass_ ## testnum: \
 
 #define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
     TEST_CASE( testnum, x1, result, \
-      inst x1, x0, imm; \
+      inst x1, x0, SEXT_IMM(imm); \
     )
 
 #define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
     TEST_CASE( testnum, x0, 0, \
       li  x1, val1; \
-      inst x0, x1, imm; \
+      inst x0, x1, SEXT_IMM(imm); \
     )
 
 #-----------------------------------------------------------------------
@@ -563,9 +565,9 @@ test_ ## testnum: \
 #-----------------------------------------------------------------------
 
 #define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2) \
-  setpcr status, SR_EI; \
+  csrs status, SR_EI; \
   la a0, handler ## testnum; \
-  mtpcr a0, evec; \
+  csrw evec, a0; \
   vsetcfg nxreg, nfreg; \
   li a0, 4; \
   vsetvl a0, a0; \
@@ -624,9 +626,9 @@ handler ## testnum: \
   bne a1,a2,fail; \
 
 #define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \
-  setpcr status, SR_EI; \
+  csrs status, SR_EI; \
   la a0, handler ## testnum; \
-  mtpcr a0, evec; \
+  csrw evec, a0; \
   vsetcfg nxreg, nfreg; \
   li a0, 4; \
   vsetvl a0, a0; \

diff --git a/isa/macros/vector/test_macros.h b/isa/macros/vector/test_macros.h
index 59e9e77bcb1a250fa66cc8ce401cb827d328c372..932aba3c4affeeaa95eb8c6dc1aac44148906b18 100644 (file)
--- a/isa/macros/vector/test_macros.h
+++ b/isa/macros/vector/test_macros.h
@@ -64,22 +64,24 @@ next ## testnum :
 # Tests for instructions with immediate operand
 #-----------------------------------------------------------------------
 
+#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
+
 #define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
       li  x1, val1; \
-      inst x3, x1, imm; \
+      inst x3, x1, SEXT_IMM(imm); \
     )
 
 #define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
     TEST_CASE_NREG( testnum, 2, 0, x1, result, \
       li  x1, val1; \
-      inst x1, x1, imm; \
+      inst x1, x1, SEXT_IMM(imm); \
     )
 
 #define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
     TEST_CASE_NREG( testnum, 5, 0, x4, result, \
       li  x1, val1; \
-      inst x3, x1, imm; \
+      inst x3, x1, SEXT_IMM(imm); \
       TEST_INSERT_NOPS_ ## nop_cycles \
       addi  x4, x3, 0; \
     )
@@ -88,18 +90,18 @@ next ## testnum :
     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
       li  x1, val1; \
       TEST_INSERT_NOPS_ ## nop_cycles \
-      inst x3, x1, imm; \
+      inst x3, x1, SEXT_IMM(imm); \
     )
 
 #define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
     TEST_CASE_NREG( testnum, 2, 0, x1, result, \
-      inst x1, x0, imm; \
+      inst x1, x0, SEXT_IMM(imm); \
     )
 
 #define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
     TEST_CASE_NREG( testnum, 2, 0, x0, 0, \
       li  x1, val1; \
-      inst x0, x1, imm; \
+      inst x0, x1, SEXT_IMM(imm); \
     )
 
 #-----------------------------------------------------------------------

diff --git a/isa/rv64si/coreid.S b/isa/rv64si/coreid.S
index 47336db5d9fa23bfe2ed240657bf2a995d196f98..ed33f117cf49c86bcc62e6b39b094e9d9a79284a 100644 (file)
--- a/isa/rv64si/coreid.S
+++ b/isa/rv64si/coreid.S
@@ -15,7 +15,7 @@ RVTEST_CODE_BEGIN
   # Basic tests
   #-------------------------------------------------------------
 
-  TEST_CASE( 2, x1, 0x0, mfpcr x1, hartid );
+  TEST_CASE( 2, x1, 0x0, csrr x1, hartid );
 
   TEST_PASSFAIL
 

diff --git a/isa/rv64si/ipi.S b/isa/rv64si/ipi.S
index 8db016369aeb87aac96c959c7f501e25c2d5b72d..95a108a8f3922f15ceeb9a929642d92be753baba 100644 (file)
--- a/isa/rv64si/ipi.S
+++ b/isa/rv64si/ipi.S
@@ -13,12 +13,12 @@ RVTEST_CODE_BEGIN
 
   # clear pending IPIs then enable interrupts
   la a0, handler
-  mtpcr a0, evec
-  mtpcr x0, clear_ipi
-  mfpcr a0, status
+  csrw evec, a0
+  csrw clear_ipi, x0
+  csrr a0, status
   li a1, SR_EI | (1 << (IRQ_IPI + SR_IM_SHIFT))
   or a0, a0, a1
-  mtpcr a0, status
+  csrw status, a0
 
   # wait for all cores to boot
   la a0, coreid
@@ -29,15 +29,15 @@ RVTEST_CODE_BEGIN
   blt a1, a3, 1b
 
   # IPI dominoes
-  mfpcr a0, hartid
+  csrr a0, hartid
   1: bnez a0, 1b
   add a0, a0, 1
   rem a0, a0, a3
-  mtpcr a0, send_ipi
+  csrw send_ipi, a0
   1: b 1b
 
   handler:
-  mfpcr a0, hartid
+  csrr a0, hartid
   bnez a0, 2f
   RVTEST_PASS
 
@@ -45,7 +45,7 @@ RVTEST_CODE_BEGIN
 
   2: add a0, a0, 1
   rem a0, a0, a3
-  mtpcr a0, send_ipi
+  csrw send_ipi, a0
   1: b 1b
 
 RVTEST_CODE_END

diff --git a/isa/rv64sv/illegal_cfg_nfpr.S b/isa/rv64sv/illegal_cfg_nfpr.S
index 2440cbbf745e9a8fa85988cc134c55a828829855..a636a3605f768bf87d3a03a5f679eec40bc93ef1 100644 (file)
--- a/isa/rv64sv/illegal_cfg_nfpr.S
+++ b/isa/rv64sv/illegal_cfg_nfpr.S
@@ -11,17 +11,17 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  setpcr status, SR_EA # enable accelerator
-  setpcr status, SR_EI # enable interrupt
+  li a0, SR_EA | SR_EI
+  csrs status, a0
 
   la a3,handler
-  mtpcr a3,evec # set exception handler
+  csrw evec,a3 # set exception handler
 
-  mfpcr a3,status
+  csrr a3,status
   li a4,(1 << IRQ_COP)
   slli a4,a4,SR_IM_SHIFT
   or a3,a3,a4 # enable IM[COP]
-  mtpcr a3,status
+  csrw status,a3
 
   li a0,33
   slli a0,a0,6

diff --git a/isa/rv64sv/illegal_cfg_nxpr.S b/isa/rv64sv/illegal_cfg_nxpr.S
index c61d4d9f2c1976fdbc3274ac92a4e6796428ae79..e6190c9c99bad4160351136d3e91992dcaa3f348 100644 (file)
--- a/isa/rv64sv/illegal_cfg_nxpr.S
+++ b/isa/rv64sv/illegal_cfg_nxpr.S
@@ -11,17 +11,17 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  setpcr status, SR_EA # enable accelerator
-  setpcr status, SR_EI # enable interrupt
+  li a0, SR_EA | SR_EI
+  csrs status, a0
 
   la a3,handler
-  mtpcr a3,evec # set exception handler
+  csrw evec,a3 # set exception handler
 
-  mfpcr a3,status
+  csrr a3,status
   li a4,(1 << IRQ_COP)
   slli a4,a4,SR_IM_SHIFT
   or a3,a3,a4 # enable IM[COP]
-  mtpcr a3,status
+  csrw status,a3
 
   li a0,33
   vsetcfg a0

diff --git a/isa/rv64sv/illegal_inst.S b/isa/rv64sv/illegal_inst.S
index ff8cee10b142abdaddc0ac523fdbb2400a66cd72..c16086e919747f29f524c8ee74ceb5642f5d811f 100644 (file)
--- a/isa/rv64sv/illegal_inst.S
+++ b/isa/rv64sv/illegal_inst.S
@@ -11,17 +11,17 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  setpcr status, SR_EA # enable accelerator
-  setpcr status, SR_EI # enable interrupt
+  li a0, SR_EA | SR_EI
+  csrs status, a0
 
   la a3,handler
-  mtpcr a3,evec # set exception handler
+  csrw evec,a3 # set exception handler
 
-  mfpcr a3,status
+  csrr a3,status
   li a4,(1 << IRQ_COP)
   slli a4,a4,SR_IM_SHIFT
   or a3,a3,a4 # enable IM[COP]
-  mtpcr a3,status
+  csrw status,a3
 
   .word 0xff00002b
 

diff --git a/isa/rv64sv/illegal_tvec_regid.S b/isa/rv64sv/illegal_tvec_regid.S
index 4cfa1e0c3cc5122d9ee93515c03f706834f0081f..70a6c27a6e3d92927b2f3f597535000333b4b65d 100644 (file)
--- a/isa/rv64sv/illegal_tvec_regid.S
+++ b/isa/rv64sv/illegal_tvec_regid.S
@@ -11,13 +11,14 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  setpcr status, SR_EA # enable accelerator
+  li a0, SR_EA
+  csrs status, a0
 
-  mfpcr a3,status
+  csrr a3,status
   li a4,(1 << IRQ_COP)
   slli a4,a4,SR_IM_SHIFT
   or a3,a3,a4 # enable IM[COP]
-  mtpcr a3,status
+  csrw status,a3
 
   TEST_ILLEGAL_TVEC_REGID(2, 5, 5, vsd, vx7, a2)
   TEST_ILLEGAL_TVEC_REGID(3, 5, 5, vld, vx7, a2)

diff --git a/isa/rv64sv/illegal_vt_inst.S b/isa/rv64sv/illegal_vt_inst.S
index 9bb586b5190f098e37208ea34f83ba00cb9adbb2..ce4fe82bf8a49ec3a0d35215838822f896c1f442 100644 (file)
--- a/isa/rv64sv/illegal_vt_inst.S
+++ b/isa/rv64sv/illegal_vt_inst.S
@@ -11,17 +11,17 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  setpcr status, SR_EA # enable accelerator
-  setpcr status, SR_EI # enable interrupt
+  li a0, SR_EA | SR_EI
+  csrs status, a0
 
   la a3,handler
-  mtpcr a3,evec # set exception handler
+  csrw evec,a3 # set exception handler
 
-  mfpcr a3,status
+  csrr a3,status
   li a4,(1 << IRQ_COP)
   slli a4,a4,SR_IM_SHIFT
   or a3,a3,a4 # enable IM[COP]
-  mtpcr a3,status
+  csrw status,a3
 
   vsetcfg 32,0
   li a3,4

diff --git a/isa/rv64sv/illegal_vt_regid.S b/isa/rv64sv/illegal_vt_regid.S
index 120facc9c5b39c6fb09eb4428e15cf21739516c5..df8aeefeb6663b6394348558a1790cb0563ceef2 100644 (file)
--- a/isa/rv64sv/illegal_vt_regid.S
+++ b/isa/rv64sv/illegal_vt_regid.S
@@ -11,13 +11,14 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  setpcr status, SR_EA # enable accelerator
+  li a0, SR_EA
+  csrs status, a0
 
-  mfpcr a3,status
+  csrr a3,status
   li a4,(1 << IRQ_COP)
   slli a4,a4,SR_IM_SHIFT
   or a3,a3,a4 # enable IM[COP]
-  mtpcr a3,status
+  csrw status,a3
 
   TEST_ILLEGAL_VT_REGID(2, 5, 5, add, x7, x1, x2)
   TEST_ILLEGAL_VT_REGID(3, 5, 5, add, x1, x7, x2)

diff --git a/isa/rv64sv/ma_utld.S b/isa/rv64sv/ma_utld.S
index aff6e1ae27cc9ad0c27f89b1e50933a0ec033808..c48e134df4fed3b6b0c94e372857d705be632d3a 100644 (file)
--- a/isa/rv64sv/ma_utld.S
+++ b/isa/rv64sv/ma_utld.S
@@ -11,17 +11,17 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  setpcr status, SR_EA # enable accelerator
-  setpcr status, SR_EI # enable interrupt
+  li a0, SR_EA | SR_EI
+  csrs status, a0
 
   la a3,handler
-  mtpcr a3,evec # set exception handler
+  csrw evec,a3 # set exception handler
 
-  mfpcr a3,status
+  csrr a3,status
   li a4,(1 << IRQ_COP)
   slli a4,a4,SR_IM_SHIFT
   or a3,a3,a4 # enable IM[COP]
-  mtpcr a3,status
+  csrw status,a3
 
   vsetcfg 32,0
   li a3,4

diff --git a/isa/rv64sv/ma_utsd.S b/isa/rv64sv/ma_utsd.S
index 20249e3334d60ddeac8d0c70745cdd9150241c4c..3879d51faf7708b5d0a6241708502aa927317b97 100644 (file)
--- a/isa/rv64sv/ma_utsd.S
+++ b/isa/rv64sv/ma_utsd.S
@@ -10,18 +10,17 @@
 
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
-
-  setpcr status, SR_EA # enable accelerator
-  setpcr status, SR_EI # enable interrupt
+  li a0, SR_EA | SR_EI
+  csrs status, a0
 
   la a3,handler
-  mtpcr a3,evec # set exception handler
+  csrw evec,a3 # set exception handler
 
-  mfpcr a3,status
+  csrr a3,status
   li a4,(1 << IRQ_COP)
   slli a4,a4,SR_IM_SHIFT
   or a3,a3,a4 # enable IM[COP]
-  mtpcr a3,status
+  csrw status,a3
 
   vsetcfg 32,0
   li a3,4

diff --git a/isa/rv64sv/ma_vld.S b/isa/rv64sv/ma_vld.S
index b353c431bb559727615eef5a3d1ad177e7f50870..d66c42f879ac0d60b559037839a4bc23863c9e70 100644 (file)
--- a/isa/rv64sv/ma_vld.S
+++ b/isa/rv64sv/ma_vld.S
@@ -11,17 +11,17 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  setpcr status, SR_EA # enable accelerator
-  setpcr status, SR_EI # enable interrupt
+  li a0, SR_EA | SR_EI
+  csrs status, a0
 
   la a3,handler
-  mtpcr a3,evec # set exception handler
+  csrw evec,a3 # set exception handler
 
-  mfpcr a3,status
+  csrr a3,status
   li a4,(1 << IRQ_COP)
   slli a4,a4,SR_IM_SHIFT
   or a3,a3,a4 # enable IM[COP]
-  mtpcr a3,status
+  csrw status,a3
 
   vsetcfg 32,0
   li a3,4

diff --git a/isa/rv64sv/ma_vsd.S b/isa/rv64sv/ma_vsd.S
index 227955c9d964ccf5d1c6cfe23cd90db5f8a6db08..715e6a2f2767b5d87b6db38e43e5c572ef605d58 100644 (file)
--- a/isa/rv64sv/ma_vsd.S
+++ b/isa/rv64sv/ma_vsd.S
@@ -11,17 +11,17 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  setpcr status, SR_EA # enable accelerator
-  setpcr status, SR_EI # enable interrupt
+  li a0, SR_EA | SR_EI
+  csrs status, a0
 
   la a3,handler
-  mtpcr a3,evec # set exception handler
+  csrw evec,a3
 
-  mfpcr a3,status
+  csrr a3,status
   li a4,(1 << IRQ_COP)
   slli a4,a4,SR_IM_SHIFT
   or a3,a3,a4 # enable IM[COP]
-  mtpcr a3,status
+  csrw status,a3
 
   vsetcfg 32,0
   li a3,4

diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S
index 85667e42c04314dfc058f54a1c16ad5cb23e3314..c8ef5ad143c1df92fc95b6ea53119d969f8f1139 100644 (file)
--- a/isa/rv64sv/ma_vt_inst.S
+++ b/isa/rv64sv/ma_vt_inst.S
@@ -11,17 +11,17 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  setpcr status, SR_EA # enable accelerator
-  setpcr status, SR_EI # enable interrupt
+  li a0, SR_EA | SR_EI
+  csrs status, a0
 
   la a3,handler
-  mtpcr a3,evec # set exception handler
+  csrw evec,a3
 
-  mfpcr a3,status
+  csrr a3,status
   li a4,(1 << IRQ_COP)
   slli a4,a4,SR_IM_SHIFT
   or a3,a3,a4 # enable IM[COP]
-  mtpcr a3,status
+  csrw status,a3
 
   vsetcfg 32,0
   li a3,4

diff --git a/isa/rv64sv/privileged_inst.S b/isa/rv64sv/privileged_inst.S
index 64a75081ec87e467617ed4aca5c678a9c6fa29f7..1a88ca324cb74e7b9c3e18662ea7c146776bece9 100644 (file)
--- a/isa/rv64sv/privileged_inst.S
+++ b/isa/rv64sv/privileged_inst.S
@@ -11,20 +11,21 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  setpcr status, SR_EA # enable accelerator
-  setpcr status, SR_EI # enable interrupt
+  li a0, SR_EA | SR_EI
+  csrs status, a0
 
   la a3,handler
-  mtpcr a3,evec # set exception handler
+  csrw evec,a3 # set exception handler
 
-  mfpcr a3,status
+  csrr a3,status
   li a4,(1 << IRQ_COP)
   slli a4,a4,SR_IM_SHIFT
   or a3,a3,a4 # enable IM[COP]
-  mtpcr a3,status
+  csrw status,a3
 
-  setpcr status, SR_U64
-  clearpcr status, SR_S # clear S bit
+  la a0, SR_U64
+  csrs status, a0
+  csrc status, SR_S
 
 privileged_inst:
   vxcptcause a3 # privileged inst