+++ /dev/null
-# Mesa 3-D graphics library
-#
-# Copyright (C) 2013 LunarG Inc.
-#
-# Permission is hereby granted, free of charge, to any person obtaining a
-# copy of this software and associated documentation files (the "Software"),
-# to deal in the Software without restriction, including without limitation
-# the rights to use, copy, modify, merge, publish, distribute, sublicense,
-# and/or sell copies of the Software, and to permit persons to whom the
-# Software is furnished to do so, subject to the following conditions:
-#
-# The above copyright notice and this permission notice shall be included
-# in all copies or substantial portions of the Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-# DEALINGS IN THE SOFTWARE.
-
-LOCAL_PATH := $(call my-dir)
-
-# get C_SOURCES
-include $(LOCAL_PATH)/Makefile.sources
-
-include $(CLEAR_VARS)
-
-LOCAL_SRC_FILES := $(C_SOURCES)
-
-LOCAL_MODULE := libmesa_pipe_ilo
-
-include $(GALLIUM_COMMON_MK)
-include $(BUILD_STATIC_LIBRARY)
+++ /dev/null
-if HAVE_GALLIUM_ILO
-
-TARGET_DRIVERS += ilo
-TARGET_CPPFLAGS += -DGALLIUM_ILO
-TARGET_LIB_DEPS += \
- $(top_builddir)/src/gallium/winsys/intel/drm/libintelwinsys.la \
- $(top_builddir)/src/gallium/drivers/ilo/libilo.la \
- $(INTEL_LIBS) \
- $(LIBDRM_LIBS)
-
-endif
+++ /dev/null
-# Copyright © 2012 Intel Corporation
-# Copyright (C) 2013 LunarG, Inc.
-#
-# Permission is hereby granted, free of charge, to any person obtaining a
-# copy of this software and associated documentation files (the "Software"),
-# to deal in the Software without restriction, including without limitation
-# the rights to use, copy, modify, merge, publish, distribute, sublicense,
-# and/or sell copies of the Software, and to permit persons to whom the
-# Software is furnished to do so, subject to the following conditions:
-#
-# The above copyright notice and this permission notice (including the next
-# paragraph) shall be included in all copies or substantial portions of the
-# Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-# HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-# DEALINGS IN THE SOFTWARE.
-
-include Makefile.sources
-include $(top_srcdir)/src/gallium/Automake.inc
-
-AM_CPPFLAGS = \
- $(GALLIUM_DRIVER_CFLAGS)
-
-noinst_HEADERS = $(GENHW_FILES)
-noinst_LTLIBRARIES = libilo.la
-
-libilo_la_SOURCES = $(C_SOURCES)
+++ /dev/null
-C_SOURCES := \
- core/ilo_builder.c \
- core/ilo_builder.h \
- core/ilo_builder_3d.h \
- core/ilo_builder_3d_bottom.h \
- core/ilo_builder_3d_top.h \
- core/ilo_builder_blt.h \
- core/ilo_builder_decode.c \
- core/ilo_builder_media.h \
- core/ilo_builder_mi.h \
- core/ilo_builder_render.h \
- core/ilo_core.h \
- core/ilo_debug.c \
- core/ilo_debug.h \
- core/ilo_dev.c \
- core/ilo_dev.h \
- core/ilo_image.c \
- core/ilo_image.h \
- core/ilo_state_cc.c \
- core/ilo_state_cc.h \
- core/ilo_state_compute.c \
- core/ilo_state_compute.h \
- core/ilo_state_raster.c \
- core/ilo_state_raster.h \
- core/ilo_state_sampler.c \
- core/ilo_state_sampler.h \
- core/ilo_state_sbe.c \
- core/ilo_state_sbe.h \
- core/ilo_state_shader.c \
- core/ilo_state_shader_ps.c \
- core/ilo_state_shader.h \
- core/ilo_state_sol.c \
- core/ilo_state_sol.h \
- core/ilo_state_surface.c \
- core/ilo_state_surface_format.c \
- core/ilo_state_surface.h \
- core/ilo_state_urb.c \
- core/ilo_state_urb.h \
- core/ilo_state_vf.c \
- core/ilo_state_vf.h \
- core/ilo_state_viewport.c \
- core/ilo_state_viewport.h \
- core/ilo_state_zs.c \
- core/ilo_state_zs.h \
- core/ilo_vma.h \
- core/intel_winsys.h \
- ilo_blit.c \
- ilo_blit.h \
- ilo_blitter.c \
- ilo_blitter.h \
- ilo_blitter_blt.c \
- ilo_blitter_pipe.c \
- ilo_blitter_rectlist.c \
- ilo_common.h \
- ilo_context.c \
- ilo_context.h \
- ilo_cp.c \
- ilo_cp.h \
- ilo_draw.c \
- ilo_draw.h \
- ilo_format.c \
- ilo_format.h \
- ilo_gpgpu.c \
- ilo_gpgpu.h \
- ilo_public.h \
- ilo_query.c \
- ilo_query.h \
- ilo_render.c \
- ilo_render.h \
- ilo_render_gen.h \
- ilo_render_dynamic.c \
- ilo_render_gen6.c \
- ilo_render_gen7.c \
- ilo_render_gen8.c \
- ilo_render_media.c \
- ilo_render_surface.c \
- ilo_resource.c \
- ilo_resource.h \
- ilo_screen.c \
- ilo_screen.h \
- ilo_shader.c \
- ilo_shader.h \
- ilo_state.c \
- ilo_state.h \
- ilo_transfer.c \
- ilo_transfer.h \
- ilo_video.c \
- ilo_video.h \
- \
- shader/ilo_shader_cs.c \
- shader/ilo_shader_fs.c \
- shader/ilo_shader_gs.c \
- shader/ilo_shader_internal.h \
- shader/ilo_shader_vs.c \
- shader/toy_compiler.c \
- shader/toy_compiler.h \
- shader/toy_compiler_asm.c \
- shader/toy_compiler_disasm.c \
- shader/toy_compiler_reg.h \
- shader/toy_helpers.h \
- shader/toy_legalize.c \
- shader/toy_legalize.h \
- shader/toy_legalize_ra.c \
- shader/toy_optimize.c \
- shader/toy_optimize.h \
- shader/toy_tgsi.c \
- shader/toy_tgsi.h
-
-GENHW_FILES := \
- genhw/gen_blitter.xml.h \
- genhw/gen_eu_isa.xml.h \
- genhw/gen_eu_message.xml.h \
- genhw/genhw.h \
- genhw/gen_mi.xml.h \
- genhw/gen_regs.xml.h \
- genhw/gen_render.xml.h \
- genhw/gen_render_3d.xml.h \
- genhw/gen_render_dynamic.xml.h \
- genhw/gen_render_media.xml.h \
- genhw/gen_render_surface.xml.h
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "util/u_memory.h"
-
-#include "ilo_builder.h"
-#include "ilo_builder_render.h" /* for ilo_builder_batch_patch_sba() */
-
-enum ilo_builder_writer_flags {
- /*
- * When this bit is set, ilo_builder_begin() will not realllocate. New
- * data will be appended instead.
- */
- WRITER_FLAG_APPEND = 1 << 0,
-
- /*
- * When this bit is set, the writer grows when full. When not, callers
- * must make sure the writer never needs to grow.
- */
- WRITER_FLAG_GROW = 1 << 1,
-
- /*
- * The writer will be mapped directly.
- */
- WRITER_FLAG_MAP = 1 << 2,
-};
-
-/**
- * Set the initial size and flags of a writer.
- */
-static void
-ilo_builder_writer_init(struct ilo_builder *builder,
- enum ilo_builder_writer_type which)
-{
- struct ilo_builder_writer *writer = &builder->writers[which];
-
- switch (which) {
- case ILO_BUILDER_WRITER_BATCH:
- writer->size = sizeof(uint32_t) * 8192;
- break;
- case ILO_BUILDER_WRITER_INSTRUCTION:
- /*
- * The EUs pretch some instructions. But since the kernel invalidates
- * the instruction cache between batch buffers, we can set
- * WRITER_FLAG_APPEND without worrying the EUs would see invalid
- * instructions prefetched.
- */
- writer->flags = WRITER_FLAG_APPEND | WRITER_FLAG_GROW;
- writer->size = 8192;
- break;
- default:
- assert(!"unknown builder writer");
- return;
- break;
- }
-
- if (builder->dev->has_llc)
- writer->flags |= WRITER_FLAG_MAP;
-}
-
-/**
- * Free all resources used by a writer. Note that the initial size is not
- * reset.
- */
-static void
-ilo_builder_writer_reset(struct ilo_builder *builder,
- enum ilo_builder_writer_type which)
-{
- struct ilo_builder_writer *writer = &builder->writers[which];
-
- if (writer->ptr) {
- if (writer->flags & WRITER_FLAG_MAP)
- intel_bo_unmap(writer->bo);
- else
- FREE(writer->ptr);
-
- writer->ptr = NULL;
- }
-
- intel_bo_unref(writer->bo);
- writer->bo = NULL;
-
- writer->used = 0;
- writer->stolen = 0;
-
- if (writer->items) {
- FREE(writer->items);
- writer->item_alloc = 0;
- writer->item_used = 0;
- }
-}
-
-/**
- * Discard everything written so far.
- */
-void
-ilo_builder_writer_discard(struct ilo_builder *builder,
- enum ilo_builder_writer_type which)
-{
- struct ilo_builder_writer *writer = &builder->writers[which];
-
- intel_bo_truncate_relocs(writer->bo, 0);
- writer->used = 0;
- writer->stolen = 0;
- writer->item_used = 0;
-}
-
-static struct intel_bo *
-alloc_writer_bo(struct intel_winsys *winsys,
- enum ilo_builder_writer_type which,
- unsigned size)
-{
- static const char *writer_names[ILO_BUILDER_WRITER_COUNT] = {
- [ILO_BUILDER_WRITER_BATCH] = "batch",
- [ILO_BUILDER_WRITER_INSTRUCTION] = "instruction",
- };
-
- return intel_winsys_alloc_bo(winsys, writer_names[which], size, true);
-}
-
-static void *
-map_writer_bo(struct intel_bo *bo, unsigned flags)
-{
- assert(flags & WRITER_FLAG_MAP);
-
- if (flags & WRITER_FLAG_APPEND)
- return intel_bo_map_gtt_async(bo);
- else
- return intel_bo_map(bo, true);
-}
-
-/**
- * Allocate and map the buffer for writing.
- */
-static bool
-ilo_builder_writer_alloc_and_map(struct ilo_builder *builder,
- enum ilo_builder_writer_type which)
-{
- struct ilo_builder_writer *writer = &builder->writers[which];
-
- /* allocate a new bo when not appending */
- if (!(writer->flags & WRITER_FLAG_APPEND) || !writer->bo) {
- struct intel_bo *bo;
-
- bo = alloc_writer_bo(builder->winsys, which, writer->size);
- if (bo) {
- intel_bo_unref(writer->bo);
- writer->bo = bo;
- } else if (writer->bo) {
- /* reuse the old bo */
- ilo_builder_writer_discard(builder, which);
- } else {
- return false;
- }
-
- writer->used = 0;
- writer->stolen = 0;
- writer->item_used = 0;
- }
-
- /* map the bo or allocate the staging system memory */
- if (writer->flags & WRITER_FLAG_MAP)
- writer->ptr = map_writer_bo(writer->bo, writer->flags);
- else if (!writer->ptr)
- writer->ptr = MALLOC(writer->size);
-
- return (writer->ptr != NULL);
-}
-
-/**
- * Unmap the buffer for submission.
- */
-static bool
-ilo_builder_writer_unmap(struct ilo_builder *builder,
- enum ilo_builder_writer_type which)
-{
- struct ilo_builder_writer *writer = &builder->writers[which];
- unsigned offset;
- int err = 0;
-
- if (writer->flags & WRITER_FLAG_MAP) {
- intel_bo_unmap(writer->bo);
- writer->ptr = NULL;
- return true;
- }
-
- offset = builder->begin_used[which];
- if (writer->used > offset) {
- err = intel_bo_pwrite(writer->bo, offset, writer->used - offset,
- (char *) writer->ptr + offset);
- }
-
- if (writer->stolen && !err) {
- const unsigned offset = writer->size - writer->stolen;
- err = intel_bo_pwrite(writer->bo, offset, writer->stolen,
- (const char *) writer->ptr + offset);
- }
-
- /* keep writer->ptr */
-
- return !err;
-}
-
-/**
- * Grow a mapped writer to at least \p new_size.
- */
-bool
-ilo_builder_writer_grow(struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- unsigned new_size, bool preserve)
-{
- struct ilo_builder_writer *writer = &builder->writers[which];
- struct intel_bo *new_bo;
- void *new_ptr;
-
- if (!(writer->flags & WRITER_FLAG_GROW))
- return false;
-
- /* stolen data may already be referenced and cannot be moved */
- if (writer->stolen)
- return false;
-
- if (new_size < writer->size << 1)
- new_size = writer->size << 1;
- /* STATE_BASE_ADDRESS requires page-aligned buffers */
- new_size = align(new_size, 4096);
-
- new_bo = alloc_writer_bo(builder->winsys, which, new_size);
- if (!new_bo)
- return false;
-
- /* map and copy the data over */
- if (writer->flags & WRITER_FLAG_MAP) {
- new_ptr = map_writer_bo(new_bo, writer->flags);
-
- /*
- * When WRITER_FLAG_APPEND and WRITER_FLAG_GROW are both set, we may end
- * up copying between two GTT-mapped BOs. That is slow. The issue
- * could be solved by adding intel_bo_map_async(), or callers may choose
- * to manually grow the writer without preserving the data.
- */
- if (new_ptr && preserve)
- memcpy(new_ptr, writer->ptr, writer->used);
- } else if (preserve) {
- new_ptr = REALLOC(writer->ptr, writer->size, new_size);
- } else {
- new_ptr = MALLOC(new_size);
- }
-
- if (!new_ptr) {
- intel_bo_unref(new_bo);
- return false;
- }
-
- if (writer->flags & WRITER_FLAG_MAP)
- intel_bo_unmap(writer->bo);
- else if (!preserve)
- FREE(writer->ptr);
-
- intel_bo_unref(writer->bo);
-
- writer->size = new_size;
- writer->bo = new_bo;
- writer->ptr = new_ptr;
-
- return true;
-}
-
-/**
- * Record an item for later decoding.
- */
-bool
-ilo_builder_writer_record(struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- enum ilo_builder_item_type type,
- unsigned offset, unsigned size)
-{
- struct ilo_builder_writer *writer = &builder->writers[which];
- struct ilo_builder_item *item;
-
- if (writer->item_used == writer->item_alloc) {
- const unsigned new_alloc = (writer->item_alloc) ?
- writer->item_alloc << 1 : 256;
- struct ilo_builder_item *items;
-
- items = REALLOC(writer->items,
- sizeof(writer->items[0]) * writer->item_alloc,
- sizeof(writer->items[0]) * new_alloc);
- if (!items)
- return false;
-
- writer->items = items;
- writer->item_alloc = new_alloc;
- }
-
- item = &writer->items[writer->item_used++];
- item->type = type;
- item->offset = offset;
- item->size = size;
-
- return true;
-}
-
-/**
- * Initialize the builder.
- */
-void
-ilo_builder_init(struct ilo_builder *builder,
- const struct ilo_dev *dev,
- struct intel_winsys *winsys)
-{
- unsigned i;
-
- assert(ilo_is_zeroed(builder, sizeof(*builder)));
-
- builder->dev = dev;
- builder->winsys = winsys;
-
- /* gen6_SURFACE_STATE() may override this */
- switch (ilo_dev_gen(dev)) {
- case ILO_GEN(8):
- builder->mocs = GEN8_MOCS_MT_WB | GEN8_MOCS_CT_L3;
- break;
- case ILO_GEN(7.5):
- case ILO_GEN(7):
- builder->mocs = GEN7_MOCS_L3_WB;
- break;
- default:
- builder->mocs = 0;
- break;
- }
-
- for (i = 0; i < ILO_BUILDER_WRITER_COUNT; i++)
- ilo_builder_writer_init(builder, i);
-}
-
-/**
- * Reset the builder and free all resources used. After resetting, the
- * builder behaves as if it is newly initialized, except for potentially
- * larger initial bo sizes.
- */
-void
-ilo_builder_reset(struct ilo_builder *builder)
-{
- unsigned i;
-
- for (i = 0; i < ILO_BUILDER_WRITER_COUNT; i++)
- ilo_builder_writer_reset(builder, i);
-}
-
-/**
- * Allocate and map the BOs. It may re-allocate or reuse existing BOs if
- * there is any.
- *
- * Most builder functions can only be called after ilo_builder_begin() and
- * before ilo_builder_end().
- */
-bool
-ilo_builder_begin(struct ilo_builder *builder)
-{
- unsigned i;
-
- for (i = 0; i < ILO_BUILDER_WRITER_COUNT; i++) {
- if (!ilo_builder_writer_alloc_and_map(builder, i)) {
- ilo_builder_reset(builder);
- return false;
- }
-
- builder->begin_used[i] = builder->writers[i].used;
- }
-
- builder->unrecoverable_error = false;
- builder->sba_instruction_pos = 0;
-
- return true;
-}
-
-/**
- * Unmap BOs and make sure the written data landed the BOs. The batch buffer
- * ready for submission is returned.
- */
-struct intel_bo *
-ilo_builder_end(struct ilo_builder *builder, unsigned *used)
-{
- struct ilo_builder_writer *bat;
- unsigned i;
-
- ilo_builder_batch_patch_sba(builder);
-
- assert(ilo_builder_validate(builder, 0, NULL));
-
- for (i = 0; i < ILO_BUILDER_WRITER_COUNT; i++) {
- if (!ilo_builder_writer_unmap(builder, i))
- builder->unrecoverable_error = true;
- }
-
- if (builder->unrecoverable_error)
- return NULL;
-
- bat = &builder->writers[ILO_BUILDER_WRITER_BATCH];
-
- *used = bat->used;
-
- return bat->bo;
-}
-
-/**
- * Return true if the builder is in a valid state, after accounting for the
- * additional BOs specified. The additional BOs can be listed to avoid
- * snapshotting and restoring when they are known ahead of time.
- *
- * The number of additional BOs should not be more than a few. Like two, for
- * copying between two BOs.
- *
- * Callers must make sure the builder is in a valid state when
- * ilo_builder_end() is called.
- */
-bool
-ilo_builder_validate(struct ilo_builder *builder,
- unsigned bo_count, struct intel_bo **bos)
-{
- const unsigned max_bo_count = 2;
- struct intel_bo *bos_to_submit[ILO_BUILDER_WRITER_COUNT + max_bo_count];
- int i;
-
- for (i = 0; i < ILO_BUILDER_WRITER_COUNT; i++)
- bos_to_submit[i] = builder->writers[i].bo;
-
- if (bo_count) {
- assert(bo_count <= max_bo_count);
- if (bo_count > max_bo_count)
- return false;
-
- memcpy(&bos_to_submit[ILO_BUILDER_WRITER_COUNT],
- bos, sizeof(*bos) * bo_count);
- i += bo_count;
- }
-
- return intel_winsys_can_submit_bo(builder->winsys, bos_to_submit, i);
-}
-
-/**
- * Take a snapshot of the writer state.
- */
-void
-ilo_builder_batch_snapshot(const struct ilo_builder *builder,
- struct ilo_builder_snapshot *snapshot)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
- const struct ilo_builder_writer *writer = &builder->writers[which];
-
- snapshot->reloc_count = intel_bo_get_reloc_count(writer->bo);
- snapshot->used = writer->used;
- snapshot->stolen = writer->stolen;
- snapshot->item_used = writer->item_used;
-}
-
-/**
- * Restore the writer state to when the snapshot was taken, except that it
- * does not (unnecessarily) shrink BOs or the item array.
- */
-void
-ilo_builder_batch_restore(struct ilo_builder *builder,
- const struct ilo_builder_snapshot *snapshot)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
- struct ilo_builder_writer *writer = &builder->writers[which];
-
- intel_bo_truncate_relocs(writer->bo, snapshot->reloc_count);
- writer->used = snapshot->used;
- writer->stolen = snapshot->stolen;
- writer->item_used = snapshot->item_used;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_BUILDER_H
-#define ILO_BUILDER_H
-
-#include "intel_winsys.h"
-
-#include "ilo_core.h"
-#include "ilo_debug.h"
-#include "ilo_dev.h"
-
-enum ilo_builder_writer_type {
- ILO_BUILDER_WRITER_BATCH,
- ILO_BUILDER_WRITER_INSTRUCTION,
-
- ILO_BUILDER_WRITER_COUNT,
-};
-
-enum ilo_builder_item_type {
- /* for dynamic buffer */
- ILO_BUILDER_ITEM_BLOB,
- ILO_BUILDER_ITEM_CLIP_VIEWPORT,
- ILO_BUILDER_ITEM_SF_VIEWPORT,
- ILO_BUILDER_ITEM_SCISSOR_RECT,
- ILO_BUILDER_ITEM_CC_VIEWPORT,
- ILO_BUILDER_ITEM_COLOR_CALC,
- ILO_BUILDER_ITEM_DEPTH_STENCIL,
- ILO_BUILDER_ITEM_BLEND,
- ILO_BUILDER_ITEM_SAMPLER,
- ILO_BUILDER_ITEM_INTERFACE_DESCRIPTOR,
-
- /* for surface buffer */
- ILO_BUILDER_ITEM_SURFACE,
- ILO_BUILDER_ITEM_BINDING_TABLE,
-
- /* for instruction buffer */
- ILO_BUILDER_ITEM_KERNEL,
-
- ILO_BUILDER_ITEM_COUNT,
-};
-
-struct ilo_builder_item {
- enum ilo_builder_item_type type;
- unsigned offset;
- unsigned size;
-};
-
-struct ilo_builder_writer {
- /* internal flags */
- unsigned flags;
-
- unsigned size;
- struct intel_bo *bo;
- void *ptr;
-
- /* data written to the bottom */
- unsigned used;
- /* data written to the top */
- unsigned stolen;
-
- /* for decoding */
- struct ilo_builder_item *items;
- unsigned item_alloc;
- unsigned item_used;
-};
-
-/**
- * A snapshot of the writer state.
- */
-struct ilo_builder_snapshot {
- unsigned reloc_count;
-
- unsigned used;
- unsigned stolen;
- unsigned item_used;
-};
-
-struct ilo_builder {
- const struct ilo_dev *dev;
- struct intel_winsys *winsys;
- uint32_t mocs;
-
- struct ilo_builder_writer writers[ILO_BUILDER_WRITER_COUNT];
- bool unrecoverable_error;
-
- /* for writers that have their data appended */
- unsigned begin_used[ILO_BUILDER_WRITER_COUNT];
-
- /* for STATE_BASE_ADDRESS */
- unsigned sba_instruction_pos;
-};
-
-void
-ilo_builder_init(struct ilo_builder *builder,
- const struct ilo_dev *dev,
- struct intel_winsys *winsys);
-
-void
-ilo_builder_reset(struct ilo_builder *builder);
-
-void
-ilo_builder_decode(struct ilo_builder *builder);
-
-bool
-ilo_builder_begin(struct ilo_builder *builder);
-
-struct intel_bo *
-ilo_builder_end(struct ilo_builder *builder, unsigned *used);
-
-bool
-ilo_builder_validate(struct ilo_builder *builder,
- unsigned bo_count, struct intel_bo **bos);
-
-/**
- * Return true if the builder has a relocation entry for \p bo.
- */
-static inline bool
-ilo_builder_has_reloc(const struct ilo_builder *builder,
- struct intel_bo *bo)
-{
- int i;
-
- for (i = 0; i < ILO_BUILDER_WRITER_COUNT; i++) {
- const struct ilo_builder_writer *writer = &builder->writers[i];
- if (intel_bo_has_reloc(writer->bo, bo))
- return true;
- }
-
- return false;
-}
-
-void
-ilo_builder_writer_discard(struct ilo_builder *builder,
- enum ilo_builder_writer_type which);
-
-bool
-ilo_builder_writer_grow(struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- unsigned new_size, bool preserve);
-
-bool
-ilo_builder_writer_record(struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- enum ilo_builder_item_type type,
- unsigned offset, unsigned size);
-
-static inline void
-ilo_builder_writer_checked_record(struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- enum ilo_builder_item_type item,
- unsigned offset, unsigned size)
-{
- if (unlikely(ilo_debug & (ILO_DEBUG_BATCH | ILO_DEBUG_HANG))) {
- if (!ilo_builder_writer_record(builder, which, item, offset, size)) {
- builder->unrecoverable_error = true;
- builder->writers[which].item_used = 0;
- }
- }
-}
-
-/**
- * Return an offset to a region that is aligned to \p alignment and has at
- * least \p size bytes. The region is reserved from the bottom.
- */
-static inline unsigned
-ilo_builder_writer_reserve_bottom(struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- unsigned alignment, unsigned size)
-{
- struct ilo_builder_writer *writer = &builder->writers[which];
- unsigned offset;
-
- assert(alignment && util_is_power_of_two(alignment));
- offset = align(writer->used, alignment);
-
- if (unlikely(offset + size > writer->size - writer->stolen)) {
- if (!ilo_builder_writer_grow(builder, which,
- offset + size + writer->stolen, true)) {
- builder->unrecoverable_error = true;
- ilo_builder_writer_discard(builder, which);
- offset = 0;
- }
-
- assert(offset + size <= writer->size - writer->stolen);
- }
-
- return offset;
-}
-
-/**
- * Similar to ilo_builder_writer_reserve_bottom(), but reserve from the top.
- */
-static inline unsigned
-ilo_builder_writer_reserve_top(struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- unsigned alignment, unsigned size)
-{
- struct ilo_builder_writer *writer = &builder->writers[which];
- unsigned offset;
-
- assert(alignment && util_is_power_of_two(alignment));
- offset = (writer->size - writer->stolen - size) & ~(alignment - 1);
-
- if (unlikely(offset < writer->used ||
- size > writer->size - writer->stolen)) {
- if (!ilo_builder_writer_grow(builder, which,
- align(writer->used, alignment) + size + writer->stolen, true)) {
- builder->unrecoverable_error = true;
- ilo_builder_writer_discard(builder, which);
- }
-
- offset = (writer->size - writer->stolen - size) & ~(alignment - 1);
- assert(offset + size <= writer->size - writer->stolen);
- }
-
- return offset;
-}
-
-/**
- * Add a relocation entry to the writer.
- */
-static inline void
-ilo_builder_writer_reloc(struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- unsigned offset, struct intel_bo *bo,
- unsigned bo_offset, unsigned reloc_flags,
- bool write_presumed_offset_hi)
-{
- struct ilo_builder_writer *writer = &builder->writers[which];
- uint64_t presumed_offset;
- int err;
-
- if (write_presumed_offset_hi)
- ILO_DEV_ASSERT(builder->dev, 8, 8);
- else
- ILO_DEV_ASSERT(builder->dev, 6, 7.5);
-
- assert(offset + sizeof(uint32_t) <= writer->used ||
- (offset >= writer->size - writer->stolen &&
- offset + sizeof(uint32_t) <= writer->size));
-
- err = intel_bo_add_reloc(writer->bo, offset, bo, bo_offset,
- reloc_flags, &presumed_offset);
- if (unlikely(err))
- builder->unrecoverable_error = true;
-
- if (write_presumed_offset_hi) {
- *((uint64_t *) ((char *) writer->ptr + offset)) = presumed_offset;
- } else {
- /* 32-bit addressing */
- assert(presumed_offset == (uint64_t) ((uint32_t) presumed_offset));
- *((uint32_t *) ((char *) writer->ptr + offset)) = presumed_offset;
- }
-}
-
-/**
- * Reserve a region from the dynamic buffer. Both the offset, in bytes, and
- * the pointer to the reserved region are returned. The pointer is only valid
- * until the next reserve call.
- *
- * Note that \p alignment is in bytes and \p len is in DWords.
- */
-static inline uint32_t
-ilo_builder_dynamic_pointer(struct ilo_builder *builder,
- enum ilo_builder_item_type item,
- unsigned alignment, unsigned len,
- uint32_t **dw)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
- const unsigned size = len << 2;
- const unsigned offset = ilo_builder_writer_reserve_top(builder,
- which, alignment, size);
- struct ilo_builder_writer *writer = &builder->writers[which];
-
- /* all states are at least aligned to 32-bytes */
- if (item != ILO_BUILDER_ITEM_BLOB)
- assert(alignment % 32 == 0);
-
- *dw = (uint32_t *) ((char *) writer->ptr + offset);
-
- writer->stolen = writer->size - offset;
-
- ilo_builder_writer_checked_record(builder, which, item, offset, size);
-
- return offset;
-}
-
-/**
- * Write a dynamic state to the dynamic buffer.
- */
-static inline uint32_t
-ilo_builder_dynamic_write(struct ilo_builder *builder,
- enum ilo_builder_item_type item,
- unsigned alignment, unsigned len,
- const uint32_t *dw)
-{
- uint32_t offset, *dst;
-
- offset = ilo_builder_dynamic_pointer(builder, item, alignment, len, &dst);
- memcpy(dst, dw, len << 2);
-
- return offset;
-}
-
-/**
- * Reserve some space from the top (for prefetches).
- */
-static inline void
-ilo_builder_dynamic_pad_top(struct ilo_builder *builder, unsigned len)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
- const unsigned size = len << 2;
- struct ilo_builder_writer *writer = &builder->writers[which];
-
- if (writer->stolen < size) {
- ilo_builder_writer_reserve_top(builder, which,
- 1, size - writer->stolen);
- writer->stolen = size;
- }
-}
-
-static inline unsigned
-ilo_builder_dynamic_used(const struct ilo_builder *builder)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
- const struct ilo_builder_writer *writer = &builder->writers[which];
-
- return writer->stolen >> 2;
-}
-
-/**
- * Reserve a region from the surface buffer. Both the offset, in bytes, and
- * the pointer to the reserved region are returned. The pointer is only valid
- * until the next reserve call.
- *
- * Note that \p alignment is in bytes and \p len is in DWords.
- */
-static inline uint32_t
-ilo_builder_surface_pointer(struct ilo_builder *builder,
- enum ilo_builder_item_type item,
- unsigned alignment, unsigned len,
- uint32_t **dw)
-{
- assert(item == ILO_BUILDER_ITEM_SURFACE ||
- item == ILO_BUILDER_ITEM_BINDING_TABLE);
-
- return ilo_builder_dynamic_pointer(builder, item, alignment, len, dw);
-}
-
-/**
- * Add a relocation entry for a DWord of a surface state.
- */
-static inline void
-ilo_builder_surface_reloc(struct ilo_builder *builder,
- uint32_t offset, unsigned dw_index,
- struct intel_bo *bo, unsigned bo_offset,
- unsigned reloc_flags)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
-
- ilo_builder_writer_reloc(builder, which, offset + (dw_index << 2),
- bo, bo_offset, reloc_flags, false);
-}
-
-static inline void
-ilo_builder_surface_reloc64(struct ilo_builder *builder,
- uint32_t offset, unsigned dw_index,
- struct intel_bo *bo, unsigned bo_offset,
- unsigned reloc_flags)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
-
- ilo_builder_writer_reloc(builder, which, offset + (dw_index << 2),
- bo, bo_offset, reloc_flags, true);
-}
-
-static inline unsigned
-ilo_builder_surface_used(const struct ilo_builder *builder)
-{
- return ilo_builder_dynamic_used(builder);
-}
-
-/**
- * Write a kernel to the instruction buffer. The offset, in bytes, of the
- * kernel is returned.
- */
-static inline uint32_t
-ilo_builder_instruction_write(struct ilo_builder *builder,
- unsigned size, const void *kernel)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_INSTRUCTION;
- /*
- * From the Sandy Bridge PRM, volume 4 part 2, page 112:
- *
- * "Due to prefetch of the instruction stream, the EUs may attempt to
- * access up to 8 instructions (128 bytes) beyond the end of the
- * kernel program - possibly into the next memory page. Although
- * these instructions will not be executed, software must account for
- * the prefetch in order to avoid invalid page access faults."
- */
- const unsigned reserved_size = size + 128;
- /* kernels are aligned to 64 bytes */
- const unsigned alignment = 64;
- const unsigned offset = ilo_builder_writer_reserve_bottom(builder,
- which, alignment, reserved_size);
- struct ilo_builder_writer *writer = &builder->writers[which];
-
- memcpy((char *) writer->ptr + offset, kernel, size);
-
- writer->used = offset + size;
-
- ilo_builder_writer_checked_record(builder, which,
- ILO_BUILDER_ITEM_KERNEL, offset, size);
-
- return offset;
-}
-
-/**
- * Reserve a region from the batch buffer. Both the offset, in DWords, and
- * the pointer to the reserved region are returned. The pointer is only valid
- * until the next reserve call.
- *
- * Note that \p len is in DWords.
- */
-static inline unsigned
-ilo_builder_batch_pointer(struct ilo_builder *builder,
- unsigned len, uint32_t **dw)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
- /*
- * We know the batch bo is always aligned. Using 1 here should allow the
- * compiler to optimize away aligning.
- */
- const unsigned alignment = 1;
- const unsigned size = len << 2;
- const unsigned offset = ilo_builder_writer_reserve_bottom(builder,
- which, alignment, size);
- struct ilo_builder_writer *writer = &builder->writers[which];
-
- assert(offset % 4 == 0);
- *dw = (uint32_t *) ((char *) writer->ptr + offset);
-
- writer->used = offset + size;
-
- return offset >> 2;
-}
-
-/**
- * Write a command to the batch buffer.
- */
-static inline unsigned
-ilo_builder_batch_write(struct ilo_builder *builder,
- unsigned len, const uint32_t *dw)
-{
- unsigned pos;
- uint32_t *dst;
-
- pos = ilo_builder_batch_pointer(builder, len, &dst);
- memcpy(dst, dw, len << 2);
-
- return pos;
-}
-
-/**
- * Add a relocation entry for a DWord of a command.
- */
-static inline void
-ilo_builder_batch_reloc(struct ilo_builder *builder, unsigned pos,
- struct intel_bo *bo, unsigned bo_offset,
- unsigned reloc_flags)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
-
- ilo_builder_writer_reloc(builder, which, pos << 2,
- bo, bo_offset, reloc_flags, false);
-}
-
-static inline void
-ilo_builder_batch_reloc64(struct ilo_builder *builder, unsigned pos,
- struct intel_bo *bo, unsigned bo_offset,
- unsigned reloc_flags)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
-
- ilo_builder_writer_reloc(builder, which, pos << 2,
- bo, bo_offset, reloc_flags, true);
-}
-
-static inline unsigned
-ilo_builder_batch_used(const struct ilo_builder *builder)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
- const struct ilo_builder_writer *writer = &builder->writers[which];
-
- return writer->used >> 2;
-}
-
-static inline unsigned
-ilo_builder_batch_space(const struct ilo_builder *builder)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
- const struct ilo_builder_writer *writer = &builder->writers[which];
-
- return (writer->size - writer->stolen - writer->used) >> 2;
-}
-
-static inline void
-ilo_builder_batch_discard(struct ilo_builder *builder)
-{
- ilo_builder_writer_discard(builder, ILO_BUILDER_WRITER_BATCH);
-}
-
-static inline void
-ilo_builder_batch_print_stats(const struct ilo_builder *builder)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
- const struct ilo_builder_writer *writer = &builder->writers[which];
-
- ilo_printf("%d+%d bytes (%d%% full)\n",
- writer->used, writer->stolen,
- (writer->used + writer->stolen) * 100 / writer->size);
-}
-
-void
-ilo_builder_batch_snapshot(const struct ilo_builder *builder,
- struct ilo_builder_snapshot *snapshot);
-
-void
-ilo_builder_batch_restore(struct ilo_builder *builder,
- const struct ilo_builder_snapshot *snapshot);
-
-#endif /* ILO_BUILDER_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_BUILDER_3D_H
-#define ILO_BUILDER_3D_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-#include "ilo_builder_3d_top.h"
-#include "ilo_builder_3d_bottom.h"
-
-struct gen6_3dprimitive_info {
- enum gen_3dprim_type topology;
- bool indexed;
-
- uint32_t vertex_count;
- uint32_t vertex_start;
- uint32_t instance_count;
- uint32_t instance_start;
- int32_t vertex_base;
-};
-
-static inline void
-gen6_3DPRIMITIVE(struct ilo_builder *builder,
- const struct gen6_3dprimitive_info *info)
-{
- const uint8_t cmd_len = 6;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DPRIMITIVE) | (cmd_len - 2) |
- info->topology << GEN6_3DPRIM_DW0_TYPE__SHIFT;
- if (info->indexed)
- dw[0] |= GEN6_3DPRIM_DW0_ACCESS_RANDOM;
-
- dw[1] = info->vertex_count;
- dw[2] = info->vertex_start;
- dw[3] = info->instance_count;
- dw[4] = info->instance_start;
- dw[5] = info->vertex_base;
-}
-
-static inline void
-gen7_3DPRIMITIVE(struct ilo_builder *builder,
- const struct gen6_3dprimitive_info *info)
-{
- const uint8_t cmd_len = 7;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DPRIMITIVE) | (cmd_len - 2);
-
- dw[1] = info->topology << GEN7_3DPRIM_DW1_TYPE__SHIFT;
- if (info->indexed)
- dw[1] |= GEN7_3DPRIM_DW1_ACCESS_RANDOM;
-
- dw[2] = info->vertex_count;
- dw[3] = info->vertex_start;
- dw[4] = info->instance_count;
- dw[5] = info->instance_start;
- dw[6] = info->vertex_base;
-}
-
-#endif /* ILO_BUILDER_3D_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_BUILDER_3D_BOTTOM_H
-#define ILO_BUILDER_3D_BOTTOM_H
-
-#include "genhw/genhw.h"
-#include "intel_winsys.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-#include "ilo_state_cc.h"
-#include "ilo_state_raster.h"
-#include "ilo_state_sbe.h"
-#include "ilo_state_shader.h"
-#include "ilo_state_viewport.h"
-#include "ilo_state_zs.h"
-#include "ilo_vma.h"
-#include "ilo_builder.h"
-#include "ilo_builder_3d_top.h"
-
-static inline void
-gen6_3DSTATE_CLIP(struct ilo_builder *builder,
- const struct ilo_state_raster *rs)
-{
- const uint8_t cmd_len = 4;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_CLIP) | (cmd_len - 2);
- /* see raster_set_gen6_3DSTATE_CLIP() */
- dw[1] = rs->clip[0];
- dw[2] = rs->clip[1];
- dw[3] = rs->clip[2];
-}
-
-static inline void
-gen6_3DSTATE_SF(struct ilo_builder *builder,
- const struct ilo_state_raster *rs,
- const struct ilo_state_sbe *sbe)
-{
- const uint8_t cmd_len = 20;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_SF) | (cmd_len - 2);
- /* see sbe_set_gen8_3DSTATE_SBE() */
- dw[1] = sbe->sbe[0];
-
- /* see raster_set_gen7_3DSTATE_SF() */
- dw[2] = rs->sf[0];
- dw[3] = rs->sf[1];
- dw[4] = rs->sf[2];
- dw[5] = rs->raster[1];
- dw[6] = rs->raster[2];
- dw[7] = rs->raster[3];
-
- /* see sbe_set_gen8_3DSTATE_SBE_SWIZ() */
- memcpy(&dw[8], sbe->swiz, sizeof(*dw) * 8);
-
- dw[16] = sbe->sbe[1];
- dw[17] = sbe->sbe[2];
- /* WrapShortest enables */
- dw[18] = 0;
- dw[19] = 0;
-}
-
-static inline void
-gen7_3DSTATE_SF(struct ilo_builder *builder,
- const struct ilo_state_raster *rs)
-{
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 4 : 7;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_SF) | (cmd_len - 2);
-
- /* see raster_set_gen7_3DSTATE_SF() or raster_set_gen8_3DSTATE_SF() */
- dw[1] = rs->sf[0];
- dw[2] = rs->sf[1];
- dw[3] = rs->sf[2];
- if (ilo_dev_gen(builder->dev) < ILO_GEN(8)) {
- dw[4] = rs->raster[1];
- dw[5] = rs->raster[2];
- dw[6] = rs->raster[3];
- }
-}
-
-static inline void
-gen7_3DSTATE_SBE(struct ilo_builder *builder,
- const struct ilo_state_sbe *sbe)
-{
- const uint8_t cmd_len = 14;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 7.5);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_SBE) | (cmd_len - 2);
- /* see sbe_set_gen8_3DSTATE_SBE() and sbe_set_gen8_3DSTATE_SBE_SWIZ() */
- dw[1] = sbe->sbe[0];
- memcpy(&dw[2], sbe->swiz, sizeof(*dw) * 8);
- dw[10] = sbe->sbe[1];
- dw[11] = sbe->sbe[2];
-
- /* WrapShortest enables */
- dw[12] = 0;
- dw[13] = 0;
-}
-
-static inline void
-gen8_3DSTATE_SBE(struct ilo_builder *builder,
- const struct ilo_state_sbe *sbe)
-{
- const uint8_t cmd_len = 4;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- /* see sbe_set_gen8_3DSTATE_SBE() */
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_SBE) | (cmd_len - 2);
- dw[1] = sbe->sbe[0];
- dw[2] = sbe->sbe[1];
- dw[3] = sbe->sbe[2];
-}
-
-static inline void
-gen8_3DSTATE_SBE_SWIZ(struct ilo_builder *builder,
- const struct ilo_state_sbe *sbe)
-{
- const uint8_t cmd_len = 11;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_SBE_SWIZ) | (cmd_len - 2);
- /* see sbe_set_gen8_3DSTATE_SBE_SWIZ() */
- memcpy(&dw[1], sbe->swiz, sizeof(*dw) * 8);
- /* WrapShortest enables */
- dw[9] = 0;
- dw[10] = 0;
-}
-
-static inline void
-gen8_3DSTATE_RASTER(struct ilo_builder *builder,
- const struct ilo_state_raster *rs)
-{
- const uint8_t cmd_len = 5;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_RASTER) | (cmd_len - 2);
- /* see raster_set_gen8_3DSTATE_RASTER() */
- dw[1] = rs->raster[0];
- dw[2] = rs->raster[1];
- dw[3] = rs->raster[2];
- dw[4] = rs->raster[3];
-}
-
-static inline void
-gen6_3DSTATE_WM(struct ilo_builder *builder,
- const struct ilo_state_raster *rs,
- const struct ilo_state_ps *ps,
- uint32_t kernel_offset,
- struct intel_bo *scratch_bo)
-{
- const uint8_t cmd_len = 9;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_WM) | (cmd_len - 2);
- dw[1] = kernel_offset;
- /* see raster_set_gen6_3dstate_wm() and ps_set_gen6_3dstate_wm() */
- dw[2] = ps->ps[0];
- dw[3] = ps->ps[1];
- dw[4] = rs->wm[0] | ps->ps[2];
- dw[5] = rs->wm[1] | ps->ps[3];
- dw[6] = rs->wm[2] | ps->ps[4];
- dw[7] = 0; /* kernel 1 */
- dw[8] = 0; /* kernel 2 */
-
- if (ilo_state_ps_get_scratch_size(ps)) {
- ilo_builder_batch_reloc(builder, pos + 2, scratch_bo,
- ps->ps[0], 0);
- }
-}
-
-static inline void
-gen7_3DSTATE_WM(struct ilo_builder *builder,
- const struct ilo_state_raster *rs,
- const struct ilo_state_ps *ps)
-{
- const uint8_t cmd_len = 3;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 7.5);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_WM) | (cmd_len - 2);
- /* see raster_set_gen8_3DSTATE_WM() and ps_set_gen7_3dstate_wm() */
- dw[1] = rs->wm[0] | ps->ps[0];
- dw[2] = ps->ps[1];
-}
-
-static inline void
-gen8_3DSTATE_WM(struct ilo_builder *builder,
- const struct ilo_state_raster *rs)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_WM) | (cmd_len - 2);
- /* see raster_set_gen8_3DSTATE_WM() */
- dw[1] = rs->wm[0];
-}
-
-static inline void
-gen8_3DSTATE_WM_DEPTH_STENCIL(struct ilo_builder *builder,
- const struct ilo_state_cc *cc)
-{
- const uint8_t cmd_len = 3;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_WM_DEPTH_STENCIL) | (cmd_len - 2);
- /* see cc_set_gen8_3DSTATE_WM_DEPTH_STENCIL() */
- dw[1] = cc->ds[0];
- dw[2] = cc->ds[1];
-}
-
-static inline void
-gen8_3DSTATE_WM_HZ_OP(struct ilo_builder *builder,
- const struct ilo_state_raster *rs,
- uint16_t width, uint16_t height)
-{
- const uint8_t cmd_len = 5;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_WM_HZ_OP) | (cmd_len - 2);
- /* see raster_set_gen8_3dstate_wm_hz_op() */
- dw[1] = rs->wm[1];
- dw[2] = 0;
- /* exclusive */
- dw[3] = height << 16 | width;
- dw[4] = rs->wm[2];
-}
-
-static inline void
-gen8_disable_3DSTATE_WM_HZ_OP(struct ilo_builder *builder)
-{
- const uint8_t cmd_len = 5;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_WM_HZ_OP) | (cmd_len - 2);
- dw[1] = 0;
- dw[2] = 0;
- dw[3] = 0;
- dw[4] = 0;
-}
-
-static inline void
-gen8_3DSTATE_WM_CHROMAKEY(struct ilo_builder *builder)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_WM_CHROMAKEY) | (cmd_len - 2);
- dw[1] = 0;
-}
-
-static inline void
-gen7_3DSTATE_PS(struct ilo_builder *builder,
- const struct ilo_state_ps *ps,
- uint32_t kernel_offset,
- struct intel_bo *scratch_bo)
-{
- const uint8_t cmd_len = 8;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 7, 7.5);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_PS) | (cmd_len - 2);
- dw[1] = kernel_offset;
- /* see ps_set_gen7_3DSTATE_PS() */
- dw[2] = ps->ps[2];
- dw[3] = ps->ps[3];
- dw[4] = ps->ps[4];
- dw[5] = ps->ps[5];
- dw[6] = 0; /* kernel 1 */
- dw[7] = 0; /* kernel 2 */
-
- if (ilo_state_ps_get_scratch_size(ps)) {
- ilo_builder_batch_reloc(builder, pos + 3, scratch_bo,
- ps->ps[3], 0);
- }
-}
-
-static inline void
-gen8_3DSTATE_PS(struct ilo_builder *builder,
- const struct ilo_state_ps *ps,
- uint32_t kernel_offset,
- struct intel_bo *scratch_bo)
-{
- const uint8_t cmd_len = 12;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_PS) | (cmd_len - 2);
- dw[1] = kernel_offset;
- dw[2] = 0;
- /* see ps_set_gen8_3DSTATE_PS() */
- dw[3] = ps->ps[0];
- dw[4] = ps->ps[1];
- dw[5] = 0;
- dw[6] = ps->ps[2];
- dw[7] = ps->ps[3];
- dw[8] = 0; /* kernel 1 */
- dw[9] = 0;
- dw[10] = 0; /* kernel 2 */
- dw[11] = 0;
-
- if (ilo_state_ps_get_scratch_size(ps)) {
- ilo_builder_batch_reloc64(builder, pos + 4, scratch_bo,
- ps->ps[1], 0);
- }
-}
-
-static inline void
-gen8_3DSTATE_PS_EXTRA(struct ilo_builder *builder,
- const struct ilo_state_ps *ps)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_PS_EXTRA) | (cmd_len - 2);
- /* see ps_set_gen8_3DSTATE_PS_EXTRA() */
- dw[1] = ps->ps[4];
-}
-
-static inline void
-gen8_3DSTATE_PS_BLEND(struct ilo_builder *builder,
- const struct ilo_state_cc *cc)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_PS_BLEND) | (cmd_len - 2);
- /* see cc_set_gen8_3DSTATE_PS_BLEND() */
- dw[1] = cc->blend[0];
-}
-
-static inline void
-gen6_3DSTATE_CONSTANT_PS(struct ilo_builder *builder,
- const uint32_t *bufs, const int *sizes,
- int num_bufs)
-{
- gen6_3dstate_constant(builder, GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_PS,
- bufs, sizes, num_bufs);
-}
-
-static inline void
-gen7_3DSTATE_CONSTANT_PS(struct ilo_builder *builder,
- const uint32_t *bufs, const int *sizes,
- int num_bufs)
-{
- gen7_3dstate_constant(builder, GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_PS,
- bufs, sizes, num_bufs);
-}
-
-static inline void
-gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(struct ilo_builder *builder,
- uint32_t binding_table)
-{
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_PS,
- binding_table);
-}
-
-static inline void
-gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(struct ilo_builder *builder,
- uint32_t sampler_state)
-{
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_PS,
- sampler_state);
-}
-
-static inline void
-gen6_3DSTATE_MULTISAMPLE(struct ilo_builder *builder,
- const struct ilo_state_raster *rs,
- const struct ilo_state_sample_pattern *pattern,
- uint8_t sample_count)
-{
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ? 4 : 3;
- const uint32_t *packed = (const uint32_t *)
- ilo_state_sample_pattern_get_packed_offsets(pattern,
- builder->dev, sample_count);
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 7.5);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_MULTISAMPLE) | (cmd_len - 2);
- /* see raster_set_gen8_3DSTATE_MULTISAMPLE() */
- dw[1] = rs->sample[0];
-
- /* see sample_pattern_set_gen8_3DSTATE_SAMPLE_PATTERN() */
- dw[2] = (sample_count >= 4) ? packed[0] : 0;
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(7))
- dw[3] = (sample_count >= 8) ? packed[1] : 0;
-}
-
-static inline void
-gen8_3DSTATE_MULTISAMPLE(struct ilo_builder *builder,
- const struct ilo_state_raster *rs)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_MULTISAMPLE) | (cmd_len - 2);
- /* see raster_set_gen8_3DSTATE_MULTISAMPLE() */
- dw[1] = rs->sample[0];
-}
-
-static inline void
-gen8_3DSTATE_SAMPLE_PATTERN(struct ilo_builder *builder,
- const struct ilo_state_sample_pattern *pattern)
-{
- const uint8_t cmd_len = 9;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_SAMPLE_PATTERN) | (cmd_len - 2);
- dw[1] = 0;
- dw[2] = 0;
- dw[3] = 0;
- dw[4] = 0;
- /* see sample_pattern_set_gen8_3DSTATE_SAMPLE_PATTERN() */
- dw[5] = ((const uint32_t *) pattern->pattern_8x)[1];
- dw[6] = ((const uint32_t *) pattern->pattern_8x)[0];
- dw[7] = ((const uint32_t *) pattern->pattern_4x)[0];
- dw[8] = pattern->pattern_1x[0] << 16 |
- ((const uint16_t *) pattern->pattern_2x)[0];
-}
-
-static inline void
-gen6_3DSTATE_SAMPLE_MASK(struct ilo_builder *builder,
- const struct ilo_state_raster *rs)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_SAMPLE_MASK) | (cmd_len - 2);
- /* see raster_set_gen6_3DSTATE_SAMPLE_MASK() */
- dw[1] = rs->sample[1];
-}
-
-static inline void
-gen6_3DSTATE_DRAWING_RECTANGLE(struct ilo_builder *builder,
- unsigned x, unsigned y,
- unsigned width, unsigned height)
-{
- const uint8_t cmd_len = 4;
- unsigned xmax = x + width - 1;
- unsigned ymax = y + height - 1;
- unsigned rect_limit;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) {
- rect_limit = 16383;
- }
- else {
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 230:
- *
- * "[DevSNB] Errata: This field (Clipped Drawing Rectangle Y Min)
- * must be an even number"
- */
- assert(y % 2 == 0);
-
- rect_limit = 8191;
- }
-
- if (x > rect_limit) x = rect_limit;
- if (y > rect_limit) y = rect_limit;
- if (xmax > rect_limit) xmax = rect_limit;
- if (ymax > rect_limit) ymax = rect_limit;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_DRAWING_RECTANGLE) | (cmd_len - 2);
- dw[1] = y << 16 | x;
- dw[2] = ymax << 16 | xmax;
- /*
- * There is no need to set the origin. It is intended to support front
- * buffer rendering.
- */
- dw[3] = 0;
-}
-
-static inline void
-gen6_3DSTATE_POLY_STIPPLE_OFFSET(struct ilo_builder *builder,
- const struct ilo_state_poly_stipple *stipple)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_POLY_STIPPLE_OFFSET) | (cmd_len - 2);
- /* constant */
- dw[1] = 0;
-}
-
-static inline void
-gen6_3DSTATE_POLY_STIPPLE_PATTERN(struct ilo_builder *builder,
- const struct ilo_state_poly_stipple *stipple)
-{
- const uint8_t cmd_len = 33;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_POLY_STIPPLE_PATTERN) | (cmd_len - 2);
- /* see poly_stipple_set_gen6_3DSTATE_POLY_STIPPLE_PATTERN() */
- memcpy(&dw[1], stipple->stipple, sizeof(stipple->stipple));
-}
-
-static inline void
-gen6_3DSTATE_LINE_STIPPLE(struct ilo_builder *builder,
- const struct ilo_state_line_stipple *stipple)
-{
- const uint8_t cmd_len = 3;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_LINE_STIPPLE) | (cmd_len - 2);
- /* see line_stipple_set_gen6_3DSTATE_LINE_STIPPLE() */
- dw[1] = stipple->stipple[0];
- dw[2] = stipple->stipple[1];
-}
-
-static inline void
-gen6_3DSTATE_AA_LINE_PARAMETERS(struct ilo_builder *builder,
- const struct ilo_state_raster *rs)
-{
- const uint8_t cmd_len = 3;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_AA_LINE_PARAMETERS) | (cmd_len - 2);
- /* constant */
- dw[1] = 0 << GEN6_AA_LINE_DW1_BIAS__SHIFT |
- 0 << GEN6_AA_LINE_DW1_SLOPE__SHIFT;
- dw[2] = 0 << GEN6_AA_LINE_DW2_CAP_BIAS__SHIFT |
- 0 << GEN6_AA_LINE_DW2_CAP_SLOPE__SHIFT;
-}
-
-static inline void
-gen6_3DSTATE_DEPTH_BUFFER(struct ilo_builder *builder,
- const struct ilo_state_zs *zs)
-{
- const uint32_t cmd = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ?
- GEN7_RENDER_CMD(3D, 3DSTATE_DEPTH_BUFFER) :
- GEN6_RENDER_CMD(3D, 3DSTATE_DEPTH_BUFFER);
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 8 : 7;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = cmd | (cmd_len - 2);
-
- /*
- * see zs_set_gen6_3DSTATE_DEPTH_BUFFER() and
- * zs_set_gen7_3DSTATE_DEPTH_BUFFER()
- */
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw[1] = zs->depth[0];
- dw[2] = 0;
- dw[3] = 0;
- dw[4] = zs->depth[2];
- dw[5] = zs->depth[3];
- dw[6] = 0;
- dw[7] = zs->depth[4];
-
- dw[5] |= builder->mocs << GEN8_DEPTH_DW5_MOCS__SHIFT;
-
- if (zs->z_vma) {
- ilo_builder_batch_reloc64(builder, pos + 2, zs->z_vma->bo,
- zs->z_vma->bo_offset + zs->depth[1],
- (zs->z_readonly) ? 0 : INTEL_RELOC_WRITE);
- }
- } else {
- dw[1] = zs->depth[0];
- dw[2] = 0;
- dw[3] = zs->depth[2];
- dw[4] = zs->depth[3];
- dw[5] = 0;
- dw[6] = zs->depth[4];
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(7))
- dw[4] |= builder->mocs << GEN7_DEPTH_DW4_MOCS__SHIFT;
- else
- dw[6] |= builder->mocs << GEN6_DEPTH_DW6_MOCS__SHIFT;
-
- if (zs->z_vma) {
- ilo_builder_batch_reloc(builder, pos + 2, zs->z_vma->bo,
- zs->z_vma->bo_offset + zs->depth[1],
- (zs->z_readonly) ? 0 : INTEL_RELOC_WRITE);
- }
- }
-}
-
-static inline void
-gen6_3DSTATE_STENCIL_BUFFER(struct ilo_builder *builder,
- const struct ilo_state_zs *zs)
-{
- const uint32_t cmd = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ?
- GEN7_RENDER_CMD(3D, 3DSTATE_STENCIL_BUFFER) :
- GEN6_RENDER_CMD(3D, 3DSTATE_STENCIL_BUFFER);
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 5 : 3;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = cmd | (cmd_len - 2);
-
- /* see zs_set_gen6_3DSTATE_STENCIL_BUFFER() */
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw[1] = zs->stencil[0];
- dw[2] = 0;
- dw[3] = 0;
- dw[4] = zs->stencil[2];
-
- dw[1] |= builder->mocs << GEN8_STENCIL_DW1_MOCS__SHIFT;
-
- if (zs->s_vma) {
- ilo_builder_batch_reloc64(builder, pos + 2, zs->s_vma->bo,
- zs->s_vma->bo_offset + zs->stencil[1],
- (zs->s_readonly) ? 0 : INTEL_RELOC_WRITE);
- }
- } else {
- dw[1] = zs->stencil[0];
- dw[2] = 0;
-
- dw[1] |= builder->mocs << GEN6_STENCIL_DW1_MOCS__SHIFT;
-
- if (zs->s_vma) {
- ilo_builder_batch_reloc(builder, pos + 2, zs->s_vma->bo,
- zs->s_vma->bo_offset + zs->stencil[1],
- (zs->s_readonly) ? 0 : INTEL_RELOC_WRITE);
- }
- }
-}
-
-static inline void
-gen6_3DSTATE_HIER_DEPTH_BUFFER(struct ilo_builder *builder,
- const struct ilo_state_zs *zs)
-{
- const uint32_t cmd = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ?
- GEN7_RENDER_CMD(3D, 3DSTATE_HIER_DEPTH_BUFFER) :
- GEN6_RENDER_CMD(3D, 3DSTATE_HIER_DEPTH_BUFFER);
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 5 : 3;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = cmd | (cmd_len - 2);
-
- /* see zs_set_gen6_3DSTATE_HIER_DEPTH_BUFFER() */
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw[1] = zs->hiz[0];
- dw[2] = 0;
- dw[3] = 0;
- dw[4] = zs->hiz[2];
-
- dw[1] |= builder->mocs << GEN8_HIZ_DW1_MOCS__SHIFT;
-
- if (zs->hiz_vma) {
- ilo_builder_batch_reloc64(builder, pos + 2, zs->hiz_vma->bo,
- zs->hiz_vma->bo_offset + zs->hiz[1],
- (zs->z_readonly) ? 0 : INTEL_RELOC_WRITE);
- }
- } else {
- dw[1] = zs->hiz[0];
- dw[2] = 0;
-
- dw[1] |= builder->mocs << GEN6_HIZ_DW1_MOCS__SHIFT;
-
- if (zs->hiz_vma) {
- ilo_builder_batch_reloc(builder, pos + 2, zs->hiz_vma->bo,
- zs->hiz_vma->bo_offset + zs->hiz[1],
- (zs->z_readonly) ? 0 : INTEL_RELOC_WRITE);
- }
- }
-}
-
-static inline void
-gen6_3DSTATE_CLEAR_PARAMS(struct ilo_builder *builder,
- uint32_t clear_val)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_CLEAR_PARAMS) |
- GEN6_CLEAR_PARAMS_DW0_VALID |
- (cmd_len - 2);
- dw[1] = clear_val;
-}
-
-static inline void
-gen7_3DSTATE_CLEAR_PARAMS(struct ilo_builder *builder,
- uint32_t clear_val)
-{
- const uint8_t cmd_len = 3;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_CLEAR_PARAMS) | (cmd_len - 2);
- dw[1] = clear_val;
- dw[2] = GEN7_CLEAR_PARAMS_DW2_VALID;
-}
-
-static inline void
-gen6_3DSTATE_VIEWPORT_STATE_POINTERS(struct ilo_builder *builder,
- uint32_t clip_viewport,
- uint32_t sf_viewport,
- uint32_t cc_viewport)
-{
- const uint8_t cmd_len = 4;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_VIEWPORT_STATE_POINTERS) |
- GEN6_VP_PTR_DW0_CLIP_CHANGED |
- GEN6_VP_PTR_DW0_SF_CHANGED |
- GEN6_VP_PTR_DW0_CC_CHANGED |
- (cmd_len - 2);
- dw[1] = clip_viewport;
- dw[2] = sf_viewport;
- dw[3] = cc_viewport;
-}
-
-static inline void
-gen6_3DSTATE_SCISSOR_STATE_POINTERS(struct ilo_builder *builder,
- uint32_t scissor_rect)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_SCISSOR_STATE_POINTERS) |
- (cmd_len - 2);
- dw[1] = scissor_rect;
-}
-
-static inline void
-gen6_3DSTATE_CC_STATE_POINTERS(struct ilo_builder *builder,
- uint32_t blend_state,
- uint32_t depth_stencil_state,
- uint32_t color_calc_state)
-{
- const uint8_t cmd_len = 4;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_CC_STATE_POINTERS) | (cmd_len - 2);
- dw[1] = blend_state | GEN6_CC_PTR_DW1_BLEND_CHANGED;
- dw[2] = depth_stencil_state | GEN6_CC_PTR_DW2_ZS_CHANGED;
- dw[3] = color_calc_state | GEN6_CC_PTR_DW3_CC_CHANGED;
-}
-
-static inline void
-gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(struct ilo_builder *builder,
- uint32_t sf_clip_viewport)
-{
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
- sf_clip_viewport);
-}
-
-static inline void
-gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(struct ilo_builder *builder,
- uint32_t cc_viewport)
-{
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
- cc_viewport);
-}
-
-static inline void
-gen7_3DSTATE_CC_STATE_POINTERS(struct ilo_builder *builder,
- uint32_t color_calc_state)
-{
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8))
- color_calc_state |= 1;
-
- gen7_3dstate_pointer(builder,
- GEN6_RENDER_OPCODE_3DSTATE_CC_STATE_POINTERS, color_calc_state);
-}
-
-static inline void
-gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(struct ilo_builder *builder,
- uint32_t depth_stencil_state)
-{
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
- depth_stencil_state);
-}
-
-static inline void
-gen7_3DSTATE_BLEND_STATE_POINTERS(struct ilo_builder *builder,
- uint32_t blend_state)
-{
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8))
- blend_state |= 1;
-
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_BLEND_STATE_POINTERS,
- blend_state);
-}
-
-static inline uint32_t
-gen6_CLIP_VIEWPORT(struct ilo_builder *builder,
- const struct ilo_state_viewport *vp)
-{
- const int state_align = 32;
- const int state_len = 4 * vp->count;
- uint32_t state_offset, *dw;
- int i;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- state_offset = ilo_builder_dynamic_pointer(builder,
- ILO_BUILDER_ITEM_CLIP_VIEWPORT, state_align, state_len, &dw);
-
- for (i = 0; i < vp->count; i++) {
- /* see viewport_matrix_set_gen7_SF_CLIP_VIEWPORT() */
- dw[0] = vp->sf_clip[i][8];
- dw[1] = vp->sf_clip[i][9];
- dw[2] = vp->sf_clip[i][10];
- dw[3] = vp->sf_clip[i][11];
-
- dw += 4;
- }
-
- return state_offset;
-}
-
-static inline uint32_t
-gen6_SF_VIEWPORT(struct ilo_builder *builder,
- const struct ilo_state_viewport *vp)
-{
- const int state_align = 32;
- const int state_len = 8 * vp->count;
- uint32_t state_offset, *dw;
- int i;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- state_offset = ilo_builder_dynamic_pointer(builder,
- ILO_BUILDER_ITEM_SF_VIEWPORT, state_align, state_len, &dw);
-
- for (i = 0; i < vp->count; i++) {
- /* see viewport_matrix_set_gen7_SF_CLIP_VIEWPORT() */
- memcpy(dw, vp->sf_clip[i], sizeof(*dw) * 8);
-
- dw += 8;
- }
-
- return state_offset;
-}
-
-static inline uint32_t
-gen7_SF_CLIP_VIEWPORT(struct ilo_builder *builder,
- const struct ilo_state_viewport *vp)
-{
- const int state_align = 64;
- const int state_len = 16 * vp->count;
-
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- /* see viewport_matrix_set_gen7_SF_CLIP_VIEWPORT() */
- return ilo_builder_dynamic_write(builder, ILO_BUILDER_ITEM_SF_VIEWPORT,
- state_align, state_len, (const uint32_t *) vp->sf_clip);
-}
-
-static inline uint32_t
-gen6_CC_VIEWPORT(struct ilo_builder *builder,
- const struct ilo_state_viewport *vp)
-{
- const int state_align = 32;
- const int state_len = 2 * vp->count;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- /* see viewport_matrix_set_gen6_CC_VIEWPORT() */
- return ilo_builder_dynamic_write(builder, ILO_BUILDER_ITEM_CC_VIEWPORT,
- state_align, state_len, (const uint32_t *) vp->cc);
-}
-
-static inline uint32_t
-gen6_SCISSOR_RECT(struct ilo_builder *builder,
- const struct ilo_state_viewport *vp)
-{
- const int state_align = 32;
- const int state_len = 2 * vp->count;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- /* see viewport_scissor_set_gen6_SCISSOR_RECT() */
- return ilo_builder_dynamic_write(builder, ILO_BUILDER_ITEM_SCISSOR_RECT,
- state_align, state_len, (const uint32_t *) vp->scissor);
-}
-
-static inline uint32_t
-gen6_COLOR_CALC_STATE(struct ilo_builder *builder,
- const struct ilo_state_cc *cc)
-{
- const int state_align = 64;
- const int state_len = 6;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- /* see cc_params_set_gen6_COLOR_CALC_STATE() */
- return ilo_builder_dynamic_write(builder, ILO_BUILDER_ITEM_COLOR_CALC,
- state_align, state_len, cc->cc);
-}
-
-static inline uint32_t
-gen6_DEPTH_STENCIL_STATE(struct ilo_builder *builder,
- const struct ilo_state_cc *cc)
-{
- const int state_align = 64;
- const int state_len = 3;
-
- ILO_DEV_ASSERT(builder->dev, 6, 7.5);
-
- /* see cc_set_gen6_DEPTH_STENCIL_STATE() */
- return ilo_builder_dynamic_write(builder, ILO_BUILDER_ITEM_DEPTH_STENCIL,
- state_align, state_len, cc->ds);
-}
-
-static inline uint32_t
-gen6_BLEND_STATE(struct ilo_builder *builder,
- const struct ilo_state_cc *cc)
-{
- const int state_align = 64;
- const int state_len = 2 * cc->blend_state_count;
-
- ILO_DEV_ASSERT(builder->dev, 6, 7.5);
-
- if (!state_len)
- return 0;
-
- /* see cc_set_gen6_BLEND_STATE() */
- return ilo_builder_dynamic_write(builder, ILO_BUILDER_ITEM_BLEND,
- state_align, state_len, cc->blend);
-}
-
-static inline uint32_t
-gen8_BLEND_STATE(struct ilo_builder *builder,
- const struct ilo_state_cc *cc)
-{
- const int state_align = 64;
- const int state_len = 1 + 2 * cc->blend_state_count;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- /* see cc_set_gen8_BLEND_STATE() */
- return ilo_builder_dynamic_write(builder, ILO_BUILDER_ITEM_BLEND,
- state_align, state_len, &cc->blend[1]);
-}
-
-#endif /* ILO_BUILDER_3D_BOTTOM_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_BUILDER_3D_TOP_H
-#define ILO_BUILDER_3D_TOP_H
-
-#include "genhw/genhw.h"
-#include "intel_winsys.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-#include "ilo_state_sampler.h"
-#include "ilo_state_shader.h"
-#include "ilo_state_sol.h"
-#include "ilo_state_surface.h"
-#include "ilo_state_urb.h"
-#include "ilo_state_vf.h"
-#include "ilo_vma.h"
-#include "ilo_builder.h"
-
-static inline void
-gen6_3DSTATE_URB(struct ilo_builder *builder,
- const struct ilo_state_urb *urb)
-{
- const uint8_t cmd_len = 3;
- uint32_t *dw;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_URB) | (cmd_len - 2);
- /* see urb_set_gen6_3DSTATE_URB() */
- dw[1] = urb->urb[0];
- dw[2] = urb->urb[1];
-}
-
-static inline void
-gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(struct ilo_builder *builder,
- const struct ilo_state_urb *urb)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_PUSH_CONSTANT_ALLOC_VS) |
- (cmd_len - 2);
- /* see urb_set_gen7_3dstate_push_constant_alloc() */
- dw[1] = urb->pcb[0];
-}
-
-static inline void
-gen7_3DSTATE_PUSH_CONSTANT_ALLOC_HS(struct ilo_builder *builder,
- const struct ilo_state_urb *urb)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_PUSH_CONSTANT_ALLOC_HS) |
- (cmd_len - 2);
- /* see urb_set_gen7_3dstate_push_constant_alloc() */
- dw[1] = urb->pcb[1];
-}
-
-static inline void
-gen7_3DSTATE_PUSH_CONSTANT_ALLOC_DS(struct ilo_builder *builder,
- const struct ilo_state_urb *urb)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_PUSH_CONSTANT_ALLOC_DS) |
- (cmd_len - 2);
- /* see urb_set_gen7_3dstate_push_constant_alloc() */
- dw[1] = urb->pcb[2];
-}
-
-static inline void
-gen7_3DSTATE_PUSH_CONSTANT_ALLOC_GS(struct ilo_builder *builder,
- const struct ilo_state_urb *urb)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_PUSH_CONSTANT_ALLOC_GS) |
- (cmd_len - 2);
- /* see urb_set_gen7_3dstate_push_constant_alloc() */
- dw[1] = urb->pcb[3];
-}
-
-static inline void
-gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(struct ilo_builder *builder,
- const struct ilo_state_urb *urb)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_PUSH_CONSTANT_ALLOC_PS) |
- (cmd_len - 2);
- /* see urb_set_gen7_3dstate_push_constant_alloc() */
- dw[1] = urb->pcb[4];
-}
-
-static inline void
-gen7_3DSTATE_URB_VS(struct ilo_builder *builder,
- const struct ilo_state_urb *urb)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_URB_VS) | (cmd_len - 2);
- /* see urb_set_gen7_3dstate_push_constant_alloc() */
- dw[1] = urb->urb[0];
-}
-
-static inline void
-gen7_3DSTATE_URB_HS(struct ilo_builder *builder,
- const struct ilo_state_urb *urb)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_URB_HS) | (cmd_len - 2);
- /* see urb_set_gen7_3dstate_push_constant_alloc() */
- dw[1] = urb->urb[1];
-}
-
-static inline void
-gen7_3DSTATE_URB_DS(struct ilo_builder *builder,
- const struct ilo_state_urb *urb)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_URB_DS) | (cmd_len - 2);
- /* see urb_set_gen7_3dstate_push_constant_alloc() */
- dw[1] = urb->urb[2];
-}
-
-static inline void
-gen7_3DSTATE_URB_GS(struct ilo_builder *builder,
- const struct ilo_state_urb *urb)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_URB_GS) | (cmd_len - 2);
- /* see urb_set_gen7_3dstate_push_constant_alloc() */
- dw[1] = urb->urb[3];
-}
-
-static inline void
-gen75_3DSTATE_VF(struct ilo_builder *builder,
- const struct ilo_state_vf *vf)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7.5, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- /* see vf_params_set_gen75_3DSTATE_VF() */
- dw[0] = GEN75_RENDER_CMD(3D, 3DSTATE_VF) | (cmd_len - 2) |
- vf->cut[0];
- dw[1] = vf->cut[1];
-}
-
-static inline void
-gen6_3DSTATE_VF_STATISTICS(struct ilo_builder *builder,
- bool enable)
-{
- const uint8_t cmd_len = 1;
- const uint32_t dw0 = GEN6_RENDER_CMD(SINGLE_DW, 3DSTATE_VF_STATISTICS) |
- enable;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- ilo_builder_batch_write(builder, cmd_len, &dw0);
-}
-
-static inline void
-gen8_3DSTATE_VF_TOPOLOGY(struct ilo_builder *builder,
- enum gen_3dprim_type topology)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_VF_TOPOLOGY) | (cmd_len - 2);
- dw[1] = topology << GEN8_TOPOLOGY_DW1_TYPE__SHIFT;
-}
-
-static inline void
-gen8_3DSTATE_VF_INSTANCING(struct ilo_builder *builder,
- const struct ilo_state_vf *vf,
- uint32_t attr)
-{
- const uint8_t cmd_len = 3;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_VF_INSTANCING) | (cmd_len - 2);
- dw[1] = attr << GEN8_INSTANCING_DW1_VE_INDEX__SHIFT;
- dw[2] = 0;
- /* see vf_set_gen8_3DSTATE_VF_INSTANCING() */
- if (attr >= vf->internal_ve_count) {
- attr -= vf->internal_ve_count;
-
- dw[1] |= vf->user_instancing[attr][0];
- dw[2] |= vf->user_instancing[attr][1];
- }
-}
-
-static inline void
-gen8_3DSTATE_VF_SGVS(struct ilo_builder *builder,
- const struct ilo_state_vf *vf)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_VF_SGVS) | (cmd_len - 2);
- /* see vf_params_set_gen8_3DSTATE_VF_SGVS() */
- dw[1] = vf->sgvs[0];
-}
-
-static inline void
-gen6_3DSTATE_VERTEX_BUFFERS(struct ilo_builder *builder,
- const struct ilo_state_vf *vf,
- const struct ilo_state_vertex_buffer *vb,
- unsigned vb_count)
-{
- uint8_t cmd_len;
- uint32_t *dw;
- unsigned pos, i;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 82:
- *
- * "From 1 to 33 VBs can be specified..."
- */
- assert(vb_count <= 33);
-
- if (!vb_count)
- return;
-
- cmd_len = 1 + 4 * vb_count;
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_VERTEX_BUFFERS) | (cmd_len - 2);
- dw++;
- pos++;
-
- for (i = 0; i < vb_count; i++) {
- const struct ilo_state_vertex_buffer *b = &vb[i];
-
- /* see vertex_buffer_set_gen8_vertex_buffer_state() */
- dw[0] = b->vb[0] |
- i << GEN6_VB_DW0_INDEX__SHIFT;
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8))
- dw[0] |= builder->mocs << GEN8_VB_DW0_MOCS__SHIFT;
- else
- dw[0] |= builder->mocs << GEN6_VB_DW0_MOCS__SHIFT;
-
- dw[1] = 0;
- dw[2] = 0;
- dw[3] = 0;
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- if (b->vma) {
- ilo_builder_batch_reloc64(builder, pos + 1, b->vma->bo,
- b->vma->bo_offset + b->vb[1], 0);
- }
-
- dw[3] |= b->vb[2];
- } else {
- const int8_t elem = vf->vb_to_first_elem[i];
-
- /* see vf_set_gen6_vertex_buffer_state() */
- if (elem >= 0) {
- dw[0] |= vf->user_instancing[elem][0];
- dw[3] |= vf->user_instancing[elem][1];
- }
-
- if (b->vma) {
- ilo_builder_batch_reloc(builder, pos + 1, b->vma->bo,
- b->vma->bo_offset + b->vb[1], 0);
- ilo_builder_batch_reloc(builder, pos + 2, b->vma->bo,
- b->vma->bo_offset + b->vb[2], 0);
- }
- }
-
- dw += 4;
- pos += 4;
- }
-}
-
-/* the user vertex buffer must be uploaded with gen6_user_vertex_buffer() */
-static inline void
-gen6_user_3DSTATE_VERTEX_BUFFERS(struct ilo_builder *builder,
- uint32_t vb_begin, uint32_t vb_end,
- uint32_t stride)
-{
- const struct ilo_builder_writer *bat =
- &builder->writers[ILO_BUILDER_WRITER_BATCH];
- const uint8_t cmd_len = 1 + 4;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 7.5);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_VERTEX_BUFFERS) | (cmd_len - 2);
- dw++;
- pos++;
-
- /* VERTEX_BUFFER_STATE */
- dw[0] = 0 << GEN6_VB_DW0_INDEX__SHIFT |
- GEN6_VB_DW0_ACCESS_VERTEXDATA |
- stride << GEN6_VB_DW0_PITCH__SHIFT;
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(7))
- dw[0] |= GEN7_VB_DW0_ADDR_MODIFIED;
-
- dw[3] = 0;
-
- ilo_builder_batch_reloc(builder, pos + 1, bat->bo, vb_begin, 0);
- ilo_builder_batch_reloc(builder, pos + 2, bat->bo, vb_end, 0);
-}
-
-static inline void
-gen6_3DSTATE_VERTEX_ELEMENTS(struct ilo_builder *builder,
- const struct ilo_state_vf *vf)
-{
- uint8_t cmd_len;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- cmd_len = 1 + 2 * (vf->internal_ve_count + vf->user_ve_count);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_VERTEX_ELEMENTS) | (cmd_len - 2);
- dw++;
-
- /*
- * see vf_params_set_gen6_internal_ve() and
- * vf_set_gen6_3DSTATE_VERTEX_ELEMENTS()
- */
- if (vf->internal_ve_count) {
- memcpy(dw, vf->internal_ve,
- sizeof(vf->internal_ve[0]) * vf->internal_ve_count);
- dw += 2 * vf->internal_ve_count;
- }
-
- memcpy(dw, vf->user_ve, sizeof(vf->user_ve[0]) * vf->user_ve_count);
-}
-
-static inline void
-gen6_3DSTATE_INDEX_BUFFER(struct ilo_builder *builder,
- const struct ilo_state_vf *vf,
- const struct ilo_state_index_buffer *ib)
-{
- const uint8_t cmd_len = 3;
- uint32_t dw0, *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 7.5);
-
- dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_INDEX_BUFFER) | (cmd_len - 2) |
- builder->mocs << GEN6_IB_DW0_MOCS__SHIFT;
-
- /*
- * see index_buffer_set_gen8_3DSTATE_INDEX_BUFFER() and
- * vf_params_set_gen6_3dstate_index_buffer()
- */
- dw0 |= ib->ib[0];
- if (ilo_dev_gen(builder->dev) <= ILO_GEN(7))
- dw0 |= vf->cut[0];
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = dw0;
- if (ib->vma) {
- ilo_builder_batch_reloc(builder, pos + 1, ib->vma->bo,
- ib->vma->bo_offset + ib->ib[1], 0);
- ilo_builder_batch_reloc(builder, pos + 2, ib->vma->bo,
- ib->vma->bo_offset + ib->ib[2], 0);
- } else {
- dw[1] = 0;
- dw[2] = 0;
- }
-}
-
-static inline void
-gen8_3DSTATE_INDEX_BUFFER(struct ilo_builder *builder,
- const struct ilo_state_vf *vf,
- const struct ilo_state_index_buffer *ib)
-{
- const uint8_t cmd_len = 5;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_INDEX_BUFFER) | (cmd_len - 2);
- /* see index_buffer_set_gen8_3DSTATE_INDEX_BUFFER() */
- dw[1] = ib->ib[0] |
- builder->mocs << GEN8_IB_DW1_MOCS__SHIFT;
-
- if (ib->vma) {
- ilo_builder_batch_reloc64(builder, pos + 2, ib->vma->bo,
- ib->vma->bo_offset + ib->ib[1], 0);
- } else {
- dw[2] = 0;
- dw[3] = 0;
- }
-
- dw[4] = ib->ib[2];
-}
-
-static inline void
-gen6_3DSTATE_VS(struct ilo_builder *builder,
- const struct ilo_state_vs *vs,
- uint32_t kernel_offset,
- struct intel_bo *scratch_bo)
-{
- const uint8_t cmd_len = 6;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 7.5);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_VS) | (cmd_len - 2);
- dw[1] = kernel_offset;
- /* see vs_set_gen6_3DSTATE_VS() */
- dw[2] = vs->vs[0];
- dw[3] = vs->vs[1];
- dw[4] = vs->vs[2];
- dw[5] = vs->vs[3];
-
- if (ilo_state_vs_get_scratch_size(vs)) {
- ilo_builder_batch_reloc(builder, pos + 3, scratch_bo,
- vs->vs[1], 0);
- }
-}
-
-static inline void
-gen8_3DSTATE_VS(struct ilo_builder *builder,
- const struct ilo_state_vs *vs,
- uint32_t kernel_offset,
- struct intel_bo *scratch_bo)
-{
- const uint8_t cmd_len = 9;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_VS) | (cmd_len - 2);
- dw[1] = kernel_offset;
- dw[2] = 0;
- /* see vs_set_gen6_3DSTATE_VS() */
- dw[3] = vs->vs[0];
- dw[4] = vs->vs[1];
- dw[5] = 0;
- dw[6] = vs->vs[2];
- dw[7] = vs->vs[3];
- dw[8] = vs->vs[4];
-
- if (ilo_state_vs_get_scratch_size(vs)) {
- ilo_builder_batch_reloc64(builder, pos + 4, scratch_bo,
- vs->vs[1], 0);
- }
-}
-
-static inline void
-gen7_3DSTATE_HS(struct ilo_builder *builder,
- const struct ilo_state_hs *hs,
- uint32_t kernel_offset,
- struct intel_bo *scratch_bo)
-{
- const uint8_t cmd_len = 7;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 7, 7.5);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_HS) | (cmd_len - 2);
- /* see hs_set_gen7_3DSTATE_HS() */
- dw[1] = hs->hs[0];
- dw[2] = hs->hs[1];
- dw[3] = kernel_offset;
- dw[4] = hs->hs[2];
- dw[5] = hs->hs[3];
- dw[6] = 0;
-
- if (ilo_state_hs_get_scratch_size(hs)) {
- ilo_builder_batch_reloc(builder, pos + 4, scratch_bo,
- hs->hs[2], 0);
- }
-}
-
-static inline void
-gen8_3DSTATE_HS(struct ilo_builder *builder,
- const struct ilo_state_hs *hs,
- uint32_t kernel_offset,
- struct intel_bo *scratch_bo)
-{
- const uint8_t cmd_len = 9;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_HS) | (cmd_len - 2);
- /* see hs_set_gen7_3DSTATE_HS() */
- dw[1] = hs->hs[0];
- dw[2] = hs->hs[1];
- dw[3] = kernel_offset;
- dw[4] = 0;
- dw[5] = hs->hs[2];
- dw[6] = 0;
- dw[7] = hs->hs[3];
- dw[8] = 0;
-
- if (ilo_state_hs_get_scratch_size(hs)) {
- ilo_builder_batch_reloc64(builder, pos + 5, scratch_bo,
- hs->hs[2], 0);
- }
-}
-
-static inline void
-gen7_3DSTATE_TE(struct ilo_builder *builder,
- const struct ilo_state_ds *ds)
-{
- const uint8_t cmd_len = 4;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_TE) | (cmd_len - 2);
- /* see ds_set_gen7_3DSTATE_TE() */
- dw[1] = ds->te[0];
- dw[2] = ds->te[1];
- dw[3] = ds->te[2];
-}
-
-static inline void
-gen7_3DSTATE_DS(struct ilo_builder *builder,
- const struct ilo_state_ds *ds,
- uint32_t kernel_offset,
- struct intel_bo *scratch_bo)
-{
- const uint8_t cmd_len = 6;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 7, 7.5);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_DS) | (cmd_len - 2);
- /* see ds_set_gen7_3DSTATE_DS() */
- dw[1] = kernel_offset;
- dw[2] = ds->ds[0];
- dw[3] = ds->ds[1];
- dw[4] = ds->ds[2];
- dw[5] = ds->ds[3];
-
- if (ilo_state_ds_get_scratch_size(ds)) {
- ilo_builder_batch_reloc(builder, pos + 3, scratch_bo,
- ds->ds[1], 0);
- }
-}
-
-static inline void
-gen8_3DSTATE_DS(struct ilo_builder *builder,
- const struct ilo_state_ds *ds,
- uint32_t kernel_offset,
- struct intel_bo *scratch_bo)
-{
- const uint8_t cmd_len = 9;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_DS) | (cmd_len - 2);
- /* see ds_set_gen7_3DSTATE_DS() */
- dw[1] = kernel_offset;
- dw[2] = 0;
- dw[3] = ds->ds[0];
- dw[4] = ds->ds[1];
- dw[5] = 0;
- dw[6] = ds->ds[2];
- dw[7] = ds->ds[3];
- dw[8] = ds->ds[4];
-
- if (ilo_state_ds_get_scratch_size(ds)) {
- ilo_builder_batch_reloc64(builder, pos + 4, scratch_bo,
- ds->ds[1], 0);
- }
-}
-
-static inline void
-gen6_3DSTATE_GS(struct ilo_builder *builder,
- const struct ilo_state_gs *gs,
- uint32_t kernel_offset,
- struct intel_bo *scratch_bo)
-{
- const uint8_t cmd_len = 7;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_GS) | (cmd_len - 2);
- dw[1] = kernel_offset;
- /* see gs_set_gen6_3DSTATE_GS() */
- dw[2] = gs->gs[0];
- dw[3] = gs->gs[1];
- dw[4] = gs->gs[2];
- dw[5] = gs->gs[3];
- dw[6] = gs->gs[4];
-
- if (ilo_state_gs_get_scratch_size(gs)) {
- ilo_builder_batch_reloc(builder, pos + 3, scratch_bo,
- gs->gs[1], 0);
- }
-}
-
-static inline void
-gen6_3DSTATE_GS_SVB_INDEX(struct ilo_builder *builder,
- int index, unsigned svbi,
- unsigned max_svbi,
- bool load_vertex_count)
-{
- const uint8_t cmd_len = 4;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
- assert(index >= 0 && index < 4);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_GS_SVB_INDEX) | (cmd_len - 2);
-
- dw[1] = index << GEN6_SVBI_DW1_INDEX__SHIFT;
- if (load_vertex_count)
- dw[1] |= GEN6_SVBI_DW1_LOAD_INTERNAL_VERTEX_COUNT;
-
- dw[2] = svbi;
- dw[3] = max_svbi;
-}
-
-static inline void
-gen7_3DSTATE_GS(struct ilo_builder *builder,
- const struct ilo_state_gs *gs,
- uint32_t kernel_offset,
- struct intel_bo *scratch_bo)
-{
- const uint8_t cmd_len = 7;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 7, 7.5);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_GS) | (cmd_len - 2);
- dw[1] = kernel_offset;
- /* see gs_set_gen7_3DSTATE_GS() */
- dw[2] = gs->gs[0];
- dw[3] = gs->gs[1];
- dw[4] = gs->gs[2];
- dw[5] = gs->gs[3];
- dw[6] = 0;
-
- if (ilo_state_gs_get_scratch_size(gs)) {
- ilo_builder_batch_reloc(builder, pos + 3, scratch_bo,
- gs->gs[1], 0);
- }
-}
-
-static inline void
-gen8_3DSTATE_GS(struct ilo_builder *builder,
- const struct ilo_state_gs *gs,
- uint32_t kernel_offset,
- struct intel_bo *scratch_bo)
-{
- const uint8_t cmd_len = 10;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_GS) | (cmd_len - 2);
- dw[1] = kernel_offset;
- dw[2] = 0;
- /* see gs_set_gen7_3DSTATE_GS() */
- dw[3] = gs->gs[0];
- dw[4] = gs->gs[1];
- dw[5] = 0;
- dw[6] = gs->gs[2];
- dw[7] = gs->gs[3];
- dw[8] = 0;
- dw[9] = gs->gs[4];
-
- if (ilo_state_gs_get_scratch_size(gs)) {
- ilo_builder_batch_reloc64(builder, pos + 4, scratch_bo,
- gs->gs[1], 0);
- }
-}
-
-static inline void
-gen7_3DSTATE_STREAMOUT(struct ilo_builder *builder,
- const struct ilo_state_sol *sol)
-{
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 5 : 3;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_STREAMOUT) | (cmd_len - 2);
- /* see sol_set_gen7_3DSTATE_STREAMOUT() */
- dw[1] = sol->streamout[0];
- dw[2] = sol->streamout[1];
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw[3] = sol->strides[1] << GEN8_SO_DW3_BUFFER1_PITCH__SHIFT |
- sol->strides[0] << GEN8_SO_DW3_BUFFER0_PITCH__SHIFT;
- dw[4] = sol->strides[3] << GEN8_SO_DW4_BUFFER3_PITCH__SHIFT |
- sol->strides[2] << GEN8_SO_DW4_BUFFER2_PITCH__SHIFT;
- }
-}
-
-static inline void
-gen7_3DSTATE_SO_DECL_LIST(struct ilo_builder *builder,
- const struct ilo_state_sol *sol)
-{
- /*
- * Note that "DWord Length" has 9 bits for this command and the type of
- * cmd_len cannot be uint8_t.
- */
- uint16_t cmd_len;
- int cmd_decl_count;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(7.5)) {
- cmd_decl_count = sol->decl_count;
- } else {
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 201:
- *
- * "Errata: All 128 decls for all four streams must be included
- * whenever this command is issued. The "Num Entries [n]" fields
- * still contain the actual numbers of valid decls."
- */
- cmd_decl_count = 128;
- }
-
- cmd_len = 3 + 2 * cmd_decl_count;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_SO_DECL_LIST) | (cmd_len - 2);
- /* see sol_set_gen7_3DSTATE_SO_DECL_LIST() */
- dw[1] = sol->so_decl[0];
- dw[2] = sol->so_decl[1];
- memcpy(&dw[3], sol->decl, sizeof(sol->decl[0]) * sol->decl_count);
-
- if (sol->decl_count < cmd_decl_count) {
- memset(&dw[3 + 2 * sol->decl_count], 0, sizeof(sol->decl[0]) *
- cmd_decl_count - sol->decl_count);
- }
-}
-
-static inline void
-gen7_3DSTATE_SO_BUFFER(struct ilo_builder *builder,
- const struct ilo_state_sol *sol,
- const struct ilo_state_sol_buffer *sb,
- uint8_t buffer)
-{
- const uint8_t cmd_len = 4;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 7, 7.5);
-
- assert(buffer < ILO_STATE_SOL_MAX_BUFFER_COUNT);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_SO_BUFFER) | (cmd_len - 2);
- /* see sol_buffer_set_gen7_3dstate_so_buffer() */
- dw[1] = buffer << GEN7_SO_BUF_DW1_INDEX__SHIFT |
- builder->mocs << GEN7_SO_BUF_DW1_MOCS__SHIFT |
- sol->strides[buffer] << GEN7_SO_BUF_DW1_PITCH__SHIFT;
-
- if (sb->vma) {
- ilo_builder_batch_reloc(builder, pos + 2, sb->vma->bo,
- sb->vma->bo_offset + sb->so_buf[0], INTEL_RELOC_WRITE);
- ilo_builder_batch_reloc(builder, pos + 3, sb->vma->bo,
- sb->vma->bo_offset + sb->so_buf[1], INTEL_RELOC_WRITE);
- } else {
- dw[2] = 0;
- dw[3] = 0;
- }
-}
-
-static inline void
-gen8_3DSTATE_SO_BUFFER(struct ilo_builder *builder,
- const struct ilo_state_sol *sol,
- const struct ilo_state_sol_buffer *sb,
- uint8_t buffer)
-{
- const uint8_t cmd_len = 8;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_SO_BUFFER) | (cmd_len - 2);
- /* see sol_buffer_set_gen8_3dstate_so_buffer() */
- dw[1] = sb->so_buf[0] |
- buffer << GEN7_SO_BUF_DW1_INDEX__SHIFT |
- builder->mocs << GEN8_SO_BUF_DW1_MOCS__SHIFT;
-
- if (sb->vma) {
- ilo_builder_batch_reloc64(builder, pos + 2, sb->vma->bo,
- sb->vma->bo_offset + sb->so_buf[1], INTEL_RELOC_WRITE);
- } else {
- dw[2] = 0;
- dw[3] = 0;
- }
-
- dw[4] = sb->so_buf[2];
-
- if (sb->write_offset_vma) {
- ilo_builder_batch_reloc64(builder, pos + 5, sb->write_offset_vma->bo,
- sb->write_offset_vma->bo_offset + sizeof(uint32_t) * buffer,
- INTEL_RELOC_WRITE);
- } else {
- dw[5] = 0;
- dw[6] = 0;
- }
-
- dw[7] = sb->so_buf[3];
-}
-
-static inline void
-gen6_3DSTATE_BINDING_TABLE_POINTERS(struct ilo_builder *builder,
- uint32_t vs_binding_table,
- uint32_t gs_binding_table,
- uint32_t ps_binding_table)
-{
- const uint8_t cmd_len = 4;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_BINDING_TABLE_POINTERS) |
- GEN6_BINDING_TABLE_PTR_DW0_VS_CHANGED |
- GEN6_BINDING_TABLE_PTR_DW0_GS_CHANGED |
- GEN6_BINDING_TABLE_PTR_DW0_PS_CHANGED |
- (cmd_len - 2);
- dw[1] = vs_binding_table;
- dw[2] = gs_binding_table;
- dw[3] = ps_binding_table;
-}
-
-static inline void
-gen6_3DSTATE_SAMPLER_STATE_POINTERS(struct ilo_builder *builder,
- uint32_t vs_sampler_state,
- uint32_t gs_sampler_state,
- uint32_t ps_sampler_state)
-{
- const uint8_t cmd_len = 4;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_SAMPLER_STATE_POINTERS) |
- GEN6_SAMPLER_PTR_DW0_VS_CHANGED |
- GEN6_SAMPLER_PTR_DW0_GS_CHANGED |
- GEN6_SAMPLER_PTR_DW0_PS_CHANGED |
- (cmd_len - 2);
- dw[1] = vs_sampler_state;
- dw[2] = gs_sampler_state;
- dw[3] = ps_sampler_state;
-}
-
-static inline void
-gen7_3dstate_pointer(struct ilo_builder *builder,
- int subop, uint32_t pointer)
-{
- const uint32_t cmd = GEN6_RENDER_TYPE_RENDER |
- GEN6_RENDER_SUBTYPE_3D |
- subop;
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = cmd | (cmd_len - 2);
- dw[1] = pointer;
-}
-
-static inline void
-gen7_3DSTATE_BINDING_TABLE_POINTERS_VS(struct ilo_builder *builder,
- uint32_t binding_table)
-{
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_VS,
- binding_table);
-}
-
-static inline void
-gen7_3DSTATE_BINDING_TABLE_POINTERS_HS(struct ilo_builder *builder,
- uint32_t binding_table)
-{
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_HS,
- binding_table);
-}
-
-static inline void
-gen7_3DSTATE_BINDING_TABLE_POINTERS_DS(struct ilo_builder *builder,
- uint32_t binding_table)
-{
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_DS,
- binding_table);
-}
-
-static inline void
-gen7_3DSTATE_BINDING_TABLE_POINTERS_GS(struct ilo_builder *builder,
- uint32_t binding_table)
-{
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_GS,
- binding_table);
-}
-
-static inline void
-gen7_3DSTATE_SAMPLER_STATE_POINTERS_VS(struct ilo_builder *builder,
- uint32_t sampler_state)
-{
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_VS,
- sampler_state);
-}
-
-static inline void
-gen7_3DSTATE_SAMPLER_STATE_POINTERS_HS(struct ilo_builder *builder,
- uint32_t sampler_state)
-{
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_HS,
- sampler_state);
-}
-
-static inline void
-gen7_3DSTATE_SAMPLER_STATE_POINTERS_DS(struct ilo_builder *builder,
- uint32_t sampler_state)
-{
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_DS,
- sampler_state);
-}
-
-static inline void
-gen7_3DSTATE_SAMPLER_STATE_POINTERS_GS(struct ilo_builder *builder,
- uint32_t sampler_state)
-{
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_GS,
- sampler_state);
-}
-
-static inline void
-gen6_3dstate_constant(struct ilo_builder *builder, int subop,
- const uint32_t *bufs, const int *sizes,
- int num_bufs)
-{
- const uint32_t cmd = GEN6_RENDER_TYPE_RENDER |
- GEN6_RENDER_SUBTYPE_3D |
- subop;
- const uint8_t cmd_len = 5;
- unsigned buf_enabled = 0x0;
- uint32_t buf_dw[4], *dw;
- int max_read_length, total_read_length;
- int i;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- assert(num_bufs <= 4);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 138:
- *
- * "(3DSTATE_CONSTANT_VS) The sum of all four read length fields (each
- * incremented to represent the actual read length) must be less than
- * or equal to 32"
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 161:
- *
- * "(3DSTATE_CONSTANT_GS) The sum of all four read length fields (each
- * incremented to represent the actual read length) must be less than
- * or equal to 64"
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 287:
- *
- * "(3DSTATE_CONSTANT_PS) The sum of all four read length fields (each
- * incremented to represent the actual read length) must be less than
- * or equal to 64"
- */
- switch (subop) {
- case GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_VS:
- max_read_length = 32;
- break;
- case GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_GS:
- case GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_PS:
- max_read_length = 64;
- break;
- default:
- assert(!"unknown pcb subop");
- max_read_length = 0;
- break;
- }
-
- total_read_length = 0;
- for (i = 0; i < 4; i++) {
- if (i < num_bufs && sizes[i]) {
- /* in 256-bit units */
- const int read_len = (sizes[i] + 31) / 32;
-
- assert(bufs[i] % 32 == 0);
- assert(read_len <= 32);
-
- buf_enabled |= 1 << i;
- buf_dw[i] = bufs[i] | (read_len - 1);
-
- total_read_length += read_len;
- } else {
- buf_dw[i] = 0;
- }
- }
-
- assert(total_read_length <= max_read_length);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = cmd | (cmd_len - 2) |
- buf_enabled << GEN6_CONSTANT_DW0_BUFFER_ENABLES__SHIFT |
- builder->mocs << GEN6_CONSTANT_DW0_MOCS__SHIFT;
-
- memcpy(&dw[1], buf_dw, sizeof(buf_dw));
-}
-
-static inline void
-gen6_3DSTATE_CONSTANT_VS(struct ilo_builder *builder,
- const uint32_t *bufs, const int *sizes,
- int num_bufs)
-{
- gen6_3dstate_constant(builder, GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_VS,
- bufs, sizes, num_bufs);
-}
-
-static inline void
-gen6_3DSTATE_CONSTANT_GS(struct ilo_builder *builder,
- const uint32_t *bufs, const int *sizes,
- int num_bufs)
-{
- gen6_3dstate_constant(builder, GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_GS,
- bufs, sizes, num_bufs);
-}
-
-static inline void
-gen7_3dstate_constant(struct ilo_builder *builder,
- int subop,
- const uint32_t *bufs, const int *sizes,
- int num_bufs)
-{
- const uint32_t cmd = GEN6_RENDER_TYPE_RENDER |
- GEN6_RENDER_SUBTYPE_3D |
- subop;
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 11 : 7;
- uint32_t payload[6], *dw;
- int total_read_length, i;
-
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- /* VS, HS, DS, GS, and PS variants */
- assert(subop >= GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_VS &&
- subop <= GEN7_RENDER_OPCODE_3DSTATE_CONSTANT_DS &&
- subop != GEN6_RENDER_OPCODE_3DSTATE_SAMPLE_MASK);
-
- assert(num_bufs <= 4);
-
- payload[0] = 0;
- payload[1] = 0;
-
- total_read_length = 0;
- for (i = 0; i < 4; i++) {
- int read_len;
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 112:
- *
- * "Constant buffers must be enabled in order from Constant Buffer 0
- * to Constant Buffer 3 within this command. For example, it is
- * not allowed to enable Constant Buffer 1 by programming a
- * non-zero value in the VS Constant Buffer 1 Read Length without a
- * non-zero value in VS Constant Buffer 0 Read Length."
- */
- if (i >= num_bufs || !sizes[i]) {
- for (; i < 4; i++) {
- assert(i >= num_bufs || !sizes[i]);
- payload[2 + i] = 0;
- }
- break;
- }
-
- /* read lengths are in 256-bit units */
- read_len = (sizes[i] + 31) / 32;
- /* the lower 5 bits are used for memory object control state */
- assert(bufs[i] % 32 == 0);
-
- payload[i / 2] |= read_len << ((i % 2) ? 16 : 0);
- payload[2 + i] = bufs[i];
-
- total_read_length += read_len;
- }
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 113:
- *
- * "The sum of all four read length fields must be less than or equal
- * to the size of 64"
- */
- assert(total_read_length <= 64);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = cmd | (cmd_len - 2);
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw[1] = payload[0];
- dw[2] = payload[1];
- dw[3] = payload[2];
- dw[4] = 0;
- dw[5] = payload[3];
- dw[6] = 0;
- dw[7] = payload[4];
- dw[8] = 0;
- dw[9] = payload[5];
- dw[10] = 0;
- } else {
- payload[2] |= builder->mocs << GEN7_CONSTANT_DW_ADDR_MOCS__SHIFT;
-
- memcpy(&dw[1], payload, sizeof(payload));
- }
-}
-
-static inline void
-gen7_3DSTATE_CONSTANT_VS(struct ilo_builder *builder,
- const uint32_t *bufs, const int *sizes,
- int num_bufs)
-{
- gen7_3dstate_constant(builder, GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_VS,
- bufs, sizes, num_bufs);
-}
-
-static inline void
-gen7_3DSTATE_CONSTANT_HS(struct ilo_builder *builder,
- const uint32_t *bufs, const int *sizes,
- int num_bufs)
-{
- gen7_3dstate_constant(builder, GEN7_RENDER_OPCODE_3DSTATE_CONSTANT_HS,
- bufs, sizes, num_bufs);
-}
-
-static inline void
-gen7_3DSTATE_CONSTANT_DS(struct ilo_builder *builder,
- const uint32_t *bufs, const int *sizes,
- int num_bufs)
-{
- gen7_3dstate_constant(builder, GEN7_RENDER_OPCODE_3DSTATE_CONSTANT_DS,
- bufs, sizes, num_bufs);
-}
-
-static inline void
-gen7_3DSTATE_CONSTANT_GS(struct ilo_builder *builder,
- const uint32_t *bufs, const int *sizes,
- int num_bufs)
-{
- gen7_3dstate_constant(builder, GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_GS,
- bufs, sizes, num_bufs);
-}
-
-static inline uint32_t
-gen6_BINDING_TABLE_STATE(struct ilo_builder *builder,
- const uint32_t *surface_states,
- int num_surface_states)
-{
- const int state_align = 32;
- const int state_len = num_surface_states;
- uint32_t state_offset, *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 69:
- *
- * "It is stored as an array of up to 256 elements..."
- */
- assert(num_surface_states <= 256);
-
- if (!num_surface_states)
- return 0;
-
- state_offset = ilo_builder_surface_pointer(builder,
- ILO_BUILDER_ITEM_BINDING_TABLE, state_align, state_len, &dw);
- memcpy(dw, surface_states, state_len << 2);
-
- return state_offset;
-}
-
-static inline uint32_t
-gen6_SURFACE_STATE(struct ilo_builder *builder,
- const struct ilo_state_surface *surf)
-{
- int state_align, state_len;
- uint32_t state_offset, *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- state_align = 64;
- state_len = 13;
-
- state_offset = ilo_builder_surface_pointer(builder,
- ILO_BUILDER_ITEM_SURFACE, state_align, state_len, &dw);
- memcpy(dw, surf->surface, state_len << 2);
-
- if (surf->vma) {
- const uint32_t mocs = (surf->scanout) ?
- (GEN8_MOCS_MT_PTE | GEN8_MOCS_CT_L3) : builder->mocs;
-
- dw[1] |= mocs << GEN8_SURFACE_DW1_MOCS__SHIFT;
-
- ilo_builder_surface_reloc64(builder, state_offset, 8, surf->vma->bo,
- surf->vma->bo_offset + surf->surface[8],
- (surf->readonly) ? 0 : INTEL_RELOC_WRITE);
- }
- } else {
- state_align = 32;
- state_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ? 8 : 6;
-
- state_offset = ilo_builder_surface_pointer(builder,
- ILO_BUILDER_ITEM_SURFACE, state_align, state_len, &dw);
- memcpy(dw, surf->surface, state_len << 2);
-
- if (surf->vma) {
- /*
- * For scanouts, we should not enable caching in LLC. Since we only
- * enable that on Gen8+, we are fine here.
- */
- dw[5] |= builder->mocs << GEN6_SURFACE_DW5_MOCS__SHIFT;
-
- ilo_builder_surface_reloc(builder, state_offset, 1, surf->vma->bo,
- surf->vma->bo_offset + surf->surface[1],
- (surf->readonly) ? 0 : INTEL_RELOC_WRITE);
- }
- }
-
- return state_offset;
-}
-
-static inline uint32_t
-gen6_SAMPLER_STATE(struct ilo_builder *builder,
- const struct ilo_state_sampler *samplers,
- const uint32_t *sampler_border_colors,
- int sampler_count)
-{
- const int state_align = 32;
- const int state_len = 4 * sampler_count;
- uint32_t state_offset, *dw;
- int i;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 101:
- *
- * "The sampler state is stored as an array of up to 16 elements..."
- */
- assert(sampler_count <= 16);
-
- if (!sampler_count)
- return 0;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 132:
- *
- * "(Sampler Count of 3DSTATE_VS) Specifies how many samplers (in
- * multiples of 4) the vertex shader 0 kernel uses. Used only for
- * prefetching the associated sampler state entries.
- *
- * It also applies to other shader stages.
- */
- ilo_builder_dynamic_pad_top(builder, 4 * (4 - (sampler_count % 4)));
-
- state_offset = ilo_builder_dynamic_pointer(builder,
- ILO_BUILDER_ITEM_SAMPLER, state_align, state_len, &dw);
-
- for (i = 0; i < sampler_count; i++) {
- /* see sampler_set_gen6_SAMPLER_STATE() */
- dw[0] = samplers[i].sampler[0];
- dw[1] = samplers[i].sampler[1];
- dw[3] = samplers[i].sampler[2];
-
- assert(!(sampler_border_colors[i] & 0x1f));
- dw[2] = sampler_border_colors[i];
-
- dw += 4;
- }
-
- return state_offset;
-}
-
-static inline uint32_t
-gen6_SAMPLER_BORDER_COLOR_STATE(struct ilo_builder *builder,
- const struct ilo_state_sampler_border *border)
-{
- const int state_align =
- (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 64 : 32;
- const int state_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ? 4 : 12;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- /*
- * see border_set_gen6_SAMPLER_BORDER_COLOR_STATE() and
- * border_set_gen7_SAMPLER_BORDER_COLOR_STATE()
- */
- return ilo_builder_dynamic_write(builder, ILO_BUILDER_ITEM_BLOB,
- state_align, state_len, border->color);
-}
-
-static inline uint32_t
-gen6_push_constant_buffer(struct ilo_builder *builder,
- int size, void **pcb)
-{
- /*
- * For all VS, GS, FS, and CS push constant buffers, they must be aligned
- * to 32 bytes, and their sizes are specified in 256-bit units.
- */
- const int state_align = 32;
- const int state_len = align(size, 32) / 4;
- uint32_t state_offset;
- char *buf;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- state_offset = ilo_builder_dynamic_pointer(builder,
- ILO_BUILDER_ITEM_BLOB, state_align, state_len, (uint32_t **) &buf);
-
- /* zero out the unused range */
- if (size < state_len * 4)
- memset(&buf[size], 0, state_len * 4 - size);
-
- if (pcb)
- *pcb = buf;
-
- return state_offset;
-}
-
-static inline uint32_t
-gen6_user_vertex_buffer(struct ilo_builder *builder,
- int size, const void *vertices)
-{
- const int state_align = 8;
- const int state_len = size / 4;
-
- ILO_DEV_ASSERT(builder->dev, 6, 7.5);
-
- assert(size % 4 == 0);
-
- return ilo_builder_dynamic_write(builder, ILO_BUILDER_ITEM_BLOB,
- state_align, state_len, vertices);
-}
-
-#endif /* ILO_BUILDER_3D_TOP_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_BUILDER_BLT_H
-#define ILO_BUILDER_BLT_H
-
-#include "genhw/genhw.h"
-#include "intel_winsys.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-#include "ilo_builder.h"
-
-enum gen6_blt_mask {
- GEN6_BLT_MASK_8,
- GEN6_BLT_MASK_16,
- GEN6_BLT_MASK_32,
- GEN6_BLT_MASK_32_LO,
- GEN6_BLT_MASK_32_HI,
-};
-
-struct gen6_blt_bo {
- struct intel_bo *bo;
- uint32_t offset;
- int16_t pitch;
-};
-
-struct gen6_blt_xy_bo {
- struct intel_bo *bo;
- uint32_t offset;
- int16_t pitch;
-
- enum gen_surface_tiling tiling;
- int16_t x, y;
-};
-
-/*
- * From the Sandy Bridge PRM, volume 1 part 5, page 7:
- *
- * "The BLT engine is capable of transferring very large quantities of
- * graphics data. Any graphics data read from and written to the
- * destination is permitted to represent a number of pixels that occupies
- * up to 65,536 scan lines and up to 32,768 bytes per scan line at the
- * destination. The maximum number of pixels that may be represented per
- * scan line's worth of graphics data depends on the color depth."
- */
-static const int gen6_blt_max_bytes_per_scanline = 32768;
-static const int gen6_blt_max_scanlines = 65536;
-
-static inline uint32_t
-gen6_blt_translate_value_mask(enum gen6_blt_mask value_mask)
-{
- switch (value_mask) {
- case GEN6_BLT_MASK_8: return GEN6_BLITTER_BR13_FORMAT_8;
- case GEN6_BLT_MASK_16: return GEN6_BLITTER_BR13_FORMAT_565;
- default: return GEN6_BLITTER_BR13_FORMAT_8888;
- }
-}
-
-static inline uint32_t
-gen6_blt_translate_value_cpp(enum gen6_blt_mask value_mask)
-{
- switch (value_mask) {
- case GEN6_BLT_MASK_8: return 1;
- case GEN6_BLT_MASK_16: return 2;
- default: return 4;
- }
-}
-
-static inline uint32_t
-gen6_blt_translate_write_mask(enum gen6_blt_mask write_mask)
-{
- switch (write_mask) {
- case GEN6_BLT_MASK_32: return GEN6_BLITTER_BR00_WRITE_RGB |
- GEN6_BLITTER_BR00_WRITE_A;
- case GEN6_BLT_MASK_32_LO: return GEN6_BLITTER_BR00_WRITE_RGB;
- case GEN6_BLT_MASK_32_HI: return GEN6_BLITTER_BR00_WRITE_A;
- default: return 0;
- }
-}
-
-static inline void
-gen6_COLOR_BLT(struct ilo_builder *builder,
- const struct gen6_blt_bo *dst, uint32_t pattern,
- uint16_t width, uint16_t height, uint8_t rop,
- enum gen6_blt_mask value_mask,
- enum gen6_blt_mask write_mask)
-{
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 6 : 5;
- const int cpp = gen6_blt_translate_value_cpp(value_mask);
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- assert(width < gen6_blt_max_bytes_per_scanline);
- assert(height < gen6_blt_max_scanlines);
- /* offsets are naturally aligned and pitches are dword-aligned */
- assert(dst->offset % cpp == 0 && dst->pitch % 4 == 0);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_BLITTER_CMD(COLOR_BLT) |
- gen6_blt_translate_write_mask(write_mask) |
- (cmd_len - 2);
- dw[1] = rop << GEN6_BLITTER_BR13_ROP__SHIFT |
- gen6_blt_translate_value_mask(value_mask) |
- dst->pitch;
- dw[2] = height << 16 | width;
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw[5] = pattern;
-
- ilo_builder_batch_reloc64(builder, pos + 3,
- dst->bo, dst->offset, INTEL_RELOC_WRITE);
- } else {
- dw[4] = pattern;
-
- ilo_builder_batch_reloc(builder, pos + 3,
- dst->bo, dst->offset, INTEL_RELOC_WRITE);
- }
-}
-
-static inline void
-gen6_XY_COLOR_BLT(struct ilo_builder *builder,
- const struct gen6_blt_xy_bo *dst, uint32_t pattern,
- uint16_t width, uint16_t height, uint8_t rop,
- enum gen6_blt_mask value_mask,
- enum gen6_blt_mask write_mask)
-{
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 7 : 6;
- const int cpp = gen6_blt_translate_value_cpp(value_mask);
- int dst_align = 4, dst_pitch_shift = 0;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- assert(width * cpp < gen6_blt_max_bytes_per_scanline);
- assert(height < gen6_blt_max_scanlines);
- /* INT16_MAX */
- assert(dst->x + width <= 32767 && dst->y + height <= 32767);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_BLITTER_CMD(XY_COLOR_BLT) |
- gen6_blt_translate_write_mask(write_mask) |
- (cmd_len - 2);
-
- if (dst->tiling != GEN6_TILING_NONE) {
- dw[0] |= GEN6_BLITTER_BR00_DST_TILED;
-
- assert(dst->tiling == GEN6_TILING_X || dst->tiling == GEN6_TILING_Y);
- dst_align = (dst->tiling == GEN6_TILING_Y) ? 128 : 512;
- /* in dwords when tiled */
- dst_pitch_shift = 2;
- }
-
- assert(dst->offset % dst_align == 0 && dst->pitch % dst_align == 0);
-
- dw[1] = rop << GEN6_BLITTER_BR13_ROP__SHIFT |
- gen6_blt_translate_value_mask(value_mask) |
- dst->pitch >> dst_pitch_shift;
- dw[2] = dst->y << 16 | dst->x;
- dw[3] = (dst->y + height) << 16 | (dst->x + width);
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw[6] = pattern;
-
- ilo_builder_batch_reloc64(builder, pos + 4,
- dst->bo, dst->offset, INTEL_RELOC_WRITE);
- } else {
- dw[5] = pattern;
-
- ilo_builder_batch_reloc(builder, pos + 4,
- dst->bo, dst->offset, INTEL_RELOC_WRITE);
- }
-}
-
-static inline void
-gen6_SRC_COPY_BLT(struct ilo_builder *builder,
- const struct gen6_blt_bo *dst,
- const struct gen6_blt_bo *src,
- uint16_t width, uint16_t height, uint8_t rop,
- enum gen6_blt_mask value_mask,
- enum gen6_blt_mask write_mask)
-{
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 8 : 6;
- const int cpp = gen6_blt_translate_value_cpp(value_mask);
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- assert(width < gen6_blt_max_bytes_per_scanline);
- assert(height < gen6_blt_max_scanlines);
- /* offsets are naturally aligned and pitches are dword-aligned */
- assert(dst->offset % cpp == 0 && dst->pitch % 4 == 0);
- assert(src->offset % cpp == 0 && src->pitch % 4 == 0);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_BLITTER_CMD(SRC_COPY_BLT) |
- gen6_blt_translate_write_mask(write_mask) |
- (cmd_len - 2);
- dw[1] = rop << GEN6_BLITTER_BR13_ROP__SHIFT |
- gen6_blt_translate_value_mask(value_mask) |
- dst->pitch;
- dw[2] = height << 16 | width;
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw[5] = src->pitch;
-
- ilo_builder_batch_reloc64(builder, pos + 3,
- dst->bo, dst->offset, INTEL_RELOC_WRITE);
- ilo_builder_batch_reloc64(builder, pos + 6, src->bo, src->offset, 0);
- } else {
- dw[4] = src->pitch;
-
- ilo_builder_batch_reloc(builder, pos + 3,
- dst->bo, dst->offset, INTEL_RELOC_WRITE);
- ilo_builder_batch_reloc(builder, pos + 5, src->bo, src->offset, 0);
- }
-}
-
-static inline void
-gen6_XY_SRC_COPY_BLT(struct ilo_builder *builder,
- const struct gen6_blt_xy_bo *dst,
- const struct gen6_blt_xy_bo *src,
- uint16_t width, uint16_t height, uint8_t rop,
- enum gen6_blt_mask value_mask,
- enum gen6_blt_mask write_mask)
-{
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 10 : 8;
- const int cpp = gen6_blt_translate_value_cpp(value_mask);
- int dst_align = 4, dst_pitch_shift = 0;
- int src_align = 4, src_pitch_shift = 0;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- assert(width * cpp < gen6_blt_max_bytes_per_scanline);
- assert(height < gen6_blt_max_scanlines);
- /* INT16_MAX */
- assert(dst->x + width <= 32767 && dst->y + height <= 32767);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_BLITTER_CMD(XY_SRC_COPY_BLT) |
- gen6_blt_translate_write_mask(write_mask) |
- (cmd_len - 2);
-
- if (dst->tiling != GEN6_TILING_NONE) {
- dw[0] |= GEN6_BLITTER_BR00_DST_TILED;
-
- assert(dst->tiling == GEN6_TILING_X || dst->tiling == GEN6_TILING_Y);
- dst_align = (dst->tiling == GEN6_TILING_Y) ? 128 : 512;
- /* in dwords when tiled */
- dst_pitch_shift = 2;
- }
-
- if (src->tiling != GEN6_TILING_NONE) {
- dw[0] |= GEN6_BLITTER_BR00_SRC_TILED;
-
- assert(src->tiling == GEN6_TILING_X || src->tiling == GEN6_TILING_Y);
- src_align = (src->tiling == GEN6_TILING_Y) ? 128 : 512;
- /* in dwords when tiled */
- src_pitch_shift = 2;
- }
-
- assert(dst->offset % dst_align == 0 && dst->pitch % dst_align == 0);
- assert(src->offset % src_align == 0 && src->pitch % src_align == 0);
-
- dw[1] = rop << GEN6_BLITTER_BR13_ROP__SHIFT |
- gen6_blt_translate_value_mask(value_mask) |
- dst->pitch >> dst_pitch_shift;
- dw[2] = dst->y << 16 | dst->x;
- dw[3] = (dst->y + height) << 16 | (dst->x + width);
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw[6] = src->y << 16 | src->x;
- dw[7] = src->pitch >> src_pitch_shift;
-
- ilo_builder_batch_reloc64(builder, pos + 4,
- dst->bo, dst->offset, INTEL_RELOC_WRITE);
- ilo_builder_batch_reloc64(builder, pos + 8, src->bo, src->offset, 0);
- } else {
- dw[5] = src->y << 16 | src->x;
- dw[6] = src->pitch >> src_pitch_shift;
-
- ilo_builder_batch_reloc(builder, pos + 4,
- dst->bo, dst->offset, INTEL_RELOC_WRITE);
- ilo_builder_batch_reloc(builder, pos + 7, src->bo, src->offset, 0);
- }
-}
-
-#endif /* ILO_BUILDER_BLT_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include <stdio.h>
-#include <stdarg.h>
-#include "genhw/genhw.h"
-#include "../shader/toy_compiler.h"
-
-#include "intel_winsys.h"
-#include "ilo_builder.h"
-
-static const uint32_t *
-writer_pointer(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- unsigned offset)
-{
- const struct ilo_builder_writer *writer = &builder->writers[which];
- return (const uint32_t *) ((const char *) writer->ptr + offset);
-}
-
-static uint32_t _util_printf_format(5, 6)
-writer_dw(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- unsigned offset, unsigned dw_index,
- const char *format, ...)
-{
- const uint32_t *dw = writer_pointer(builder, which, offset);
- va_list ap;
- char desc[16];
- int len;
-
- ilo_printf("0x%08x: 0x%08x: ",
- offset + (dw_index << 2), dw[dw_index]);
-
- va_start(ap, format);
- len = vsnprintf(desc, sizeof(desc), format, ap);
- va_end(ap);
-
- if (len >= sizeof(desc)) {
- len = sizeof(desc) - 1;
- desc[len] = '\0';
- }
-
- if (desc[len - 1] == '\n') {
- desc[len - 1] = '\0';
- ilo_printf("%8s: \n", desc);
- } else {
- ilo_printf("%8s: ", desc);
- }
-
- return dw[dw_index];
-}
-
-static void
-writer_decode_blob(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- const unsigned state_size = sizeof(uint32_t);
- const unsigned count = item->size / state_size;
- unsigned offset = item->offset;
- unsigned i;
-
- for (i = 0; i < count; i += 4) {
- const uint32_t *dw = writer_pointer(builder, which, offset);
-
- writer_dw(builder, which, offset, 0, "BLOB%d", i / 4);
-
- switch (count - i) {
- case 1:
- ilo_printf("(%10.4f, %10c, %10c, %10c) "
- "(0x%08x, %10c, %10c, %10c)\n",
- uif(dw[0]), 'X', 'X', 'X',
- dw[0], 'X', 'X', 'X');
- break;
- case 2:
- ilo_printf("(%10.4f, %10.4f, %10c, %10c) "
- "(0x%08x, 0x%08x, %10c, %10c)\n",
- uif(dw[0]), uif(dw[1]), 'X', 'X',
- dw[0], dw[1], 'X', 'X');
- break;
- case 3:
- ilo_printf("(%10.4f, %10.4f, %10.4f, %10c) "
- "(0x%08x, 0x%08x, 0x%08x, %10c)\n",
- uif(dw[0]), uif(dw[1]), uif(dw[2]), 'X',
- dw[0], dw[1], dw[2], 'X');
- break;
- default:
- ilo_printf("(%10.4f, %10.4f, %10.4f, %10.4f) "
- "(0x%08x, 0x%08x, 0x%08x, 0x%08x)\n",
- uif(dw[0]), uif(dw[1]), uif(dw[2]), uif(dw[3]),
- dw[0], dw[1], dw[2], dw[3]);
- break;
- }
-
- offset += state_size * 4;
- }
-}
-
-static void
-writer_decode_clip_viewport(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- const unsigned state_size = sizeof(uint32_t) * 4;
- const unsigned count = item->size / state_size;
- unsigned offset = item->offset;
- unsigned i;
-
- for (i = 0; i < count; i++) {
- uint32_t dw;
-
- dw = writer_dw(builder, which, offset, 0, "CLIP VP%d", i);
- ilo_printf("xmin = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 1, "CLIP VP%d", i);
- ilo_printf("xmax = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 2, "CLIP VP%d", i);
- ilo_printf("ymin = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 3, "CLIP VP%d", i);
- ilo_printf("ymax = %f\n", uif(dw));
-
- offset += state_size;
- }
-}
-
-static void
-writer_decode_sf_clip_viewport_gen7(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- const unsigned state_size = sizeof(uint32_t) * 16;
- const unsigned count = item->size / state_size;
- unsigned offset = item->offset;
- unsigned i;
-
- for (i = 0; i < count; i++) {
- uint32_t dw;
-
- dw = writer_dw(builder, which, offset, 0, "SF_CLIP VP%d", i);
- ilo_printf("m00 = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 1, "SF_CLIP VP%d", i);
- ilo_printf("m11 = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 2, "SF_CLIP VP%d", i);
- ilo_printf("m22 = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 3, "SF_CLIP VP%d", i);
- ilo_printf("m30 = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 4, "SF_CLIP VP%d", i);
- ilo_printf("m31 = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 5, "SF_CLIP VP%d", i);
- ilo_printf("m32 = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 8, "SF_CLIP VP%d", i);
- ilo_printf("guardband xmin = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 9, "SF_CLIP VP%d", i);
- ilo_printf("guardband xmax = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 10, "SF_CLIP VP%d", i);
- ilo_printf("guardband ymin = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 11, "SF_CLIP VP%d", i);
- ilo_printf("guardband ymax = %f\n", uif(dw));
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw = writer_dw(builder, which, offset, 12, "SF_CLIP VP%d", i);
- ilo_printf("extent xmin = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 13, "SF_CLIP VP%d", i);
- ilo_printf("extent xmax = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 14, "SF_CLIP VP%d", i);
- ilo_printf("extent ymin = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 15, "SF_CLIP VP%d", i);
- ilo_printf("extent ymax = %f\n", uif(dw));
- }
-
- offset += state_size;
- }
-}
-
-static void
-writer_decode_sf_viewport_gen6(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- const unsigned state_size = sizeof(uint32_t) * 8;
- const unsigned count = item->size / state_size;
- unsigned offset = item->offset;
- unsigned i;
-
- for (i = 0; i < count; i++) {
- uint32_t dw;
-
- dw = writer_dw(builder, which, offset, 0, "SF VP%d", i);
- ilo_printf("m00 = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 1, "SF VP%d", i);
- ilo_printf("m11 = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 2, "SF VP%d", i);
- ilo_printf("m22 = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 3, "SF VP%d", i);
- ilo_printf("m30 = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 4, "SF VP%d", i);
- ilo_printf("m31 = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 5, "SF VP%d", i);
- ilo_printf("m32 = %f\n", uif(dw));
-
- offset += state_size;
- }
-}
-
-static void
-writer_decode_sf_viewport(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(7))
- writer_decode_sf_clip_viewport_gen7(builder, which, item);
- else
- writer_decode_sf_viewport_gen6(builder, which, item);
-}
-
-static void
-writer_decode_scissor_rect(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- const unsigned state_size = sizeof(uint32_t) * 2;
- const unsigned count = item->size / state_size;
- unsigned offset = item->offset;
- unsigned i;
-
- for (i = 0; i < count; i++) {
- uint32_t dw;
-
- dw = writer_dw(builder, which, offset, 0, "SCISSOR%d", i);
- ilo_printf("xmin %d, ymin %d\n",
- GEN_EXTRACT(dw, GEN6_SCISSOR_DW0_MIN_X),
- GEN_EXTRACT(dw, GEN6_SCISSOR_DW0_MIN_Y));
-
- dw = writer_dw(builder, which, offset, 1, "SCISSOR%d", i);
- ilo_printf("xmax %d, ymax %d\n",
- GEN_EXTRACT(dw, GEN6_SCISSOR_DW1_MAX_X),
- GEN_EXTRACT(dw, GEN6_SCISSOR_DW1_MAX_Y));
-
- offset += state_size;
- }
-}
-
-static void
-writer_decode_cc_viewport(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- const unsigned state_size = sizeof(uint32_t) * 2;
- const unsigned count = item->size / state_size;
- unsigned offset = item->offset;
- unsigned i;
-
- for (i = 0; i < count; i++) {
- uint32_t dw;
-
- dw = writer_dw(builder, which, offset, 0, "CC VP%d", i);
- ilo_printf("min_depth = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 1, "CC VP%d", i);
- ilo_printf("max_depth = %f\n", uif(dw));
-
- offset += state_size;
- }
-}
-
-static void
-writer_decode_color_calc(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- uint32_t dw;
-
- dw = writer_dw(builder, which, item->offset, 0, "CC");
- ilo_printf("alpha test format %s, round disable %d, "
- "stencil ref %d, bf stencil ref %d\n",
- GEN_EXTRACT(dw, GEN6_CC_DW0_ALPHATEST) ? "FLOAT32" : "UNORM8",
- (bool) (dw & GEN6_CC_DW0_ROUND_DISABLE_DISABLE),
- GEN_EXTRACT(dw, GEN6_CC_DW0_STENCIL_REF),
- GEN_EXTRACT(dw, GEN6_CC_DW0_STENCIL1_REF));
-
- writer_dw(builder, which, item->offset, 1, "CC\n");
-
- dw = writer_dw(builder, which, item->offset, 2, "CC");
- ilo_printf("constant red %f\n", uif(dw));
-
- dw = writer_dw(builder, which, item->offset, 3, "CC");
- ilo_printf("constant green %f\n", uif(dw));
-
- dw = writer_dw(builder, which, item->offset, 4, "CC");
- ilo_printf("constant blue %f\n", uif(dw));
-
- dw = writer_dw(builder, which, item->offset, 5, "CC");
- ilo_printf("constant alpha %f\n", uif(dw));
-}
-
-static void
-writer_decode_depth_stencil(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- uint32_t dw;
-
- dw = writer_dw(builder, which, item->offset, 0, "D_S");
- ilo_printf("stencil %sable, func %d, write %sable\n",
- (dw & GEN6_ZS_DW0_STENCIL_TEST_ENABLE) ? "en" : "dis",
- GEN_EXTRACT(dw, GEN6_ZS_DW0_STENCIL_FUNC),
- (dw & GEN6_ZS_DW0_STENCIL_WRITE_ENABLE) ? "en" : "dis");
-
- dw = writer_dw(builder, which, item->offset, 1, "D_S");
- ilo_printf("stencil test mask 0x%x, write mask 0x%x\n",
- GEN_EXTRACT(dw, GEN6_ZS_DW1_STENCIL_TEST_MASK),
- GEN_EXTRACT(dw, GEN6_ZS_DW1_STENCIL_WRITE_MASK));
-
- dw = writer_dw(builder, which, item->offset, 2, "D_S");
- ilo_printf("depth test %sable, func %d, write %sable\n",
- (dw & GEN6_ZS_DW2_DEPTH_TEST_ENABLE) ? "en" : "dis",
- GEN_EXTRACT(dw, GEN6_ZS_DW2_DEPTH_FUNC),
- (dw & GEN6_ZS_DW2_DEPTH_WRITE_ENABLE) ? "en" : "dis");
-}
-
-static void
-writer_decode_blend(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- const unsigned state_size = sizeof(uint32_t) * 2;
- const unsigned count = item->size / state_size;
- unsigned offset = item->offset;
- unsigned i;
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- writer_dw(builder, which, offset, 0, "BLEND\n");
- offset += 4;
- }
-
- for (i = 0; i < count; i++) {
- writer_dw(builder, which, offset, 0, "BLEND%d\n", i);
- writer_dw(builder, which, offset, 1, "BLEND%d\n", i);
-
- offset += state_size;
- }
-}
-
-static void
-writer_decode_sampler(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- const unsigned state_size = sizeof(uint32_t) * 4;
- const unsigned count = item->size / state_size;
- unsigned offset = item->offset;
- unsigned i;
-
- for (i = 0; i < count; i++) {
- writer_dw(builder, which, offset, 0, "WM SAMP%d", i);
- ilo_printf("filtering\n");
-
- writer_dw(builder, which, offset, 1, "WM SAMP%d", i);
- ilo_printf("wrapping, lod\n");
-
- writer_dw(builder, which, offset, 2, "WM SAMP%d", i);
- ilo_printf("default color pointer\n");
-
- writer_dw(builder, which, offset, 3, "WM SAMP%d", i);
- ilo_printf("chroma key, aniso\n");
-
- offset += state_size;
- }
-}
-
-static void
-writer_decode_interface_descriptor(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- const unsigned state_size = sizeof(uint32_t) * 8;
- const unsigned count = item->size / state_size;
- unsigned offset = item->offset;
- unsigned i;
-
- for (i = 0; i < count; i++) {
- writer_dw(builder, which, offset, 0, "IDRT[%d]", i);
- ilo_printf("kernel\n");
-
- writer_dw(builder, which, offset, 1, "IDRT[%d]", i);
- ilo_printf("spf, fp mode\n");
-
- writer_dw(builder, which, offset, 2, "IDRT[%d]", i);
- ilo_printf("sampler\n");
-
- writer_dw(builder, which, offset, 3, "IDRT[%d]", i);
- ilo_printf("binding table\n");
-
- writer_dw(builder, which, offset, 4, "IDRT[%d]", i);
- ilo_printf("curbe read len\n");
-
- writer_dw(builder, which, offset, 5, "IDRT[%d]", i);
- ilo_printf("rounding mode, slm size\n");
-
- writer_dw(builder, which, offset, 6, "IDRT[%d]", i);
- ilo_printf("cross-thread curbe read len\n");
-
- writer_dw(builder, which, offset, 7, "IDRT[%d]", i);
- ilo_printf("mbz\n");
-
- offset += state_size;
- }
-}
-
-static void
-writer_decode_surface_gen7(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- uint32_t dw;
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw = writer_dw(builder, which, item->offset, 0, "SURF");
- ilo_printf("type 0x%x, format 0x%x, tiling %d, %s array\n",
- GEN_EXTRACT(dw, GEN7_SURFACE_DW0_TYPE),
- GEN_EXTRACT(dw, GEN7_SURFACE_DW0_FORMAT),
- GEN_EXTRACT(dw, GEN8_SURFACE_DW0_TILING),
- (dw & GEN7_SURFACE_DW0_IS_ARRAY) ? "is" : "not");
-
- writer_dw(builder, which, item->offset, 1, "SURF");
- ilo_printf("qpitch\n");
- } else {
- dw = writer_dw(builder, which, item->offset, 0, "SURF");
- ilo_printf("type 0x%x, format 0x%x, tiling %d, %s array\n",
- GEN_EXTRACT(dw, GEN7_SURFACE_DW0_TYPE),
- GEN_EXTRACT(dw, GEN7_SURFACE_DW0_FORMAT),
- GEN_EXTRACT(dw, GEN7_SURFACE_DW0_TILING),
- (dw & GEN7_SURFACE_DW0_IS_ARRAY) ? "is" : "not");
-
- writer_dw(builder, which, item->offset, 1, "SURF");
- ilo_printf("offset\n");
- }
-
- dw = writer_dw(builder, which, item->offset, 2, "SURF");
- ilo_printf("%dx%d size\n",
- GEN_EXTRACT(dw, GEN7_SURFACE_DW2_WIDTH),
- GEN_EXTRACT(dw, GEN7_SURFACE_DW2_HEIGHT));
-
- dw = writer_dw(builder, which, item->offset, 3, "SURF");
- ilo_printf("depth %d, pitch %d\n",
- GEN_EXTRACT(dw, GEN7_SURFACE_DW3_DEPTH),
- GEN_EXTRACT(dw, GEN7_SURFACE_DW3_PITCH));
-
- dw = writer_dw(builder, which, item->offset, 4, "SURF");
- ilo_printf("min array element %d, array extent %d\n",
- GEN_EXTRACT(dw, GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT),
- GEN_EXTRACT(dw, GEN7_SURFACE_DW4_RT_VIEW_EXTENT));
-
- dw = writer_dw(builder, which, item->offset, 5, "SURF");
- ilo_printf("mip base %d, mips %d, x,y offset: %d,%d\n",
- GEN_EXTRACT(dw, GEN7_SURFACE_DW5_MIN_LOD),
- GEN_EXTRACT(dw, GEN7_SURFACE_DW5_MIP_COUNT_LOD),
- GEN_EXTRACT(dw, GEN7_SURFACE_DW5_X_OFFSET),
- GEN_EXTRACT(dw, GEN7_SURFACE_DW5_Y_OFFSET));
-
- writer_dw(builder, which, item->offset, 6, "SURF\n");
- writer_dw(builder, which, item->offset, 7, "SURF\n");
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- writer_dw(builder, which, item->offset, 8, "SURF\n");
- writer_dw(builder, which, item->offset, 9, "SURF\n");
- writer_dw(builder, which, item->offset, 10, "SURF\n");
- writer_dw(builder, which, item->offset, 11, "SURF\n");
- writer_dw(builder, which, item->offset, 12, "SURF\n");
- }
-}
-
-static void
-writer_decode_surface_gen6(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- uint32_t dw;
-
- dw = writer_dw(builder, which, item->offset, 0, "SURF");
- ilo_printf("type 0x%x, format 0x%x\n",
- GEN_EXTRACT(dw, GEN6_SURFACE_DW0_TYPE),
- GEN_EXTRACT(dw, GEN6_SURFACE_DW0_FORMAT));
-
- writer_dw(builder, which, item->offset, 1, "SURF");
- ilo_printf("offset\n");
-
- dw = writer_dw(builder, which, item->offset, 2, "SURF");
- ilo_printf("%dx%d size, %d mips\n",
- GEN_EXTRACT(dw, GEN6_SURFACE_DW2_WIDTH),
- GEN_EXTRACT(dw, GEN6_SURFACE_DW2_HEIGHT),
- GEN_EXTRACT(dw, GEN6_SURFACE_DW2_MIP_COUNT_LOD));
-
- dw = writer_dw(builder, which, item->offset, 3, "SURF");
- ilo_printf("pitch %d, tiling %d\n",
- GEN_EXTRACT(dw, GEN6_SURFACE_DW3_PITCH),
- GEN_EXTRACT(dw, GEN6_SURFACE_DW3_TILING));
-
- dw = writer_dw(builder, which, item->offset, 4, "SURF");
- ilo_printf("mip base %d\n",
- GEN_EXTRACT(dw, GEN6_SURFACE_DW4_MIN_LOD));
-
- dw = writer_dw(builder, which, item->offset, 5, "SURF");
- ilo_printf("x,y offset: %d,%d\n",
- GEN_EXTRACT(dw, GEN6_SURFACE_DW5_X_OFFSET),
- GEN_EXTRACT(dw, GEN6_SURFACE_DW5_Y_OFFSET));
-}
-
-static void
-writer_decode_surface(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(7))
- writer_decode_surface_gen7(builder, which, item);
- else
- writer_decode_surface_gen6(builder, which, item);
-}
-
-static void
-writer_decode_binding_table(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- const unsigned state_size = sizeof(uint32_t) * 1;
- const unsigned count = item->size / state_size;
- unsigned offset = item->offset;
- unsigned i;
-
- for (i = 0; i < count; i++) {
- writer_dw(builder, which, offset, 0, "BIND");
- ilo_printf("BINDING_TABLE_STATE[%d]\n", i);
-
- offset += state_size;
- }
-}
-
-static void
-writer_decode_kernel(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- const void *kernel;
-
- ilo_printf("0x%08x:\n", item->offset);
- kernel = (const void *) writer_pointer(builder, which, item->offset);
- toy_compiler_disassemble(builder->dev, kernel, item->size, true);
-}
-
-static const struct {
- void (*func)(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item);
-} writer_decode_table[ILO_BUILDER_ITEM_COUNT] = {
- [ILO_BUILDER_ITEM_BLOB] = { writer_decode_blob },
- [ILO_BUILDER_ITEM_CLIP_VIEWPORT] = { writer_decode_clip_viewport },
- [ILO_BUILDER_ITEM_SF_VIEWPORT] = { writer_decode_sf_viewport },
- [ILO_BUILDER_ITEM_SCISSOR_RECT] = { writer_decode_scissor_rect },
- [ILO_BUILDER_ITEM_CC_VIEWPORT] = { writer_decode_cc_viewport },
- [ILO_BUILDER_ITEM_COLOR_CALC] = { writer_decode_color_calc },
- [ILO_BUILDER_ITEM_DEPTH_STENCIL] = { writer_decode_depth_stencil },
- [ILO_BUILDER_ITEM_BLEND] = { writer_decode_blend },
- [ILO_BUILDER_ITEM_SAMPLER] = { writer_decode_sampler },
- [ILO_BUILDER_ITEM_INTERFACE_DESCRIPTOR] = { writer_decode_interface_descriptor },
- [ILO_BUILDER_ITEM_SURFACE] = { writer_decode_surface },
- [ILO_BUILDER_ITEM_BINDING_TABLE] = { writer_decode_binding_table },
- [ILO_BUILDER_ITEM_KERNEL] = { writer_decode_kernel },
-};
-
-static void
-ilo_builder_writer_decode_items(struct ilo_builder *builder,
- enum ilo_builder_writer_type which)
-{
- struct ilo_builder_writer *writer = &builder->writers[which];
- int i;
-
- if (!writer->item_used)
- return;
-
- writer->ptr = intel_bo_map(writer->bo, false);
- if (!writer->ptr)
- return;
-
- for (i = 0; i < writer->item_used; i++) {
- const struct ilo_builder_item *item = &writer->items[i];
-
- writer_decode_table[item->type].func(builder, which, item);
- }
-
- intel_bo_unmap(writer->bo);
- writer->ptr = NULL;
-}
-
-static void
-ilo_builder_writer_decode(struct ilo_builder *builder,
- enum ilo_builder_writer_type which)
-{
- struct ilo_builder_writer *writer = &builder->writers[which];
-
- assert(writer->bo && !writer->ptr);
-
- switch (which) {
- case ILO_BUILDER_WRITER_BATCH:
- ilo_printf("decoding batch buffer: %d bytes\n", writer->used);
- if (writer->used)
- intel_winsys_decode_bo(builder->winsys, writer->bo, writer->used);
-
- ilo_printf("decoding dynamic/surface buffer: %d states\n",
- writer->item_used);
- ilo_builder_writer_decode_items(builder, which);
- break;
- case ILO_BUILDER_WRITER_INSTRUCTION:
- if (true) {
- ilo_printf("skipping instruction buffer: %d kernels\n",
- writer->item_used);
- } else {
- ilo_printf("decoding instruction buffer: %d kernels\n",
- writer->item_used);
-
- ilo_builder_writer_decode_items(builder, which);
- }
- break;
- default:
- break;
- }
-}
-
-/**
- * Decode the builder according to the recorded items. This can be called
- * only after a successful ilo_builder_end().
- */
-void
-ilo_builder_decode(struct ilo_builder *builder)
-{
- int i;
-
- assert(!builder->unrecoverable_error);
-
- for (i = 0; i < ILO_BUILDER_WRITER_COUNT; i++)
- ilo_builder_writer_decode(builder, i);
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_BUILDER_MEDIA_H
-#define ILO_BUILDER_MEDIA_H
-
-#include "genhw/genhw.h"
-#include "intel_winsys.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-#include "ilo_state_compute.h"
-#include "ilo_builder.h"
-
-static inline void
-gen6_MEDIA_VFE_STATE(struct ilo_builder *builder,
- const struct ilo_state_compute *compute)
-{
- const uint8_t cmd_len = 8;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 7.5);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(MEDIA, MEDIA_VFE_STATE) | (cmd_len - 2);
- /* see compute_set_gen6_MEDIA_VFE_STATE() */
- dw[1] = compute->vfe[0];
- dw[2] = compute->vfe[1];
- dw[3] = 0;
- dw[4] = compute->vfe[2];
- dw[5] = 0;
- dw[6] = 0;
- dw[7] = 0;
-}
-
-static inline void
-gen6_MEDIA_CURBE_LOAD(struct ilo_builder *builder,
- uint32_t offset, unsigned size)
-{
- const uint8_t cmd_len = 4;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 7.5);
-
- assert(offset % 32 == 0 && size % 32 == 0);
- /* GPU hangs if size is zero */
- assert(size);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(MEDIA, MEDIA_CURBE_LOAD) | (cmd_len - 2);
- dw[1] = 0;
- dw[2] = size;
- dw[3] = offset;
-}
-
-static inline void
-gen6_MEDIA_INTERFACE_DESCRIPTOR_LOAD(struct ilo_builder *builder,
- uint32_t offset, unsigned size)
-{
- const uint8_t cmd_len = 4;
- const unsigned idrt_alloc =
- ((ilo_dev_gen(builder->dev) >= ILO_GEN(7.5)) ? 64 : 32) * 32;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 7.5);
-
- assert(offset % 32 == 0 && size % 32 == 0);
- assert(size && size <= idrt_alloc);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(MEDIA, MEDIA_INTERFACE_DESCRIPTOR_LOAD) |
- (cmd_len - 2);
- dw[1] = 0;
- dw[2] = size;
- dw[3] = offset;
-}
-
-static inline void
-gen6_MEDIA_STATE_FLUSH(struct ilo_builder *builder)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 7.5);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(MEDIA, MEDIA_STATE_FLUSH) | (cmd_len - 2);
- dw[1] = 0;
-}
-
-static inline void
-gen7_GPGPU_WALKER(struct ilo_builder *builder,
- const unsigned thread_group_offset[3],
- const unsigned thread_group_dim[3],
- unsigned thread_group_size,
- unsigned simd_size)
-{
- const uint8_t cmd_len = 11;
- uint32_t right_execmask, bottom_execmask;
- unsigned thread_count;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 7.5);
-
- assert(simd_size == 16 || simd_size == 8);
-
- thread_count = (thread_group_size + simd_size - 1) / simd_size;
- assert(thread_count <= 64);
-
- right_execmask = thread_group_size % simd_size;
- if (right_execmask)
- right_execmask = (1 << right_execmask) - 1;
- else
- right_execmask = (1 << simd_size) - 1;
-
- bottom_execmask = 0xffffffff;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(MEDIA, GPGPU_WALKER) | (cmd_len - 2);
- dw[1] = 0; /* always first IDRT */
-
- dw[2] = (thread_count - 1) << GEN7_GPGPU_DW2_THREAD_MAX_X__SHIFT;
- if (simd_size == 16)
- dw[2] |= GEN7_GPGPU_DW2_SIMD_SIZE_SIMD16;
- else
- dw[2] |= GEN7_GPGPU_DW2_SIMD_SIZE_SIMD8;
-
- dw[3] = thread_group_offset[0];
- dw[4] = thread_group_dim[0];
- dw[5] = thread_group_offset[1];
- dw[6] = thread_group_dim[1];
- dw[7] = thread_group_offset[2];
- dw[8] = thread_group_dim[2];
-
- dw[9] = right_execmask;
- dw[10] = bottom_execmask;
-}
-
-static inline uint32_t
-gen6_INTERFACE_DESCRIPTOR_DATA(struct ilo_builder *builder,
- const struct ilo_state_compute *compute,
- const uint32_t *kernel_offsets,
- const uint32_t *sampler_offsets,
- const uint32_t *binding_table_offsets)
-{
- /*
- * From the Sandy Bridge PRM, volume 2 part 2, page 34:
- *
- * "(Interface Descriptor Total Length) This field must have the same
- * alignment as the Interface Descriptor Data Start Address.
- *
- * It must be DQWord (32-byte) aligned..."
- *
- * From the Sandy Bridge PRM, volume 2 part 2, page 35:
- *
- * "(Interface Descriptor Data Start Address) Specifies the 32-byte
- * aligned address of the Interface Descriptor data."
- */
- const int state_align = 32;
- const int state_len = (32 / 4) * compute->idrt_count;
- uint32_t state_offset, *dw;
- int i;
-
- ILO_DEV_ASSERT(builder->dev, 6, 7.5);
-
- state_offset = ilo_builder_dynamic_pointer(builder,
- ILO_BUILDER_ITEM_INTERFACE_DESCRIPTOR, state_align, state_len, &dw);
-
- for (i = 0; i < compute->idrt_count; i++) {
- /* see compute_set_gen6_INTERFACE_DESCRIPTOR_DATA() */
- dw[0] = compute->idrt[i][0] + kernel_offsets[i];
- dw[1] = 0;
- dw[2] = compute->idrt[i][1] |
- sampler_offsets[i];
- dw[3] = compute->idrt[i][2] |
- binding_table_offsets[i];
- dw[4] = compute->idrt[i][3];
- dw[5] = compute->idrt[i][4];
- dw[6] = compute->idrt[i][5];
- dw[7] = 0;
-
- dw += 8;
- }
-
- return state_offset;
-}
-
-#endif /* ILO_BUILDER_MEDIA_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_BUILDER_MI_H
-#define ILO_BUILDER_MI_H
-
-#include "genhw/genhw.h"
-#include "intel_winsys.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-#include "ilo_builder.h"
-
-static inline void
-gen6_MI_STORE_DATA_IMM(struct ilo_builder *builder,
- struct intel_bo *bo, uint32_t bo_offset,
- uint64_t val)
-{
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 6 : 5;
- uint32_t reloc_flags = INTEL_RELOC_WRITE;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- assert(bo_offset % 8 == 0);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_MI_CMD(MI_STORE_DATA_IMM) | (cmd_len - 2);
- /* must use GGTT on GEN6 as in PIPE_CONTROL */
- if (ilo_dev_gen(builder->dev) == ILO_GEN(6)) {
- dw[0] |= GEN6_MI_STORE_DATA_IMM_DW0_USE_GGTT;
- reloc_flags |= INTEL_RELOC_GGTT;
- }
-
- dw[1] = 0; /* MBZ */
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw[4] = (uint32_t) val;
- dw[5] = (uint32_t) (val >> 32);
-
- ilo_builder_batch_reloc64(builder, pos + 2, bo, bo_offset, reloc_flags);
- } else {
- dw[3] = (uint32_t) val;
- dw[4] = (uint32_t) (val >> 32);
-
- ilo_builder_batch_reloc(builder, pos + 2, bo, bo_offset, reloc_flags);
- }
-}
-
-static inline void
-gen6_MI_LOAD_REGISTER_IMM(struct ilo_builder *builder,
- uint32_t reg, uint32_t val)
-{
- const uint8_t cmd_len = 3;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- assert(reg % 4 == 0);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_MI_CMD(MI_LOAD_REGISTER_IMM) | (cmd_len - 2);
- dw[1] = reg;
- dw[2] = val;
-}
-
-static inline void
-gen6_MI_STORE_REGISTER_MEM(struct ilo_builder *builder, uint32_t reg,
- struct intel_bo *bo, uint32_t bo_offset)
-{
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 4 : 3;
- uint32_t reloc_flags = INTEL_RELOC_WRITE;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- assert(reg % 4 == 0 && bo_offset % 4 == 0);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_MI_CMD(MI_STORE_REGISTER_MEM) | (cmd_len - 2);
- dw[1] = reg;
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- ilo_builder_batch_reloc64(builder, pos + 2, bo, bo_offset, reloc_flags);
- } else {
- /* must use GGTT on Gen6 as in PIPE_CONTROL */
- if (ilo_dev_gen(builder->dev) == ILO_GEN(6)) {
- dw[0] |= GEN6_MI_STORE_REGISTER_MEM_DW0_USE_GGTT;
- reloc_flags |= INTEL_RELOC_GGTT;
- }
-
- ilo_builder_batch_reloc(builder, pos + 2, bo, bo_offset, reloc_flags);
- }
-}
-
-static inline void
-gen6_MI_FLUSH_DW(struct ilo_builder *builder)
-{
- const uint8_t cmd_len = 4;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_MI_CMD(MI_FLUSH_DW) | (cmd_len - 2);
- dw[1] = 0;
- dw[2] = 0;
- dw[3] = 0;
-}
-
-static inline void
-gen6_MI_REPORT_PERF_COUNT(struct ilo_builder *builder,
- struct intel_bo *bo, uint32_t bo_offset,
- uint32_t report_id)
-{
- const uint8_t cmd_len = 3;
- uint32_t reloc_flags = INTEL_RELOC_WRITE;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 7.5);
-
- assert(bo_offset % 64 == 0);
-
- /* must use GGTT on GEN6 as in PIPE_CONTROL */
- if (ilo_dev_gen(builder->dev) == ILO_GEN(6)) {
- bo_offset |= GEN6_MI_REPORT_PERF_COUNT_DW1_USE_GGTT;
- reloc_flags |= INTEL_RELOC_GGTT;
- }
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_MI_CMD(MI_REPORT_PERF_COUNT) | (cmd_len - 2);
- dw[2] = report_id;
-
- ilo_builder_batch_reloc(builder, pos + 1, bo, bo_offset, reloc_flags);
-}
-
-static inline void
-gen7_MI_LOAD_REGISTER_MEM(struct ilo_builder *builder, uint32_t reg,
- struct intel_bo *bo, uint32_t bo_offset)
-{
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 4 : 3;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- assert(reg % 4 == 0 && bo_offset % 4 == 0);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_MI_CMD(MI_LOAD_REGISTER_MEM) | (cmd_len - 2);
- dw[1] = reg;
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8))
- ilo_builder_batch_reloc64(builder, pos + 2, bo, bo_offset, 0);
- else
- ilo_builder_batch_reloc(builder, pos + 2, bo, bo_offset, 0);
-}
-
-/**
- * Add a MI_BATCH_BUFFER_END to the batch buffer. Pad with MI_NOOP if
- * necessary.
- */
-static inline void
-gen6_mi_batch_buffer_end(struct ilo_builder *builder)
-{
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 107:
- *
- * "The batch buffer must be QWord aligned and a multiple of QWords in
- * length."
- */
- const bool pad = !(builder->writers[ILO_BUILDER_WRITER_BATCH].used & 0x7);
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- if (pad) {
- ilo_builder_batch_pointer(builder, 2, &dw);
- dw[0] = GEN6_MI_CMD(MI_BATCH_BUFFER_END);
- dw[1] = GEN6_MI_CMD(MI_NOOP);
- } else {
- ilo_builder_batch_pointer(builder, 1, &dw);
- dw[0] = GEN6_MI_CMD(MI_BATCH_BUFFER_END);
- }
-}
-
-#endif /* ILO_BUILDER_MI_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_BUILDER_RENDER_H
-#define ILO_BUILDER_RENDER_H
-
-#include "genhw/genhw.h"
-#include "intel_winsys.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-#include "ilo_builder.h"
-
-static inline void
-gen6_STATE_SIP(struct ilo_builder *builder, uint32_t sip)
-{
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 3 : 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(COMMON, STATE_SIP) | (cmd_len - 2);
- dw[1] = sip;
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8))
- dw[2] = 0;
-}
-
-static inline void
-gen6_PIPELINE_SELECT(struct ilo_builder *builder, int pipeline)
-{
- const uint8_t cmd_len = 1;
- const uint32_t dw0 = GEN6_RENDER_CMD(SINGLE_DW, PIPELINE_SELECT) |
- pipeline;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- switch (pipeline) {
- case GEN6_PIPELINE_SELECT_DW0_SELECT_3D:
- case GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA:
- break;
- case GEN7_PIPELINE_SELECT_DW0_SELECT_GPGPU:
- assert(ilo_dev_gen(builder->dev) >= ILO_GEN(7));
- break;
- default:
- assert(!"unknown pipeline");
- break;
- }
-
- ilo_builder_batch_write(builder, cmd_len, &dw0);
-}
-
-static inline void
-gen6_PIPE_CONTROL(struct ilo_builder *builder, uint32_t dw1,
- struct intel_bo *bo, uint32_t bo_offset,
- uint64_t imm)
-{
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 6 : 5;
- uint32_t reloc_flags = INTEL_RELOC_WRITE;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- if (dw1 & GEN6_PIPE_CONTROL_CS_STALL) {
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 73:
- *
- * "1 of the following must also be set (when CS stall is set):
- *
- * * Depth Cache Flush Enable ([0] of DW1)
- * * Stall at Pixel Scoreboard ([1] of DW1)
- * * Depth Stall ([13] of DW1)
- * * Post-Sync Operation ([13] of DW1)
- * * Render Target Cache Flush Enable ([12] of DW1)
- * * Notify Enable ([8] of DW1)"
- *
- * From the Ivy Bridge PRM, volume 2 part 1, page 61:
- *
- * "One of the following must also be set (when CS stall is set):
- *
- * * Render Target Cache Flush Enable ([12] of DW1)
- * * Depth Cache Flush Enable ([0] of DW1)
- * * Stall at Pixel Scoreboard ([1] of DW1)
- * * Depth Stall ([13] of DW1)
- * * Post-Sync Operation ([13] of DW1)"
- */
- uint32_t bit_test = GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH |
- GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL |
- GEN6_PIPE_CONTROL_DEPTH_STALL;
-
- /* post-sync op */
- bit_test |= GEN6_PIPE_CONTROL_WRITE_IMM |
- GEN6_PIPE_CONTROL_WRITE_PS_DEPTH_COUNT |
- GEN6_PIPE_CONTROL_WRITE_TIMESTAMP;
-
- if (ilo_dev_gen(builder->dev) == ILO_GEN(6))
- bit_test |= GEN6_PIPE_CONTROL_NOTIFY_ENABLE;
-
- assert(dw1 & bit_test);
- }
-
- if (dw1 & GEN6_PIPE_CONTROL_DEPTH_STALL) {
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 73:
- *
- * "Following bits must be clear (when Depth Stall is set):
- *
- * * Render Target Cache Flush Enable ([12] of DW1)
- * * Depth Cache Flush Enable ([0] of DW1)"
- */
- assert(!(dw1 & (GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH |
- GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH)));
- }
-
- switch (dw1 & GEN6_PIPE_CONTROL_WRITE__MASK) {
- case GEN6_PIPE_CONTROL_WRITE_PS_DEPTH_COUNT:
- case GEN6_PIPE_CONTROL_WRITE_TIMESTAMP:
- assert(!imm);
- break;
- default:
- break;
- }
-
- assert(bo_offset % 8 == 0);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, PIPE_CONTROL) | (cmd_len - 2);
- dw[1] = dw1;
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw[4] = (uint32_t) imm;
- dw[5] = (uint32_t) (imm >> 32);
-
- if (bo) {
- ilo_builder_batch_reloc64(builder, pos + 2,
- bo, bo_offset, reloc_flags);
- } else {
- dw[2] = 0;
- dw[3] = 0;
- }
-
- } else {
- dw[3] = (uint32_t) imm;
- dw[4] = (uint32_t) (imm >> 32);
-
- if (bo) {
- /*
- * From the Sandy Bridge PRM, volume 1 part 3, page 19:
- *
- * "[DevSNB] PPGTT memory writes by MI_* (such as
- * MI_STORE_DATA_IMM) and PIPE_CONTROL are not supported."
- */
- if (ilo_dev_gen(builder->dev) == ILO_GEN(6)) {
- bo_offset |= GEN6_PIPE_CONTROL_DW2_USE_GGTT;
- reloc_flags |= INTEL_RELOC_GGTT;
- }
-
- ilo_builder_batch_reloc(builder, pos + 2,
- bo, bo_offset, reloc_flags);
- } else {
- dw[2] = 0;
- }
- }
-}
-
-static inline void
-ilo_builder_batch_patch_sba(struct ilo_builder *builder)
-{
- const struct ilo_builder_writer *inst =
- &builder->writers[ILO_BUILDER_WRITER_INSTRUCTION];
-
- if (!builder->sba_instruction_pos)
- return;
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- ilo_builder_batch_reloc64(builder, builder->sba_instruction_pos,
- inst->bo,
- builder->mocs << GEN8_SBA_MOCS__SHIFT | GEN6_SBA_ADDR_MODIFIED,
- 0);
- } else {
- ilo_builder_batch_reloc(builder, builder->sba_instruction_pos, inst->bo,
- builder->mocs << GEN6_SBA_MOCS__SHIFT | GEN6_SBA_ADDR_MODIFIED,
- 0);
- }
-}
-
-/**
- * Add a STATE_BASE_ADDRESS to the batch buffer. The relocation entry for the
- * instruction buffer is not added until ilo_builder_end() or next
- * gen6_state_base_address().
- */
-static inline void
-gen6_state_base_address(struct ilo_builder *builder, bool init_all)
-{
- const uint8_t cmd_len = 10;
- const struct ilo_builder_writer *bat =
- &builder->writers[ILO_BUILDER_WRITER_BATCH];
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 7.5);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(COMMON, STATE_BASE_ADDRESS) | (cmd_len - 2);
- dw[1] = builder->mocs << GEN6_SBA_MOCS__SHIFT |
- builder->mocs << GEN6_SBA_DW1_GENERAL_STATELESS_MOCS__SHIFT |
- init_all;
-
- ilo_builder_batch_reloc(builder, pos + 2, bat->bo,
- builder->mocs << GEN6_SBA_MOCS__SHIFT | GEN6_SBA_ADDR_MODIFIED,
- 0);
- ilo_builder_batch_reloc(builder, pos + 3, bat->bo,
- builder->mocs << GEN6_SBA_MOCS__SHIFT | GEN6_SBA_ADDR_MODIFIED,
- 0);
-
- dw[4] = builder->mocs << GEN6_SBA_MOCS__SHIFT | init_all;
-
- /*
- * Since the instruction writer has WRITER_FLAG_APPEND set, it is tempting
- * not to set Instruction Base Address. The problem is that we do not know
- * if the bo has been or will be moved by the kernel. We need a relocation
- * entry because of that.
- *
- * And since we also set WRITER_FLAG_GROW, we have to wait until
- * ilo_builder_end(), when the final bo is known, to add the relocation
- * entry.
- */
- ilo_builder_batch_patch_sba(builder);
- builder->sba_instruction_pos = pos + 5;
-
- /* skip range checks */
- dw[6] = init_all;
- dw[7] = 0xfffff000 + init_all;
- dw[8] = 0xfffff000 + init_all;
- dw[9] = init_all;
-}
-
-static inline void
-gen8_state_base_address(struct ilo_builder *builder, bool init_all)
-{
- const uint8_t cmd_len = 16;
- const struct ilo_builder_writer *bat =
- &builder->writers[ILO_BUILDER_WRITER_BATCH];
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(COMMON, STATE_BASE_ADDRESS) | (cmd_len - 2);
- dw[1] = builder->mocs << GEN8_SBA_MOCS__SHIFT | init_all;
- dw[2] = 0;
- dw[3] = builder->mocs << GEN8_SBA_DW3_STATELESS_MOCS__SHIFT;
- ilo_builder_batch_reloc64(builder, pos + 4, bat->bo,
- builder->mocs << GEN8_SBA_MOCS__SHIFT | GEN6_SBA_ADDR_MODIFIED,
- 0);
- ilo_builder_batch_reloc64(builder, pos + 6, bat->bo,
- builder->mocs << GEN8_SBA_MOCS__SHIFT | GEN6_SBA_ADDR_MODIFIED,
- 0);
- dw[8] = builder->mocs << GEN8_SBA_MOCS__SHIFT | init_all;
- dw[9] = 0;
-
- ilo_builder_batch_patch_sba(builder);
- builder->sba_instruction_pos = pos + 10;
-
- /* skip range checks */
- dw[12] = 0xfffff000 + init_all;
- dw[13] = 0xfffff000 + init_all;
- dw[14] = 0xfffff000 + init_all;
- dw[15] = 0xfffff000 + init_all;
-}
-
-#endif /* ILO_BUILDER_RENDER_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_CORE_H
-#define ILO_CORE_H
-
-#include "pipe/p_compiler.h"
-
-#include "util/u_math.h"
-
-#endif /* ILO_CORE_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-
-static const struct debug_named_value ilo_debug_flags[] = {
- { "batch", ILO_DEBUG_BATCH, "Dump batch/dynamic/surface/instruction buffers" },
- { "vs", ILO_DEBUG_VS, "Dump vertex shaders" },
- { "gs", ILO_DEBUG_GS, "Dump geometry shaders" },
- { "fs", ILO_DEBUG_FS, "Dump fragment shaders" },
- { "cs", ILO_DEBUG_CS, "Dump compute shaders" },
- { "draw", ILO_DEBUG_DRAW, "Show draw information" },
- { "submit", ILO_DEBUG_SUBMIT, "Show batch buffer submissions" },
- { "hang", ILO_DEBUG_HANG, "Detect GPU hangs" },
- { "nohw", ILO_DEBUG_NOHW, "Do not send commands to HW" },
- { "nocache", ILO_DEBUG_NOCACHE, "Always invalidate HW caches" },
- { "nohiz", ILO_DEBUG_NOHIZ, "Disable HiZ" },
- DEBUG_NAMED_VALUE_END
-};
-
-int ilo_debug;
-
-void
-ilo_debug_init(const char *name)
-{
- ilo_debug = debug_get_flags_option(name, ilo_debug_flags, 0);
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_DEBUG_H
-#define ILO_DEBUG_H
-
-#include "util/u_debug.h"
-
-#include "ilo_core.h"
-
-/* enable debug flags affecting hot pathes only with debug builds */
-#ifdef DEBUG
-#define ILO_DEBUG_HOT 1
-#else
-#define ILO_DEBUG_HOT 0
-#endif
-
-enum ilo_debug {
- ILO_DEBUG_BATCH = 1 << 0,
- ILO_DEBUG_VS = 1 << 1,
- ILO_DEBUG_GS = 1 << 2,
- ILO_DEBUG_FS = 1 << 3,
- ILO_DEBUG_CS = 1 << 4,
- ILO_DEBUG_DRAW = ILO_DEBUG_HOT << 5,
- ILO_DEBUG_SUBMIT = 1 << 6,
- ILO_DEBUG_HANG = 1 << 7,
-
- /* flags that affect the behaviors of the driver */
- ILO_DEBUG_NOHW = 1 << 20,
- ILO_DEBUG_NOCACHE = 1 << 21,
- ILO_DEBUG_NOHIZ = 1 << 22,
-};
-
-extern int ilo_debug;
-
-void
-ilo_debug_init(const char *name);
-
-/**
- * Print a message, for dumping or debugging.
- */
-static inline void _util_printf_format(1, 2)
-ilo_printf(const char *format, ...)
-{
- va_list ap;
-
- va_start(ap, format);
- _debug_vprintf(format, ap);
- va_end(ap);
-}
-
-/**
- * Print a critical error.
- */
-static inline void _util_printf_format(1, 2)
-ilo_err(const char *format, ...)
-{
- va_list ap;
-
- va_start(ap, format);
- _debug_vprintf(format, ap);
- va_end(ap);
-}
-
-/**
- * Print a warning, silenced for release builds.
- */
-static inline void _util_printf_format(1, 2)
-ilo_warn(const char *format, ...)
-{
-#ifdef DEBUG
- va_list ap;
-
- va_start(ap, format);
- _debug_vprintf(format, ap);
- va_end(ap);
-#else
-#endif
-}
-
-static inline bool
-ilo_is_zeroed(const void *ptr, size_t size)
-{
-#ifdef DEBUG
- size_t i;
-
- for (i = 0; i < size; i++) {
- if (*((const char *) ptr) != 0)
- return false;
- }
-
- return true;
-#else
- return true;
-#endif
-}
-
-#endif /* ILO_DEBUG_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "genhw/genhw.h"
-#include "intel_winsys.h"
-
-#include "ilo_debug.h"
-#include "ilo_dev.h"
-
-/**
- * Initialize the \p dev from \p winsys.
- */
-bool
-ilo_dev_init(struct ilo_dev *dev, struct intel_winsys *winsys)
-{
- const struct intel_winsys_info *info;
-
- assert(ilo_is_zeroed(dev, sizeof(*dev)));
-
- info = intel_winsys_get_info(winsys);
-
- dev->winsys = winsys;
- dev->devid = info->devid;
- dev->aperture_total = info->aperture_total;
- dev->aperture_mappable = info->aperture_mappable;
- dev->has_llc = info->has_llc;
- dev->has_address_swizzling = info->has_address_swizzling;
- dev->has_logical_context = info->has_logical_context;
- dev->has_ppgtt = info->has_ppgtt;
- dev->has_timestamp = info->has_timestamp;
- dev->has_gen7_sol_reset = info->has_gen7_sol_reset;
-
- if (!dev->has_logical_context) {
- ilo_err("missing hardware logical context support\n");
- return false;
- }
-
- /*
- * PIPE_CONTROL and MI_* use PPGTT writes on GEN7+ and privileged GGTT
- * writes on GEN6.
- *
- * From the Sandy Bridge PRM, volume 1 part 3, page 101:
- *
- * "[DevSNB] When Per-Process GTT Enable is set, it is assumed that all
- * code is in a secure environment, independent of address space.
- * Under this condition, this bit only specifies the address space
- * (GGTT or PPGTT). All commands are executed "as-is""
- *
- * We need PPGTT to be enabled on GEN6 too.
- */
- if (!dev->has_ppgtt) {
- /* experiments show that it does not really matter... */
- ilo_warn("PPGTT disabled\n");
- }
-
- if (gen_is_bdw(info->devid) || gen_is_chv(info->devid)) {
- dev->gen_opaque = ILO_GEN(8);
- dev->gt = (gen_is_bdw(info->devid)) ? gen_get_bdw_gt(info->devid) : 1;
- /* XXX random values */
- if (dev->gt == 3) {
- dev->eu_count = 48;
- dev->thread_count = 336;
- dev->urb_size = 384 * 1024;
- } else if (dev->gt == 2) {
- dev->eu_count = 24;
- dev->thread_count = 168;
- dev->urb_size = 384 * 1024;
- } else {
- dev->eu_count = 12;
- dev->thread_count = 84;
- dev->urb_size = 192 * 1024;
- }
- } else if (gen_is_hsw(info->devid)) {
- /*
- * From the Haswell PRM, volume 4, page 8:
- *
- * "Description GT3 GT2 GT1.5 GT1
- * (...)
- * EUs (Total) 40 20 12 10
- * Threads (Total) 280 140 84 70
- * (...)
- * URB Size (max, within L3$) 512KB 256KB 256KB 128KB
- */
- dev->gen_opaque = ILO_GEN(7.5);
- dev->gt = gen_get_hsw_gt(info->devid);
- if (dev->gt == 3) {
- dev->eu_count = 40;
- dev->thread_count = 280;
- dev->urb_size = 512 * 1024;
- } else if (dev->gt == 2) {
- dev->eu_count = 20;
- dev->thread_count = 140;
- dev->urb_size = 256 * 1024;
- } else {
- dev->eu_count = 10;
- dev->thread_count = 70;
- dev->urb_size = 128 * 1024;
- }
- } else if (gen_is_ivb(info->devid) || gen_is_vlv(info->devid)) {
- /*
- * From the Ivy Bridge PRM, volume 1 part 1, page 18:
- *
- * "Device # of EUs #Threads/EU
- * Ivy Bridge (GT2) 16 8
- * Ivy Bridge (GT1) 6 6"
- *
- * From the Ivy Bridge PRM, volume 4 part 2, page 17:
- *
- * "URB Size URB Rows URB Rows when SLM Enabled
- * 128k 4096 2048
- * 256k 8096 4096"
- */
- dev->gen_opaque = ILO_GEN(7);
- dev->gt = (gen_is_ivb(info->devid)) ? gen_get_ivb_gt(info->devid) : 1;
- if (dev->gt == 2) {
- dev->eu_count = 16;
- dev->thread_count = 128;
- dev->urb_size = 256 * 1024;
- } else {
- dev->eu_count = 6;
- dev->thread_count = 36;
- dev->urb_size = 128 * 1024;
- }
- } else if (gen_is_snb(info->devid)) {
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 22:
- *
- * "Device # of EUs #Threads/EU
- * SNB GT2 12 5
- * SNB GT1 6 4"
- *
- * From the Sandy Bridge PRM, volume 4 part 2, page 18:
- *
- * "[DevSNB]: The GT1 product's URB provides 32KB of storage,
- * arranged as 1024 256-bit rows. The GT2 product's URB provides
- * 64KB of storage, arranged as 2048 256-bit rows. A row
- * corresponds in size to an EU GRF register. Read/write access to
- * the URB is generally supported on a row-granular basis."
- */
- dev->gen_opaque = ILO_GEN(6);
- dev->gt = gen_get_snb_gt(info->devid);
- if (dev->gt == 2) {
- dev->eu_count = 12;
- dev->thread_count = 60;
- dev->urb_size = 64 * 1024;
- } else {
- dev->eu_count = 6;
- dev->thread_count = 24;
- dev->urb_size = 32 * 1024;
- }
- } else {
- ilo_err("unknown GPU generation\n");
- return false;
- }
-
- return true;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_DEV_H
-#define ILO_DEV_H
-
-#include "ilo_core.h"
-
-#define ILO_GEN(gen) ((int) (gen * 100))
-
-#define ILO_DEV_ASSERT(dev, min_gen, max_gen) \
- ilo_dev_assert(dev, ILO_GEN(min_gen), ILO_GEN(max_gen))
-
-struct intel_winsys;
-
-struct ilo_dev {
- struct intel_winsys *winsys;
-
- /* these mirror intel_winsys_info */
- int devid;
- size_t aperture_total;
- size_t aperture_mappable;
- bool has_llc;
- bool has_address_swizzling;
- bool has_logical_context;
- bool has_ppgtt;
- bool has_timestamp;
- bool has_gen7_sol_reset;
-
- /* use ilo_dev_gen() to access */
- int gen_opaque;
-
- int gt;
- int eu_count;
- int thread_count;
- int urb_size;
-};
-
-bool
-ilo_dev_init(struct ilo_dev *dev, struct intel_winsys *winsys);
-
-static inline int
-ilo_dev_gen(const struct ilo_dev *dev)
-{
- return dev->gen_opaque;
-}
-
-static inline void
-ilo_dev_assert(const struct ilo_dev *dev, int min_opqaue, int max_opqaue)
-{
- assert(dev->gen_opaque >= min_opqaue && dev->gen_opaque <= max_opqaue);
-}
-
-#endif /* ILO_DEV_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-#include "ilo_image.h"
-
-enum {
- IMAGE_TILING_NONE = 1 << GEN6_TILING_NONE,
- IMAGE_TILING_X = 1 << GEN6_TILING_X,
- IMAGE_TILING_Y = 1 << GEN6_TILING_Y,
- IMAGE_TILING_W = 1 << GEN8_TILING_W,
-
- IMAGE_TILING_ALL = (IMAGE_TILING_NONE |
- IMAGE_TILING_X |
- IMAGE_TILING_Y |
- IMAGE_TILING_W)
-};
-
-struct ilo_image_layout {
- enum ilo_image_walk_type walk;
- bool interleaved_samples;
-
- uint8_t valid_tilings;
- enum gen_surface_tiling tiling;
-
- enum ilo_image_aux_type aux;
-
- int align_i;
- int align_j;
-
- struct ilo_image_lod *lods;
- int walk_layer_h0;
- int walk_layer_h1;
- int walk_layer_height;
- int monolithic_width;
- int monolithic_height;
-};
-
-static enum ilo_image_walk_type
-image_get_gen6_walk(const struct ilo_dev *dev,
- const struct ilo_image_info *info)
-{
- ILO_DEV_ASSERT(dev, 6, 6);
-
- /* TODO we want LODs to be page-aligned */
- if (info->type == GEN6_SURFTYPE_3D)
- return ILO_IMAGE_WALK_3D;
-
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 115:
- *
- * "The separate stencil buffer does not support mip mapping, thus the
- * storage for LODs other than LOD 0 is not needed. The following
- * QPitch equation applies only to the separate stencil buffer:
- *
- * QPitch = h_0"
- *
- * Use ILO_IMAGE_WALK_LOD and manually offset to the (page-aligned) levels
- * when bound.
- */
- if (info->bind_zs && info->format == GEN6_FORMAT_R8_UINT)
- return ILO_IMAGE_WALK_LOD;
-
- /* compact spacing is not supported otherwise */
- return ILO_IMAGE_WALK_LAYER;
-}
-
-static enum ilo_image_walk_type
-image_get_gen7_walk(const struct ilo_dev *dev,
- const struct ilo_image_info *info)
-{
- ILO_DEV_ASSERT(dev, 7, 8);
-
- if (info->type == GEN6_SURFTYPE_3D)
- return ILO_IMAGE_WALK_3D;
-
- /*
- * From the Ivy Bridge PRM, volume 1 part 1, page 111:
- *
- * "note that the depth buffer and stencil buffer have an implied value
- * of ARYSPC_FULL"
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 66:
- *
- * "If Multisampled Surface Storage Format is MSFMT_MSS and Number of
- * Multisamples is not MULTISAMPLECOUNT_1, this field (Surface Array
- * Spacing) must be set to ARYSPC_LOD0."
- */
- if (info->sample_count > 1)
- assert(info->level_count == 1);
- return (info->bind_zs || info->level_count > 1) ?
- ILO_IMAGE_WALK_LAYER : ILO_IMAGE_WALK_LOD;
-}
-
-static bool
-image_get_gen6_interleaved_samples(const struct ilo_dev *dev,
- const struct ilo_image_info *info)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * Gen6 supports only interleaved samples. It is not explicitly stated,
- * but on Gen7+, render targets are expected to be UMS/CMS (samples
- * non-interleaved) and depth/stencil buffers are expected to be IMS
- * (samples interleaved).
- *
- * See "Multisampled Surface Storage Format" field of SURFACE_STATE.
- */
- return (ilo_dev_gen(dev) == ILO_GEN(6) || info->bind_zs);
-}
-
-static uint8_t
-image_get_gen6_valid_tilings(const struct ilo_dev *dev,
- const struct ilo_image_info *info)
-{
- uint8_t valid_tilings = IMAGE_TILING_ALL;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (info->valid_tilings)
- valid_tilings &= info->valid_tilings;
-
- /*
- * From the Sandy Bridge PRM, volume 1 part 2, page 32:
- *
- * "Display/Overlay Y-Major not supported.
- * X-Major required for Async Flips"
- */
- if (unlikely(info->bind_scanout))
- valid_tilings &= IMAGE_TILING_X;
-
- /*
- * From the Sandy Bridge PRM, volume 3 part 2, page 158:
- *
- * "The cursor surface address must be 4K byte aligned. The cursor must
- * be in linear memory, it cannot be tiled."
- */
- if (unlikely(info->bind_cursor))
- valid_tilings &= IMAGE_TILING_NONE;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 318:
- *
- * "[DevSNB+]: This field (Tiled Surface) must be set to TRUE. Linear
- * Depth Buffer is not supported."
- *
- * "The Depth Buffer, if tiled, must use Y-Major tiling."
- *
- * From the Sandy Bridge PRM, volume 1 part 2, page 22:
- *
- * "W-Major Tile Format is used for separate stencil."
- */
- if (info->bind_zs) {
- if (info->format == GEN6_FORMAT_R8_UINT)
- valid_tilings &= IMAGE_TILING_W;
- else
- valid_tilings &= IMAGE_TILING_Y;
- }
-
- if (info->bind_surface_sampler ||
- info->bind_surface_dp_render ||
- info->bind_surface_dp_typed) {
- /*
- * From the Haswell PRM, volume 2d, page 233:
- *
- * "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
- * (Tiled Surface) must be TRUE."
- */
- if (info->sample_count > 1)
- valid_tilings &= ~IMAGE_TILING_NONE;
-
- if (ilo_dev_gen(dev) < ILO_GEN(8))
- valid_tilings &= ~IMAGE_TILING_W;
- }
-
- if (info->bind_surface_dp_render) {
- /*
- * From the Sandy Bridge PRM, volume 1 part 2, page 32:
- *
- * "NOTE: 128BPE Format Color buffer ( render target ) MUST be
- * either TileX or Linear."
- *
- * From the Haswell PRM, volume 5, page 32:
- *
- * "NOTE: 128 BPP format color buffer (render target) supports
- * Linear, TiledX and TiledY."
- */
- if (ilo_dev_gen(dev) < ILO_GEN(7.5) && info->block_size == 16)
- valid_tilings &= ~IMAGE_TILING_Y;
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 63:
- *
- * "This field (Surface Vertical Aligment) must be set to VALIGN_4
- * for all tiled Y Render Target surfaces."
- *
- * "VALIGN_4 is not supported for surface format R32G32B32_FLOAT."
- *
- * R32G32B32_FLOAT is not renderable and we only need an assert() here.
- */
- if (ilo_dev_gen(dev) >= ILO_GEN(7) && ilo_dev_gen(dev) <= ILO_GEN(7.5))
- assert(info->format != GEN6_FORMAT_R32G32B32_FLOAT);
- }
-
- return valid_tilings;
-}
-
-static uint64_t
-image_get_gen6_estimated_size(const struct ilo_dev *dev,
- const struct ilo_image_info *info)
-{
- /* padding not considered */
- const uint64_t slice_size = info->width * info->height *
- info->block_size / (info->block_width * info->block_height);
- const uint64_t slice_count =
- info->depth * info->array_size * info->sample_count;
- const uint64_t estimated_size = slice_size * slice_count;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (info->level_count == 1)
- return estimated_size;
- else
- return estimated_size * 4 / 3;
-}
-
-static enum gen_surface_tiling
-image_get_gen6_tiling(const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- uint8_t valid_tilings)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- switch (valid_tilings) {
- case IMAGE_TILING_NONE:
- return GEN6_TILING_NONE;
- case IMAGE_TILING_X:
- return GEN6_TILING_X;
- case IMAGE_TILING_Y:
- return GEN6_TILING_Y;
- case IMAGE_TILING_W:
- return GEN8_TILING_W;
- default:
- break;
- }
-
- /*
- * X-tiling has the property that vertically adjacent pixels are usually in
- * the same page. When the image size is less than a page, the image
- * height is 1, or when the image is not accessed in blocks, there is no
- * reason to tile.
- *
- * Y-tiling is similar, where vertically adjacent pixels are usually in the
- * same cacheline.
- */
- if (valid_tilings & IMAGE_TILING_NONE) {
- const uint64_t estimated_size =
- image_get_gen6_estimated_size(dev, info);
-
- if (info->height == 1 || !(info->bind_surface_sampler ||
- info->bind_surface_dp_render ||
- info->bind_surface_dp_typed))
- return GEN6_TILING_NONE;
-
- if (estimated_size <= 64 || (info->prefer_linear_threshold &&
- estimated_size > info->prefer_linear_threshold))
- return GEN6_TILING_NONE;
-
- if (estimated_size <= 2048)
- valid_tilings &= ~IMAGE_TILING_X;
- }
-
- return (valid_tilings & IMAGE_TILING_Y) ? GEN6_TILING_Y :
- (valid_tilings & IMAGE_TILING_X) ? GEN6_TILING_X :
- GEN6_TILING_NONE;
-}
-
-static bool
-image_get_gen6_hiz_enable(const struct ilo_dev *dev,
- const struct ilo_image_info *info)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* depth buffer? */
- if (!info->bind_zs ||
- info->format == GEN6_FORMAT_R8_UINT ||
- info->interleaved_stencil)
- return false;
-
- /* we want to be able to force 8x4 alignments */
- if (info->type == GEN6_SURFTYPE_1D)
- return false;
-
- if (info->aux_disable)
- return false;
-
- if (ilo_debug & ILO_DEBUG_NOHIZ)
- return false;
-
- return true;
-}
-
-static bool
-image_get_gen7_mcs_enable(const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- enum gen_surface_tiling tiling)
-{
- ILO_DEV_ASSERT(dev, 7, 8);
-
- if (!info->bind_surface_sampler && !info->bind_surface_dp_render)
- return false;
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 77:
- *
- * "For Render Target and Sampling Engine Surfaces:If the surface is
- * multisampled (Number of Multisamples any value other than
- * MULTISAMPLECOUNT_1), this field (MCS Enable) must be enabled."
- *
- * "This field must be set to 0 for all SINT MSRTs when all RT channels
- * are not written"
- */
- if (info->sample_count > 1) {
- if (ilo_dev_gen(dev) < ILO_GEN(8))
- assert(!info->is_integer);
- return true;
- }
-
- if (info->aux_disable)
- return false;
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 326:
- *
- * "When MCS is buffer is used for color clear of non-multisampler
- * render target, the following restrictions apply.
- * - Support is limited to tiled render targets.
- * - Support is for non-mip-mapped and non-array surface types only.
- * - Clear is supported only on the full RT; i.e., no partial clear or
- * overlapping clears.
- * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
- * 64bpp and 128bpp.
- * ..."
- *
- * How about SURFTYPE_3D?
- */
- if (!info->bind_surface_dp_render ||
- tiling == GEN6_TILING_NONE ||
- info->level_count > 1 ||
- info->array_size > 1)
- return false;
-
- switch (info->block_size) {
- case 4:
- case 8:
- case 16:
- return true;
- default:
- return false;
- }
-}
-
-static void
-image_get_gen6_alignments(const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- int *align_i, int *align_j)
-{
- ILO_DEV_ASSERT(dev, 6, 6);
-
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 113:
- *
- * "surface format align_i align_j
- * YUV 4:2:2 formats 4 *see below
- * BC1-5 4 4
- * FXT1 8 4
- * all other formats 4 *see below"
- *
- * "- align_j = 4 for any depth buffer
- * - align_j = 2 for separate stencil buffer
- * - align_j = 4 for any render target surface is multisampled (4x)
- * - align_j = 4 for any render target surface with Surface Vertical
- * Alignment = VALIGN_4
- * - align_j = 2 for any render target surface with Surface Vertical
- * Alignment = VALIGN_2
- * - align_j = 2 for all other render target surface
- * - align_j = 2 for any sampling engine surface with Surface Vertical
- * Alignment = VALIGN_2
- * - align_j = 4 for any sampling engine surface with Surface Vertical
- * Alignment = VALIGN_4"
- *
- * From the Sandy Bridge PRM, volume 4 part 1, page 86:
- *
- * "This field (Surface Vertical Alignment) must be set to VALIGN_2 if
- * the Surface Format is 96 bits per element (BPE)."
- *
- * They can be rephrased as
- *
- * align_i align_j
- * compressed formats block width block height
- * GEN6_FORMAT_R8_UINT 4 2
- * other depth/stencil formats 4 4
- * 4x multisampled 4 4
- * bpp 96 4 2
- * others 4 2 or 4
- */
-
- *align_i = (info->compressed) ? info->block_width : 4;
- if (info->compressed) {
- *align_j = info->block_height;
- } else if (info->bind_zs) {
- *align_j = (info->format == GEN6_FORMAT_R8_UINT) ? 2 : 4;
- } else {
- *align_j = (info->sample_count > 1 || info->block_size != 12) ? 4 : 2;
- }
-}
-
-static void
-image_get_gen7_alignments(const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- enum gen_surface_tiling tiling,
- int *align_i, int *align_j)
-{
- int i, j;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 1 part 1, page 110:
- *
- * "surface defined by surface format align_i align_j
- * 3DSTATE_DEPTH_BUFFER D16_UNORM 8 4
- * not D16_UNORM 4 4
- * 3DSTATE_STENCIL_BUFFER N/A 8 8
- * SURFACE_STATE BC*, ETC*, EAC* 4 4
- * FXT1 8 4
- * all others (set by SURFACE_STATE)"
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 63:
- *
- * "- This field (Surface Vertical Aligment) is intended to be set to
- * VALIGN_4 if the surface was rendered as a depth buffer, for a
- * multisampled (4x) render target, or for a multisampled (8x)
- * render target, since these surfaces support only alignment of 4.
- * - Use of VALIGN_4 for other surfaces is supported, but uses more
- * memory.
- * - This field must be set to VALIGN_4 for all tiled Y Render Target
- * surfaces.
- * - Value of 1 is not supported for format YCRCB_NORMAL (0x182),
- * YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY (0x190)
- * - If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
- * must be set to VALIGN_4."
- * - VALIGN_4 is not supported for surface format R32G32B32_FLOAT."
- *
- * "- This field (Surface Horizontal Aligment) is intended to be set to
- * HALIGN_8 only if the surface was rendered as a depth buffer with
- * Z16 format or a stencil buffer, since these surfaces support only
- * alignment of 8.
- * - Use of HALIGN_8 for other surfaces is supported, but uses more
- * memory.
- * - This field must be set to HALIGN_4 if the Surface Format is BC*.
- * - This field must be set to HALIGN_8 if the Surface Format is
- * FXT1."
- *
- * They can be rephrased as
- *
- * align_i align_j
- * compressed formats block width block height
- * GEN6_FORMAT_R16_UNORM 8 4
- * GEN6_FORMAT_R8_UINT 8 8
- * other depth/stencil formats 4 4
- * 2x or 4x multisampled 4 or 8 4
- * tiled Y 4 or 8 4 (if rt)
- * GEN6_FORMAT_R32G32B32_FLOAT 4 or 8 2
- * others 4 or 8 2 or 4
- */
- if (info->compressed) {
- i = info->block_width;
- j = info->block_height;
- } else if (info->bind_zs) {
- switch (info->format) {
- case GEN6_FORMAT_R16_UNORM:
- i = 8;
- j = 4;
- break;
- case GEN6_FORMAT_R8_UINT:
- i = 8;
- j = 8;
- break;
- default:
- i = 4;
- j = 4;
- break;
- }
- } else {
- const bool valign_4 =
- (info->sample_count > 1 || ilo_dev_gen(dev) >= ILO_GEN(8) ||
- (tiling == GEN6_TILING_Y && info->bind_surface_dp_render));
-
- if (ilo_dev_gen(dev) < ILO_GEN(8) && valign_4)
- assert(info->format != GEN6_FORMAT_R32G32B32_FLOAT);
-
- i = 4;
- j = (valign_4) ? 4 : 2;
- }
-
- *align_i = i;
- *align_j = j;
-}
-
-static bool
-image_init_gen6_hardware_layout(const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- struct ilo_image_layout *layout)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- layout->walk = image_get_gen7_walk(dev, info);
- else
- layout->walk = image_get_gen6_walk(dev, info);
-
- layout->interleaved_samples =
- image_get_gen6_interleaved_samples(dev, info);
-
- layout->valid_tilings = image_get_gen6_valid_tilings(dev, info);
- if (!layout->valid_tilings)
- return false;
-
- layout->tiling = image_get_gen6_tiling(dev, info, layout->valid_tilings);
-
- if (image_get_gen6_hiz_enable(dev, info))
- layout->aux = ILO_IMAGE_AUX_HIZ;
- else if (ilo_dev_gen(dev) >= ILO_GEN(7) &&
- image_get_gen7_mcs_enable(dev, info, layout->tiling))
- layout->aux = ILO_IMAGE_AUX_MCS;
- else
- layout->aux = ILO_IMAGE_AUX_NONE;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- image_get_gen7_alignments(dev, info, layout->tiling,
- &layout->align_i, &layout->align_j);
- } else {
- image_get_gen6_alignments(dev, info,
- &layout->align_i, &layout->align_j);
- }
-
- return true;
-}
-
-static bool
-image_init_gen6_transfer_layout(const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- struct ilo_image_layout *layout)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* we can define our own layout to save space */
- layout->walk = ILO_IMAGE_WALK_LOD;
- layout->interleaved_samples = false;
- layout->valid_tilings = IMAGE_TILING_NONE;
- layout->tiling = GEN6_TILING_NONE;
- layout->aux = ILO_IMAGE_AUX_NONE;
- layout->align_i = info->block_width;
- layout->align_j = info->block_height;
-
- return true;
-}
-
-static void
-image_get_gen6_slice_size(const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- const struct ilo_image_layout *layout,
- uint8_t level,
- int *width, int *height)
-{
- int w, h;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- w = u_minify(info->width, level);
- h = u_minify(info->height, level);
-
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 114:
- *
- * "The dimensions of the mip maps are first determined by applying the
- * sizing algorithm presented in Non-Power-of-Two Mipmaps above. Then,
- * if necessary, they are padded out to compression block boundaries."
- */
- w = align(w, info->block_width);
- h = align(h, info->block_height);
-
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 111:
- *
- * "If the surface is multisampled (4x), these values must be adjusted
- * as follows before proceeding:
- *
- * W_L = ceiling(W_L / 2) * 4
- * H_L = ceiling(H_L / 2) * 4"
- *
- * From the Ivy Bridge PRM, volume 1 part 1, page 108:
- *
- * "If the surface is multisampled and it is a depth or stencil surface
- * or Multisampled Surface StorageFormat in SURFACE_STATE is
- * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
- * proceeding:
- *
- * #samples W_L = H_L =
- * 2 ceiling(W_L / 2) * 4 HL [no adjustment]
- * 4 ceiling(W_L / 2) * 4 ceiling(H_L / 2) * 4
- * 8 ceiling(W_L / 2) * 8 ceiling(H_L / 2) * 4
- * 16 ceiling(W_L / 2) * 8 ceiling(H_L / 2) * 8"
- *
- * For interleaved samples (4x), where pixels
- *
- * (x, y ) (x+1, y )
- * (x, y+1) (x+1, y+1)
- *
- * would be is occupied by
- *
- * (x, y , si0) (x+1, y , si0) (x, y , si1) (x+1, y , si1)
- * (x, y+1, si0) (x+1, y+1, si0) (x, y+1, si1) (x+1, y+1, si1)
- * (x, y , si2) (x+1, y , si2) (x, y , si3) (x+1, y , si3)
- * (x, y+1, si2) (x+1, y+1, si2) (x, y+1, si3) (x+1, y+1, si3)
- *
- * Thus the need to
- *
- * w = align(w, 2) * 2;
- * y = align(y, 2) * 2;
- */
- if (layout->interleaved_samples) {
- switch (info->sample_count) {
- case 1:
- break;
- case 2:
- w = align(w, 2) * 2;
- break;
- case 4:
- w = align(w, 2) * 2;
- h = align(h, 2) * 2;
- break;
- case 8:
- w = align(w, 2) * 4;
- h = align(h, 2) * 2;
- break;
- case 16:
- w = align(w, 2) * 4;
- h = align(h, 2) * 4;
- break;
- default:
- assert(!"unsupported sample count");
- break;
- }
- }
-
- /*
- * From the Ivy Bridge PRM, volume 1 part 1, page 108:
- *
- * "For separate stencil buffer, the width must be mutiplied by 2 and
- * height divided by 2..."
- *
- * To make things easier (for transfer), we will just double the stencil
- * stride in 3DSTATE_STENCIL_BUFFER.
- */
- w = align(w, layout->align_i);
- h = align(h, layout->align_j);
-
- *width = w;
- *height = h;
-}
-
-static int
-image_get_gen6_layer_count(const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- const struct ilo_image_layout *layout)
-{
- int count = info->array_size;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* samples of the same index are stored in a layer */
- if (!layout->interleaved_samples)
- count *= info->sample_count;
-
- return count;
-}
-
-static void
-image_get_gen6_walk_layer_heights(const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- struct ilo_image_layout *layout)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- layout->walk_layer_h0 = layout->lods[0].slice_height;
-
- if (info->level_count > 1) {
- layout->walk_layer_h1 = layout->lods[1].slice_height;
- } else {
- int dummy;
- image_get_gen6_slice_size(dev, info, layout, 1,
- &dummy, &layout->walk_layer_h1);
- }
-
- if (image_get_gen6_layer_count(dev, info, layout) == 1) {
- layout->walk_layer_height = 0;
- return;
- }
-
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 115:
- *
- * "The following equation is used for surface formats other than
- * compressed textures:
- *
- * QPitch = (h0 + h1 + 11j)"
- *
- * "The equation for compressed textures (BC* and FXT1 surface formats)
- * follows:
- *
- * QPitch = (h0 + h1 + 11j) / 4"
- *
- * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the
- * value calculated in the equation above, for every other odd Surface
- * Height starting from 1 i.e. 1,5,9,13"
- *
- * From the Ivy Bridge PRM, volume 1 part 1, page 111-112:
- *
- * "If Surface Array Spacing is set to ARYSPC_FULL (note that the depth
- * buffer and stencil buffer have an implied value of ARYSPC_FULL):
- *
- * QPitch = (h0 + h1 + 12j)
- * QPitch = (h0 + h1 + 12j) / 4 (compressed)
- *
- * (There are many typos or missing words here...)"
- *
- * To access the N-th slice, an offset of (Stride * QPitch * N) is added to
- * the base address. The PRM divides QPitch by 4 for compressed formats
- * because the block height for those formats are 4, and it wants QPitch to
- * mean the number of memory rows, as opposed to texel rows, between
- * slices. Since we use texel rows everywhere, we do not need to divide
- * QPitch by 4.
- */
- layout->walk_layer_height = layout->walk_layer_h0 + layout->walk_layer_h1 +
- ((ilo_dev_gen(dev) >= ILO_GEN(7)) ? 12 : 11) * layout->align_j;
-
- if (ilo_dev_gen(dev) == ILO_GEN(6) && info->sample_count > 1 &&
- info->height % 4 == 1)
- layout->walk_layer_height += 4;
-}
-
-static void
-image_get_gen6_monolithic_size(const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- struct ilo_image_layout *layout,
- int max_x, int max_y)
-{
- int align_w = 1, align_h = 1, pad_h = 0;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 118:
- *
- * "To determine the necessary padding on the bottom and right side of
- * the surface, refer to the table in Section 7.18.3.4 for the i and j
- * parameters for the surface format in use. The surface must then be
- * extended to the next multiple of the alignment unit size in each
- * dimension, and all texels contained in this extended surface must
- * have valid GTT entries."
- *
- * "For cube surfaces, an additional two rows of padding are required
- * at the bottom of the surface. This must be ensured regardless of
- * whether the surface is stored tiled or linear. This is due to the
- * potential rotation of cache line orientation from memory to cache."
- *
- * "For compressed textures (BC* and FXT1 surface formats), padding at
- * the bottom of the surface is to an even compressed row, which is
- * equal to a multiple of 8 uncompressed texel rows. Thus, for padding
- * purposes, these surfaces behave as if j = 8 only for surface
- * padding purposes. The value of 4 for j still applies for mip level
- * alignment and QPitch calculation."
- */
- if (info->bind_surface_sampler) {
- align_w = MAX2(align_w, layout->align_i);
- align_h = MAX2(align_h, layout->align_j);
-
- if (info->type == GEN6_SURFTYPE_CUBE)
- pad_h += 2;
-
- if (info->compressed)
- align_h = MAX2(align_h, layout->align_j * 2);
- }
-
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 118:
- *
- * "If the surface contains an odd number of rows of data, a final row
- * below the surface must be allocated."
- */
- if (info->bind_surface_dp_render)
- align_h = MAX2(align_h, 2);
-
- /*
- * Depth Buffer Clear/Resolve works in 8x4 sample blocks. Pad to allow HiZ
- * for unaligned non-mipmapped and non-array images.
- */
- if (layout->aux == ILO_IMAGE_AUX_HIZ &&
- info->level_count == 1 && info->array_size == 1 && info->depth == 1) {
- align_w = MAX2(align_w, 8);
- align_h = MAX2(align_h, 4);
- }
-
- layout->monolithic_width = align(max_x, align_w);
- layout->monolithic_height = align(max_y + pad_h, align_h);
-}
-
-static void
-image_get_gen6_lods(const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- struct ilo_image_layout *layout)
-{
- const int layer_count = image_get_gen6_layer_count(dev, info, layout);
- int cur_x, cur_y, max_x, max_y;
- uint8_t lv;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- cur_x = 0;
- cur_y = 0;
- max_x = 0;
- max_y = 0;
- for (lv = 0; lv < info->level_count; lv++) {
- int slice_w, slice_h, lod_w, lod_h;
-
- image_get_gen6_slice_size(dev, info, layout, lv, &slice_w, &slice_h);
-
- layout->lods[lv].x = cur_x;
- layout->lods[lv].y = cur_y;
- layout->lods[lv].slice_width = slice_w;
- layout->lods[lv].slice_height = slice_h;
-
- switch (layout->walk) {
- case ILO_IMAGE_WALK_LAYER:
- lod_w = slice_w;
- lod_h = slice_h;
-
- /* MIPLAYOUT_BELOW */
- if (lv == 1)
- cur_x += lod_w;
- else
- cur_y += lod_h;
- break;
- case ILO_IMAGE_WALK_LOD:
- lod_w = slice_w;
- lod_h = slice_h * layer_count;
-
- if (lv == 1)
- cur_x += lod_w;
- else
- cur_y += lod_h;
-
- /* every LOD begins at tile boundaries */
- if (info->level_count > 1) {
- assert(info->format == GEN6_FORMAT_R8_UINT);
- cur_x = align(cur_x, 64);
- cur_y = align(cur_y, 64);
- }
- break;
- case ILO_IMAGE_WALK_3D:
- {
- const int slice_count = u_minify(info->depth, lv);
- const int slice_count_per_row = 1 << lv;
- const int row_count =
- (slice_count + slice_count_per_row - 1) / slice_count_per_row;
-
- lod_w = slice_w * slice_count_per_row;
- lod_h = slice_h * row_count;
- }
-
- cur_y += lod_h;
- break;
- default:
- assert(!"unknown walk type");
- lod_w = 0;
- lod_h = 0;
- break;
- }
-
- if (max_x < layout->lods[lv].x + lod_w)
- max_x = layout->lods[lv].x + lod_w;
- if (max_y < layout->lods[lv].y + lod_h)
- max_y = layout->lods[lv].y + lod_h;
- }
-
- if (layout->walk == ILO_IMAGE_WALK_LAYER) {
- image_get_gen6_walk_layer_heights(dev, info, layout);
- if (layer_count > 1)
- max_y += layout->walk_layer_height * (layer_count - 1);
- } else {
- layout->walk_layer_h0 = 0;
- layout->walk_layer_h1 = 0;
- layout->walk_layer_height = 0;
- }
-
- image_get_gen6_monolithic_size(dev, info, layout, max_x, max_y);
-}
-
-static bool
-image_bind_gpu(const struct ilo_image_info *info)
-{
- return (info->bind_surface_sampler ||
- info->bind_surface_dp_render ||
- info->bind_surface_dp_typed ||
- info->bind_zs ||
- info->bind_scanout ||
- info->bind_cursor);
-}
-
-static bool
-image_validate_gen6(const struct ilo_dev *dev,
- const struct ilo_image_info *info)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 314:
- *
- * "The separate stencil buffer is always enabled, thus the field in
- * 3DSTATE_DEPTH_BUFFER to explicitly enable the separate stencil
- * buffer has been removed Surface formats with interleaved depth and
- * stencil are no longer supported"
- */
- if (ilo_dev_gen(dev) >= ILO_GEN(7) && info->bind_zs)
- assert(!info->interleaved_stencil);
-
- return true;
-}
-
-static bool
-image_get_gen6_layout(const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- struct ilo_image_layout *layout)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (!image_validate_gen6(dev, info))
- return false;
-
- if (image_bind_gpu(info) || info->level_count > 1) {
- if (!image_init_gen6_hardware_layout(dev, info, layout))
- return false;
- } else {
- if (!image_init_gen6_transfer_layout(dev, info, layout))
- return false;
- }
-
- /*
- * the fact that align i and j are multiples of block width and height
- * respectively is what makes the size of the bo a multiple of the block
- * size, slices start at block boundaries, and many of the computations
- * work.
- */
- assert(layout->align_i % info->block_width == 0);
- assert(layout->align_j % info->block_height == 0);
-
- /* make sure align() works */
- assert(util_is_power_of_two(layout->align_i) &&
- util_is_power_of_two(layout->align_j));
- assert(util_is_power_of_two(info->block_width) &&
- util_is_power_of_two(info->block_height));
-
- image_get_gen6_lods(dev, info, layout);
-
- assert(layout->walk_layer_height % info->block_height == 0);
- assert(layout->monolithic_width % info->block_width == 0);
- assert(layout->monolithic_height % info->block_height == 0);
-
- return true;
-}
-
-static bool
-image_set_gen6_bo_size(struct ilo_image *img,
- const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- const struct ilo_image_layout *layout)
-{
- int stride, height;
- int align_w, align_h;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- stride = (layout->monolithic_width / info->block_width) * info->block_size;
- height = layout->monolithic_height / info->block_height;
-
- /*
- * From the Haswell PRM, volume 5, page 163:
- *
- * "For linear surfaces, additional padding of 64 bytes is required
- * at the bottom of the surface. This is in addition to the padding
- * required above."
- */
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5) && info->bind_surface_sampler &&
- layout->tiling == GEN6_TILING_NONE)
- height += (64 + stride - 1) / stride;
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 81:
- *
- * "- For linear render target surfaces, the pitch must be a multiple
- * of the element size for non-YUV surface formats. Pitch must be a
- * multiple of 2 * element size for YUV surface formats.
- *
- * - For other linear surfaces, the pitch can be any multiple of
- * bytes.
- * - For tiled surfaces, the pitch must be a multiple of the tile
- * width."
- *
- * Different requirements may exist when the image is used in different
- * places, but our alignments here should be good enough that we do not
- * need to check info->bind_x.
- */
- switch (layout->tiling) {
- case GEN6_TILING_X:
- align_w = 512;
- align_h = 8;
- break;
- case GEN6_TILING_Y:
- align_w = 128;
- align_h = 32;
- break;
- case GEN8_TILING_W:
- /*
- * From the Sandy Bridge PRM, volume 1 part 2, page 22:
- *
- * "A 4KB tile is subdivided into 8-high by 8-wide array of
- * Blocks for W-Major Tiles (W Tiles). Each Block is 8 rows by 8
- * bytes."
- */
- align_w = 64;
- align_h = 64;
- break;
- default:
- assert(layout->tiling == GEN6_TILING_NONE);
- /* some good enough values */
- align_w = 64;
- align_h = 2;
- break;
- }
-
- if (info->force_bo_stride) {
- if (info->force_bo_stride % align_w || info->force_bo_stride < stride)
- return false;
-
- img->bo_stride = info->force_bo_stride;
- } else {
- img->bo_stride = align(stride, align_w);
- }
-
- img->bo_height = align(height, align_h);
-
- return true;
-}
-
-static bool
-image_set_gen6_hiz(struct ilo_image *img,
- const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- const struct ilo_image_layout *layout)
-{
- const int hz_align_j = 8;
- enum ilo_image_walk_type hz_walk;
- int hz_width, hz_height;
- int hz_clear_w, hz_clear_h;
- uint8_t lv;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(layout->aux == ILO_IMAGE_AUX_HIZ);
-
- assert(layout->walk == ILO_IMAGE_WALK_LAYER ||
- layout->walk == ILO_IMAGE_WALK_3D);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 312:
- *
- * "The hierarchical depth buffer does not support the LOD field, it is
- * assumed by hardware to be zero. A separate hierarachical depth
- * buffer is required for each LOD used, and the corresponding
- * buffer's state delivered to hardware each time a new depth buffer
- * state with modified LOD is delivered."
- *
- * We will put all LODs in a single bo with ILO_IMAGE_WALK_LOD.
- */
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- hz_walk = layout->walk;
- else
- hz_walk = ILO_IMAGE_WALK_LOD;
-
- /*
- * See the Sandy Bridge PRM, volume 2 part 1, page 312, and the Ivy Bridge
- * PRM, volume 2 part 1, page 312-313.
- *
- * It seems HiZ buffer is aligned to 8x8, with every two rows packed into a
- * memory row.
- */
- switch (hz_walk) {
- case ILO_IMAGE_WALK_LAYER:
- {
- const int h0 = align(layout->walk_layer_h0, hz_align_j);
- const int h1 = align(layout->walk_layer_h1, hz_align_j);
- const int htail =
- ((ilo_dev_gen(dev) >= ILO_GEN(7)) ? 12 : 11) * hz_align_j;
- const int hz_qpitch = h0 + h1 + htail;
-
- hz_width = align(layout->lods[0].slice_width, 16);
-
- hz_height = hz_qpitch * info->array_size / 2;
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- hz_height = align(hz_height, 8);
-
- img->aux.walk_layer_height = hz_qpitch;
- }
- break;
- case ILO_IMAGE_WALK_LOD:
- {
- int lod_tx[ILO_IMAGE_MAX_LEVEL_COUNT];
- int lod_ty[ILO_IMAGE_MAX_LEVEL_COUNT];
- int cur_tx, cur_ty;
-
- /* figure out the tile offsets of LODs */
- hz_width = 0;
- hz_height = 0;
- cur_tx = 0;
- cur_ty = 0;
- for (lv = 0; lv < info->level_count; lv++) {
- int tw, th;
-
- lod_tx[lv] = cur_tx;
- lod_ty[lv] = cur_ty;
-
- tw = align(layout->lods[lv].slice_width, 16);
- th = align(layout->lods[lv].slice_height, hz_align_j) *
- info->array_size / 2;
- /* convert to Y-tiles */
- tw = (tw + 127) / 128;
- th = (th + 31) / 32;
-
- if (hz_width < cur_tx + tw)
- hz_width = cur_tx + tw;
- if (hz_height < cur_ty + th)
- hz_height = cur_ty + th;
-
- if (lv == 1)
- cur_tx += tw;
- else
- cur_ty += th;
- }
-
- /* convert tile offsets to memory offsets */
- for (lv = 0; lv < info->level_count; lv++) {
- img->aux.walk_lod_offsets[lv] =
- (lod_ty[lv] * hz_width + lod_tx[lv]) * 4096;
- }
-
- hz_width *= 128;
- hz_height *= 32;
- }
- break;
- case ILO_IMAGE_WALK_3D:
- hz_width = align(layout->lods[0].slice_width, 16);
-
- hz_height = 0;
- for (lv = 0; lv < info->level_count; lv++) {
- const int h = align(layout->lods[lv].slice_height, hz_align_j);
- /* according to the formula, slices are packed together vertically */
- hz_height += h * u_minify(info->depth, lv);
- }
- hz_height /= 2;
- break;
- default:
- assert(!"unknown HiZ walk");
- hz_width = 0;
- hz_height = 0;
- break;
- }
-
- /*
- * In hiz_align_fb(), we will align the LODs to 8x4 sample blocks.
- * Experiments on Haswell show that aligning the RECTLIST primitive and
- * 3DSTATE_DRAWING_RECTANGLE alone are not enough. The LOD sizes must be
- * aligned.
- */
- hz_clear_w = 8;
- hz_clear_h = 4;
- switch (info->sample_count) {
- case 1:
- default:
- break;
- case 2:
- hz_clear_w /= 2;
- break;
- case 4:
- hz_clear_w /= 2;
- hz_clear_h /= 2;
- break;
- case 8:
- hz_clear_w /= 4;
- hz_clear_h /= 2;
- break;
- case 16:
- hz_clear_w /= 4;
- hz_clear_h /= 4;
- break;
- }
-
- for (lv = 0; lv < info->level_count; lv++) {
- if (u_minify(info->width, lv) % hz_clear_w ||
- u_minify(info->height, lv) % hz_clear_h)
- break;
- img->aux.enables |= 1 << lv;
- }
-
- /* we padded to allow this in image_get_gen6_monolithic_size() */
- if (info->level_count == 1 && info->array_size == 1 && info->depth == 1)
- img->aux.enables |= 0x1;
-
- /* align to Y-tile */
- img->aux.bo_stride = align(hz_width, 128);
- img->aux.bo_height = align(hz_height, 32);
-
- return true;
-}
-
-static bool
-image_set_gen7_mcs(struct ilo_image *img,
- const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- const struct ilo_image_layout *layout)
-{
- int mcs_width, mcs_height, mcs_cpp;
- int downscale_x, downscale_y;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- assert(layout->aux == ILO_IMAGE_AUX_MCS);
-
- if (info->sample_count > 1) {
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 326, the clear
- * rectangle is scaled down by 8x2 for 4X MSAA and 2x2 for 8X MSAA. The
- * need of scale down could be that the clear rectangle is used to clear
- * the MCS instead of the RT.
- *
- * For 8X MSAA, we need 32 bits in MCS for every pixel in the RT. The
- * 2x2 factor could come from that the hardware writes 128 bits (an
- * OWord) at a time, and the OWord in MCS maps to a 2x2 pixel block in
- * the RT. For 4X MSAA, we need 8 bits in MCS for every pixel in the
- * RT. Similarly, we could reason that an OWord in 4X MCS maps to a 8x2
- * pixel block in the RT.
- */
- switch (info->sample_count) {
- case 2:
- case 4:
- downscale_x = 8;
- downscale_y = 2;
- mcs_cpp = 1;
- break;
- case 8:
- downscale_x = 2;
- downscale_y = 2;
- mcs_cpp = 4;
- break;
- case 16:
- downscale_x = 2;
- downscale_y = 1;
- mcs_cpp = 8;
- break;
- default:
- assert(!"unsupported sample count");
- return false;
- break;
- }
-
- /*
- * It also appears that the 2x2 subspans generated by the scaled-down
- * clear rectangle cannot be masked. The scale-down clear rectangle
- * thus must be aligned to 2x2, and we need to pad.
- */
- mcs_width = align(info->width, downscale_x * 2);
- mcs_height = align(info->height, downscale_y * 2);
- } else {
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 327:
- *
- * " Pixels Lines
- * TiledY RT CL
- * bpp
- * 32 8 4
- * 64 4 4
- * 128 2 4
- *
- * TiledX RT CL
- * bpp
- * 32 16 2
- * 64 8 2
- * 128 4 2"
- *
- * This table and the two following tables define the RT alignments, the
- * clear rectangle alignments, and the clear rectangle scale factors.
- * Viewing the RT alignments as the sizes of 128-byte blocks, we can see
- * that the clear rectangle alignments are 16x32 blocks, and the clear
- * rectangle scale factors are 8x16 blocks.
- *
- * For non-MSAA RT, we need 1 bit in MCS for every 128-byte block in the
- * RT. Similar to the MSAA cases, we can argue that an OWord maps to
- * 8x16 blocks.
- *
- * One problem with this reasoning is that a Y-tile in MCS has 8x32
- * OWords and maps to 64x512 128-byte blocks. This differs from i965,
- * which says that a Y-tile maps to 128x256 blocks (\see
- * intel_get_non_msrt_mcs_alignment). It does not really change
- * anything except for the size of the allocated MCS. Let's see if we
- * hit out-of-bound access.
- */
- switch (layout->tiling) {
- case GEN6_TILING_X:
- downscale_x = 64 / info->block_size;
- downscale_y = 2;
- break;
- case GEN6_TILING_Y:
- downscale_x = 32 / info->block_size;
- downscale_y = 4;
- break;
- default:
- assert(!"unsupported tiling mode");
- return false;
- break;
- }
-
- downscale_x *= 8;
- downscale_y *= 16;
-
- /*
- * From the Haswell PRM, volume 7, page 652:
- *
- * "Clear rectangle must be aligned to two times the number of
- * pixels in the table shown below due to 16X16 hashing across the
- * slice."
- *
- * The scaled-down clear rectangle must be aligned to 4x4 instead of
- * 2x2, and we need to pad.
- */
- mcs_width = align(info->width, downscale_x * 4) / downscale_x;
- mcs_height = align(info->height, downscale_y * 4) / downscale_y;
- mcs_cpp = 16; /* an OWord */
- }
-
- img->aux.enables = (1 << info->level_count) - 1;
- /* align to Y-tile */
- img->aux.bo_stride = align(mcs_width * mcs_cpp, 128);
- img->aux.bo_height = align(mcs_height, 32);
-
- return true;
-}
-
-bool
-ilo_image_init(struct ilo_image *img,
- const struct ilo_dev *dev,
- const struct ilo_image_info *info)
-{
- struct ilo_image_layout layout;
-
- assert(ilo_is_zeroed(img, sizeof(*img)));
-
- memset(&layout, 0, sizeof(layout));
- layout.lods = img->lods;
-
- if (!image_get_gen6_layout(dev, info, &layout))
- return false;
-
- img->type = info->type;
-
- img->format = info->format;
- img->block_width = info->block_width;
- img->block_height = info->block_height;
- img->block_size = info->block_size;
-
- img->width0 = info->width;
- img->height0 = info->height;
- img->depth0 = info->depth;
- img->array_size = info->array_size;
- img->level_count = info->level_count;
- img->sample_count = info->sample_count;
-
- img->walk = layout.walk;
- img->interleaved_samples = layout.interleaved_samples;
-
- img->tiling = layout.tiling;
-
- img->aux.type = layout.aux;
-
- img->align_i = layout.align_i;
- img->align_j = layout.align_j;
-
- img->walk_layer_height = layout.walk_layer_height;
-
- if (!image_set_gen6_bo_size(img, dev, info, &layout))
- return false;
-
- img->scanout = info->bind_scanout;
-
- switch (layout.aux) {
- case ILO_IMAGE_AUX_HIZ:
- image_set_gen6_hiz(img, dev, info, &layout);
- break;
- case ILO_IMAGE_AUX_MCS:
- image_set_gen7_mcs(img, dev, info, &layout);
- break;
- default:
- break;
- }
-
- return true;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_IMAGE_H
-#define ILO_IMAGE_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-
-/*
- * From the Ivy Bridge PRM, volume 4 part 1, page 75:
- *
- * "(MIP Count / LOD) representing [1,15] MIP levels"
- */
-#define ILO_IMAGE_MAX_LEVEL_COUNT 15
-
-enum ilo_image_aux_type {
- ILO_IMAGE_AUX_NONE,
- ILO_IMAGE_AUX_HIZ,
- ILO_IMAGE_AUX_MCS,
-};
-
-enum ilo_image_walk_type {
- /*
- * LODs of each array layer are first packed together in MIPLAYOUT_BELOW.
- * Array layers are then stacked together vertically.
- *
- * This can be used for mipmapped 2D textures.
- */
- ILO_IMAGE_WALK_LAYER,
-
- /*
- * Array layers of each LOD are first stacked together vertically and
- * tightly. LODs are then packed together in MIPLAYOUT_BELOW with each LOD
- * starting at page boundaries.
- *
- * This is usually used for non-mipmapped 2D textures, as multiple LODs are
- * not supported natively.
- */
- ILO_IMAGE_WALK_LOD,
-
- /*
- * 3D slices of each LOD are first packed together horizontally and tightly
- * with wrapping. LODs are then stacked together vertically and tightly.
- *
- * This is used for 3D textures.
- */
- ILO_IMAGE_WALK_3D,
-};
-
-struct ilo_image_info {
- enum gen_surface_type type;
-
- enum gen_surface_format format;
- bool interleaved_stencil;
- bool is_integer;
- /* width, height and size of pixel blocks */
- bool compressed;
- unsigned block_width;
- unsigned block_height;
- unsigned block_size;
-
- /* image size */
- uint16_t width;
- uint16_t height;
- uint16_t depth;
- uint16_t array_size;
- uint8_t level_count;
- uint8_t sample_count;
-
- /* disable optional aux */
- bool aux_disable;
-
- /* tilings to consider, if any bit is set */
- uint8_t valid_tilings;
-
- /*
- * prefer GEN6_TILING_NONE when the (estimated) image size exceeds the
- * threshold; ignored when zero
- */
- uint32_t prefer_linear_threshold;
-
- /* force a stride when non-zero */
- uint32_t force_bo_stride;
-
- bool bind_surface_sampler;
- bool bind_surface_dp_render;
- bool bind_surface_dp_typed;
- bool bind_zs;
- bool bind_scanout;
- bool bind_cursor;
-};
-
-/*
- * When the walk type is ILO_IMAGE_WALK_LAYER, there is only a slice in each
- * LOD and this is used to describe LODs in the first array layer. Otherwise,
- * there can be multiple slices in each LOD and this is used to describe the
- * first slice in each LOD.
- */
-struct ilo_image_lod {
- /* physical position in pixels */
- unsigned x;
- unsigned y;
-
- /* physical size of a slice in pixels */
- unsigned slice_width;
- unsigned slice_height;
-};
-
-/**
- * Texture layout.
- */
-struct ilo_image {
- enum gen_surface_type type;
-
- enum gen_surface_format format;
- bool interleaved_stencil;
-
- /* size, format, etc for programming hardware states */
- unsigned width0;
- unsigned height0;
- unsigned depth0;
- unsigned array_size;
- unsigned level_count;
- unsigned sample_count;
-
- /*
- * width, height, and size of pixel blocks for conversion between pixel
- * positions and memory offsets
- */
- unsigned block_width;
- unsigned block_height;
- unsigned block_size;
-
- enum ilo_image_walk_type walk;
- bool interleaved_samples;
-
- enum gen_surface_tiling tiling;
-
- /* physical LOD slice alignments */
- unsigned align_i;
- unsigned align_j;
-
- struct ilo_image_lod lods[ILO_IMAGE_MAX_LEVEL_COUNT];
-
- /* physical layer height for ILO_IMAGE_WALK_LAYER */
- unsigned walk_layer_height;
-
- /* distance in bytes between two pixel block rows */
- unsigned bo_stride;
- /* number of pixel block rows */
- unsigned bo_height;
-
- bool scanout;
-
- struct {
- enum ilo_image_aux_type type;
-
- /* bitmask of levels that can use aux */
- unsigned enables;
-
- /* LOD offsets for ILO_IMAGE_WALK_LOD */
- unsigned walk_lod_offsets[ILO_IMAGE_MAX_LEVEL_COUNT];
-
- unsigned walk_layer_height;
- unsigned bo_stride;
- unsigned bo_height;
- } aux;
-};
-
-bool
-ilo_image_init(struct ilo_image *img,
- const struct ilo_dev *dev,
- const struct ilo_image_info *info);
-
-static inline bool
-ilo_image_can_enable_aux(const struct ilo_image *img, unsigned level)
-{
- return (img->aux.enables & (1 << level));
-}
-
-/**
- * Convert from pixel position to 2D memory offset.
- */
-static inline void
-ilo_image_pos_to_mem(const struct ilo_image *img,
- unsigned pos_x, unsigned pos_y,
- unsigned *mem_x, unsigned *mem_y)
-{
- assert(pos_x % img->block_width == 0);
- assert(pos_y % img->block_height == 0);
-
- *mem_x = pos_x / img->block_width * img->block_size;
- *mem_y = pos_y / img->block_height;
-}
-
-/**
- * Convert from 2D memory offset to linear offset.
- */
-static inline unsigned
-ilo_image_mem_to_linear(const struct ilo_image *img,
- unsigned mem_x, unsigned mem_y)
-{
- return mem_y * img->bo_stride + mem_x;
-}
-
-/**
- * Convert from 2D memory offset to raw offset.
- */
-static inline unsigned
-ilo_image_mem_to_raw(const struct ilo_image *img,
- unsigned mem_x, unsigned mem_y)
-{
- unsigned tile_w, tile_h;
-
- switch (img->tiling) {
- case GEN6_TILING_NONE:
- tile_w = 1;
- tile_h = 1;
- break;
- case GEN6_TILING_X:
- tile_w = 512;
- tile_h = 8;
- break;
- case GEN6_TILING_Y:
- tile_w = 128;
- tile_h = 32;
- break;
- case GEN8_TILING_W:
- tile_w = 64;
- tile_h = 64;
- break;
- default:
- assert(!"unknown tiling");
- tile_w = 1;
- tile_h = 1;
- break;
- }
-
- assert(mem_x % tile_w == 0);
- assert(mem_y % tile_h == 0);
-
- return mem_y * img->bo_stride + mem_x * tile_h;
-}
-
-/**
- * Return the stride, in bytes, between slices within a level.
- */
-static inline unsigned
-ilo_image_get_slice_stride(const struct ilo_image *img, unsigned level)
-{
- unsigned h;
-
- switch (img->walk) {
- case ILO_IMAGE_WALK_LAYER:
- h = img->walk_layer_height;
- break;
- case ILO_IMAGE_WALK_LOD:
- h = img->lods[level].slice_height;
- break;
- case ILO_IMAGE_WALK_3D:
- if (level == 0) {
- h = img->lods[0].slice_height;
- break;
- }
- /* fall through */
- default:
- assert(!"no single stride to walk across slices");
- h = 0;
- break;
- }
-
- assert(h % img->block_height == 0);
-
- return (h / img->block_height) * img->bo_stride;
-}
-
-/**
- * Return the physical size, in bytes, of a slice in a level.
- */
-static inline unsigned
-ilo_image_get_slice_size(const struct ilo_image *img, unsigned level)
-{
- const unsigned w = img->lods[level].slice_width;
- const unsigned h = img->lods[level].slice_height;
-
- assert(w % img->block_width == 0);
- assert(h % img->block_height == 0);
-
- return (w / img->block_width * img->block_size) *
- (h / img->block_height);
-}
-
-/**
- * Return the pixel position of a slice.
- */
-static inline void
-ilo_image_get_slice_pos(const struct ilo_image *img,
- unsigned level, unsigned slice,
- unsigned *x, unsigned *y)
-{
- switch (img->walk) {
- case ILO_IMAGE_WALK_LAYER:
- *x = img->lods[level].x;
- *y = img->lods[level].y + img->walk_layer_height * slice;
- break;
- case ILO_IMAGE_WALK_LOD:
- *x = img->lods[level].x;
- *y = img->lods[level].y + img->lods[level].slice_height * slice;
- break;
- case ILO_IMAGE_WALK_3D:
- {
- /* slices are packed horizontally with wrapping */
- const unsigned sx = slice & ((1 << level) - 1);
- const unsigned sy = slice >> level;
-
- assert(slice < u_minify(img->depth0, level));
-
- *x = img->lods[level].x + img->lods[level].slice_width * sx;
- *y = img->lods[level].y + img->lods[level].slice_height * sy;
- }
- break;
- default:
- assert(!"unknown img walk type");
- *x = 0;
- *y = 0;
- break;
- }
-
- /* should not exceed the bo size */
- assert(*y + img->lods[level].slice_height <=
- img->bo_height * img->block_height);
-}
-
-#endif /* ILO_IMAGE_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-#include "ilo_state_cc.h"
-
-static bool
-cc_validate_gen6_stencil(const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info)
-{
- const struct ilo_state_cc_stencil_info *stencil = &info->stencil;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 359:
- *
- * "If the Depth Buffer is either undefined or does not have a surface
- * format of D32_FLOAT_S8X24_UINT or D24_UNORM_S8_UINT and separate
- * stencil buffer is disabled, Stencil Test Enable must be DISABLED"
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 370:
- *
- * "This field (Stencil Test Enable) cannot be enabled if Surface
- * Format in 3DSTATE_DEPTH_BUFFER is set to D16_UNORM."
- */
- if (stencil->test_enable)
- assert(stencil->cv_has_buffer);
-
- return true;
-}
-
-static bool
-cc_validate_gen6_depth(const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info)
-{
- const struct ilo_state_cc_depth_info *depth = &info->depth;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 360:
- *
- * "Enabling the Depth Test function without defining a Depth Buffer is
- * UNDEFINED."
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 375:
- *
- * "A Depth Buffer must be defined before enabling writes to it, or
- * operation is UNDEFINED."
- */
- if (depth->test_enable || depth->write_enable)
- assert(depth->cv_has_buffer);
-
- return true;
-}
-
-static bool
-cc_set_gen6_DEPTH_STENCIL_STATE(struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info)
-{
- const struct ilo_state_cc_stencil_info *stencil = &info->stencil;
- const struct ilo_state_cc_depth_info *depth = &info->depth;
- const struct ilo_state_cc_params_info *params = &info->params;
- uint32_t dw0, dw1, dw2;
-
- ILO_DEV_ASSERT(dev, 6, 7.5);
-
- if (!cc_validate_gen6_stencil(dev, info) ||
- !cc_validate_gen6_depth(dev, info))
- return false;
-
- dw0 = 0;
- dw1 = 0;
- if (stencil->test_enable) {
- const struct ilo_state_cc_stencil_op_info *front = &stencil->front;
- const struct ilo_state_cc_stencil_params_info *front_p =
- ¶ms->stencil_front;
- const struct ilo_state_cc_stencil_op_info *back;
- const struct ilo_state_cc_stencil_params_info *back_p;
-
- dw0 |= GEN6_ZS_DW0_STENCIL_TEST_ENABLE;
-
- if (stencil->twosided_enable) {
- dw0 |= GEN6_ZS_DW0_STENCIL1_ENABLE;
-
- back = &stencil->back;
- back_p = ¶ms->stencil_back;
- } else {
- back = &stencil->front;
- back_p = ¶ms->stencil_front;
- }
-
- dw0 |= front->test_func << GEN6_ZS_DW0_STENCIL_FUNC__SHIFT |
- front->fail_op << GEN6_ZS_DW0_STENCIL_FAIL_OP__SHIFT |
- front->zfail_op << GEN6_ZS_DW0_STENCIL_ZFAIL_OP__SHIFT |
- front->zpass_op << GEN6_ZS_DW0_STENCIL_ZPASS_OP__SHIFT |
- back->test_func << GEN6_ZS_DW0_STENCIL1_FUNC__SHIFT |
- back->fail_op << GEN6_ZS_DW0_STENCIL1_FAIL_OP__SHIFT |
- back->zfail_op << GEN6_ZS_DW0_STENCIL1_ZFAIL_OP__SHIFT |
- back->zpass_op << GEN6_ZS_DW0_STENCIL1_ZPASS_OP__SHIFT;
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 363:
- *
- * "If this field (Stencil Buffer Write Enable) is enabled, Stencil
- * Test Enable must also be enabled."
- *
- * This is different from depth write enable, which is independent from
- * depth test enable.
- */
- if (front_p->write_mask || back_p->write_mask)
- dw0 |= GEN6_ZS_DW0_STENCIL_WRITE_ENABLE;
-
- dw1 |= front_p->test_mask << GEN6_ZS_DW1_STENCIL_TEST_MASK__SHIFT |
- front_p->write_mask << GEN6_ZS_DW1_STENCIL_WRITE_MASK__SHIFT |
- back_p->test_mask << GEN6_ZS_DW1_STENCIL1_TEST_MASK__SHIFT |
- back_p->write_mask << GEN6_ZS_DW1_STENCIL1_WRITE_MASK__SHIFT;
- }
-
- dw2 = 0;
- if (depth->test_enable) {
- dw2 |= GEN6_ZS_DW2_DEPTH_TEST_ENABLE |
- depth->test_func << GEN6_ZS_DW2_DEPTH_FUNC__SHIFT;
- } else {
- dw2 |= GEN6_COMPAREFUNCTION_ALWAYS << GEN6_ZS_DW2_DEPTH_FUNC__SHIFT;
- }
-
- /* independent from depth->test_enable */
- if (depth->write_enable)
- dw2 |= GEN6_ZS_DW2_DEPTH_WRITE_ENABLE;
-
- STATIC_ASSERT(ARRAY_SIZE(cc->ds) >= 3);
- cc->ds[0] = dw0;
- cc->ds[1] = dw1;
- cc->ds[2] = dw2;
-
- return true;
-}
-
-static bool
-cc_set_gen8_3DSTATE_WM_DEPTH_STENCIL(struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info)
-{
- const struct ilo_state_cc_stencil_info *stencil = &info->stencil;
- const struct ilo_state_cc_depth_info *depth = &info->depth;
- const struct ilo_state_cc_params_info *params = &info->params;
- uint32_t dw1, dw2;
-
- ILO_DEV_ASSERT(dev, 8, 8);
-
- if (!cc_validate_gen6_stencil(dev, info) ||
- !cc_validate_gen6_depth(dev, info))
- return false;
-
- dw1 = 0;
- dw2 = 0;
- if (stencil->test_enable) {
- const struct ilo_state_cc_stencil_op_info *front = &stencil->front;
- const struct ilo_state_cc_stencil_params_info *front_p =
- ¶ms->stencil_front;
- const struct ilo_state_cc_stencil_op_info *back;
- const struct ilo_state_cc_stencil_params_info *back_p;
-
- dw1 |= GEN8_ZS_DW1_STENCIL_TEST_ENABLE;
-
- if (stencil->twosided_enable) {
- dw1 |= GEN8_ZS_DW1_STENCIL1_ENABLE;
-
- back = &stencil->back;
- back_p = ¶ms->stencil_back;
- } else {
- back = &stencil->front;
- back_p = ¶ms->stencil_front;
- }
-
- dw1 |= front->fail_op << GEN8_ZS_DW1_STENCIL_FAIL_OP__SHIFT |
- front->zfail_op << GEN8_ZS_DW1_STENCIL_ZFAIL_OP__SHIFT |
- front->zpass_op << GEN8_ZS_DW1_STENCIL_ZPASS_OP__SHIFT |
- back->test_func << GEN8_ZS_DW1_STENCIL1_FUNC__SHIFT |
- back->fail_op << GEN8_ZS_DW1_STENCIL1_FAIL_OP__SHIFT |
- back->zfail_op << GEN8_ZS_DW1_STENCIL1_ZFAIL_OP__SHIFT |
- back->zpass_op << GEN8_ZS_DW1_STENCIL1_ZPASS_OP__SHIFT |
- front->test_func << GEN8_ZS_DW1_STENCIL_FUNC__SHIFT;
-
- if (front_p->write_mask || back_p->write_mask)
- dw1 |= GEN8_ZS_DW1_STENCIL_WRITE_ENABLE;
-
- dw2 |= front_p->test_mask << GEN8_ZS_DW2_STENCIL_TEST_MASK__SHIFT |
- front_p->write_mask << GEN8_ZS_DW2_STENCIL_WRITE_MASK__SHIFT |
- back_p->test_mask << GEN8_ZS_DW2_STENCIL1_TEST_MASK__SHIFT |
- back_p->write_mask << GEN8_ZS_DW2_STENCIL1_WRITE_MASK__SHIFT;
- }
-
- if (depth->test_enable) {
- dw1 |= GEN8_ZS_DW1_DEPTH_TEST_ENABLE |
- depth->test_func << GEN8_ZS_DW1_DEPTH_FUNC__SHIFT;
- } else {
- dw1 |= GEN6_COMPAREFUNCTION_ALWAYS << GEN8_ZS_DW1_DEPTH_FUNC__SHIFT;
- }
-
- if (depth->write_enable)
- dw1 |= GEN8_ZS_DW1_DEPTH_WRITE_ENABLE;
-
- STATIC_ASSERT(ARRAY_SIZE(cc->ds) >= 2);
- cc->ds[0] = dw1;
- cc->ds[1] = dw2;
-
- return true;
-}
-
-static bool
-is_dual_source_blend_factor(enum gen_blend_factor factor)
-{
- switch (factor) {
- case GEN6_BLENDFACTOR_SRC1_COLOR:
- case GEN6_BLENDFACTOR_SRC1_ALPHA:
- case GEN6_BLENDFACTOR_INV_SRC1_COLOR:
- case GEN6_BLENDFACTOR_INV_SRC1_ALPHA:
- return true;
- default:
- return false;
- }
-}
-
-static bool
-cc_get_gen6_dual_source_blending(const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info)
-{
- const struct ilo_state_cc_blend_info *blend = &info->blend;
- bool dual_source_blending;
- uint8_t i;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- dual_source_blending = (blend->rt_count &&
- (is_dual_source_blend_factor(blend->rt[0].rgb_src) ||
- is_dual_source_blend_factor(blend->rt[0].rgb_dst) ||
- is_dual_source_blend_factor(blend->rt[0].a_src) ||
- is_dual_source_blend_factor(blend->rt[0].a_dst)));
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 356:
- *
- * "Dual Source Blending: When using "Dual Source" Render Target
- * Write messages, the Source1 pixel color+alpha passed in the
- * message can be selected as a src/dst blend factor. See Color
- * Buffer Blending. In single-source mode, those blend factor
- * selections are invalid. If SRC1 is included in a src/dst blend
- * factor and a DualSource RT Write message is not utilized,
- * results are UNDEFINED. (This reflects the same restriction in DX
- * APIs, where undefined results are produced if "o1" is not
- * written by a PS - there are no default values defined). If SRC1
- * is not included in a src/dst blend factor, dual source blending
- * must be disabled."
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 356:
- *
- * "The single source message will not cause a write to the render
- * target if Dual Source Blend Enable in 3DSTATE_WM is enabled."
- *
- * "The dual source message will revert to a single source message
- * using source 0 if Dual Source Blend Enable in 3DSTATE_WM is
- * disabled."
- *
- * Dual source blending must be enabled or disabled universally.
- */
- for (i = 1; i < blend->rt_count; i++) {
- assert(dual_source_blending ==
- (is_dual_source_blend_factor(blend->rt[i].rgb_src) ||
- is_dual_source_blend_factor(blend->rt[i].rgb_dst) ||
- is_dual_source_blend_factor(blend->rt[i].a_src) ||
- is_dual_source_blend_factor(blend->rt[i].a_dst)));
- }
-
- return dual_source_blending;
-}
-
-static bool
-cc_validate_gen6_alpha(const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info)
-{
- const struct ilo_state_cc_alpha_info *alpha = &info->alpha;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 356:
- *
- * "Alpha values from the pixel shader are treated as FLOAT32 format
- * for computing the AlphaToCoverage Mask."
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 378:
- *
- * "If set (AlphaToCoverage Enable), Source0 Alpha is converted to a
- * temporary 1/2/4-bit coverage mask and the mask bit corresponding to
- * the sample# ANDed with the sample mask bit. If set, sample coverage
- * is computed based on src0 alpha value. Value of 0 disables all
- * samples and value of 1 enables all samples for that pixel. The same
- * coverage needs to apply to all the RTs in MRT case. Further, any
- * value of src0 alpha between 0 and 1 monotonically increases the
- * number of enabled pixels.
- *
- * The same coverage needs to be applied to all the RTs in MRT case."
- *
- * "If set (AlphaToOne Enable), Source0 Alpha is set to 1.0f after
- * (possibly) being used to generate the AlphaToCoverage coverage
- * mask.
- *
- * The same coverage needs to be applied to all the RTs in MRT case.
- *
- * If Dual Source Blending is enabled, this bit must be disabled."
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 382:
- *
- * "Alpha Test can only be enabled if Pixel Shader outputs a float
- * alpha value.
- *
- * Alpha Test is applied independently on each render target by
- * comparing that render target's alpha value against the alpha
- * reference value. If the alpha test fails, the corresponding pixel
- * write will be supressed only for that render target. The
- * depth/stencil update will occur if alpha test passes for any render
- * target."
- *
- * From the Sandy Bridge PRM, volume 4 part 1, page 194:
- *
- * "Multiple render targets are supported with the single source and
- * replicate data messages. Each render target is accessed with a
- * separate Render Target Write message, each with a different surface
- * indicated (different binding table index). The depth buffer is
- * written only by the message(s) to the last render target, indicated
- * by the Last Render Target Select bit set to clear the pixel
- * scoreboard bits."
- *
- * When AlphaToCoverage/AlphaToOne/AlphaTest is enabled, it is
- * required/desirable for the RT write messages to set "Source0 Alpha
- * Present to RenderTarget" in the MRT case. It is also required/desirable
- * for the alpha values to be FLOAT32.
- */
- if (alpha->alpha_to_coverage || alpha->alpha_to_one || alpha->test_enable)
- assert(alpha->cv_float_source0_alpha);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 356:
- *
- * "[DevSNB]: When NumSamples = 1, AlphaToCoverage and AlphaTo
- * Coverage Dither both must be disabled."
- */
- if (ilo_dev_gen(dev) == ILO_GEN(6) && alpha->alpha_to_coverage)
- assert(alpha->cv_sample_count_one);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 378:
- *
- * "If Dual Source Blending is enabled, this bit (AlphaToOne Enable)
- * must be disabled."
- */
- if (alpha->alpha_to_one)
- assert(!cc_get_gen6_dual_source_blending(dev, info));
-
- return true;
-}
-
-static bool
-cc_validate_gen6_blend(const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info)
-{
- const struct ilo_state_cc_blend_info *blend = &info->blend;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(blend->rt_count <= ILO_STATE_CC_BLEND_MAX_RT_COUNT);
-
- return true;
-}
-
-static enum gen_blend_factor
-get_dst_alpha_one_blend_factor(enum gen_blend_factor factor, bool is_rgb)
-{
- switch (factor) {
- case GEN6_BLENDFACTOR_DST_ALPHA:
- return GEN6_BLENDFACTOR_ONE;
- case GEN6_BLENDFACTOR_INV_DST_ALPHA:
- return GEN6_BLENDFACTOR_ZERO;
- case GEN6_BLENDFACTOR_SRC_ALPHA_SATURATE:
- return (is_rgb) ? GEN6_BLENDFACTOR_ZERO : GEN6_BLENDFACTOR_ONE;
- default:
- return factor;
- }
-}
-
-static void
-cc_get_gen6_effective_rt(const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info,
- uint8_t rt_index,
- struct ilo_state_cc_blend_rt_info *dst)
-{
- const struct ilo_state_cc_blend_rt_info *rt = &info->blend.rt[rt_index];
-
- if (rt->logicop_enable || rt->blend_enable ||
- rt->argb_write_disables != 0xf)
- assert(rt->cv_has_buffer);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 365:
- *
- * "Logic Ops are only supported on *_UNORM surfaces (excluding _SRGB
- * variants), otherwise Logic Ops must be DISABLED."
- *
- * From the Broadwell PRM, volume 7, page 671:
- *
- * "Logic Ops are supported on all blendable render targets and render
- * targets with *INT formats."
- */
- if (ilo_dev_gen(dev) < ILO_GEN(8) && rt->logicop_enable)
- assert(rt->cv_is_unorm);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 361:
- *
- * "Only certain surface formats support Color Buffer Blending. Refer
- * to the Surface Format tables in Sampling Engine. Blending must be
- * disabled on a RenderTarget if blending is not supported."
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 365:
- *
- * "Color Buffer Blending and Logic Ops must not be enabled
- * simultaneously, or behavior is UNDEFINED."
- */
- if (rt->blend_enable)
- assert(!rt->cv_is_integer && !rt->logicop_enable);
-
- *dst = *rt;
- if (rt->blend_enable) {
- /* 0x0 is reserved in enum gen_blend_factor */
- assert(rt->rgb_src && rt->rgb_dst && rt->a_src && rt->a_dst);
-
- if (rt->force_dst_alpha_one) {
- dst->rgb_src = get_dst_alpha_one_blend_factor(rt->rgb_src, true);
- dst->rgb_dst = get_dst_alpha_one_blend_factor(rt->rgb_dst, true);
- dst->a_src = get_dst_alpha_one_blend_factor(rt->a_src, false);
- dst->a_dst = get_dst_alpha_one_blend_factor(rt->a_dst, false);
- dst->force_dst_alpha_one = false;
- }
- } else {
- dst->rgb_src = GEN6_BLENDFACTOR_ONE;
- dst->rgb_dst = GEN6_BLENDFACTOR_ZERO;
- dst->rgb_func = GEN6_BLENDFUNCTION_ADD;
- dst->a_src = dst->rgb_src;
- dst->a_dst = dst->rgb_dst;
- dst->a_func = dst->rgb_func;
- }
-}
-
-static bool
-cc_set_gen6_BLEND_STATE(struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info)
-{
- const struct ilo_state_cc_alpha_info *alpha = &info->alpha;
- const struct ilo_state_cc_blend_info *blend = &info->blend;
- uint32_t dw_rt[2 * ILO_STATE_CC_BLEND_MAX_RT_COUNT], dw1_invariant;
- uint32_t dw0, dw1;
- uint8_t i;
-
- ILO_DEV_ASSERT(dev, 6, 7.5);
-
- if (!cc_validate_gen6_alpha(dev, info) ||
- !cc_validate_gen6_blend(dev, info))
- return false;
-
- /*
- * According to the Sandy Bridge PRM, volume 2 part 1, page 360, pre-blend
- * and post-blend color clamps must be enabled in most cases. For the
- * other cases, they are either desirable or ignored. We can enable them
- * unconditionally.
- */
- dw1 = GEN6_RT_DW1_COLORCLAMP_RTFORMAT |
- GEN6_RT_DW1_PRE_BLEND_CLAMP |
- GEN6_RT_DW1_POST_BLEND_CLAMP;
-
- if (alpha->alpha_to_coverage) {
- dw1 |= GEN6_RT_DW1_ALPHA_TO_COVERAGE;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 379:
- *
- * "[DevSNB]: This bit (AlphaToCoverage Dither Enable) must be
- * disabled."
- */
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- dw1 |= GEN6_RT_DW1_ALPHA_TO_COVERAGE_DITHER;
- }
-
- if (alpha->alpha_to_one)
- dw1 |= GEN6_RT_DW1_ALPHA_TO_ONE;
-
- if (alpha->test_enable) {
- dw1 |= GEN6_RT_DW1_ALPHA_TEST_ENABLE |
- alpha->test_func << GEN6_RT_DW1_ALPHA_TEST_FUNC__SHIFT;
- } else {
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 371:
- *
- * "When Alpha Test is disabled, Alpha Test Function must be
- * COMPAREFUNCTION_ALWAYS."
- */
- dw1 |= GEN6_COMPAREFUNCTION_ALWAYS <<
- GEN6_RT_DW1_ALPHA_TEST_FUNC__SHIFT;
- }
-
- if (blend->dither_enable)
- dw1 |= GEN6_RT_DW1_DITHER_ENABLE;
-
- dw1_invariant = dw1;
-
- for (i = 0; i < blend->rt_count; i++) {
- struct ilo_state_cc_blend_rt_info rt;
-
- cc_get_gen6_effective_rt(dev, info, i, &rt);
-
- /* 0x0 is reserved for blend factors and we have to set them all */
- dw0 = rt.a_func << GEN6_RT_DW0_ALPHA_FUNC__SHIFT |
- rt.a_src << GEN6_RT_DW0_SRC_ALPHA_FACTOR__SHIFT |
- rt.a_dst << GEN6_RT_DW0_DST_ALPHA_FACTOR__SHIFT |
- rt.rgb_func << GEN6_RT_DW0_COLOR_FUNC__SHIFT |
- rt.rgb_src << GEN6_RT_DW0_SRC_COLOR_FACTOR__SHIFT |
- rt.rgb_dst << GEN6_RT_DW0_DST_COLOR_FACTOR__SHIFT;
-
- if (rt.blend_enable) {
- dw0 |= GEN6_RT_DW0_BLEND_ENABLE;
-
- if (rt.a_src != rt.rgb_src ||
- rt.a_dst != rt.rgb_dst ||
- rt.a_func != rt.rgb_func)
- dw0 |= GEN6_RT_DW0_INDEPENDENT_ALPHA_ENABLE;
- }
-
- dw1 = dw1_invariant |
- rt.argb_write_disables << GEN6_RT_DW1_WRITE_DISABLES__SHIFT;
-
- if (rt.logicop_enable) {
- dw1 |= GEN6_RT_DW1_LOGICOP_ENABLE |
- rt.logicop_func << GEN6_RT_DW1_LOGICOP_FUNC__SHIFT;
- }
-
- dw_rt[2 * i + 0] = dw0;
- dw_rt[2 * i + 1] = dw1;
- }
-
-
- STATIC_ASSERT(ARRAY_SIZE(cc->blend) >= ARRAY_SIZE(dw_rt));
- memcpy(&cc->blend[0], dw_rt, sizeof(uint32_t) * 2 * blend->rt_count);
- cc->blend_state_count = info->blend.rt_count;
-
- return true;
-}
-
-static bool
-cc_set_gen8_BLEND_STATE(struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info)
-{
- const struct ilo_state_cc_alpha_info *alpha = &info->alpha;
- const struct ilo_state_cc_blend_info *blend = &info->blend;
- uint32_t dw_rt[2 * ILO_STATE_CC_BLEND_MAX_RT_COUNT], dw0, dw1;
- bool indep_alpha_enable;
- uint8_t i;
-
- ILO_DEV_ASSERT(dev, 8, 8);
-
- if (!cc_validate_gen6_alpha(dev, info) ||
- !cc_validate_gen6_blend(dev, info))
- return false;
-
- indep_alpha_enable = false;
- for (i = 0; i < blend->rt_count; i++) {
- struct ilo_state_cc_blend_rt_info rt;
-
- cc_get_gen6_effective_rt(dev, info, i, &rt);
-
- dw0 = rt.rgb_src << GEN8_RT_DW0_SRC_COLOR_FACTOR__SHIFT |
- rt.rgb_dst << GEN8_RT_DW0_DST_COLOR_FACTOR__SHIFT |
- rt.rgb_func << GEN8_RT_DW0_COLOR_FUNC__SHIFT |
- rt.a_src << GEN8_RT_DW0_SRC_ALPHA_FACTOR__SHIFT |
- rt.a_dst << GEN8_RT_DW0_DST_ALPHA_FACTOR__SHIFT |
- rt.a_func << GEN8_RT_DW0_ALPHA_FUNC__SHIFT |
- rt.argb_write_disables << GEN8_RT_DW0_WRITE_DISABLES__SHIFT;
-
- if (rt.blend_enable) {
- dw0 |= GEN8_RT_DW0_BLEND_ENABLE;
-
- if (rt.a_src != rt.rgb_src ||
- rt.a_dst != rt.rgb_dst ||
- rt.a_func != rt.rgb_func)
- indep_alpha_enable = true;
- }
-
- dw1 = GEN8_RT_DW1_COLORCLAMP_RTFORMAT |
- GEN8_RT_DW1_PRE_BLEND_CLAMP |
- GEN8_RT_DW1_POST_BLEND_CLAMP;
-
- if (rt.logicop_enable) {
- dw1 |= GEN8_RT_DW1_LOGICOP_ENABLE |
- rt.logicop_func << GEN8_RT_DW1_LOGICOP_FUNC__SHIFT;
- }
-
- dw_rt[2 * i + 0] = dw0;
- dw_rt[2 * i + 1] = dw1;
- }
-
- dw0 = 0;
-
- if (alpha->alpha_to_coverage) {
- dw0 |= GEN8_BLEND_DW0_ALPHA_TO_COVERAGE |
- GEN8_BLEND_DW0_ALPHA_TO_COVERAGE_DITHER;
- }
-
- if (indep_alpha_enable)
- dw0 |= GEN8_BLEND_DW0_INDEPENDENT_ALPHA_ENABLE;
-
- if (alpha->alpha_to_one)
- dw0 |= GEN8_BLEND_DW0_ALPHA_TO_ONE;
-
- if (alpha->test_enable) {
- dw0 |= GEN8_BLEND_DW0_ALPHA_TEST_ENABLE |
- alpha->test_func << GEN8_BLEND_DW0_ALPHA_TEST_FUNC__SHIFT;
- } else {
- dw0 |= GEN6_COMPAREFUNCTION_ALWAYS <<
- GEN8_BLEND_DW0_ALPHA_TEST_FUNC__SHIFT;
- }
-
- if (blend->dither_enable)
- dw0 |= GEN8_BLEND_DW0_DITHER_ENABLE;
-
- STATIC_ASSERT(ARRAY_SIZE(cc->blend) >= 2 + ARRAY_SIZE(dw_rt));
- cc->blend[1] = dw0;
- memcpy(&cc->blend[2], dw_rt, sizeof(uint32_t) * 2 * blend->rt_count);
- cc->blend_state_count = info->blend.rt_count;
-
- return true;
-}
-
-static bool
-cc_set_gen8_3DSTATE_PS_BLEND(struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info)
-{
- const struct ilo_state_cc_alpha_info *alpha = &info->alpha;
- const struct ilo_state_cc_blend_info *blend = &info->blend;
- uint32_t dw1;
-
- ILO_DEV_ASSERT(dev, 8, 8);
-
- dw1 = 0;
-
- if (alpha->alpha_to_coverage)
- dw1 |= GEN8_PS_BLEND_DW1_ALPHA_TO_COVERAGE;
-
- if (alpha->test_enable)
- dw1 |= GEN8_PS_BLEND_DW1_ALPHA_TEST_ENABLE;
-
- if (blend->rt_count) {
- struct ilo_state_cc_blend_rt_info rt0;
- uint8_t i;
-
- cc_get_gen6_effective_rt(dev, info, 0, &rt0);
-
- /* 0x0 is reserved for blend factors and we have to set them all */
- dw1 |= rt0.a_src << GEN8_PS_BLEND_DW1_RT0_SRC_ALPHA_FACTOR__SHIFT |
- rt0.a_dst << GEN8_PS_BLEND_DW1_RT0_DST_ALPHA_FACTOR__SHIFT |
- rt0.rgb_src << GEN8_PS_BLEND_DW1_RT0_SRC_COLOR_FACTOR__SHIFT |
- rt0.rgb_dst << GEN8_PS_BLEND_DW1_RT0_DST_COLOR_FACTOR__SHIFT;
-
- for (i = 0; i < blend->rt_count; i++) {
- if (blend->rt[i].argb_write_disables != 0xf) {
- dw1 |= GEN8_PS_BLEND_DW1_WRITABLE_RT;
- break;
- }
- }
-
- if (rt0.blend_enable) {
- dw1 |= GEN8_PS_BLEND_DW1_RT0_BLEND_ENABLE;
-
- if (rt0.a_src != rt0.rgb_src || rt0.a_dst != rt0.rgb_dst)
- dw1 |= GEN8_PS_BLEND_DW1_RT0_INDEPENDENT_ALPHA_ENABLE;
- }
- }
-
- STATIC_ASSERT(ARRAY_SIZE(cc->blend) >= 1);
- cc->blend[0] = dw1;
-
- return true;
-}
-
-static bool
-cc_params_set_gen6_COLOR_CALC_STATE(struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc_params_info *params)
-{
- uint32_t dw0;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- dw0 = params->stencil_front.test_ref << GEN6_CC_DW0_STENCIL_REF__SHIFT |
- params->stencil_back.test_ref << GEN6_CC_DW0_STENCIL1_REF__SHIFT |
- GEN6_CC_DW0_ALPHATEST_FLOAT32;
-
- STATIC_ASSERT(ARRAY_SIZE(cc->cc) >= 6);
- cc->cc[0] = dw0;
- cc->cc[1] = fui(params->alpha_ref);
- cc->cc[2] = fui(params->blend_rgba[0]);
- cc->cc[3] = fui(params->blend_rgba[1]);
- cc->cc[4] = fui(params->blend_rgba[2]);
- cc->cc[5] = fui(params->blend_rgba[3]);
-
- return true;
-}
-
-bool
-ilo_state_cc_init(struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info)
-{
- assert(ilo_is_zeroed(cc, sizeof(*cc)));
- return ilo_state_cc_set_info(cc, dev, info);
-}
-
-bool
-ilo_state_cc_set_info(struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info)
-{
- bool ret = true;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- ret &= cc_set_gen8_3DSTATE_WM_DEPTH_STENCIL(cc, dev, info);
- ret &= cc_set_gen8_BLEND_STATE(cc, dev, info);
- ret &= cc_set_gen8_3DSTATE_PS_BLEND(cc, dev, info);
- } else {
- ret &= cc_set_gen6_DEPTH_STENCIL_STATE(cc, dev, info);
- ret &= cc_set_gen6_BLEND_STATE(cc, dev, info);
- }
-
- ret &= cc_params_set_gen6_COLOR_CALC_STATE(cc, dev, &info->params);
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_cc_set_params(struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc_params_info *params)
-{
- /* modify stencil masks */
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- uint32_t dw1 = cc->ds[0];
- uint32_t dw2 = cc->ds[1];
-
- if (dw1 & GEN8_ZS_DW1_STENCIL_TEST_ENABLE) {
- const bool twosided_enable = (dw1 & GEN8_ZS_DW1_STENCIL1_ENABLE);
- const struct ilo_state_cc_stencil_params_info *front_p =
- ¶ms->stencil_front;
- const struct ilo_state_cc_stencil_params_info *back_p =
- (twosided_enable) ? ¶ms->stencil_back :
- ¶ms->stencil_front;
-
- if (front_p->write_mask || back_p->write_mask)
- dw1 |= GEN8_ZS_DW1_STENCIL_WRITE_ENABLE;
- else
- dw1 &= ~GEN8_ZS_DW1_STENCIL_WRITE_ENABLE;
-
- dw2 =
- front_p->test_mask << GEN8_ZS_DW2_STENCIL_TEST_MASK__SHIFT |
- front_p->write_mask << GEN8_ZS_DW2_STENCIL_WRITE_MASK__SHIFT |
- back_p->test_mask << GEN8_ZS_DW2_STENCIL1_TEST_MASK__SHIFT |
- back_p->write_mask << GEN8_ZS_DW2_STENCIL1_WRITE_MASK__SHIFT;
- }
-
- cc->ds[0] = dw1;
- cc->ds[1] = dw2;
- } else {
- uint32_t dw0 = cc->ds[0];
- uint32_t dw1 = cc->ds[1];
-
- if (dw0 & GEN6_ZS_DW0_STENCIL_TEST_ENABLE) {
- const bool twosided_enable = (dw0 & GEN6_ZS_DW0_STENCIL1_ENABLE);
- const struct ilo_state_cc_stencil_params_info *front_p =
- ¶ms->stencil_front;
- const struct ilo_state_cc_stencil_params_info *back_p =
- (twosided_enable) ? ¶ms->stencil_back :
- ¶ms->stencil_front;
-
- if (front_p->write_mask || back_p->write_mask)
- dw0 |= GEN6_ZS_DW0_STENCIL_WRITE_ENABLE;
- else
- dw0 &= ~GEN6_ZS_DW0_STENCIL_WRITE_ENABLE;
-
- dw1 =
- front_p->test_mask << GEN6_ZS_DW1_STENCIL_TEST_MASK__SHIFT |
- front_p->write_mask << GEN6_ZS_DW1_STENCIL_WRITE_MASK__SHIFT |
- back_p->test_mask << GEN6_ZS_DW1_STENCIL1_TEST_MASK__SHIFT |
- back_p->write_mask << GEN6_ZS_DW1_STENCIL1_WRITE_MASK__SHIFT;
- }
-
- cc->ds[0] = dw0;
- cc->ds[1] = dw1;
- }
-
- /* modify COLOR_CALC_STATE */
- cc_params_set_gen6_COLOR_CALC_STATE(cc, dev, params);
-
- return true;
-}
-
-void
-ilo_state_cc_full_delta(const struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- struct ilo_state_cc_delta *delta)
-{
- delta->dirty = ILO_STATE_CC_BLEND_STATE |
- ILO_STATE_CC_COLOR_CALC_STATE;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- delta->dirty |= ILO_STATE_CC_3DSTATE_WM_DEPTH_STENCIL |
- ILO_STATE_CC_3DSTATE_PS_BLEND;
- } else {
- delta->dirty |= ILO_STATE_CC_DEPTH_STENCIL_STATE;
- }
-}
-
-void
-ilo_state_cc_get_delta(const struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc *old,
- struct ilo_state_cc_delta *delta)
-{
- delta->dirty = 0;
-
- if (memcmp(cc->ds, old->ds, sizeof(cc->ds))) {
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- delta->dirty |= ILO_STATE_CC_3DSTATE_WM_DEPTH_STENCIL;
- else
- delta->dirty |= ILO_STATE_CC_DEPTH_STENCIL_STATE;
- }
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- if (cc->blend[0] != old->blend[0])
- delta->dirty |= ILO_STATE_CC_3DSTATE_PS_BLEND;
-
- if (memcmp(&cc->blend[1], &old->blend[1],
- sizeof(uint32_t) * (1 + 2 * cc->blend_state_count)))
- delta->dirty |= ILO_STATE_CC_BLEND_STATE;
- } else if (memcmp(cc->blend, old->blend,
- sizeof(uint32_t) * 2 * cc->blend_state_count)) {
- delta->dirty |= ILO_STATE_CC_BLEND_STATE;
- }
-
- if (memcmp(cc->cc, old->cc, sizeof(cc->cc)))
- delta->dirty |= ILO_STATE_CC_COLOR_CALC_STATE;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_STATE_CC_H
-#define ILO_STATE_CC_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-
-/*
- * From the Sandy Bridge PRM, volume 2 part 1, page 38:
- *
- * "Render Target Index. Specifies the render target index that will be
- * used to select blend state from BLEND_STATE.
- * Format = U3"
- */
-#define ILO_STATE_CC_BLEND_MAX_RT_COUNT 8
-
-enum ilo_state_cc_dirty_bits {
- ILO_STATE_CC_3DSTATE_WM_DEPTH_STENCIL = (1 << 0),
- ILO_STATE_CC_3DSTATE_PS_BLEND = (1 << 1),
- ILO_STATE_CC_DEPTH_STENCIL_STATE = (1 << 2),
- ILO_STATE_CC_BLEND_STATE = (1 << 3),
- ILO_STATE_CC_COLOR_CALC_STATE = (1 << 4),
-};
-
-/**
- * AlphaCoverage and AlphaTest.
- */
-struct ilo_state_cc_alpha_info {
- bool cv_sample_count_one;
- bool cv_float_source0_alpha;
-
- bool alpha_to_coverage;
- bool alpha_to_one;
-
- bool test_enable;
- enum gen_compare_function test_func;
-};
-
-struct ilo_state_cc_stencil_op_info {
- enum gen_compare_function test_func;
- enum gen_stencil_op fail_op;
- enum gen_stencil_op zfail_op;
- enum gen_stencil_op zpass_op;
-};
-
-/**
- * StencilTest.
- */
-struct ilo_state_cc_stencil_info {
- bool cv_has_buffer;
-
- bool test_enable;
- bool twosided_enable;
-
- struct ilo_state_cc_stencil_op_info front;
- struct ilo_state_cc_stencil_op_info back;
-};
-
-/**
- * DepthTest.
- */
-struct ilo_state_cc_depth_info {
- bool cv_has_buffer;
-
- bool test_enable;
- /* independent from test_enable */
- bool write_enable;
-
- enum gen_compare_function test_func;
-};
-
-struct ilo_state_cc_blend_rt_info {
- bool cv_has_buffer;
- bool cv_is_unorm;
- bool cv_is_integer;
-
- uint8_t argb_write_disables;
-
- bool logicop_enable;
- enum gen_logic_op logicop_func;
-
- bool blend_enable;
- bool force_dst_alpha_one;
- enum gen_blend_factor rgb_src;
- enum gen_blend_factor rgb_dst;
- enum gen_blend_function rgb_func;
- enum gen_blend_factor a_src;
- enum gen_blend_factor a_dst;
- enum gen_blend_function a_func;
-};
-
-/**
- * ColorBufferBlending, Dithering, and LogicOps.
- */
-struct ilo_state_cc_blend_info {
- const struct ilo_state_cc_blend_rt_info *rt;
- uint8_t rt_count;
-
- bool dither_enable;
-};
-
-struct ilo_state_cc_stencil_params_info {
- uint8_t test_ref;
- uint8_t test_mask;
- uint8_t write_mask;
-};
-
-/**
- * CC parameters.
- */
-struct ilo_state_cc_params_info {
- float alpha_ref;
-
- struct ilo_state_cc_stencil_params_info stencil_front;
- struct ilo_state_cc_stencil_params_info stencil_back;
-
- float blend_rgba[4];
-};
-
-/**
- * Pixel processing.
- */
-struct ilo_state_cc_info {
- struct ilo_state_cc_alpha_info alpha;
- struct ilo_state_cc_stencil_info stencil;
- struct ilo_state_cc_depth_info depth;
- struct ilo_state_cc_blend_info blend;
-
- struct ilo_state_cc_params_info params;
-};
-
-struct ilo_state_cc {
- uint32_t ds[3];
-
- uint8_t blend_state_count;
- uint32_t blend[1 + 1 + 2 * ILO_STATE_CC_BLEND_MAX_RT_COUNT];
-
- uint32_t cc[6];
-};
-
-struct ilo_state_cc_delta {
- uint32_t dirty;
-};
-
-bool
-ilo_state_cc_init(struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info);
-
-bool
-ilo_state_cc_set_info(struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info);
-
-bool
-ilo_state_cc_set_params(struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc_params_info *params);
-
-void
-ilo_state_cc_full_delta(const struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- struct ilo_state_cc_delta *delta);
-
-void
-ilo_state_cc_get_delta(const struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc *old,
- struct ilo_state_cc_delta *delta);
-
-#endif /* ILO_STATE_CC_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-#include "ilo_state_compute.h"
-
-struct compute_urb_configuration {
- int idrt_entry_count;
- int curbe_entry_count;
-
- int urb_entry_count;
- /* in 256-bit register increments */
- int urb_entry_size;
-};
-
-static int
-get_gen6_rob_entry_count(const struct ilo_dev *dev)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 2, page 60:
- *
- * "ROB has 64KB of storage; 2048 entries."
- *
- * From the valid ranges of "CURBE Allocation Size", we can also conclude
- * that interface entries and CURBE data must be in ROB. And that ROB
- * should be 16KB, or 512 entries, on Gen7 GT1.
- */
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5))
- return 2048;
- else if (ilo_dev_gen(dev) >= ILO_GEN(7))
- return (dev->gt == 2) ? 2048 : 512;
- else
- return (dev->gt == 2) ? 2048 : 1024;
-}
-
-static int
-get_gen6_idrt_entry_count(const struct ilo_dev *dev)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 2, page 21:
- *
- * "The first 32 URB entries are reserved for the interface
- * descriptor..."
- *
- * From the Haswell PRM, volume 7, page 836:
- *
- * "The first 64 URB entries are reserved for the interface
- * description..."
- */
- return (ilo_dev_gen(dev) >= ILO_GEN(7.5)) ? 64 : 32;
-}
-
-static int
-get_gen6_curbe_entry_count(const struct ilo_dev *dev, uint32_t curbe_size)
-{
- /*
- * From the Ivy Bridge PRM, volume 2 part 2, page 21:
- *
- * "(CURBE Allocation Size) Specifies the total length allocated for
- * CURBE, in 256-bit register increments.
- */
- const int entry_count = (curbe_size + 31) / 32;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(get_gen6_idrt_entry_count(dev) + entry_count <=
- get_gen6_rob_entry_count(dev));
-
- return entry_count;
-}
-
-static bool
-compute_get_gen6_urb_configuration(const struct ilo_dev *dev,
- const struct ilo_state_compute_info *info,
- struct compute_urb_configuration *urb)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- urb->idrt_entry_count = get_gen6_idrt_entry_count(dev);
- urb->curbe_entry_count =
- get_gen6_curbe_entry_count(dev, info->curbe_alloc_size);
-
- /*
- * From the Broadwell PRM, volume 2b, page 451:
- *
- * "Please note that 0 is not allowed for this field (Number of URB
- * Entries)."
- */
- urb->urb_entry_count = (ilo_dev_gen(dev) >= ILO_GEN(8)) ? 1 : 0;
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 2, page 52:
- *
- * "(URB Entry Allocation Size) Specifies the length of each URB entry
- * used by the unit, in 256-bit register increments - 1."
- */
- urb->urb_entry_size = 1;
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 2, page 22:
- *
- * MEDIA_VFE_STATE specifies the amount of CURBE space, the URB handle
- * size and the number of URB handles. The driver must ensure that
- * ((URB_handle_size * URB_num_handle) - CURBE - 32) <=
- * URB_allocation_in_L3."
- */
- assert(urb->idrt_entry_count + urb->curbe_entry_count +
- urb->urb_entry_count * urb->urb_entry_size <=
- info->cv_urb_alloc_size / 32);
-
- return true;
-}
-
-static int
-compute_interface_get_gen6_read_end(const struct ilo_dev *dev,
- const struct ilo_state_compute_interface_info *interface)
-{
- const int per_thread_read = (interface->curbe_read_length + 31) / 32;
- const int cross_thread_read =
- (interface->cross_thread_curbe_read_length + 31) / 32;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(interface->curbe_read_offset % 32 == 0);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 2, page 60:
- *
- * "(Constant URB Entry Read Length) [0,63]"
- */
- assert(per_thread_read <= 63);
-
- /*
- * From the Haswell PRM, volume 2d, page 199:
- *
- * "(Cross-Thread Constant Data Read Length) [0,127]"
- */
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5))
- assert(cross_thread_read <= 127);
- else
- assert(!cross_thread_read);
-
- if (per_thread_read || cross_thread_read) {
- return interface->curbe_read_offset / 32 + cross_thread_read +
- per_thread_read * interface->thread_group_size;
- } else {
- return 0;
- }
-}
-
-static bool
-compute_validate_gen6(const struct ilo_dev *dev,
- const struct ilo_state_compute_info *info,
- const struct compute_urb_configuration *urb)
-{
- int min_curbe_entry_count;
- uint8_t i;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(info->interface_count <= urb->idrt_entry_count);
-
- min_curbe_entry_count = 0;
- for (i = 0; i < info->interface_count; i++) {
- const int read_end =
- compute_interface_get_gen6_read_end(dev, &info->interfaces[i]);
-
- if (min_curbe_entry_count < read_end)
- min_curbe_entry_count = read_end;
- }
-
- assert(min_curbe_entry_count <= urb->curbe_entry_count);
-
- /*
- * From the Broadwell PRM, volume 2b, page 452:
- *
- * "CURBE Allocation Size should be 0 for GPGPU workloads that uses
- * indirect instead of CURBE."
- */
- if (!min_curbe_entry_count)
- assert(!urb->curbe_entry_count);
-
- return true;
-}
-
-static uint32_t
-compute_get_gen6_per_thread_scratch_size(const struct ilo_dev *dev,
- const struct ilo_state_compute_info *info,
- uint8_t *per_thread_space)
-{
- ILO_DEV_ASSERT(dev, 6, 7);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 2, page 30:
- *
- * "(Per Thread Scratch Space)
- * Range = [0,11] indicating [1k bytes, 12k bytes] [DevSNB]"
- */
- assert(info->per_thread_scratch_size <= 12 * 1024);
-
- if (!info->per_thread_scratch_size) {
- *per_thread_space = 0;
- return 0;
- }
-
- *per_thread_space = (info->per_thread_scratch_size > 1024) ?
- (info->per_thread_scratch_size - 1) / 1024 : 0;
-
- return 1024 * (1 + *per_thread_space);
-}
-
-static uint32_t
-compute_get_gen75_per_thread_scratch_size(const struct ilo_dev *dev,
- const struct ilo_state_compute_info *info,
- uint8_t *per_thread_space)
-{
- ILO_DEV_ASSERT(dev, 7.5, 8);
-
- /*
- * From the Haswell PRM, volume 2b, page 407:
- *
- * "(Per Thread Scratch Space)
- * [0,10] Indicating [2k bytes, 2 Mbytes]"
- *
- * "Note: The scratch space should be declared as 2x the desired
- * scratch space. The stack will start at the half-way point instead
- * of the end. The upper half of scratch space will not be accessed
- * and so does not have to be allocated in memory."
- *
- * From the Broadwell PRM, volume 2a, page 450:
- *
- * "(Per Thread Scratch Space)
- * [0,11] indicating [1k bytes, 2 Mbytes]"
- */
- assert(info->per_thread_scratch_size <=
- ((ilo_dev_gen(dev) >= ILO_GEN(8)) ? 2 : 1) * 1024 * 1024);
-
- if (!info->per_thread_scratch_size) {
- *per_thread_space = 0;
- return 0;
- }
-
- /* next power of two, starting from 1KB */
- *per_thread_space = (info->per_thread_scratch_size > 1024) ?
- (util_last_bit(info->per_thread_scratch_size - 1) - 10) : 0;
-
- return 1 << (10 + *per_thread_space);
-}
-
-static bool
-compute_set_gen6_MEDIA_VFE_STATE(struct ilo_state_compute *compute,
- const struct ilo_dev *dev,
- const struct ilo_state_compute_info *info)
-{
- struct compute_urb_configuration urb;
- uint32_t per_thread_size;
- uint8_t per_thread_space;
-
- uint32_t dw1, dw2, dw4;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (!compute_get_gen6_urb_configuration(dev, info, &urb) ||
- !compute_validate_gen6(dev, info, &urb))
- return false;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5)) {
- per_thread_size = compute_get_gen75_per_thread_scratch_size(dev,
- info, &per_thread_space);
- } else {
- per_thread_size = compute_get_gen6_per_thread_scratch_size(dev,
- info, &per_thread_space);
- }
-
- dw1 = per_thread_space << GEN6_VFE_DW1_SCRATCH_SPACE_PER_THREAD__SHIFT;
-
- dw2 = (dev->thread_count - 1) << GEN6_VFE_DW2_MAX_THREADS__SHIFT |
- urb.urb_entry_count << GEN6_VFE_DW2_URB_ENTRY_COUNT__SHIFT |
- GEN6_VFE_DW2_RESET_GATEWAY_TIMER |
- GEN6_VFE_DW2_BYPASS_GATEWAY_CONTROL;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7) && ilo_dev_gen(dev) <= ILO_GEN(7.5))
- dw2 |= GEN7_VFE_DW2_GPGPU_MODE;
-
- assert(urb.urb_entry_size);
-
- dw4 = (urb.urb_entry_size - 1) << GEN6_VFE_DW4_URB_ENTRY_SIZE__SHIFT |
- urb.curbe_entry_count << GEN6_VFE_DW4_CURBE_SIZE__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(compute->vfe) >= 3);
- compute->vfe[0] = dw1;
- compute->vfe[1] = dw2;
- compute->vfe[2] = dw4;
-
- compute->scratch_size = per_thread_size * dev->thread_count;
-
- return true;
-}
-
-static uint8_t
-compute_interface_get_gen6_sampler_count(const struct ilo_dev *dev,
- const struct ilo_state_compute_interface_info *interface)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
- return (interface->sampler_count <= 12) ?
- (interface->sampler_count + 3) / 4 : 4;
-}
-
-static uint8_t
-compute_interface_get_gen6_surface_count(const struct ilo_dev *dev,
- const struct ilo_state_compute_interface_info *interface)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
- return (interface->surface_count <= 31) ? interface->surface_count : 31;
-}
-
-static uint8_t
-compute_interface_get_gen7_slm_size(const struct ilo_dev *dev,
- const struct ilo_state_compute_interface_info *interface)
-{
- ILO_DEV_ASSERT(dev, 7, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 2, page 61:
- *
- * "The amount is specified in 4k blocks, but only powers of 2 are
- * allowed: 0, 4k, 8k, 16k, 32k and 64k per half-slice."
- */
- assert(interface->slm_size <= 64 * 1024);
-
- return util_next_power_of_two((interface->slm_size + 4095) / 4096);
-}
-
-static bool
-compute_set_gen6_INTERFACE_DESCRIPTOR_DATA(struct ilo_state_compute *compute,
- const struct ilo_dev *dev,
- const struct ilo_state_compute_info *info)
-{
- uint8_t i;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- for (i = 0; i < info->interface_count; i++) {
- const struct ilo_state_compute_interface_info *interface =
- &info->interfaces[i];
- uint16_t read_offset, per_thread_read_len, cross_thread_read_len;
- uint8_t sampler_count, surface_count;
- uint32_t dw0, dw2, dw3, dw4, dw5, dw6;
-
- assert(interface->kernel_offset % 64 == 0);
- assert(interface->thread_group_size);
-
- read_offset = interface->curbe_read_offset / 32;
- per_thread_read_len = (interface->curbe_read_length + 31) / 32;
- cross_thread_read_len =
- (interface->cross_thread_curbe_read_length + 31) / 32;
-
- sampler_count =
- compute_interface_get_gen6_sampler_count(dev, interface);
- surface_count =
- compute_interface_get_gen6_surface_count(dev, interface);
-
- dw0 = interface->kernel_offset;
- dw2 = sampler_count << GEN6_IDRT_DW2_SAMPLER_COUNT__SHIFT;
- dw3 = surface_count << GEN6_IDRT_DW3_BINDING_TABLE_SIZE__SHIFT;
- dw4 = per_thread_read_len << GEN6_IDRT_DW4_CURBE_READ_LEN__SHIFT |
- read_offset << GEN6_IDRT_DW4_CURBE_READ_OFFSET__SHIFT;
-
- dw5 = 0;
- dw6 = 0;
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- const uint8_t slm_size =
- compute_interface_get_gen7_slm_size(dev, interface);
-
- dw5 |= GEN7_IDRT_DW5_ROUNDING_MODE_RTNE;
-
- if (slm_size) {
- dw5 |= GEN7_IDRT_DW5_BARRIER_ENABLE |
- slm_size << GEN7_IDRT_DW5_SLM_SIZE__SHIFT;
- }
-
- /*
- * From the Haswell PRM, volume 2d, page 199:
- *
- * "(Number of Threads in GPGPU Thread Group) Specifies the
- * number of threads that are in this thread group. Used to
- * program the barrier for the number of messages to expect. The
- * minimum value is 0 (which will disable the barrier), while
- * the maximum value is the number of threads in a subslice for
- * local barriers."
- *
- * From the Broadwell PRM, volume 2d, page 183:
- *
- * "(Number of Threads in GPGPU Thread Group) Specifies the
- * number of threads that are in this thread group. The minimum
- * value is 1, while the maximum value is the number of threads
- * in a subslice for local barriers. See vol1b Configurations
- * for the number of threads per subslice for different
- * products. The maximum value for global barriers is limited
- * by the number of threads in the system, or by 511, whichever
- * is lower. This field should not be set to 0 even if the
- * barrier is disabled, since an accurate value is needed for
- * proper pre-emption."
- */
- if (slm_size || ilo_dev_gen(dev) >= ILO_GEN(8)) {
- dw5 |= interface->thread_group_size <<
- GEN7_IDRT_DW5_THREAD_GROUP_SIZE__SHIFT;
- }
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5)) {
- dw6 |= cross_thread_read_len <<
- GEN75_IDRT_DW6_CROSS_THREAD_CURBE_READ_LEN__SHIFT;
- }
- }
-
- STATIC_ASSERT(ARRAY_SIZE(compute->idrt[i]) >= 6);
- compute->idrt[i][0] = dw0;
- compute->idrt[i][1] = dw2;
- compute->idrt[i][2] = dw3;
- compute->idrt[i][3] = dw4;
- compute->idrt[i][4] = dw5;
- compute->idrt[i][5] = dw6;
- }
-
- return true;
-}
-
-bool
-ilo_state_compute_init(struct ilo_state_compute *compute,
- const struct ilo_dev *dev,
- const struct ilo_state_compute_info *info)
-{
- bool ret = true;
-
- assert(ilo_is_zeroed(compute, sizeof(*compute)));
- assert(ilo_is_zeroed(info->data, info->data_size));
-
- assert(ilo_state_compute_data_size(dev, info->interface_count) <=
- info->data_size);
- compute->idrt = (uint32_t (*)[6]) info->data;
-
- ret &= compute_set_gen6_MEDIA_VFE_STATE(compute, dev, info);
- ret &= compute_set_gen6_INTERFACE_DESCRIPTOR_DATA(compute, dev, info);
-
- assert(ret);
-
- return ret;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_STATE_COMPUTE_H
-#define ILO_STATE_COMPUTE_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-
-/*
- * From the Haswell PRM, volume 7, page 836:
- *
- * "The first 64 URB entries are reserved for the interface
- * description..."
- */
-#define ILO_STATE_COMPUTE_MAX_INTERFACE_COUNT 64
-
-struct ilo_state_compute_interface_info {
- /* usually 0 unless there are multiple interfaces */
- uint32_t kernel_offset;
-
- uint8_t sampler_count;
- uint8_t surface_count;
-
- uint16_t thread_group_size;
- uint32_t slm_size;
-
- uint16_t curbe_read_offset;
- uint16_t curbe_read_length;
- uint16_t cross_thread_curbe_read_length;
-};
-
-struct ilo_state_compute_info {
- void *data;
- size_t data_size;
-
- const struct ilo_state_compute_interface_info *interfaces;
- uint8_t interface_count;
-
- uint32_t per_thread_scratch_size;
-
- uint32_t cv_urb_alloc_size;
- uint32_t curbe_alloc_size;
-};
-
-struct ilo_state_compute {
- uint32_t vfe[3];
-
- uint32_t (*idrt)[6];
- uint8_t idrt_count;
-
- uint32_t scratch_size;
-};
-
-static inline size_t
-ilo_state_compute_data_size(const struct ilo_dev *dev,
- uint8_t interface_count)
-{
- const struct ilo_state_compute *compute = NULL;
- return sizeof(compute->idrt[0]) * interface_count;
-}
-
-bool
-ilo_state_compute_init(struct ilo_state_compute *compute,
- const struct ilo_dev *dev,
- const struct ilo_state_compute_info *info);
-
-static inline uint32_t
-ilo_state_compute_get_scratch_size(const struct ilo_state_compute *compute)
-{
- return compute->scratch_size;
-}
-
-#endif /* ILO_STATE_COMPUTE_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-#include "ilo_state_raster.h"
-
-static bool
-raster_validate_gen6_clip(const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info)
-{
- const struct ilo_state_raster_clip_info *clip = &info->clip;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(clip->viewport_count);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 188:
- *
- * ""Clip Distance Cull Test Enable Bitmask" and "Clip Distance Clip
- * Test Enable Bitmask" should not have overlapping bits in the mask,
- * else the results are undefined."
- */
- assert(!(clip->user_cull_enables & clip->user_clip_enables));
-
- if (ilo_dev_gen(dev) < ILO_GEN(9))
- assert(clip->z_near_enable == clip->z_far_enable);
-
- return true;
-}
-
-static bool
-raster_set_gen6_3DSTATE_CLIP(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info)
-{
- const struct ilo_state_raster_clip_info *clip = &info->clip;
- const struct ilo_state_raster_setup_info *setup = &info->setup;
- const struct ilo_state_raster_tri_info *tri = &info->tri;
- const struct ilo_state_raster_scan_info *scan = &info->scan;
- uint32_t dw1, dw2, dw3;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (!raster_validate_gen6_clip(dev, info))
- return false;
-
- dw1 = clip->user_cull_enables << GEN6_CLIP_DW1_UCP_CULL_ENABLES__SHIFT;
-
- if (clip->stats_enable)
- dw1 |= GEN6_CLIP_DW1_STATISTICS;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 219:
- *
- * "Workaround : Due to Hardware issue "EarlyCull" needs to be
- * enabled only for the cases where the incoming primitive topology
- * into the clipper guaranteed to be Trilist."
- *
- * What does this mean?
- */
- dw1 |= GEN7_CLIP_DW1_SUBPIXEL_8BITS |
- GEN7_CLIP_DW1_EARLY_CULL_ENABLE;
-
- if (ilo_dev_gen(dev) <= ILO_GEN(7.5)) {
- dw1 |= tri->front_winding << GEN7_CLIP_DW1_FRONT_WINDING__SHIFT |
- tri->cull_mode << GEN7_CLIP_DW1_CULL_MODE__SHIFT;
- }
- }
-
- dw2 = clip->user_clip_enables << GEN6_CLIP_DW2_UCP_CLIP_ENABLES__SHIFT |
- GEN6_CLIPMODE_NORMAL << GEN6_CLIP_DW2_CLIP_MODE__SHIFT;
-
- if (clip->clip_enable)
- dw2 |= GEN6_CLIP_DW2_CLIP_ENABLE;
-
- if (clip->z_near_zero)
- dw2 |= GEN6_CLIP_DW2_APIMODE_D3D;
- else
- dw2 |= GEN6_CLIP_DW2_APIMODE_OGL;
-
- if (clip->xy_test_enable)
- dw2 |= GEN6_CLIP_DW2_XY_TEST_ENABLE;
-
- if (ilo_dev_gen(dev) < ILO_GEN(8) && clip->z_near_enable)
- dw2 |= GEN6_CLIP_DW2_Z_TEST_ENABLE;
-
- if (clip->gb_test_enable)
- dw2 |= GEN6_CLIP_DW2_GB_TEST_ENABLE;
-
- if (scan->barycentric_interps & (GEN6_INTERP_NONPERSPECTIVE_PIXEL |
- GEN6_INTERP_NONPERSPECTIVE_CENTROID |
- GEN6_INTERP_NONPERSPECTIVE_SAMPLE))
- dw2 |= GEN6_CLIP_DW2_NONPERSPECTIVE_BARYCENTRIC_ENABLE;
-
- if (setup->first_vertex_provoking) {
- dw2 |= 0 << GEN6_CLIP_DW2_TRI_PROVOKE__SHIFT |
- 0 << GEN6_CLIP_DW2_LINE_PROVOKE__SHIFT |
- 1 << GEN6_CLIP_DW2_TRIFAN_PROVOKE__SHIFT;
- } else {
- dw2 |= 2 << GEN6_CLIP_DW2_TRI_PROVOKE__SHIFT |
- 1 << GEN6_CLIP_DW2_LINE_PROVOKE__SHIFT |
- 2 << GEN6_CLIP_DW2_TRIFAN_PROVOKE__SHIFT;
- }
-
- dw3 = 0x1 << GEN6_CLIP_DW3_MIN_POINT_WIDTH__SHIFT |
- 0x7ff << GEN6_CLIP_DW3_MAX_POINT_WIDTH__SHIFT |
- (clip->viewport_count - 1) << GEN6_CLIP_DW3_MAX_VPINDEX__SHIFT;
-
- if (clip->force_rtaindex_zero)
- dw3 |= GEN6_CLIP_DW3_FORCE_RTAINDEX_ZERO;
-
- STATIC_ASSERT(ARRAY_SIZE(rs->clip) >= 3);
- rs->clip[0] = dw1;
- rs->clip[1] = dw2;
- rs->clip[2] = dw3;
-
- return true;
-}
-
-static bool
-raster_params_is_gen6_line_aa_allowed(const struct ilo_dev *dev,
- const struct ilo_state_raster_params_info *params)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 251:
- *
- * "This field (Anti-aliasing Enable) must be disabled if any of the
- * render targets have integer (UINT or SINT) surface format."
- */
- if (params->any_integer_rt)
- return false;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 321:
- *
- * "[DevSNB+]: This field (Hierarchical Depth Buffer Enable) must be
- * disabled if Anti-aliasing Enable in 3DSTATE_SF is enabled.
- */
- if (ilo_dev_gen(dev) == ILO_GEN(6) && params->hiz_enable)
- return false;
-
- return true;
-}
-
-static void
-raster_get_gen6_effective_line(const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info,
- struct ilo_state_raster_line_info *line)
-{
- const struct ilo_state_raster_setup_info *setup = &info->setup;
- const struct ilo_state_raster_params_info *params = &info->params;
-
- *line = info->line;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 251:
- *
- * "This field (Anti-aliasing Enable) is ignored when Multisample
- * Rasterization Mode is MSRASTMODE_ON_xx."
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 251:
- *
- * "Setting a Line Width of 0.0 specifies the rasterization of the
- * "thinnest" (one-pixel-wide), non-antialiased lines. Note that
- * this effectively overrides the effect of AAEnable (though the
- * AAEnable state variable is not modified). Lines rendered with
- * zero Line Width are rasterized using GIQ (Grid Intersection
- * Quantization) rules as specified by the GDI and Direct3D APIs."
- *
- * "Software must not program a value of 0.0 when running in
- * MSRASTMODE_ON_xxx modes - zero-width lines are not available
- * when multisampling rasterization is enabled."
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 294:
- *
- * "Line stipple, controlled via the Line Stipple Enable state variable
- * in WM_STATE, discards certain pixels that are produced by non-AA
- * line rasterization."
- */
- if (setup->line_msaa_enable ||
- !raster_params_is_gen6_line_aa_allowed(dev, params))
- line->aa_enable = false;
- if (setup->line_msaa_enable || line->aa_enable) {
- line->stipple_enable = false;
- line->giq_enable = false;
- line->giq_last_pixel = false;
- }
-}
-
-static bool
-raster_validate_gen8_raster(const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info)
-{
- const struct ilo_state_raster_setup_info *setup = &info->setup;
- const struct ilo_state_raster_tri_info *tri = &info->tri;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 249:
- *
- * "This setting (SOLID) is required when rendering rectangle
- * (RECTLIST) objects.
- */
- if (tri->fill_mode_front != GEN6_FILLMODE_SOLID ||
- tri->fill_mode_back != GEN6_FILLMODE_SOLID)
- assert(!setup->cv_is_rectangle);
-
- return true;
-}
-
-static enum gen_msrast_mode
-raster_setup_get_gen6_msrast_mode(const struct ilo_dev *dev,
- const struct ilo_state_raster_setup_info *setup)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (setup->line_msaa_enable) {
- return (setup->msaa_enable) ? GEN6_MSRASTMODE_ON_PATTERN :
- GEN6_MSRASTMODE_ON_PIXEL;
- } else {
- return (setup->msaa_enable) ? GEN6_MSRASTMODE_OFF_PATTERN :
- GEN6_MSRASTMODE_OFF_PIXEL;
- }
-}
-
-static int
-get_gen6_line_width(const struct ilo_dev *dev, float fwidth,
- bool line_aa_enable, bool line_giq_enable)
-{
- int line_width;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* in U3.7 */
- line_width = (int) (fwidth * 128.0f + 0.5f);
-
- /*
- * Smooth lines should intersect ceil(line_width) or (ceil(line_width) + 1)
- * pixels in the minor direction. We have to make the lines slightly
- * thicker, 0.5 pixel on both sides, so that they intersect that many
- * pixels.
- */
- if (line_aa_enable)
- line_width += 128;
-
- line_width = CLAMP(line_width, 1, 1023);
-
- if (line_giq_enable && line_width == 128)
- line_width = 0;
-
- return line_width;
-}
-
-static int
-get_gen6_point_width(const struct ilo_dev *dev, float fwidth)
-{
- int point_width;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* in U8.3 */
- point_width = (int) (fwidth * 8.0f + 0.5f);
- point_width = CLAMP(point_width, 1, 2047);
-
- return point_width;
-}
-
-static bool
-raster_set_gen7_3DSTATE_SF(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info,
- const struct ilo_state_raster_line_info *line)
-{
- const struct ilo_state_raster_clip_info *clip = &info->clip;
- const struct ilo_state_raster_setup_info *setup = &info->setup;
- const struct ilo_state_raster_point_info *point = &info->point;
- const struct ilo_state_raster_tri_info *tri = &info->tri;
- const struct ilo_state_raster_params_info *params = &info->params;
- const enum gen_msrast_mode msrast =
- raster_setup_get_gen6_msrast_mode(dev, setup);
- const int line_width = get_gen6_line_width(dev, params->line_width,
- line->aa_enable, line->giq_enable);
- const int point_width = get_gen6_point_width(dev, params->point_width);
- uint32_t dw1, dw2, dw3;
-
- ILO_DEV_ASSERT(dev, 6, 7.5);
-
- if (!raster_validate_gen8_raster(dev, info))
- return false;
-
- dw1 = tri->fill_mode_front << GEN7_SF_DW1_FILL_MODE_FRONT__SHIFT |
- tri->fill_mode_back << GEN7_SF_DW1_FILL_MODE_BACK__SHIFT |
- tri->front_winding << GEN7_SF_DW1_FRONT_WINDING__SHIFT;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7) && ilo_dev_gen(dev) <= ILO_GEN(7.5)) {
- enum gen_depth_format format;
-
- /* do it here as we want 0x0 to be valid */
- switch (tri->depth_offset_format) {
- case GEN6_ZFORMAT_D32_FLOAT_S8X24_UINT:
- format = GEN6_ZFORMAT_D32_FLOAT;
- break;
- case GEN6_ZFORMAT_D24_UNORM_S8_UINT:
- format = GEN6_ZFORMAT_D24_UNORM_X8_UINT;
- break;
- default:
- format = tri->depth_offset_format;
- break;
- }
-
- dw1 |= format << GEN7_SF_DW1_DEPTH_FORMAT__SHIFT;
- }
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 248:
- *
- * "This bit (Statistics Enable) should be set whenever clipping is
- * enabled and the Statistics Enable bit is set in CLIP_STATE. It
- * should be cleared if clipping is disabled or Statistics Enable in
- * CLIP_STATE is clear."
- */
- if (clip->stats_enable && clip->clip_enable)
- dw1 |= GEN7_SF_DW1_STATISTICS;
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 258:
- *
- * "This bit (Legacy Global Depth Bias Enable, Global Depth Offset
- * Enable Solid , Global Depth Offset Enable Wireframe, and Global
- * Depth Offset Enable Point) should be set whenever non zero depth
- * bias (Slope, Bias) values are used. Setting this bit may have some
- * degradation of performance for some workloads."
- *
- * But it seems fine to ignore that.
- */
- if (tri->depth_offset_solid)
- dw1 |= GEN7_SF_DW1_DEPTH_OFFSET_SOLID;
- if (tri->depth_offset_wireframe)
- dw1 |= GEN7_SF_DW1_DEPTH_OFFSET_WIREFRAME;
- if (tri->depth_offset_point)
- dw1 |= GEN7_SF_DW1_DEPTH_OFFSET_POINT;
-
- if (setup->viewport_transform)
- dw1 |= GEN7_SF_DW1_VIEWPORT_TRANSFORM;
-
- dw2 = tri->cull_mode << GEN7_SF_DW2_CULL_MODE__SHIFT |
- line_width << GEN7_SF_DW2_LINE_WIDTH__SHIFT |
- GEN7_SF_DW2_AA_LINE_CAP_1_0 |
- msrast << GEN7_SF_DW2_MSRASTMODE__SHIFT;
-
- if (line->aa_enable)
- dw2 |= GEN7_SF_DW2_AA_LINE_ENABLE;
-
- if (ilo_dev_gen(dev) == ILO_GEN(7.5) && line->stipple_enable)
- dw2 |= GEN75_SF_DW2_LINE_STIPPLE_ENABLE;
-
- if (setup->scissor_enable)
- dw2 |= GEN7_SF_DW2_SCISSOR_ENABLE;
-
- dw3 = GEN7_SF_DW3_TRUE_AA_LINE_DISTANCE |
- GEN7_SF_DW3_SUBPIXEL_8BITS;
-
- /* this has no effect when line_width != 0 */
- if (line->giq_last_pixel)
- dw3 |= GEN7_SF_DW3_LINE_LAST_PIXEL_ENABLE;
-
- if (setup->first_vertex_provoking) {
- dw3 |= 0 << GEN7_SF_DW3_TRI_PROVOKE__SHIFT |
- 0 << GEN7_SF_DW3_LINE_PROVOKE__SHIFT |
- 1 << GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT;
- } else {
- dw3 |= 2 << GEN7_SF_DW3_TRI_PROVOKE__SHIFT |
- 1 << GEN7_SF_DW3_LINE_PROVOKE__SHIFT |
- 2 << GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT;
- }
-
- /* setup->point_aa_enable is ignored */
- if (!point->programmable_width) {
- dw3 |= GEN7_SF_DW3_USE_POINT_WIDTH |
- point_width << GEN7_SF_DW3_POINT_WIDTH__SHIFT;
- }
-
- STATIC_ASSERT(ARRAY_SIZE(rs->sf) >= 3);
- rs->sf[0] = dw1;
- rs->sf[1] = dw2;
- rs->sf[2] = dw3;
-
- STATIC_ASSERT(ARRAY_SIZE(rs->raster) >= 4);
- rs->raster[0] = 0;
- rs->raster[1] = fui(params->depth_offset_const);
- rs->raster[2] = fui(params->depth_offset_scale);
- rs->raster[3] = fui(params->depth_offset_clamp);
-
- rs->line_aa_enable = line->aa_enable;
- rs->line_giq_enable = line->giq_enable;
-
- return true;
-}
-
-static bool
-raster_set_gen8_3DSTATE_SF(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info,
- const struct ilo_state_raster_line_info *line)
-{
- const struct ilo_state_raster_clip_info *clip = &info->clip;
- const struct ilo_state_raster_setup_info *setup = &info->setup;
- const struct ilo_state_raster_point_info *point = &info->point;
- const struct ilo_state_raster_params_info *params = &info->params;
- const int line_width = get_gen6_line_width(dev, params->line_width,
- line->aa_enable, line->giq_enable);
- const int point_width = get_gen6_point_width(dev, params->point_width);
- uint32_t dw1, dw2, dw3;
-
- ILO_DEV_ASSERT(dev, 8, 8);
-
- dw1 = 0;
-
- if (clip->stats_enable && clip->clip_enable)
- dw1 |= GEN7_SF_DW1_STATISTICS;
-
- if (setup->viewport_transform)
- dw1 |= GEN7_SF_DW1_VIEWPORT_TRANSFORM;
-
- dw2 = line_width << GEN7_SF_DW2_LINE_WIDTH__SHIFT |
- GEN7_SF_DW2_AA_LINE_CAP_1_0;
-
- dw3 = GEN7_SF_DW3_TRUE_AA_LINE_DISTANCE |
- GEN7_SF_DW3_SUBPIXEL_8BITS;
-
- /* this has no effect when line_width != 0 */
- if (line->giq_last_pixel)
- dw3 |= GEN7_SF_DW3_LINE_LAST_PIXEL_ENABLE;
-
- if (setup->first_vertex_provoking) {
- dw3 |= 0 << GEN7_SF_DW3_TRI_PROVOKE__SHIFT |
- 0 << GEN7_SF_DW3_LINE_PROVOKE__SHIFT |
- 1 << GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT;
- } else {
- dw3 |= 2 << GEN7_SF_DW3_TRI_PROVOKE__SHIFT |
- 1 << GEN7_SF_DW3_LINE_PROVOKE__SHIFT |
- 2 << GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT;
- }
-
- if (!point->programmable_width) {
- dw3 |= GEN7_SF_DW3_USE_POINT_WIDTH |
- point_width << GEN7_SF_DW3_POINT_WIDTH__SHIFT;
- }
-
- STATIC_ASSERT(ARRAY_SIZE(rs->sf) >= 3);
- rs->sf[0] = dw1;
- rs->sf[1] = dw2;
- rs->sf[2] = dw3;
-
- return true;
-}
-
-static bool
-raster_set_gen8_3DSTATE_RASTER(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info,
- const struct ilo_state_raster_line_info *line)
-{
- const struct ilo_state_raster_clip_info *clip = &info->clip;
- const struct ilo_state_raster_setup_info *setup = &info->setup;
- const struct ilo_state_raster_point_info *point = &info->point;
- const struct ilo_state_raster_tri_info *tri = &info->tri;
- const struct ilo_state_raster_params_info *params = &info->params;
- uint32_t dw1;
-
- ILO_DEV_ASSERT(dev, 8, 8);
-
- if (!raster_validate_gen8_raster(dev, info))
- return false;
-
- dw1 = tri->front_winding << GEN8_RASTER_DW1_FRONT_WINDING__SHIFT |
- tri->cull_mode << GEN8_RASTER_DW1_CULL_MODE__SHIFT |
- tri->fill_mode_front << GEN8_RASTER_DW1_FILL_MODE_FRONT__SHIFT |
- tri->fill_mode_back << GEN8_RASTER_DW1_FILL_MODE_BACK__SHIFT;
-
- if (point->aa_enable)
- dw1 |= GEN8_RASTER_DW1_SMOOTH_POINT_ENABLE;
-
- /* where should line_msaa_enable be set? */
- if (setup->msaa_enable)
- dw1 |= GEN8_RASTER_DW1_DX_MULTISAMPLE_ENABLE;
-
- if (tri->depth_offset_solid)
- dw1 |= GEN8_RASTER_DW1_DEPTH_OFFSET_SOLID;
- if (tri->depth_offset_wireframe)
- dw1 |= GEN8_RASTER_DW1_DEPTH_OFFSET_WIREFRAME;
- if (tri->depth_offset_point)
- dw1 |= GEN8_RASTER_DW1_DEPTH_OFFSET_POINT;
-
- if (line->aa_enable)
- dw1 |= GEN8_RASTER_DW1_AA_LINE_ENABLE;
-
- if (setup->scissor_enable)
- dw1 |= GEN8_RASTER_DW1_SCISSOR_ENABLE;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(9)) {
- if (clip->z_far_enable)
- dw1 |= GEN9_RASTER_DW1_Z_TEST_FAR_ENABLE;
- if (clip->z_near_enable)
- dw1 |= GEN9_RASTER_DW1_Z_TEST_NEAR_ENABLE;
- } else {
- if (clip->z_near_enable)
- dw1 |= GEN8_RASTER_DW1_Z_TEST_ENABLE;
- }
-
- STATIC_ASSERT(ARRAY_SIZE(rs->raster) >= 4);
- rs->raster[0] = dw1;
- rs->raster[1] = fui(params->depth_offset_const);
- rs->raster[2] = fui(params->depth_offset_scale);
- rs->raster[3] = fui(params->depth_offset_clamp);
-
- rs->line_aa_enable = line->aa_enable;
- rs->line_giq_enable = line->giq_enable;
-
- return true;
-}
-
-static enum gen_sample_count
-get_gen6_sample_count(const struct ilo_dev *dev, uint8_t sample_count)
-{
- enum gen_sample_count c;
- int min_gen;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- switch (sample_count) {
- case 1:
- c = GEN6_NUMSAMPLES_1;
- min_gen = ILO_GEN(6);
- break;
- case 2:
- c = GEN8_NUMSAMPLES_2;
- min_gen = ILO_GEN(8);
- break;
- case 4:
- c = GEN6_NUMSAMPLES_4;
- min_gen = ILO_GEN(6);
- break;
- case 8:
- c = GEN7_NUMSAMPLES_8;
- min_gen = ILO_GEN(7);
- break;
- default:
- assert(!"unexpected sample count");
- c = GEN6_NUMSAMPLES_1;
- break;
- }
-
- assert(ilo_dev_gen(dev) >= min_gen);
-
- return c;
-}
-
-static bool
-raster_set_gen8_3DSTATE_MULTISAMPLE(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info)
-{
- const struct ilo_state_raster_setup_info *setup = &info->setup;
- const struct ilo_state_raster_scan_info *scan = &info->scan;
- const enum gen_sample_count count =
- get_gen6_sample_count(dev, scan->sample_count);
- uint32_t dw1;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 307:
- *
- * "Setting Multisample Rasterization Mode to MSRASTMODE_xxx_PATTERN
- * when Number of Multisamples == NUMSAMPLES_1 is UNDEFINED."
- */
- if (setup->msaa_enable)
- assert(scan->sample_count > 1);
-
- dw1 = scan->pixloc << GEN6_MULTISAMPLE_DW1_PIXEL_LOCATION__SHIFT |
- count << GEN6_MULTISAMPLE_DW1_NUM_SAMPLES__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(rs->sample) >= 1);
- rs->sample[0] = dw1;
-
- return true;
-}
-
-static bool
-raster_set_gen6_3DSTATE_SAMPLE_MASK(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info)
-{
- const struct ilo_state_raster_scan_info *scan = &info->scan;
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 294:
- *
- * "If Number of Multisamples is NUMSAMPLES_1, bits 7:1 of this field
- * (Sample Mask) must be zero.
- *
- * If Number of Multisamples is NUMSAMPLES_4, bits 7:4 of this field
- * must be zero."
- */
- const uint32_t mask = (1 << scan->sample_count) - 1;
- uint32_t dw1;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- dw1 = (scan->sample_mask & mask) << GEN6_SAMPLE_MASK_DW1_VAL__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(rs->sample) >= 2);
- rs->sample[1] = dw1;
-
- return true;
-}
-
-static bool
-raster_validate_gen6_wm(const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info)
-{
- const struct ilo_state_raster_scan_info *scan = &info->scan;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (ilo_dev_gen(dev) == ILO_GEN(6))
- assert(scan->earlyz_control == GEN7_EDSC_NORMAL);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 272:
- *
- * "This bit (Statistics Enable) must be disabled if either of these
- * bits is set: Depth Buffer Clear , Hierarchical Depth Buffer Resolve
- * Enable or Depth Buffer Resolve Enable."
- */
- if (scan->earlyz_op != ILO_STATE_RASTER_EARLYZ_NORMAL)
- assert(!scan->stats_enable);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 273:
- *
- * "If this field (Depth Buffer Resolve Enable) is enabled, the Depth
- * Buffer Clear and Hierarchical Depth Buffer Resolve Enable fields
- * must both be disabled."
- *
- * "If this field (Hierarchical Depth Buffer Resolve Enable) is
- * enabled, the Depth Buffer Clear and Depth Buffer Resolve Enable
- * fields must both be disabled."
- *
- * This is guaranteed.
- */
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 314-315:
- *
- * "Stencil buffer clear can be performed at the same time by enabling
- * Stencil Buffer Write Enable."
- *
- * "Note also that stencil buffer clear can be performed without depth
- * buffer clear."
- */
- if (scan->earlyz_stencil_clear) {
- assert(scan->earlyz_op == ILO_STATE_RASTER_EARLYZ_NORMAL ||
- scan->earlyz_op == ILO_STATE_RASTER_EARLYZ_DEPTH_CLEAR);
- }
-
- return true;
-}
-
-static bool
-raster_set_gen6_3dstate_wm(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info,
- const struct ilo_state_raster_line_info *line)
-{
- const struct ilo_state_raster_tri_info *tri = &info->tri;
- const struct ilo_state_raster_setup_info *setup = &info->setup;
- const struct ilo_state_raster_scan_info *scan = &info->scan;
- const enum gen_msrast_mode msrast =
- raster_setup_get_gen6_msrast_mode(dev, setup);
- /* only scan conversion states are set, as in Gen8+ */
- uint32_t dw4, dw5, dw6;
-
- ILO_DEV_ASSERT(dev, 6, 6);
-
- if (!raster_validate_gen6_wm(dev, info))
- return false;
-
- dw4 = 0;
-
- if (scan->stats_enable)
- dw4 |= GEN6_WM_DW4_STATISTICS;
-
- switch (scan->earlyz_op) {
- case ILO_STATE_RASTER_EARLYZ_DEPTH_CLEAR:
- dw4 |= GEN6_WM_DW4_DEPTH_CLEAR;
- break;
- case ILO_STATE_RASTER_EARLYZ_DEPTH_RESOLVE:
- dw4 |= GEN6_WM_DW4_DEPTH_RESOLVE;
- break;
- case ILO_STATE_RASTER_EARLYZ_HIZ_RESOLVE:
- dw4 |= GEN6_WM_DW4_HIZ_RESOLVE;
- break;
- default:
- if (scan->earlyz_stencil_clear)
- dw4 |= GEN6_WM_DW4_DEPTH_CLEAR;
- break;
- }
-
- dw5 = GEN6_WM_DW5_AA_LINE_CAP_1_0 | /* same as in 3DSTATE_SF */
- GEN6_WM_DW5_AA_LINE_WIDTH_2_0;
-
- if (tri->poly_stipple_enable)
- dw5 |= GEN6_WM_DW5_POLY_STIPPLE_ENABLE;
- if (line->stipple_enable)
- dw5 |= GEN6_WM_DW5_LINE_STIPPLE_ENABLE;
-
- dw6 = scan->zw_interp << GEN6_WM_DW6_ZW_INTERP__SHIFT |
- scan->barycentric_interps << GEN6_WM_DW6_BARYCENTRIC_INTERP__SHIFT |
- GEN6_WM_DW6_POINT_RASTRULE_UPPER_RIGHT |
- msrast << GEN6_WM_DW6_MSRASTMODE__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(rs->wm) >= 3);
- rs->wm[0] = dw4;
- rs->wm[1] = dw5;
- rs->wm[2] = dw6;
-
- return true;
-}
-
-static bool
-raster_set_gen8_3DSTATE_WM(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info,
- const struct ilo_state_raster_line_info *line)
-{
- const struct ilo_state_raster_tri_info *tri = &info->tri;
- const struct ilo_state_raster_setup_info *setup = &info->setup;
- const struct ilo_state_raster_scan_info *scan = &info->scan;
- const enum gen_msrast_mode msrast =
- raster_setup_get_gen6_msrast_mode(dev, setup);
- uint32_t dw1;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- if (!raster_validate_gen6_wm(dev, info))
- return false;
-
- dw1 = scan->earlyz_control << GEN7_WM_DW1_EDSC__SHIFT |
- scan->zw_interp << GEN7_WM_DW1_ZW_INTERP__SHIFT |
- scan->barycentric_interps << GEN7_WM_DW1_BARYCENTRIC_INTERP__SHIFT |
- GEN7_WM_DW1_AA_LINE_CAP_1_0 | /* same as in 3DSTATE_SF */
- GEN7_WM_DW1_AA_LINE_WIDTH_2_0 |
- GEN7_WM_DW1_POINT_RASTRULE_UPPER_RIGHT;
-
- if (scan->stats_enable)
- dw1 |= GEN7_WM_DW1_STATISTICS;
-
- if (ilo_dev_gen(dev) < ILO_GEN(8)) {
- switch (scan->earlyz_op) {
- case ILO_STATE_RASTER_EARLYZ_DEPTH_CLEAR:
- dw1 |= GEN7_WM_DW1_LEGACY_DEPTH_CLEAR;
- break;
- case ILO_STATE_RASTER_EARLYZ_DEPTH_RESOLVE:
- dw1 |= GEN7_WM_DW1_LEGACY_DEPTH_RESOLVE;
- break;
- case ILO_STATE_RASTER_EARLYZ_HIZ_RESOLVE:
- dw1 |= GEN7_WM_DW1_LEGACY_HIZ_RESOLVE;
- break;
- default:
- if (scan->earlyz_stencil_clear)
- dw1 |= GEN7_WM_DW1_LEGACY_DEPTH_CLEAR;
- break;
- }
- }
-
- if (tri->poly_stipple_enable)
- dw1 |= GEN7_WM_DW1_POLY_STIPPLE_ENABLE;
- if (line->stipple_enable)
- dw1 |= GEN7_WM_DW1_LINE_STIPPLE_ENABLE;
-
- if (ilo_dev_gen(dev) < ILO_GEN(8))
- dw1 |= msrast << GEN7_WM_DW1_MSRASTMODE__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(rs->wm) >= 1);
- rs->wm[0] = dw1;
-
- return true;
-}
-
-static bool
-raster_set_gen8_3dstate_wm_hz_op(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info)
-{
- const struct ilo_state_raster_scan_info *scan = &info->scan;
- const enum gen_sample_count count =
- get_gen6_sample_count(dev, scan->sample_count);
- const uint32_t mask = (1 << scan->sample_count) - 1;
- uint32_t dw1, dw4;
-
- ILO_DEV_ASSERT(dev, 8, 8);
-
- dw1 = count << GEN8_WM_HZ_DW1_NUM_SAMPLES__SHIFT;
-
- if (scan->earlyz_stencil_clear)
- dw1 |= GEN8_WM_HZ_DW1_STENCIL_CLEAR;
-
- switch (scan->earlyz_op) {
- case ILO_STATE_RASTER_EARLYZ_DEPTH_CLEAR:
- dw1 |= GEN8_WM_HZ_DW1_DEPTH_CLEAR;
- break;
- case ILO_STATE_RASTER_EARLYZ_DEPTH_RESOLVE:
- dw1 |= GEN8_WM_HZ_DW1_DEPTH_RESOLVE;
- break;
- case ILO_STATE_RASTER_EARLYZ_HIZ_RESOLVE:
- dw1 |= GEN8_WM_HZ_DW1_HIZ_RESOLVE;
- break;
- default:
- break;
- }
-
- dw4 = (scan->sample_mask & mask) << GEN8_WM_HZ_DW4_SAMPLE_MASK__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(rs->wm) >= 3);
- rs->wm[1] = dw1;
- rs->wm[2] = dw4;
-
- return true;
-}
-
-static bool
-sample_pattern_get_gen6_packed_offsets(const struct ilo_dev *dev,
- uint8_t sample_count,
- const struct ilo_state_sample_pattern_offset_info *in,
- uint8_t *out)
-{
- uint8_t max_dist, i;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- max_dist = 0;
- for (i = 0; i < sample_count; i++) {
- const int8_t dist_x = (int8_t) in[i].x - 8;
- const int8_t dist_y = (int8_t) in[i].y - 8;
- const uint8_t dist = dist_x * dist_x + dist_y * dist_y;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 305:
- *
- * "Programming Note: When programming the sample offsets (for
- * NUMSAMPLES_4 or _8 and MSRASTMODE_xxx_PATTERN), the order of the
- * samples 0 to 3 (or 7 for 8X) must have monotonically increasing
- * distance from the pixel center. This is required to get the
- * correct centroid computation in the device."
- */
- assert(dist >= max_dist);
- max_dist = dist;
-
- assert(in[i].x < 16);
- assert(in[i].y < 16);
-
- out[i] = in[i].x << 4 | in[i].y;
- }
-
- return true;
-}
-
-static bool
-line_stipple_set_gen6_3DSTATE_LINE_STIPPLE(struct ilo_state_line_stipple *stipple,
- const struct ilo_dev *dev,
- const struct ilo_state_line_stipple_info *info)
-{
- uint32_t dw1, dw2;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(info->repeat_count >= 1 && info->repeat_count <= 256);
-
- dw1 = info->pattern;
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- /* in U1.16 */
- const uint32_t inverse = 65536 / info->repeat_count;
- dw2 = inverse << GEN7_LINE_STIPPLE_DW2_INVERSE_REPEAT_COUNT__SHIFT |
- info->repeat_count << GEN6_LINE_STIPPLE_DW2_REPEAT_COUNT__SHIFT;
- } else {
- /* in U1.13 */
- const uint16_t inverse = 8192 / info->repeat_count;
- dw2 = inverse << GEN6_LINE_STIPPLE_DW2_INVERSE_REPEAT_COUNT__SHIFT |
- info->repeat_count << GEN6_LINE_STIPPLE_DW2_REPEAT_COUNT__SHIFT;
- }
-
- STATIC_ASSERT(ARRAY_SIZE(stipple->stipple) >= 2);
- stipple->stipple[0] = dw1;
- stipple->stipple[1] = dw2;
-
- return true;
-}
-
-static bool
-sample_pattern_set_gen8_3DSTATE_SAMPLE_PATTERN(struct ilo_state_sample_pattern *pattern,
- const struct ilo_dev *dev,
- const struct ilo_state_sample_pattern_info *info)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- STATIC_ASSERT(ARRAY_SIZE(pattern->pattern_1x) >= 1);
- STATIC_ASSERT(ARRAY_SIZE(pattern->pattern_2x) >= 2);
- STATIC_ASSERT(ARRAY_SIZE(pattern->pattern_4x) >= 4);
- STATIC_ASSERT(ARRAY_SIZE(pattern->pattern_8x) >= 8);
- STATIC_ASSERT(ARRAY_SIZE(pattern->pattern_16x) >= 16);
-
- return (sample_pattern_get_gen6_packed_offsets(dev, 1,
- info->pattern_1x, pattern->pattern_1x) &&
- sample_pattern_get_gen6_packed_offsets(dev, 2,
- info->pattern_2x, pattern->pattern_2x) &&
- sample_pattern_get_gen6_packed_offsets(dev, 4,
- info->pattern_4x, pattern->pattern_4x) &&
- sample_pattern_get_gen6_packed_offsets(dev, 8,
- info->pattern_8x, pattern->pattern_8x) &&
- sample_pattern_get_gen6_packed_offsets(dev, 16,
- info->pattern_16x, pattern->pattern_16x));
-
-}
-
-static bool
-poly_stipple_set_gen6_3DSTATE_POLY_STIPPLE_PATTERN(struct ilo_state_poly_stipple *stipple,
- const struct ilo_dev *dev,
- const struct ilo_state_poly_stipple_info *info)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- STATIC_ASSERT(ARRAY_SIZE(stipple->stipple) >= 32);
- memcpy(stipple->stipple, info->pattern, sizeof(info->pattern));
-
- return true;
-}
-
-bool
-ilo_state_raster_init(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info)
-{
- assert(ilo_is_zeroed(rs, sizeof(*rs)));
- return ilo_state_raster_set_info(rs, dev, info);
-}
-
-bool
-ilo_state_raster_init_for_rectlist(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- uint8_t sample_count,
- enum ilo_state_raster_earlyz_op earlyz_op,
- bool earlyz_stencil_clear)
-{
- struct ilo_state_raster_info info;
-
- memset(&info, 0, sizeof(info));
-
- info.clip.viewport_count = 1;
- info.setup.cv_is_rectangle = true;
- info.setup.msaa_enable = (sample_count > 1);
- info.scan.sample_count = sample_count;
- info.scan.sample_mask = ~0u;
- info.scan.earlyz_op = earlyz_op;
- info.scan.earlyz_stencil_clear = earlyz_stencil_clear;
-
- return ilo_state_raster_init(rs, dev, &info);
-}
-
-bool
-ilo_state_raster_set_info(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info)
-{
- struct ilo_state_raster_line_info line;
- bool ret = true;
-
- ret &= raster_set_gen6_3DSTATE_CLIP(rs, dev, info);
-
- raster_get_gen6_effective_line(dev, info, &line);
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- ret &= raster_set_gen8_3DSTATE_SF(rs, dev, info, &line);
- ret &= raster_set_gen8_3DSTATE_RASTER(rs, dev, info, &line);
- } else {
- ret &= raster_set_gen7_3DSTATE_SF(rs, dev, info, &line);
- }
-
- ret &= raster_set_gen8_3DSTATE_MULTISAMPLE(rs, dev, info);
- ret &= raster_set_gen6_3DSTATE_SAMPLE_MASK(rs, dev, info);
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- ret &= raster_set_gen8_3DSTATE_WM(rs, dev, info, &line);
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- ret &= raster_set_gen8_3dstate_wm_hz_op(rs, dev, info);
- } else {
- ret &= raster_set_gen6_3dstate_wm(rs, dev, info, &line);
- }
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_raster_set_params(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_params_info *params)
-{
- const bool line_aa_enable = (rs->line_aa_enable &&
- raster_params_is_gen6_line_aa_allowed(dev, params));
- const int line_width = get_gen6_line_width(dev, params->line_width,
- line_aa_enable, rs->line_giq_enable);
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* modify line AA enable */
- if (rs->line_aa_enable) {
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- if (line_aa_enable)
- rs->raster[0] |= GEN8_RASTER_DW1_AA_LINE_ENABLE;
- else
- rs->raster[0] &= ~GEN8_RASTER_DW1_AA_LINE_ENABLE;
- } else {
- if (line_aa_enable)
- rs->sf[1] |= GEN7_SF_DW2_AA_LINE_ENABLE;
- else
- rs->sf[1] &= ~GEN7_SF_DW2_AA_LINE_ENABLE;
- }
- }
-
- /* modify line width */
- rs->sf[1] = (rs->sf[1] & ~GEN7_SF_DW2_LINE_WIDTH__MASK) |
- line_width << GEN7_SF_DW2_LINE_WIDTH__SHIFT;
-
- /* modify point width */
- if (rs->sf[2] & GEN7_SF_DW3_USE_POINT_WIDTH) {
- const int point_width = get_gen6_point_width(dev, params->point_width);
-
- rs->sf[2] = (rs->sf[2] & ~GEN7_SF_DW3_POINT_WIDTH__MASK) |
- point_width << GEN7_SF_DW3_POINT_WIDTH__SHIFT;
- }
-
- /* modify depth offset */
- rs->raster[1] = fui(params->depth_offset_const);
- rs->raster[2] = fui(params->depth_offset_scale);
- rs->raster[3] = fui(params->depth_offset_clamp);
-
- return true;
-}
-
-void
-ilo_state_raster_full_delta(const struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- struct ilo_state_raster_delta *delta)
-{
- delta->dirty = ILO_STATE_RASTER_3DSTATE_CLIP |
- ILO_STATE_RASTER_3DSTATE_SF |
- ILO_STATE_RASTER_3DSTATE_MULTISAMPLE |
- ILO_STATE_RASTER_3DSTATE_SAMPLE_MASK |
- ILO_STATE_RASTER_3DSTATE_WM |
- ILO_STATE_RASTER_3DSTATE_AA_LINE_PARAMETERS;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- delta->dirty |= ILO_STATE_RASTER_3DSTATE_RASTER |
- ILO_STATE_RASTER_3DSTATE_WM_HZ_OP;
- }
-}
-
-void
-ilo_state_raster_get_delta(const struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster *old,
- struct ilo_state_raster_delta *delta)
-{
- delta->dirty = 0;
-
- if (memcmp(rs->clip, old->clip, sizeof(rs->clip)))
- delta->dirty |= ILO_STATE_RASTER_3DSTATE_CLIP;
-
- if (memcmp(rs->sf, old->sf, sizeof(rs->sf)))
- delta->dirty |= ILO_STATE_RASTER_3DSTATE_SF;
-
- if (memcmp(rs->raster, old->raster, sizeof(rs->raster))) {
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- delta->dirty |= ILO_STATE_RASTER_3DSTATE_RASTER;
- else
- delta->dirty |= ILO_STATE_RASTER_3DSTATE_SF;
- }
-
- if (memcmp(rs->sample, old->sample, sizeof(rs->sample))) {
- delta->dirty |= ILO_STATE_RASTER_3DSTATE_MULTISAMPLE |
- ILO_STATE_RASTER_3DSTATE_SAMPLE_MASK;
- }
-
- if (memcmp(rs->wm, old->wm, sizeof(rs->wm))) {
- delta->dirty |= ILO_STATE_RASTER_3DSTATE_WM;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- delta->dirty |= ILO_STATE_RASTER_3DSTATE_WM_HZ_OP;
- }
-}
-
-bool
-ilo_state_sample_pattern_init(struct ilo_state_sample_pattern *pattern,
- const struct ilo_dev *dev,
- const struct ilo_state_sample_pattern_info *info)
-{
- bool ret = true;
-
- ret &= sample_pattern_set_gen8_3DSTATE_SAMPLE_PATTERN(pattern, dev, info);
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_sample_pattern_init_default(struct ilo_state_sample_pattern *pattern,
- const struct ilo_dev *dev)
-{
- static const struct ilo_state_sample_pattern_info default_info = {
- .pattern_1x = {
- { 8, 8 },
- },
-
- .pattern_2x = {
- { 4, 4 }, { 12, 12 },
- },
-
- .pattern_4x = {
- { 6, 2 }, { 14, 6 }, { 2, 10 }, { 10, 14 },
- },
-
- /* \see brw_multisample_positions_8x */
- .pattern_8x = {
- { 7, 9 }, { 9, 13 }, { 11, 3 }, { 13, 11 },
- { 1, 7 }, { 5, 1 }, { 15, 5 }, { 3, 15 },
- },
-
- .pattern_16x = {
- { 8, 10 }, { 11, 8 }, { 5, 6 }, { 6, 4 },
- { 12, 11 }, { 13, 9 }, { 14, 7 }, { 10, 2 },
- { 4, 13 }, { 3, 3 }, { 7, 1 }, { 15, 5 },
- { 1, 12 }, { 9, 0 }, { 2, 14 }, { 0, 15 },
- },
- };
-
- return ilo_state_sample_pattern_init(pattern, dev, &default_info);
-}
-
-const uint8_t *
-ilo_state_sample_pattern_get_packed_offsets(const struct ilo_state_sample_pattern *pattern,
- const struct ilo_dev *dev,
- uint8_t sample_count)
-{
- switch (sample_count) {
- case 1: return pattern->pattern_1x;
- case 2: return pattern->pattern_2x;
- case 4: return pattern->pattern_4x;
- case 8: return pattern->pattern_8x;
- case 16: return pattern->pattern_16x;
- default:
- assert(!"unknown sample count");
- return NULL;
- }
-}
-
-void
-ilo_state_sample_pattern_get_offset(const struct ilo_state_sample_pattern *pattern,
- const struct ilo_dev *dev,
- uint8_t sample_count, uint8_t sample_index,
- uint8_t *x, uint8_t *y)
-{
- const const uint8_t *packed =
- ilo_state_sample_pattern_get_packed_offsets(pattern, dev, sample_count);
-
- assert(sample_index < sample_count);
-
- *x = (packed[sample_index] >> 4) & 0xf;
- *y = packed[sample_index] & 0xf;
-}
-
-/**
- * No need to initialize first.
- */
-bool
-ilo_state_line_stipple_set_info(struct ilo_state_line_stipple *stipple,
- const struct ilo_dev *dev,
- const struct ilo_state_line_stipple_info *info)
-{
- bool ret = true;
-
- ret &= line_stipple_set_gen6_3DSTATE_LINE_STIPPLE(stipple,
- dev, info);
-
- assert(ret);
-
- return ret;
-}
-
-/**
- * No need to initialize first.
- */
-bool
-ilo_state_poly_stipple_set_info(struct ilo_state_poly_stipple *stipple,
- const struct ilo_dev *dev,
- const struct ilo_state_poly_stipple_info *info)
-{
- bool ret = true;
-
- ret &= poly_stipple_set_gen6_3DSTATE_POLY_STIPPLE_PATTERN(stipple,
- dev, info);
-
- assert(ret);
-
- return ret;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_STATE_RASTER_H
-#define ILO_STATE_RASTER_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-
-enum ilo_state_raster_dirty_bits {
- ILO_STATE_RASTER_3DSTATE_CLIP = (1 << 0),
- ILO_STATE_RASTER_3DSTATE_SF = (1 << 1),
- ILO_STATE_RASTER_3DSTATE_RASTER = (1 << 2),
- ILO_STATE_RASTER_3DSTATE_MULTISAMPLE = (1 << 3),
- ILO_STATE_RASTER_3DSTATE_SAMPLE_MASK = (1 << 4),
- ILO_STATE_RASTER_3DSTATE_WM = (1 << 5),
- ILO_STATE_RASTER_3DSTATE_WM_HZ_OP = (1 << 6),
- ILO_STATE_RASTER_3DSTATE_AA_LINE_PARAMETERS = (1 << 7),
-};
-
-enum ilo_state_raster_earlyz_op {
- ILO_STATE_RASTER_EARLYZ_NORMAL,
- ILO_STATE_RASTER_EARLYZ_DEPTH_CLEAR,
- ILO_STATE_RASTER_EARLYZ_DEPTH_RESOLVE,
- ILO_STATE_RASTER_EARLYZ_HIZ_RESOLVE,
-};
-
-/**
- * VUE readback, VertexClipTest, ClipDetermination, and primitive output.
- */
-struct ilo_state_raster_clip_info {
- bool clip_enable;
- /* CL_INVOCATION_COUNT and CL_PRIMITIVES_COUNT */
- bool stats_enable;
-
- uint8_t viewport_count;
- bool force_rtaindex_zero;
-
- /* these should be mutually exclusive */
- uint8_t user_cull_enables;
- uint8_t user_clip_enables;
-
- bool gb_test_enable;
- bool xy_test_enable;
-
- /* far/near must be enabled together prior to Gen9 */
- bool z_far_enable;
- bool z_near_enable;
- bool z_near_zero;
-};
-
-/**
- * Primitive assembly, viewport transformation, scissoring, MSAA, etc.
- */
-struct ilo_state_raster_setup_info {
- bool cv_is_rectangle;
-
- bool first_vertex_provoking;
- bool viewport_transform;
-
- bool scissor_enable;
-
- /* MSAA enables for lines and non-lines */
- bool msaa_enable;
- bool line_msaa_enable;
-};
-
-/**
- * 3DOBJ_POINT rasterization rules.
- */
-struct ilo_state_raster_point_info {
- /* ignored when msaa_enable is set */
- bool aa_enable;
-
- bool programmable_width;
-};
-
-/**
- * 3DOBJ_LINE rasterization rules.
- */
-struct ilo_state_raster_line_info {
- /* ignored when line_msaa_enable is set */
- bool aa_enable;
-
- /* ignored when line_msaa_enable or aa_enable is set */
- bool stipple_enable;
- bool giq_enable;
- bool giq_last_pixel;
-};
-
-/**
- * 3DOBJ_TRIANGLE rasterization rules.
- */
-struct ilo_state_raster_tri_info {
- enum gen_front_winding front_winding;
- enum gen_cull_mode cull_mode;
- enum gen_fill_mode fill_mode_front;
- enum gen_fill_mode fill_mode_back;
-
- enum gen_depth_format depth_offset_format;
- bool depth_offset_solid;
- bool depth_offset_wireframe;
- bool depth_offset_point;
-
- bool poly_stipple_enable;
-};
-
-/**
- * Scan conversion.
- */
-struct ilo_state_raster_scan_info {
- /* PS_DEPTH_COUNT and PS_INVOCATION_COUNT */
- bool stats_enable;
-
- uint8_t sample_count;
-
- /* pixel location for non-MSAA or 1x-MSAA */
- enum gen_pixel_location pixloc;
-
- uint32_t sample_mask;
-
- /* interpolations */
- enum gen_zw_interp zw_interp;
- uint8_t barycentric_interps;
-
- /* Gen7+ only */
- enum gen_edsc_mode earlyz_control;
- enum ilo_state_raster_earlyz_op earlyz_op;
- bool earlyz_stencil_clear;
-};
-
-/**
- * Raster parameters.
- */
-struct ilo_state_raster_params_info {
- bool any_integer_rt;
- bool hiz_enable;
-
- float point_width;
- float line_width;
-
- /* const term will be scaled by 'r' */
- float depth_offset_const;
- float depth_offset_scale;
- float depth_offset_clamp;
-};
-
-struct ilo_state_raster_info {
- struct ilo_state_raster_clip_info clip;
- struct ilo_state_raster_setup_info setup;
- struct ilo_state_raster_point_info point;
- struct ilo_state_raster_line_info line;
- struct ilo_state_raster_tri_info tri;
- struct ilo_state_raster_scan_info scan;
-
- struct ilo_state_raster_params_info params;
-};
-
-struct ilo_state_raster {
- uint32_t clip[3];
- uint32_t sf[3];
- uint32_t raster[4];
- uint32_t sample[2];
- uint32_t wm[3];
-
- bool line_aa_enable;
- bool line_giq_enable;
-};
-
-struct ilo_state_raster_delta {
- uint32_t dirty;
-};
-
-struct ilo_state_sample_pattern_offset_info {
- /* in U0.4 */
- uint8_t x;
- uint8_t y;
-};
-
-struct ilo_state_sample_pattern_info {
- struct ilo_state_sample_pattern_offset_info pattern_1x[1];
- struct ilo_state_sample_pattern_offset_info pattern_2x[2];
- struct ilo_state_sample_pattern_offset_info pattern_4x[4];
- struct ilo_state_sample_pattern_offset_info pattern_8x[8];
- struct ilo_state_sample_pattern_offset_info pattern_16x[16];
-};
-
-struct ilo_state_sample_pattern {
- uint8_t pattern_1x[1];
- uint8_t pattern_2x[2];
- uint8_t pattern_4x[4];
- uint8_t pattern_8x[8];
- uint8_t pattern_16x[16];
-};
-
-struct ilo_state_line_stipple_info {
- uint16_t pattern;
- uint16_t repeat_count;
-};
-
-struct ilo_state_line_stipple {
- uint32_t stipple[2];
-};
-
-struct ilo_state_poly_stipple_info {
- uint32_t pattern[32];
-};
-
-struct ilo_state_poly_stipple {
- uint32_t stipple[32];
-};
-
-bool
-ilo_state_raster_init(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info);
-
-bool
-ilo_state_raster_init_for_rectlist(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- uint8_t sample_count,
- enum ilo_state_raster_earlyz_op earlyz_op,
- bool earlyz_stencil_clear);
-
-bool
-ilo_state_raster_set_info(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info);
-
-bool
-ilo_state_raster_set_params(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_params_info *params);
-
-void
-ilo_state_raster_full_delta(const struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- struct ilo_state_raster_delta *delta);
-
-void
-ilo_state_raster_get_delta(const struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster *old,
- struct ilo_state_raster_delta *delta);
-
-bool
-ilo_state_sample_pattern_init(struct ilo_state_sample_pattern *pattern,
- const struct ilo_dev *dev,
- const struct ilo_state_sample_pattern_info *info);
-
-bool
-ilo_state_sample_pattern_init_default(struct ilo_state_sample_pattern *pattern,
- const struct ilo_dev *dev);
-
-const uint8_t *
-ilo_state_sample_pattern_get_packed_offsets(const struct ilo_state_sample_pattern *pattern,
- const struct ilo_dev *dev,
- uint8_t sample_count);
-
-void
-ilo_state_sample_pattern_get_offset(const struct ilo_state_sample_pattern *pattern,
- const struct ilo_dev *dev,
- uint8_t sample_count, uint8_t sample_index,
- uint8_t *x, uint8_t *y);
-bool
-ilo_state_line_stipple_set_info(struct ilo_state_line_stipple *stipple,
- const struct ilo_dev *dev,
- const struct ilo_state_line_stipple_info *info);
-
-bool
-ilo_state_poly_stipple_set_info(struct ilo_state_poly_stipple *stipple,
- const struct ilo_dev *dev,
- const struct ilo_state_poly_stipple_info *info);
-
-#endif /* ILO_STATE_RASTER_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "util/u_half.h"
-
-#include "ilo_debug.h"
-#include "ilo_state_surface.h"
-#include "ilo_state_sampler.h"
-
-static bool
-sampler_validate_gen6_non_normalized(const struct ilo_dev *dev,
- const struct ilo_state_sampler_info *info)
-{
- const enum gen_texcoord_mode addr_ctrls[3] = {
- info->tcx_ctrl, info->tcy_ctrl, info->tcz_ctrl,
- };
- int i;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 98:
- *
- * "The following state must be set as indicated if this field
- * (Non-normalized Coordinate Enable) is enabled:
- *
- * - TCX/Y/Z Address Control Mode must be TEXCOORDMODE_CLAMP,
- * TEXCOORDMODE_HALF_BORDER, or TEXCOORDMODE_CLAMP_BORDER.
- * - Surface Type must be SURFTYPE_2D or SURFTYPE_3D.
- * - Mag Mode Filter must be MAPFILTER_NEAREST or
- * MAPFILTER_LINEAR.
- * - Min Mode Filter must be MAPFILTER_NEAREST or
- * MAPFILTER_LINEAR.
- * - Mip Mode Filter must be MIPFILTER_NONE.
- * - Min LOD must be 0.
- * - Max LOD must be 0.
- * - MIP Count must be 0.
- * - Surface Min LOD must be 0.
- * - Texture LOD Bias must be 0."
- */
- for (i = 0; i < 3; i++) {
- switch (addr_ctrls[i]) {
- case GEN6_TEXCOORDMODE_CLAMP:
- case GEN6_TEXCOORDMODE_CLAMP_BORDER:
- case GEN8_TEXCOORDMODE_HALF_BORDER:
- break;
- default:
- assert(!"bad non-normalized coordinate wrap mode");
- break;
- }
- }
-
- assert(info->mip_filter == GEN6_MIPFILTER_NONE);
-
- assert((info->min_filter == GEN6_MAPFILTER_NEAREST ||
- info->min_filter == GEN6_MAPFILTER_LINEAR) &&
- (info->mag_filter == GEN6_MAPFILTER_NEAREST ||
- info->mag_filter == GEN6_MAPFILTER_LINEAR));
-
- assert(info->min_lod == 0.0f &&
- info->max_lod == 0.0f &&
- info->lod_bias == 0.0f);
-
- return true;
-}
-
-static bool
-sampler_validate_gen6_sampler(const struct ilo_dev *dev,
- const struct ilo_state_sampler_info *info)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (info->non_normalized &&
- !sampler_validate_gen6_non_normalized(dev, info))
- return false;
-
- if (ilo_dev_gen(dev) < ILO_GEN(8)) {
- assert(info->tcx_ctrl != GEN8_TEXCOORDMODE_HALF_BORDER &&
- info->tcy_ctrl != GEN8_TEXCOORDMODE_HALF_BORDER &&
- info->tcz_ctrl != GEN8_TEXCOORDMODE_HALF_BORDER);
- }
-
- return true;
-}
-
-static uint32_t
-sampler_get_gen6_integer_filters(const struct ilo_dev *dev,
- const struct ilo_state_sampler_info *info)
-{
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 103:
- *
- * "MIPFILTER_LINEAR is not supported for surface formats that do not
- * support "Sampling Engine Filtering" as indicated in the Surface
- * Formats table unless using the sample_c message type."
- *
- * "Only MAPFILTER_NEAREST is supported for surface formats that do not
- * support "Sampling Engine Filtering" as indicated in the Surface
- * Formats table unless using the sample_c message type.
- */
- const enum gen_mip_filter mip_filter =
- (info->mip_filter == GEN6_MIPFILTER_LINEAR) ?
- GEN6_MIPFILTER_NEAREST : info->mip_filter;
- const enum gen_map_filter min_filter = GEN6_MAPFILTER_NEAREST;
- const enum gen_map_filter mag_filter = GEN6_MAPFILTER_NEAREST;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- return mip_filter << GEN6_SAMPLER_DW0_MIP_FILTER__SHIFT |
- mag_filter << GEN6_SAMPLER_DW0_MAG_FILTER__SHIFT |
- min_filter << GEN6_SAMPLER_DW0_MIN_FILTER__SHIFT;
-}
-
-static uint32_t
-sampler_get_gen6_3d_filters(const struct ilo_dev *dev,
- const struct ilo_state_sampler_info *info)
-{
- const enum gen_mip_filter mip_filter = info->mip_filter;
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 103:
- *
- * "Only MAPFILTER_NEAREST and MAPFILTER_LINEAR are supported for
- * surfaces of type SURFTYPE_3D."
- */
- const enum gen_map_filter min_filter =
- (info->min_filter == GEN6_MAPFILTER_NEAREST ||
- info->min_filter == GEN6_MAPFILTER_LINEAR) ?
- info->min_filter : GEN6_MAPFILTER_LINEAR;
- const enum gen_map_filter mag_filter =
- (info->mag_filter == GEN6_MAPFILTER_NEAREST ||
- info->mag_filter == GEN6_MAPFILTER_LINEAR) ?
- info->mag_filter : GEN6_MAPFILTER_LINEAR;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- return mip_filter << GEN6_SAMPLER_DW0_MIP_FILTER__SHIFT |
- mag_filter << GEN6_SAMPLER_DW0_MAG_FILTER__SHIFT |
- min_filter << GEN6_SAMPLER_DW0_MIN_FILTER__SHIFT;
-}
-
-static uint32_t
-get_gen6_addr_controls(const struct ilo_dev *dev,
- enum gen_texcoord_mode tcx_ctrl,
- enum gen_texcoord_mode tcy_ctrl,
- enum gen_texcoord_mode tcz_ctrl)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- return tcx_ctrl << GEN7_SAMPLER_DW3_U_WRAP__SHIFT |
- tcy_ctrl << GEN7_SAMPLER_DW3_V_WRAP__SHIFT |
- tcz_ctrl << GEN7_SAMPLER_DW3_R_WRAP__SHIFT;
- } else {
- return tcx_ctrl << GEN6_SAMPLER_DW1_U_WRAP__SHIFT |
- tcy_ctrl << GEN6_SAMPLER_DW1_V_WRAP__SHIFT |
- tcz_ctrl << GEN6_SAMPLER_DW1_R_WRAP__SHIFT;
- }
-}
-
-static uint32_t
-sampler_get_gen6_1d_addr_controls(const struct ilo_dev *dev,
- const struct ilo_state_sampler_info *info)
-{
- const enum gen_texcoord_mode tcx_ctrl =
- (info->tcx_ctrl == GEN6_TEXCOORDMODE_CUBE) ?
- GEN6_TEXCOORDMODE_CLAMP : info->tcx_ctrl;
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 100:
- *
- * "If this field (TCY Address Control Mode) is set to
- * TEXCOORDMODE_CLAMP_BORDER or TEXCOORDMODE_HALF_BORDER and a 1D
- * surface is sampled, incorrect blending with the border color in the
- * vertical direction may occur."
- */
- const enum gen_texcoord_mode tcy_ctrl = GEN6_TEXCOORDMODE_CLAMP;
- const enum gen_texcoord_mode tcz_ctrl = GEN6_TEXCOORDMODE_CLAMP;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- return get_gen6_addr_controls(dev, tcx_ctrl, tcy_ctrl, tcz_ctrl);
-}
-
-static uint32_t
-sampler_get_gen6_2d_3d_addr_controls(const struct ilo_dev *dev,
- const struct ilo_state_sampler_info *info)
-{
- const enum gen_texcoord_mode tcx_ctrl =
- (info->tcx_ctrl == GEN6_TEXCOORDMODE_CUBE) ?
- GEN6_TEXCOORDMODE_CLAMP : info->tcx_ctrl;
- const enum gen_texcoord_mode tcy_ctrl =
- (info->tcy_ctrl == GEN6_TEXCOORDMODE_CUBE) ?
- GEN6_TEXCOORDMODE_CLAMP : info->tcy_ctrl;
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 108:
- *
- * "[DevSNB]: if this field (TCZ Address Control Mode) is set to
- * TEXCOORDMODE_CLAMP_BORDER samples outside the map will clamp to 0
- * instead of boarder color"
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 100:
- *
- * "If this field is set to TEXCOORDMODE_CLAMP_BORDER for 3D maps on
- * formats without an alpha channel, samples straddling the map in the
- * Z direction may have their alpha channels off by 1."
- *
- * Do we want to do something here?
- */
- const enum gen_texcoord_mode tcz_ctrl =
- (info->tcz_ctrl == GEN6_TEXCOORDMODE_CUBE) ?
- GEN6_TEXCOORDMODE_CLAMP : info->tcz_ctrl;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- return get_gen6_addr_controls(dev, tcx_ctrl, tcy_ctrl, tcz_ctrl);
-}
-
-static uint32_t
-sampler_get_gen6_cube_addr_controls(const struct ilo_dev *dev,
- const struct ilo_state_sampler_info *info)
-{
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 99:
- *
- * "When using cube map texture coordinates, only TEXCOORDMODE_CLAMP
- * and TEXCOORDMODE_CUBE settings are valid, and each TC component
- * must have the same Address Control mode.
- *
- * When TEXCOORDMODE_CUBE is not used accessing a cube map, the map's
- * Cube Face Enable field must be programmed to 111111b (all faces
- * enabled)."
- *
- * From the Haswell PRM, volume 2d, page 278:
- *
- * "When using cube map texture coordinates, each TC component must
- * have the same Address Control Mode.
- *
- * When TEXCOORDMODE_CUBE is not used accessing a cube map, the map's
- * Cube Face Enable field must be programmed to 111111b (all faces
- * enabled)."
- *
- * We always enable all cube faces and only need to make sure all address
- * control modes are the same.
- */
- const enum gen_texcoord_mode tcx_ctrl =
- (ilo_dev_gen(dev) >= ILO_GEN(7.5) ||
- info->tcx_ctrl == GEN6_TEXCOORDMODE_CUBE ||
- info->tcx_ctrl == GEN6_TEXCOORDMODE_CLAMP) ?
- info->tcx_ctrl : GEN6_TEXCOORDMODE_CLAMP;
- const enum gen_texcoord_mode tcy_ctrl = tcx_ctrl;
- const enum gen_texcoord_mode tcz_ctrl = tcx_ctrl;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- return get_gen6_addr_controls(dev, tcx_ctrl, tcy_ctrl, tcz_ctrl);
-}
-
-static uint16_t
-get_gen6_lod_bias(const struct ilo_dev *dev, float bias)
-{
- /* [-16.0, 16.0) in S4.6 or S4.8 */
- const int fbits = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 8 : 6;
- const float max = 16.0f;
- const float scale = (float) (1 << fbits);
- const int mask = (1 << (1 + 4 + fbits)) - 1;
- const int scaled_max = (16 << fbits) - 1;
- int scaled;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (bias > max)
- bias = max;
- else if (bias < -max)
- bias = -max;
-
- scaled = (int) (bias * scale);
- if (scaled > scaled_max)
- scaled = scaled_max;
-
- return (scaled & mask);
-}
-
-static uint16_t
-get_gen6_lod_clamp(const struct ilo_dev *dev, float clamp)
-{
- /* [0.0, 13.0] in U4.6 or [0.0, 14.0] in U4.8 */
- const int fbits = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 8 : 6;
- const float max = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 14.0f : 13.0f;
- const float scale = (float) (1 << fbits);
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (clamp > max)
- clamp = max;
- else if (clamp < 0.0f)
- clamp = 0.0f;
-
- return (int) (clamp * scale);
-}
-
-static bool
-sampler_set_gen6_SAMPLER_STATE(struct ilo_state_sampler *sampler,
- const struct ilo_dev *dev,
- const struct ilo_state_sampler_info *info)
-{
- uint16_t lod_bias, max_lod, min_lod;
- uint32_t dw0, dw1, dw3;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (!sampler_validate_gen6_sampler(dev, info))
- return false;
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 15:
- *
- * "The per-pixel LOD is computed in an implementation-dependent manner
- * and approximates the log2 of the texel/pixel ratio at the given
- * pixel. The computation is typically based on the differential
- * texel-space distances associated with a one-pixel differential
- * distance along the screen x- and y-axes. These texel-space
- * distances are computed by evaluating neighboring pixel texture
- * coordinates, these coordinates being in units of texels on the base
- * MIP level (multiplied by the corresponding surface size in
- * texels)."
- *
- * Judging from the LOD computation pseudocode on page 16-18, the "base MIP
- * level" should be given by SurfMinLod. To summarize, for the "sample"
- * message,
- *
- * 1) LOD is set to log2(texel/pixel ratio). The number of texels is
- * measured against level SurfMinLod.
- * 2) Bias is added to LOD.
- * 3) if pre-clamp is enabled, LOD is clamped to [MinLod, MaxLod] first
- * 4) LOD is compared with Base to determine whether magnification or
- * minification is needed.
- * 5) If magnification is needed, or no mipmapping is requested, LOD is
- * set to floor(MinLod).
- * 6) LOD is clamped to [0, MIPCnt], and SurfMinLod is added to LOD.
- *
- * As an example, we could set SurfMinLod to GL_TEXTURE_BASE_LEVEL and Base
- * to 0 to match GL. But GL expects LOD to be set to 0, instead of
- * floor(MinLod), in 5). Since this is only an issue when MinLod is
- * greater than or equal to one, and, with Base being 0, a non-zero MinLod
- * implies minification, we only need to deal with the case when mipmapping
- * is disabled. We can thus do:
- *
- * if (MipFilter == MIPFILTER_NONE && MinLod) {
- * MinLod = 0;
- * MagFilter = MinFilter;
- * }
- */
-
- lod_bias = get_gen6_lod_bias(dev, info->lod_bias);
- min_lod = get_gen6_lod_clamp(dev, info->min_lod);
- max_lod = get_gen6_lod_clamp(dev, info->max_lod);
-
- dw0 = GEN6_SAMPLER_DW0_LOD_PRECLAMP_ENABLE |
- 0 << GEN6_SAMPLER_DW0_BASE_LOD__SHIFT |
- info->mip_filter << GEN6_SAMPLER_DW0_MIP_FILTER__SHIFT |
- info->mag_filter << GEN6_SAMPLER_DW0_MAG_FILTER__SHIFT |
- info->min_filter << GEN6_SAMPLER_DW0_MIN_FILTER__SHIFT;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- dw0 |= GEN7_SAMPLER_DW0_BORDER_COLOR_MODE_DX10_OGL |
- lod_bias << GEN7_SAMPLER_DW0_LOD_BIAS__SHIFT;
-
- if (info->min_filter == GEN6_MAPFILTER_ANISOTROPIC ||
- info->mag_filter == GEN6_MAPFILTER_ANISOTROPIC)
- dw0 |= GEN7_SAMPLER_DW0_ANISO_ALGO_EWA;
- } else {
- dw0 |= lod_bias << GEN6_SAMPLER_DW0_LOD_BIAS__SHIFT |
- info->shadow_func << GEN6_SAMPLER_DW0_SHADOW_FUNC__SHIFT;
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 102:
- *
- * "(Min and Mag State Not Equal) Must be set to 1 if any of the
- * following are true:
- *
- * - Mag Mode Filter and Min Mode Filter are not the same
- * - Address Rounding Enable: U address mag filter and U address
- * min filter are not the same
- * - Address Rounding Enable: V address mag filter and V address
- * min filter are not the same
- * - Address Rounding Enable: R address mag filter and R address
- * min filter are not the same"
- *
- * We set address rounding for U, V, and R uniformly. Only need to
- * check the filters.
- */
- if (info->min_filter != info->mag_filter)
- dw0 |= GEN6_SAMPLER_DW0_MIN_MAG_NOT_EQUAL;
- }
-
- dw1 = 0;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 96:
- *
- * "This field (Cube Surface Control Mode) must be set to
- * CUBECTRLMODE_PROGRAMMED"
- */
- dw1 |= min_lod << GEN7_SAMPLER_DW1_MIN_LOD__SHIFT |
- max_lod << GEN7_SAMPLER_DW1_MAX_LOD__SHIFT |
- info->shadow_func << GEN7_SAMPLER_DW1_SHADOW_FUNC__SHIFT |
- GEN7_SAMPLER_DW1_CUBECTRLMODE_PROGRAMMED;
- } else {
- dw1 |= min_lod << GEN6_SAMPLER_DW1_MIN_LOD__SHIFT |
- max_lod << GEN6_SAMPLER_DW1_MAX_LOD__SHIFT |
- GEN6_SAMPLER_DW1_CUBECTRLMODE_PROGRAMMED |
- info->tcx_ctrl << GEN6_SAMPLER_DW1_U_WRAP__SHIFT |
- info->tcy_ctrl << GEN6_SAMPLER_DW1_V_WRAP__SHIFT |
- info->tcz_ctrl << GEN6_SAMPLER_DW1_R_WRAP__SHIFT;
- }
-
- dw3 = info->max_anisotropy << GEN6_SAMPLER_DW3_MAX_ANISO__SHIFT;
-
- /* round the coordinates for linear filtering */
- if (info->min_filter != GEN6_MAPFILTER_NEAREST) {
- dw3 |= GEN6_SAMPLER_DW3_U_MIN_ROUND |
- GEN6_SAMPLER_DW3_V_MIN_ROUND |
- GEN6_SAMPLER_DW3_R_MIN_ROUND;
- }
- if (info->mag_filter != GEN6_MAPFILTER_NEAREST) {
- dw3 |= GEN6_SAMPLER_DW3_U_MAG_ROUND |
- GEN6_SAMPLER_DW3_V_MAG_ROUND |
- GEN6_SAMPLER_DW3_R_MAG_ROUND;
- }
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- dw3 |= GEN7_SAMPLER_DW3_TRIQUAL_FULL |
- info->tcx_ctrl << GEN7_SAMPLER_DW3_U_WRAP__SHIFT |
- info->tcy_ctrl << GEN7_SAMPLER_DW3_V_WRAP__SHIFT |
- info->tcz_ctrl << GEN7_SAMPLER_DW3_R_WRAP__SHIFT;
-
- if (info->non_normalized)
- dw3 |= GEN7_SAMPLER_DW3_NON_NORMALIZED_COORD;
- } else {
- if (info->non_normalized)
- dw3 |= GEN6_SAMPLER_DW3_NON_NORMALIZED_COORD;
- }
-
- STATIC_ASSERT(ARRAY_SIZE(sampler->sampler) >= 3);
- sampler->sampler[0] = dw0;
- sampler->sampler[1] = dw1;
- sampler->sampler[2] = dw3;
-
- sampler->filter_integer = sampler_get_gen6_integer_filters(dev, info);
- sampler->filter_3d = sampler_get_gen6_3d_filters(dev, info);
- sampler->addr_ctrl_1d = sampler_get_gen6_1d_addr_controls(dev, info);
- sampler->addr_ctrl_2d_3d = sampler_get_gen6_2d_3d_addr_controls(dev, info);
- sampler->addr_ctrl_cube = sampler_get_gen6_cube_addr_controls(dev, info);
-
- sampler->non_normalized = info->non_normalized;
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 21:
- *
- * "[DevSNB] Errata: Incorrect behavior is observed in cases where the
- * min and mag mode filters are different and SurfMinLOD is nonzero.
- * The determination of MagMode uses the following equation instead of
- * the one in the above pseudocode:
- *
- * MagMode = (LOD + SurfMinLOD - Base <= 0)"
- *
- * As a way to work around that, request Base to be set to SurfMinLod.
- */
- if (ilo_dev_gen(dev) == ILO_GEN(6) &&
- info->min_filter != info->mag_filter)
- sampler->base_to_surf_min_lod = true;
-
- return true;
-}
-
-static bool
-sampler_border_set_gen6_SAMPLER_BORDER_COLOR_STATE(struct ilo_state_sampler_border *border,
- const struct ilo_dev *dev,
- const struct ilo_state_sampler_border_info *info)
-{
- uint32_t dw[12];
- float rgba[4];
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 117:
- *
- * "For ([DevSNB]), if border color is used, all formats must be
- * provided. Hardware will choose the appropriate format based on
- * Surface Format and Texture Border Color Mode. The values
- * represented by each format should be the same (other than being
- * subject to range-based clamping and precision) to avoid unexpected
- * behavior."
- *
- * XXX We do not honor info->is_integer yet.
- */
-
- ILO_DEV_ASSERT(dev, 6, 6);
-
- /* make a copy so that we can clamp for SNORM and UNORM */
- memcpy(rgba, info->rgba.f, sizeof(rgba));
-
- /* IEEE_FP */
- dw[1] = fui(rgba[0]);
- dw[2] = fui(rgba[1]);
- dw[3] = fui(rgba[2]);
- dw[4] = fui(rgba[3]);
-
- /* FLOAT_16 */
- dw[5] = util_float_to_half(rgba[0]) |
- util_float_to_half(rgba[1]) << 16;
- dw[6] = util_float_to_half(rgba[2]) |
- util_float_to_half(rgba[3]) << 16;
-
- /* clamp to [-1.0f, 1.0f] */
- rgba[0] = CLAMP(rgba[0], -1.0f, 1.0f);
- rgba[1] = CLAMP(rgba[1], -1.0f, 1.0f);
- rgba[2] = CLAMP(rgba[2], -1.0f, 1.0f);
- rgba[3] = CLAMP(rgba[3], -1.0f, 1.0f);
-
- /* SNORM16 */
- dw[9] = (int16_t) util_iround(rgba[0] * 32767.0f) |
- (int16_t) util_iround(rgba[1] * 32767.0f) << 16;
- dw[10] = (int16_t) util_iround(rgba[2] * 32767.0f) |
- (int16_t) util_iround(rgba[3] * 32767.0f) << 16;
-
- /* SNORM8 */
- dw[11] = (int8_t) util_iround(rgba[0] * 127.0f) |
- (int8_t) util_iround(rgba[1] * 127.0f) << 8 |
- (int8_t) util_iround(rgba[2] * 127.0f) << 16 |
- (int8_t) util_iround(rgba[3] * 127.0f) << 24;
-
- /* clamp to [0.0f, 1.0f] */
- rgba[0] = CLAMP(rgba[0], 0.0f, 1.0f);
- rgba[1] = CLAMP(rgba[1], 0.0f, 1.0f);
- rgba[2] = CLAMP(rgba[2], 0.0f, 1.0f);
- rgba[3] = CLAMP(rgba[3], 0.0f, 1.0f);
-
- /* UNORM8 */
- dw[0] = (uint8_t) util_iround(rgba[0] * 255.0f) |
- (uint8_t) util_iround(rgba[1] * 255.0f) << 8 |
- (uint8_t) util_iround(rgba[2] * 255.0f) << 16 |
- (uint8_t) util_iround(rgba[3] * 255.0f) << 24;
-
- /* UNORM16 */
- dw[7] = (uint16_t) util_iround(rgba[0] * 65535.0f) |
- (uint16_t) util_iround(rgba[1] * 65535.0f) << 16;
- dw[8] = (uint16_t) util_iround(rgba[2] * 65535.0f) |
- (uint16_t) util_iround(rgba[3] * 65535.0f) << 16;
-
- STATIC_ASSERT(ARRAY_SIZE(border->color) >= 12);
- memcpy(border->color, dw, sizeof(dw));
-
- return true;
-}
-
-static bool
-sampler_border_set_gen7_SAMPLER_BORDER_COLOR_STATE(struct ilo_state_sampler_border *border,
- const struct ilo_dev *dev,
- const struct ilo_state_sampler_border_info *info)
-{
- ILO_DEV_ASSERT(dev, 7, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 116:
- *
- * "In DX10/OGL mode, the format of the border color is
- * R32G32B32A32_FLOAT, regardless of the surface format chosen."
- *
- * From the Haswell PRM, volume 2d, page 240:
- *
- * "So, SW will have to program the table in SAMPLER_BORDER_COLOR_STATE
- * at offsets DWORD16 to 19, as per the integer surface format type."
- *
- * From the Broadwell PRM, volume 2d, page 297:
- *
- * "DX10/OGL mode: the format of the border color depends on the format
- * of the surface being sampled. If the map format is UINT, then the
- * border color format is R32G32B32A32_UINT. If the map format is
- * SINT, then the border color format is R32G32B32A32_SINT. Otherwise,
- * the border color format is R32G32B32A32_FLOAT."
- *
- * XXX every Gen is different
- */
-
- STATIC_ASSERT(ARRAY_SIZE(border->color) >= 4);
- memcpy(border->color, info->rgba.f, sizeof(info->rgba.f));
-
- return true;
-}
-
-bool
-ilo_state_sampler_init(struct ilo_state_sampler *sampler,
- const struct ilo_dev *dev,
- const struct ilo_state_sampler_info *info)
-{
- bool ret = true;
-
- assert(ilo_is_zeroed(sampler, sizeof(*sampler)));
-
- ret &= sampler_set_gen6_SAMPLER_STATE(sampler, dev, info);
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_sampler_init_disabled(struct ilo_state_sampler *sampler,
- const struct ilo_dev *dev)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(ilo_is_zeroed(sampler, sizeof(*sampler)));
-
- sampler->sampler[0] = GEN6_SAMPLER_DW0_DISABLE;
- sampler->sampler[1] = 0;
- sampler->sampler[2] = 0;
-
- return true;
-}
-
-/**
- * Modify \p sampler to work with \p surf. There will be loss of information.
- * Callers should make a copy of the orignal sampler first.
- */
-bool
-ilo_state_sampler_set_surface(struct ilo_state_sampler *sampler,
- const struct ilo_dev *dev,
- const struct ilo_state_surface *surf)
-{
- uint32_t addr_ctrl;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (sampler->non_normalized) {
- /* see sampler_validate_gen6_non_normalized() */
- assert(surf->type == GEN6_SURFTYPE_2D ||
- surf->type == GEN6_SURFTYPE_3D);
- assert(!surf->min_lod && !surf->mip_count);
- }
-
- if (sampler->base_to_surf_min_lod) {
- const uint8_t base = surf->min_lod << GEN6_SAMPLER_DW0_BASE_LOD__RADIX;
-
- sampler->sampler[0] =
- (sampler->sampler[0] & ~GEN6_SAMPLER_DW0_BASE_LOD__MASK) |
- base << GEN6_SAMPLER_DW0_BASE_LOD__SHIFT;
- }
-
- if (surf->is_integer || surf->type == GEN6_SURFTYPE_3D) {
- const uint32_t mask = (GEN6_SAMPLER_DW0_MIP_FILTER__MASK |
- GEN6_SAMPLER_DW0_MIN_FILTER__MASK |
- GEN6_SAMPLER_DW0_MAG_FILTER__MASK);
- const uint32_t filter = (surf->is_integer) ?
- sampler->filter_integer : sampler->filter_3d;
-
- assert((filter & mask) == filter);
- sampler->sampler[0] = (sampler->sampler[0] & ~mask) |
- filter;
- }
-
- switch (surf->type) {
- case GEN6_SURFTYPE_1D:
- addr_ctrl = sampler->addr_ctrl_1d;
- break;
- case GEN6_SURFTYPE_2D:
- case GEN6_SURFTYPE_3D:
- addr_ctrl = sampler->addr_ctrl_2d_3d;
- break;
- case GEN6_SURFTYPE_CUBE:
- addr_ctrl = sampler->addr_ctrl_cube;
- break;
- default:
- assert(!"unexpected surface type");
- addr_ctrl = 0;
- break;
- }
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- const uint32_t mask = (GEN7_SAMPLER_DW3_U_WRAP__MASK |
- GEN7_SAMPLER_DW3_V_WRAP__MASK |
- GEN7_SAMPLER_DW3_R_WRAP__MASK);
-
- assert((addr_ctrl & mask) == addr_ctrl);
- sampler->sampler[2] = (sampler->sampler[2] & ~mask) |
- addr_ctrl;
- } else {
- const uint32_t mask = (GEN6_SAMPLER_DW1_U_WRAP__MASK |
- GEN6_SAMPLER_DW1_V_WRAP__MASK |
- GEN6_SAMPLER_DW1_R_WRAP__MASK);
-
- assert((addr_ctrl & mask) == addr_ctrl);
- sampler->sampler[1] = (sampler->sampler[1] & ~mask) |
- addr_ctrl;
- }
-
- return true;
-}
-
-bool
-ilo_state_sampler_border_init(struct ilo_state_sampler_border *border,
- const struct ilo_dev *dev,
- const struct ilo_state_sampler_border_info *info)
-{
- bool ret = true;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- ret &= sampler_border_set_gen7_SAMPLER_BORDER_COLOR_STATE(border,
- dev, info);
- } else {
- ret &= sampler_border_set_gen6_SAMPLER_BORDER_COLOR_STATE(border,
- dev, info);
- }
-
- assert(ret);
-
- return ret;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_STATE_SAMPLER_H
-#define ILO_STATE_SAMPLER_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-
-struct ilo_state_surface;
-
-struct ilo_state_sampler_info {
- bool non_normalized;
-
- float lod_bias;
- float min_lod;
- float max_lod;
-
- enum gen_mip_filter mip_filter;
- enum gen_map_filter min_filter;
- enum gen_map_filter mag_filter;
- enum gen_aniso_ratio max_anisotropy;
-
- enum gen_texcoord_mode tcx_ctrl;
- enum gen_texcoord_mode tcy_ctrl;
- enum gen_texcoord_mode tcz_ctrl;
-
- enum gen_prefilter_op shadow_func;
-};
-
-struct ilo_state_sampler_border_info {
- union {
- float f[4];
- uint32_t ui[4];
- } rgba;
-
- bool is_integer;
-};
-
-struct ilo_state_sampler {
- uint32_t sampler[3];
-
- uint32_t filter_integer;
- uint32_t filter_3d;
-
- uint32_t addr_ctrl_1d;
- uint32_t addr_ctrl_2d_3d;
- uint32_t addr_ctrl_cube;
-
- bool non_normalized;
- bool base_to_surf_min_lod;
-};
-
-struct ilo_state_sampler_border {
- uint32_t color[12];
-};
-
-bool
-ilo_state_sampler_init(struct ilo_state_sampler *sampler,
- const struct ilo_dev *dev,
- const struct ilo_state_sampler_info *info);
-
-bool
-ilo_state_sampler_init_disabled(struct ilo_state_sampler *sampler,
- const struct ilo_dev *dev);
-
-bool
-ilo_state_sampler_set_surface(struct ilo_state_sampler *sampler,
- const struct ilo_dev *dev,
- const struct ilo_state_surface *surf);
-
-bool
-ilo_state_sampler_border_init(struct ilo_state_sampler_border *border,
- const struct ilo_dev *dev,
- const struct ilo_state_sampler_border_info *info);
-
-#endif /* ILO_STATE_SAMPLER_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-#include "ilo_state_sbe.h"
-
-static bool
-sbe_validate_gen8(const struct ilo_dev *dev,
- const struct ilo_state_sbe_info *info)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(info->attr_count <= ILO_STATE_SBE_MAX_ATTR_COUNT);
-
- assert(info->vue_read_base + info->vue_read_count <=
- info->cv_vue_attr_count);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 248:
- *
- * "(Vertex URB Entry Read Length)
- * Format: U5
- * Range [1,16]
- *
- * Specifies the amount of URB data read for each Vertex URB entry, in
- * 256-bit register increments.
- *
- * Programming Notes
- * It is UNDEFINED to set this field to 0 indicating no Vertex URB
- * data to be read."
- *
- * "(Vertex URB Entry Read Offset)
- * Format: U6
- * Range [0,63]
- *
- * Specifies the offset (in 256-bit units) at which Vertex URB data is
- * to be read from the URB."
- */
- assert(info->vue_read_base % 2 == 0 && info->vue_read_base <= 126);
- assert(info->vue_read_count <= 32);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 268:
- *
- * "This field (Point Sprite Texture Coordinate Enable) must be
- * programmed to 0 when non-point primitives are rendered."
- */
- if (ilo_dev_gen(dev) < ILO_GEN(7.5) && info->point_sprite_enables)
- assert(info->cv_is_point);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 246:
- *
- * "(Number of SF Output Attributes) 33-48: Specifies 17-32 attributes
- * (# attributes = field value - 16). Swizzling performed on
- * Attributes 16-31 (as required) only. Attributes 0-15 passed through
- * unmodified.
- *
- * Note :
- *
- * Attribute n Component Override and Constant Source states apply to
- * Attributes 16-31 (as required) instead of Attributes 0-15. E.g.,
- * this allows an Attribute 16-31 component to be overridden with the
- * PrimitiveID value.
- *
- * Attribute n WrapShortest Enables still apply to Attributes 0-15.
- *
- * Attribute n Swizzle Select and Attribute n Source Attribute states
- * are ignored and none of the swizzling functions available through
- * these controls are performed."
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 247:
- *
- * "This bit (Attribute Swizzle Enable) controls the use of the
- * Attribute n Swizzle Select and Attribute n Source Attribute fields
- * only. If ENABLED, those fields are used as described below. If
- * DISABLED, attributes are copied from their corresponding source
- * attributes, for the purposes of Swizzle Select only.
- *
- * Note that the following fields are unaffected by this bit, and are
- * therefore always used to control their respective fields:
- * Attribute n Component Override X/Y/Z/W
- * Attribute n Constant Source
- * Attribute n WrapShortest Enables"
- *
- * From the Ivy Bridge PRM, volume 2 part 1, page 264:
- *
- * "When Attribute Swizzle Enable is ENABLED, this bit (Attribute
- * Swizzle Control Mode) controls whether attributes 0-15 or 16-31 are
- * subject to the following swizzle controls:
- *
- * - Attribute n Component Override X/Y/Z/W
- * - Attribute n Constant Source
- * - Attribute n Swizzle Select
- * - Attribute n Source Attribute
- * - Attribute n Wrap Shortest Enables"
- *
- * "SWIZ_16_31... Only valid when 16 or more attributes are output."
- */
- assert(info->swizzle_count <= ILO_STATE_SBE_MAX_SWIZZLE_COUNT);
- if (info->swizzle_16_31) {
- assert(ilo_dev_gen(dev) >= ILO_GEN(7) &&
- info->swizzle_enable &&
- info->attr_count > 16);
- }
-
- return true;
-}
-
-static uint8_t
-sbe_get_gen8_min_read_count(const struct ilo_dev *dev,
- const struct ilo_state_sbe_info *info)
-{
- uint8_t min_count = 0;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* minimum read count for non-swizzled attributes */
- if (!info->swizzle_enable || info->swizzle_count < info->attr_count) {
- if (info->swizzle_16_31 && info->swizzle_count + 16 == info->attr_count)
- min_count = 16;
- else
- min_count = info->attr_count;
- }
-
- if (info->swizzle_enable) {
- uint8_t i;
-
- for (i = 0; i < info->swizzle_count; i++) {
- const struct ilo_state_sbe_swizzle_info *swizzle =
- &info->swizzles[i];
- bool inputattr_facing;
-
- switch (swizzle->attr_select) {
- case GEN6_INPUTATTR_FACING:
- case GEN6_INPUTATTR_FACING_W:
- inputattr_facing = true;
- break;
- default:
- inputattr_facing = false;
- break;
- }
-
- if (min_count < swizzle->attr + inputattr_facing + 1)
- min_count = swizzle->attr + inputattr_facing + 1;
- }
- }
-
- return min_count;
-}
-
-static uint8_t
-sbe_get_gen8_read_length(const struct ilo_dev *dev,
- const struct ilo_state_sbe_info *info)
-{
- uint8_t read_len;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 248:
- *
- * "(Vertex URB Entry Read Length)
- * This field should be set to the minimum length required to read the
- * maximum source attribute. The maximum source attribute is indicated
- * by the maximum value of the enabled Attribute # Source Attribute if
- * Attribute Swizzle Enable is set, Number of Output Attributes -1 if
- * enable is not set.
- * read_length = ceiling((max_source_attr+1)/2)
- *
- * [errata] Corruption/Hang possible if length programmed larger than
- * recommended"
- */
- if (info->has_min_read_count) {
- read_len = info->vue_read_count;
- assert(read_len == sbe_get_gen8_min_read_count(dev, info));
- } else {
- read_len = sbe_get_gen8_min_read_count(dev, info);
- assert(read_len <= info->vue_read_count);
- }
-
- /*
- * In pairs. URB entries are aligned to 1024-bits or 512-bits. There is
- * no need to worry about reading past entries.
- */
- read_len = (read_len + 1) / 2;
- if (!read_len)
- read_len = 1;
-
- return read_len;
-}
-
-static bool
-sbe_set_gen8_3DSTATE_SBE(struct ilo_state_sbe *sbe,
- const struct ilo_dev *dev,
- const struct ilo_state_sbe_info *info)
-{
- uint8_t vue_read_offset, vue_read_len;
- uint8_t attr_count;
- uint32_t dw1, dw2, dw3;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (!sbe_validate_gen8(dev, info))
- return false;
-
- vue_read_offset = info->vue_read_base / 2;
- vue_read_len = sbe_get_gen8_read_length(dev, info);
-
- attr_count = info->attr_count;
- if (ilo_dev_gen(dev) == ILO_GEN(6) && info->swizzle_16_31)
- attr_count += 16;
-
- dw1 = attr_count << GEN7_SBE_DW1_ATTR_COUNT__SHIFT |
- vue_read_len << GEN7_SBE_DW1_URB_READ_LEN__SHIFT;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- dw1 |= GEN8_SBE_DW1_FORCE_URB_READ_LEN |
- GEN8_SBE_DW1_FORCE_URB_READ_OFFSET |
- vue_read_offset << GEN8_SBE_DW1_URB_READ_OFFSET__SHIFT;
- } else {
- dw1 |= vue_read_offset << GEN7_SBE_DW1_URB_READ_OFFSET__SHIFT;
- }
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7) && info->swizzle_16_31)
- dw1 |= GEN7_SBE_DW1_ATTR_SWIZZLE_16_31;
-
- if (info->swizzle_enable)
- dw1 |= GEN7_SBE_DW1_ATTR_SWIZZLE_ENABLE;
-
- dw1 |= (info->point_sprite_origin_lower_left) ?
- GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD_LOWERLEFT :
- GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD_UPPERLEFT;
-
- dw2 = info->point_sprite_enables;
- dw3 = info->const_interp_enables;
-
- STATIC_ASSERT(ARRAY_SIZE(sbe->sbe) >= 3);
- sbe->sbe[0] = dw1;
- sbe->sbe[1] = dw2;
- sbe->sbe[2] = dw3;
-
- return true;
-}
-
-static bool
-sbe_set_gen8_3DSTATE_SBE_SWIZ(struct ilo_state_sbe *sbe,
- const struct ilo_dev *dev,
- const struct ilo_state_sbe_info *info)
-{
- uint16_t swiz[ILO_STATE_SBE_MAX_SWIZZLE_COUNT];
- uint8_t i;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- for (i = 0; i < info->swizzle_count; i++) {
- const struct ilo_state_sbe_swizzle_info *swizzle = &info->swizzles[i];
-
- /* U5 */
- assert(swizzle->attr < 32);
- swiz[i] = swizzle->attr_select << GEN8_SBE_SWIZ_SWIZZLE_SELECT__SHIFT |
- swizzle->attr << GEN8_SBE_SWIZ_SRC_ATTR__SHIFT;
-
- if (swizzle->force_zeros) {
- swiz[i] |= GEN8_SBE_SWIZ_CONST_OVERRIDE_W |
- GEN8_SBE_SWIZ_CONST_OVERRIDE_Z |
- GEN8_SBE_SWIZ_CONST_OVERRIDE_Y |
- GEN8_SBE_SWIZ_CONST_OVERRIDE_X |
- GEN8_SBE_SWIZ_CONST_0000;
- }
- }
-
- for (; i < ARRAY_SIZE(swiz); i++) {
- swiz[i] = GEN6_INPUTATTR_NORMAL << GEN8_SBE_SWIZ_SWIZZLE_SELECT__SHIFT |
- i << GEN8_SBE_SWIZ_SRC_ATTR__SHIFT;
- }
-
- STATIC_ASSERT(sizeof(sbe->swiz) == sizeof(swiz));
- memcpy(sbe->swiz, swiz, sizeof(swiz));
-
- return true;
-}
-
-bool
-ilo_state_sbe_init(struct ilo_state_sbe *sbe,
- const struct ilo_dev *dev,
- const struct ilo_state_sbe_info *info)
-{
- assert(ilo_is_zeroed(sbe, sizeof(*sbe)));
- return ilo_state_sbe_set_info(sbe, dev, info);
-}
-
-bool
-ilo_state_sbe_init_for_rectlist(struct ilo_state_sbe *sbe,
- const struct ilo_dev *dev,
- uint8_t read_base,
- uint8_t read_count)
-{
- struct ilo_state_sbe_info info;
-
- memset(&info, 0, sizeof(info));
- info.attr_count = read_count;
- info.cv_vue_attr_count = read_base + read_count;
- info.vue_read_base = read_base;
- info.vue_read_count = read_count;
- info.has_min_read_count = true;
-
- return ilo_state_sbe_set_info(sbe, dev, &info);
-}
-
-bool
-ilo_state_sbe_set_info(struct ilo_state_sbe *sbe,
- const struct ilo_dev *dev,
- const struct ilo_state_sbe_info *info)
-{
- bool ret = true;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- ret &= sbe_set_gen8_3DSTATE_SBE(sbe, dev, info);
- ret &= sbe_set_gen8_3DSTATE_SBE_SWIZ(sbe, dev, info);
-
- assert(ret);
-
- return true;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_STATE_SBE_H
-#define ILO_STATE_SBE_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-
-/*
- * From the Sandy Bridge PRM, volume 2 part 1, page 264:
- *
- * "Number of SF Output Attributes sets the number of attributes that will
- * be output from the SF stage, not including position. This can be used
- * to specify up to 32, and may differ from the number of input
- * attributes."
- *
- * "The first or last set of 16 attributes can be swizzled according to
- * certain state fields."
- */
-#define ILO_STATE_SBE_MAX_ATTR_COUNT 32
-#define ILO_STATE_SBE_MAX_SWIZZLE_COUNT 16
-
-struct ilo_state_sbe_swizzle_info {
- /* select an attribute from read ones */
- enum gen_inputattr_select attr_select;
- uint8_t attr;
-
- bool force_zeros;
-};
-
-struct ilo_state_sbe_info {
- uint8_t attr_count;
-
- /* which VUE attributes to read */
- uint8_t cv_vue_attr_count;
- uint8_t vue_read_base;
- uint8_t vue_read_count;
- bool has_min_read_count;
-
- bool cv_is_point;
- bool point_sprite_origin_lower_left;
- /* force sprite coordinates to the four corner vertices of the point */
- uint32_t point_sprite_enables;
-
- /* force attr at the provoking vertex to a0 and zero to a1/a2 */
- uint32_t const_interp_enables;
-
- bool swizzle_enable;
- /* swizzle attribute 16 to 31 instead; Gen7+ only */
- bool swizzle_16_31;
- uint8_t swizzle_count;
- const struct ilo_state_sbe_swizzle_info *swizzles;
-};
-
-struct ilo_state_sbe {
- uint32_t sbe[3];
- uint32_t swiz[8];
-};
-
-bool
-ilo_state_sbe_init(struct ilo_state_sbe *sbe,
- const struct ilo_dev *dev,
- const struct ilo_state_sbe_info *info);
-
-bool
-ilo_state_sbe_init_for_rectlist(struct ilo_state_sbe *sbe,
- const struct ilo_dev *dev,
- uint8_t read_base,
- uint8_t read_count);
-
-bool
-ilo_state_sbe_set_info(struct ilo_state_sbe *sbe,
- const struct ilo_dev *dev,
- const struct ilo_state_sbe_info *info);
-
-#endif /* ILO_STATE_SBE_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-#include "ilo_state_shader.h"
-
-enum vertex_stage {
- STAGE_VS,
- STAGE_HS,
- STAGE_DS,
- STAGE_GS,
-};
-
-struct vertex_ff {
- uint8_t grf_start;
-
- uint8_t per_thread_scratch_space;
- uint32_t per_thread_scratch_size;
-
- uint8_t sampler_count;
- uint8_t surface_count;
- bool has_uav;
-
- uint8_t vue_read_offset;
- uint8_t vue_read_len;
-
- uint8_t user_clip_enables;
-};
-
-static bool
-vertex_validate_gen6_kernel(const struct ilo_dev *dev,
- enum vertex_stage stage,
- const struct ilo_state_shader_kernel_info *kernel)
-{
- /*
- * "Dispatch GRF Start Register for URB Data" is U4 for GS and U5 for
- * others.
- */
- const uint8_t max_grf_start = (stage == STAGE_GS) ? 16 : 32;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* we do not want to save it */
- assert(!kernel->offset);
-
- assert(kernel->grf_start < max_grf_start);
-
- return true;
-}
-
-static bool
-vertex_validate_gen6_urb(const struct ilo_dev *dev,
- enum vertex_stage stage,
- const struct ilo_state_shader_urb_info *urb)
-{
- /* "Vertex/Patch URB Entry Read Offset" is U6, in pairs */
- const uint8_t max_read_base = 63 * 2;
- /*
- * "Vertex/Patch URB Entry Read Length" is limited to 64 for DS and U6 for
- * others, in pairs
- */
- const uint8_t max_read_count = ((stage == STAGE_DS) ? 64 : 63) * 2;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(urb->read_base + urb->read_count <= urb->cv_input_attr_count);
-
- assert(urb->read_base % 2 == 0 && urb->read_base <= max_read_base);
-
- /*
- * There is no need to worry about reading past entries, as URB entries are
- * aligned to 1024-bits (Gen6) or 512-bits (Gen7+).
- */
- assert(urb->read_count <= max_read_count);
-
- return true;
-}
-
-static bool
-vertex_get_gen6_ff(const struct ilo_dev *dev,
- enum vertex_stage stage,
- const struct ilo_state_shader_kernel_info *kernel,
- const struct ilo_state_shader_resource_info *resource,
- const struct ilo_state_shader_urb_info *urb,
- uint32_t per_thread_scratch_size,
- struct vertex_ff *ff)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- memset(ff, 0, sizeof(*ff));
-
- if (!vertex_validate_gen6_kernel(dev, stage, kernel) ||
- !vertex_validate_gen6_urb(dev, stage, urb))
- return false;
-
- ff->grf_start = kernel->grf_start;
-
- if (per_thread_scratch_size) {
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 134:
- *
- * "(Per-Thread Scratch Space)
- * Range [0,11] indicating [1K Bytes, 2M Bytes]"
- */
- assert(per_thread_scratch_size <= 2 * 1024 * 1024);
-
- /* next power of two, starting from 1KB */
- ff->per_thread_scratch_space = (per_thread_scratch_size > 1024) ?
- (util_last_bit(per_thread_scratch_size - 1) - 10) : 0;
- ff->per_thread_scratch_size = 1 << (10 + ff->per_thread_scratch_space);
- }
-
- ff->sampler_count = (resource->sampler_count <= 12) ?
- (resource->sampler_count + 3) / 4 : 4;
- ff->surface_count = resource->surface_count;
- ff->has_uav = resource->has_uav;
-
- ff->vue_read_offset = urb->read_base / 2;
- ff->vue_read_len = (urb->read_count + 1) / 2;
-
- /* need to read something unless VUE handles are included */
- switch (stage) {
- case STAGE_VS:
- if (!ff->vue_read_len)
- ff->vue_read_len = 1;
-
- /* one GRF per attribute */
- assert(kernel->grf_start + urb->read_count * 2 <= 128);
- break;
- case STAGE_GS:
- if (ilo_dev_gen(dev) == ILO_GEN(6) && !ff->vue_read_len)
- ff->vue_read_len = 1;
- break;
- default:
- break;
- }
-
- ff->user_clip_enables = urb->user_clip_enables;
-
- return true;
-}
-
-static uint16_t
-vs_get_gen6_thread_count(const struct ilo_dev *dev,
- const struct ilo_state_vs_info *info)
-{
- uint16_t thread_count;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* Maximum Number of Threads of 3DSTATE_VS */
- switch (ilo_dev_gen(dev)) {
- case ILO_GEN(8):
- thread_count = 504;
- break;
- case ILO_GEN(7.5):
- thread_count = (dev->gt >= 2) ? 280 : 70;
- break;
- case ILO_GEN(7):
- case ILO_GEN(6):
- default:
- thread_count = dev->thread_count;
- break;
- }
-
- return thread_count - 1;
-}
-
-static bool
-vs_set_gen6_3DSTATE_VS(struct ilo_state_vs *vs,
- const struct ilo_dev *dev,
- const struct ilo_state_vs_info *info)
-{
- struct vertex_ff ff;
- uint16_t thread_count;
- uint32_t dw2, dw3, dw4, dw5;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (!vertex_get_gen6_ff(dev, STAGE_VS, &info->kernel, &info->resource,
- &info->urb, info->per_thread_scratch_size, &ff))
- return false;
-
- thread_count = vs_get_gen6_thread_count(dev, info);
-
- dw2 = ff.sampler_count << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT |
- ff.surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT;
-
- if (false)
- dw2 |= GEN6_THREADDISP_FP_MODE_ALT;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5) && ff.has_uav)
- dw2 |= GEN75_THREADDISP_ACCESS_UAV;
-
- dw3 = ff.per_thread_scratch_space <<
- GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT;
-
- dw4 = ff.grf_start << GEN6_VS_DW4_URB_GRF_START__SHIFT |
- ff.vue_read_len << GEN6_VS_DW4_URB_READ_LEN__SHIFT |
- ff.vue_read_offset << GEN6_VS_DW4_URB_READ_OFFSET__SHIFT;
-
- dw5 = 0;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5))
- dw5 |= thread_count << GEN75_VS_DW5_MAX_THREADS__SHIFT;
- else
- dw5 |= thread_count << GEN6_VS_DW5_MAX_THREADS__SHIFT;
-
- if (info->stats_enable)
- dw5 |= GEN6_VS_DW5_STATISTICS;
- if (info->dispatch_enable)
- dw5 |= GEN6_VS_DW5_VS_ENABLE;
-
- STATIC_ASSERT(ARRAY_SIZE(vs->vs) >= 5);
- vs->vs[0] = dw2;
- vs->vs[1] = dw3;
- vs->vs[2] = dw4;
- vs->vs[3] = dw5;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- vs->vs[4] = ff.user_clip_enables << GEN8_VS_DW8_UCP_CLIP_ENABLES__SHIFT;
-
- vs->scratch_size = ff.per_thread_scratch_size * thread_count;
-
- return true;
-}
-
-static uint16_t
-hs_get_gen7_thread_count(const struct ilo_dev *dev,
- const struct ilo_state_hs_info *info)
-{
- uint16_t thread_count;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- /* Maximum Number of Threads of 3DSTATE_HS */
- switch (ilo_dev_gen(dev)) {
- case ILO_GEN(8):
- thread_count = 504;
- break;
- case ILO_GEN(7.5):
- thread_count = (dev->gt >= 2) ? 256 : 70;
- break;
- case ILO_GEN(7):
- default:
- thread_count = dev->thread_count;
- break;
- }
-
- return thread_count - 1;
-}
-
-static bool
-hs_set_gen7_3DSTATE_HS(struct ilo_state_hs *hs,
- const struct ilo_dev *dev,
- const struct ilo_state_hs_info *info)
-{
- struct vertex_ff ff;
- uint16_t thread_count;
- uint32_t dw1, dw2, dw4, dw5;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- if (!vertex_get_gen6_ff(dev, STAGE_HS, &info->kernel, &info->resource,
- &info->urb, info->per_thread_scratch_size, &ff))
- return false;
-
- thread_count = hs_get_gen7_thread_count(dev, info);
-
- dw1 = ff.sampler_count << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT |
- ff.surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT;
-
- dw2 = 0 << GEN7_HS_DW2_INSTANCE_COUNT__SHIFT;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- dw2 |= thread_count << GEN8_HS_DW2_MAX_THREADS__SHIFT;
- else if (ilo_dev_gen(dev) >= ILO_GEN(7.5))
- dw1 |= thread_count << GEN75_HS_DW1_DISPATCH_MAX_THREADS__SHIFT;
- else
- dw1 |= thread_count << GEN7_HS_DW1_DISPATCH_MAX_THREADS__SHIFT;
-
- if (info->dispatch_enable)
- dw2 |= GEN7_HS_DW2_HS_ENABLE;
- if (info->stats_enable)
- dw2 |= GEN7_HS_DW2_STATISTICS;
-
- dw4 = ff.per_thread_scratch_space <<
- GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT;
-
- dw5 = GEN7_HS_DW5_INCLUDE_VERTEX_HANDLES |
- ff.grf_start << GEN7_HS_DW5_URB_GRF_START__SHIFT |
- ff.vue_read_len << GEN7_HS_DW5_URB_READ_LEN__SHIFT |
- ff.vue_read_offset << GEN7_HS_DW5_URB_READ_OFFSET__SHIFT;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5) && ff.has_uav)
- dw5 |= GEN75_HS_DW5_ACCESS_UAV;
-
- STATIC_ASSERT(ARRAY_SIZE(hs->hs) >= 4);
- hs->hs[0] = dw1;
- hs->hs[1] = dw2;
- hs->hs[2] = dw4;
- hs->hs[3] = dw5;
-
- hs->scratch_size = ff.per_thread_scratch_size * thread_count;
-
- return true;
-}
-
-static bool
-ds_set_gen7_3DSTATE_TE(struct ilo_state_ds *ds,
- const struct ilo_dev *dev,
- const struct ilo_state_ds_info *info)
-{
- uint32_t dw1;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- dw1 = 0;
-
- if (info->dispatch_enable) {
- dw1 |= GEN7_TE_DW1_MODE_HW |
- GEN7_TE_DW1_TE_ENABLE;
- }
-
- STATIC_ASSERT(ARRAY_SIZE(ds->te) >= 3);
- ds->te[0] = dw1;
- ds->te[1] = fui(63.0f);
- ds->te[2] = fui(64.0f);
-
- return true;
-}
-
-static uint16_t
-ds_get_gen7_thread_count(const struct ilo_dev *dev,
- const struct ilo_state_ds_info *info)
-{
- uint16_t thread_count;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- /* Maximum Number of Threads of 3DSTATE_DS */
- switch (ilo_dev_gen(dev)) {
- case ILO_GEN(8):
- thread_count = 504;
- break;
- case ILO_GEN(7.5):
- thread_count = (dev->gt >= 2) ? 280 : 70;
- break;
- case ILO_GEN(7):
- default:
- thread_count = dev->thread_count;
- break;
- }
-
- return thread_count - 1;
-}
-
-static bool
-ds_set_gen7_3DSTATE_DS(struct ilo_state_ds *ds,
- const struct ilo_dev *dev,
- const struct ilo_state_ds_info *info)
-{
- struct vertex_ff ff;
- uint16_t thread_count;
- uint32_t dw2, dw3, dw4, dw5;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- if (!vertex_get_gen6_ff(dev, STAGE_DS, &info->kernel, &info->resource,
- &info->urb, info->per_thread_scratch_size, &ff))
- return false;
-
- thread_count = ds_get_gen7_thread_count(dev, info);
-
- dw2 = ff.sampler_count << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT |
- ff.surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5) && ff.has_uav)
- dw2 |= GEN75_THREADDISP_ACCESS_UAV;
-
- dw3 = ff.per_thread_scratch_space <<
- GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT;
-
- dw4 = ff.grf_start << GEN7_DS_DW4_URB_GRF_START__SHIFT |
- ff.vue_read_len << GEN7_DS_DW4_URB_READ_LEN__SHIFT |
- ff.vue_read_offset << GEN7_DS_DW4_URB_READ_OFFSET__SHIFT;
-
- dw5 = 0;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5))
- dw5 |= thread_count << GEN75_DS_DW5_MAX_THREADS__SHIFT;
- else
- dw5 |= thread_count << GEN7_DS_DW5_MAX_THREADS__SHIFT;
-
- if (info->stats_enable)
- dw5 |= GEN7_DS_DW5_STATISTICS;
- if (info->dispatch_enable)
- dw5 |= GEN7_DS_DW5_DS_ENABLE;
-
- STATIC_ASSERT(ARRAY_SIZE(ds->ds) >= 5);
- ds->ds[0] = dw2;
- ds->ds[1] = dw3;
- ds->ds[2] = dw4;
- ds->ds[3] = dw5;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- ds->ds[4] = ff.user_clip_enables << GEN8_DS_DW8_UCP_CLIP_ENABLES__SHIFT;
-
- ds->scratch_size = ff.per_thread_scratch_size * thread_count;
-
- return true;
-}
-
-static bool
-gs_get_gen6_ff(const struct ilo_dev *dev,
- const struct ilo_state_gs_info *info,
- struct vertex_ff *ff)
-{
- const struct ilo_state_shader_urb_info *urb = &info->urb;
- const struct ilo_state_gs_sol_info *sol = &info->sol;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (!vertex_get_gen6_ff(dev, STAGE_GS, &info->kernel, &info->resource,
- &info->urb, info->per_thread_scratch_size, ff))
- return false;
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 168-169:
- *
- * "[0,62] indicating [1,63] 16B units"
- *
- * "Programming Restrictions: The vertex size must be programmed as a
- * multiple of 32B units with the following exception: Rendering is
- * disabled (as per SOL stage state) and the vertex size output by the
- * GS thread is 16B.
- *
- * If rendering is enabled (as per SOL state) the vertex size must be
- * programmed as a multiple of 32B units. In other words, the only
- * time software can program a vertex size with an odd number of 16B
- * units is when rendering is disabled."
- */
- assert(urb->output_attr_count <= 63);
- if (!sol->render_disable)
- assert(urb->output_attr_count % 2 == 0);
-
- return true;
-}
-
-static uint16_t
-gs_get_gen6_thread_count(const struct ilo_dev *dev,
- const struct ilo_state_gs_info *info)
-{
- const struct ilo_state_gs_sol_info *sol = &info->sol;
- uint16_t thread_count;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* Maximum Number of Threads of 3DSTATE_GS */
- switch (ilo_dev_gen(dev)) {
- case ILO_GEN(8):
- thread_count = 504;
- break;
- case ILO_GEN(7.5):
- thread_count = (dev->gt >= 2) ? 256 : 70;
- break;
- case ILO_GEN(7):
- case ILO_GEN(6):
- default:
- thread_count = dev->thread_count;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 154:
- *
- * "Maximum Number of Threads valid range is [0,27] when Rendering
- * Enabled bit is set."
- *
- * According to the classic driver, [0, 20] for GT1.
- */
- if (!sol->render_disable)
- thread_count = (dev->gt == 2) ? 27 : 20;
- break;
- }
-
- return thread_count - 1;
-}
-
-static bool
-gs_set_gen6_3DSTATE_GS(struct ilo_state_gs *gs,
- const struct ilo_dev *dev,
- const struct ilo_state_gs_info *info)
-{
- const struct ilo_state_gs_sol_info *sol = &info->sol;
- struct vertex_ff ff;
- uint16_t thread_count;
- uint32_t dw2, dw3, dw4, dw5, dw6;
-
- ILO_DEV_ASSERT(dev, 6, 6);
-
- if (!gs_get_gen6_ff(dev, info, &ff))
- return false;
-
- thread_count = gs_get_gen6_thread_count(dev, info);
-
- dw2 = GEN6_THREADDISP_SPF |
- ff.sampler_count << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT |
- ff.surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT;
-
- dw3 = ff.per_thread_scratch_space <<
- GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT;
-
- dw4 = ff.vue_read_len << GEN6_GS_DW4_URB_READ_LEN__SHIFT |
- ff.vue_read_offset << GEN6_GS_DW4_URB_READ_OFFSET__SHIFT |
- ff.grf_start << GEN6_GS_DW4_URB_GRF_START__SHIFT;
-
- dw5 = thread_count << GEN6_GS_DW5_MAX_THREADS__SHIFT;
-
- if (info->stats_enable)
- dw5 |= GEN6_GS_DW5_STATISTICS;
- if (sol->stats_enable)
- dw5 |= GEN6_GS_DW5_SO_STATISTICS;
- if (!sol->render_disable)
- dw5 |= GEN6_GS_DW5_RENDER_ENABLE;
-
- dw6 = 0;
-
- /* GEN7_REORDER_TRAILING is handled by the kernel */
- if (sol->tristrip_reorder == GEN7_REORDER_LEADING)
- dw6 |= GEN6_GS_DW6_REORDER_LEADING_ENABLE;
-
- if (sol->sol_enable) {
- dw6 |= GEN6_GS_DW6_SVBI_PAYLOAD_ENABLE;
-
- if (sol->svbi_post_inc) {
- dw6 |= GEN6_GS_DW6_SVBI_POST_INC_ENABLE |
- sol->svbi_post_inc << GEN6_GS_DW6_SVBI_POST_INC_VAL__SHIFT;
- }
- }
-
- if (info->dispatch_enable)
- dw6 |= GEN6_GS_DW6_GS_ENABLE;
-
- STATIC_ASSERT(ARRAY_SIZE(gs->gs) >= 5);
- gs->gs[0] = dw2;
- gs->gs[1] = dw3;
- gs->gs[2] = dw4;
- gs->gs[3] = dw5;
- gs->gs[4] = dw6;
-
- gs->scratch_size = ff.per_thread_scratch_size * thread_count;
-
- return true;
-}
-
-static uint8_t
-gs_get_gen7_vertex_size(const struct ilo_dev *dev,
- const struct ilo_state_gs_info *info)
-{
- const struct ilo_state_shader_urb_info *urb = &info->urb;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- return (urb->output_attr_count) ? urb->output_attr_count - 1 : 0;
-}
-
-static bool
-gs_set_gen7_3DSTATE_GS(struct ilo_state_gs *gs,
- const struct ilo_dev *dev,
- const struct ilo_state_gs_info *info)
-{
- struct vertex_ff ff;
- uint16_t thread_count;
- uint8_t vertex_size;
- uint32_t dw2, dw3, dw4, dw5;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- if (!gs_get_gen6_ff(dev, info, &ff))
- return false;
-
- thread_count = gs_get_gen6_thread_count(dev, info);
- vertex_size = gs_get_gen7_vertex_size(dev, info);
-
- dw2 = ff.sampler_count << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT |
- ff.surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5) && ff.has_uav)
- dw2 |= GEN75_THREADDISP_ACCESS_UAV;
-
- dw3 = ff.per_thread_scratch_space <<
- GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT;
-
- dw4 = vertex_size << GEN7_GS_DW4_OUTPUT_SIZE__SHIFT |
- 0 << GEN7_GS_DW4_OUTPUT_TOPO__SHIFT |
- ff.vue_read_len << GEN7_GS_DW4_URB_READ_LEN__SHIFT |
- GEN7_GS_DW4_INCLUDE_VERTEX_HANDLES |
- ff.vue_read_offset << GEN7_GS_DW4_URB_READ_OFFSET__SHIFT |
- ff.grf_start << GEN7_GS_DW4_URB_GRF_START__SHIFT;
-
- dw5 = 0;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5))
- dw5 = thread_count << GEN75_GS_DW5_MAX_THREADS__SHIFT;
- else
- dw5 = thread_count << GEN7_GS_DW5_MAX_THREADS__SHIFT;
-
- if (info->stats_enable)
- dw5 |= GEN7_GS_DW5_STATISTICS;
- if (info->dispatch_enable)
- dw5 |= GEN7_GS_DW5_GS_ENABLE;
-
- STATIC_ASSERT(ARRAY_SIZE(gs->gs) >= 5);
- gs->gs[0] = dw2;
- gs->gs[1] = dw3;
- gs->gs[2] = dw4;
- gs->gs[3] = dw5;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- gs->gs[4] = ff.user_clip_enables << GEN8_GS_DW9_UCP_CLIP_ENABLES__SHIFT;
-
- gs->scratch_size = ff.per_thread_scratch_size * thread_count;
-
- return true;
-}
-
-bool
-ilo_state_vs_init(struct ilo_state_vs *vs,
- const struct ilo_dev *dev,
- const struct ilo_state_vs_info *info)
-{
- bool ret = true;
-
- assert(ilo_is_zeroed(vs, sizeof(*vs)));
-
- ret &= vs_set_gen6_3DSTATE_VS(vs, dev, info);
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_vs_init_disabled(struct ilo_state_vs *vs,
- const struct ilo_dev *dev)
-{
- struct ilo_state_vs_info info;
-
- memset(&info, 0, sizeof(info));
-
- return ilo_state_vs_init(vs, dev, &info);
-}
-
-bool
-ilo_state_hs_init(struct ilo_state_hs *hs,
- const struct ilo_dev *dev,
- const struct ilo_state_hs_info *info)
-{
- bool ret = true;
-
- assert(ilo_is_zeroed(hs, sizeof(*hs)));
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- ret &= hs_set_gen7_3DSTATE_HS(hs, dev, info);
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_hs_init_disabled(struct ilo_state_hs *hs,
- const struct ilo_dev *dev)
-{
- struct ilo_state_hs_info info;
-
- memset(&info, 0, sizeof(info));
-
- return ilo_state_hs_init(hs, dev, &info);
-}
-
-bool
-ilo_state_ds_init(struct ilo_state_ds *ds,
- const struct ilo_dev *dev,
- const struct ilo_state_ds_info *info)
-{
- bool ret = true;
-
- assert(ilo_is_zeroed(ds, sizeof(*ds)));
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- ret &= ds_set_gen7_3DSTATE_TE(ds, dev, info);
- ret &= ds_set_gen7_3DSTATE_DS(ds, dev, info);
- }
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_ds_init_disabled(struct ilo_state_ds *ds,
- const struct ilo_dev *dev)
-{
- struct ilo_state_ds_info info;
-
- memset(&info, 0, sizeof(info));
-
- return ilo_state_ds_init(ds, dev, &info);
-}
-
-bool
-ilo_state_gs_init(struct ilo_state_gs *gs,
- const struct ilo_dev *dev,
- const struct ilo_state_gs_info *info)
-{
- bool ret = true;
-
- assert(ilo_is_zeroed(gs, sizeof(*gs)));
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- ret &= gs_set_gen7_3DSTATE_GS(gs, dev, info);
- else
- ret &= gs_set_gen6_3DSTATE_GS(gs, dev, info);
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_gs_init_disabled(struct ilo_state_gs *gs,
- const struct ilo_dev *dev)
-{
- struct ilo_state_gs_info info;
-
- memset(&info, 0, sizeof(info));
-
- return ilo_state_gs_init(gs, dev, &info);
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_STATE_SHADER_H
-#define ILO_STATE_SHADER_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-
-/**
- * Kernel information.
- */
-struct ilo_state_shader_kernel_info {
- /* usually 0 unless the shader has multiple kernels */
- uint32_t offset;
-
- uint8_t grf_start;
- uint8_t pcb_attr_count;
-};
-
-/**
- * Shader resources.
- */
-struct ilo_state_shader_resource_info {
- /* for prefetches */
- uint8_t sampler_count;
- uint8_t surface_count;
-
- bool has_uav;
-};
-
-/**
- * URB inputs/outputs.
- */
-struct ilo_state_shader_urb_info {
- uint8_t cv_input_attr_count;
-
- uint8_t read_base;
- uint8_t read_count;
-
- uint8_t output_attr_count;
-
- uint8_t user_cull_enables;
- uint8_t user_clip_enables;
-};
-
-struct ilo_state_vs_info {
- struct ilo_state_shader_kernel_info kernel;
- struct ilo_state_shader_resource_info resource;
- struct ilo_state_shader_urb_info urb;
-
- uint32_t per_thread_scratch_size;
- bool dispatch_enable;
- bool stats_enable;
-};
-
-struct ilo_state_hs_info {
- struct ilo_state_shader_kernel_info kernel;
- struct ilo_state_shader_resource_info resource;
- struct ilo_state_shader_urb_info urb;
-
- uint32_t per_thread_scratch_size;
- bool dispatch_enable;
- bool stats_enable;
-};
-
-struct ilo_state_ds_info {
- struct ilo_state_shader_kernel_info kernel;
- struct ilo_state_shader_resource_info resource;
- struct ilo_state_shader_urb_info urb;
-
- uint32_t per_thread_scratch_size;
- bool dispatch_enable;
- bool stats_enable;
-};
-
-/**
- * Stream output. Must be consistent with ilo_state_sol_info.
- */
-struct ilo_state_gs_sol_info {
- bool sol_enable;
- bool stats_enable;
- bool render_disable;
-
- uint16_t svbi_post_inc;
-
- enum gen_reorder_mode tristrip_reorder;
-};
-
-struct ilo_state_gs_info {
- struct ilo_state_shader_kernel_info kernel;
- struct ilo_state_shader_resource_info resource;
- struct ilo_state_shader_urb_info urb;
-
- struct ilo_state_gs_sol_info sol;
-
- uint32_t per_thread_scratch_size;
- bool dispatch_enable;
- bool stats_enable;
-};
-
-struct ilo_state_ps_io_info {
- /* inputs */
- enum gen_position_offset posoffset;
- uint8_t attr_count;
- bool use_z;
- bool use_w;
- bool use_coverage_mask;
-
- /* outputs */
- enum gen_pscdepth_mode pscdepth;
- bool has_rt_write;
- bool write_pixel_mask;
- bool write_omask;
-};
-
-struct ilo_state_ps_params_info {
- /* compatibility with raster states */
- uint32_t sample_mask;
- bool earlyz_control_psexec;
-
- /* compatibility with cc states */
- bool alpha_may_kill;
- bool dual_source_blending;
- bool has_writeable_rt;
-};
-
-struct ilo_state_ps_info {
- struct ilo_state_shader_kernel_info kernel_8;
- struct ilo_state_shader_kernel_info kernel_16;
- struct ilo_state_shader_kernel_info kernel_32;
- struct ilo_state_shader_resource_info resource;
-
- struct ilo_state_ps_io_info io;
- struct ilo_state_ps_params_info params;
-
- uint32_t per_thread_scratch_size;
-
- /* bitmask of GEN6_PS_DISPATCH_x */
- uint8_t valid_kernels;
- bool per_sample_dispatch;
- bool sample_count_one;
- bool cv_per_sample_interp;
- bool cv_has_earlyz_op;
-
- bool rt_clear_enable;
- bool rt_resolve_enable;
-
- bool cv_has_depth_buffer;
-};
-
-struct ilo_state_vs {
- uint32_t vs[5];
- uint32_t scratch_size;
-};
-
-struct ilo_state_hs {
- uint32_t hs[4];
- uint32_t scratch_size;
-};
-
-struct ilo_state_ds {
- uint32_t te[3];
- uint32_t ds[5];
- uint32_t scratch_size;
-};
-
-struct ilo_state_gs {
- uint32_t gs[5];
- uint32_t scratch_size;
-};
-
-struct ilo_state_ps {
- uint32_t ps[8];
- uint32_t scratch_size;
-
- struct ilo_state_ps_dispatch_conds {
- bool ps_valid;
-
- bool has_rt_write;
- bool write_odepth;
- bool write_ostencil;
- bool has_uav_write;
- bool ps_may_kill;
- } conds;
-};
-
-bool
-ilo_state_vs_init(struct ilo_state_vs *vs,
- const struct ilo_dev *dev,
- const struct ilo_state_vs_info *info);
-
-bool
-ilo_state_vs_init_disabled(struct ilo_state_vs *vs,
- const struct ilo_dev *dev);
-
-static inline uint32_t
-ilo_state_vs_get_scratch_size(const struct ilo_state_vs *vs)
-{
- return vs->scratch_size;
-}
-
-bool
-ilo_state_hs_init(struct ilo_state_hs *hs,
- const struct ilo_dev *dev,
- const struct ilo_state_hs_info *info);
-
-bool
-ilo_state_hs_init_disabled(struct ilo_state_hs *hs,
- const struct ilo_dev *dev);
-
-
-static inline uint32_t
-ilo_state_hs_get_scratch_size(const struct ilo_state_hs *hs)
-{
- return hs->scratch_size;
-}
-
-bool
-ilo_state_ds_init(struct ilo_state_ds *ds,
- const struct ilo_dev *dev,
- const struct ilo_state_ds_info *info);
-
-bool
-ilo_state_ds_init_disabled(struct ilo_state_ds *ds,
- const struct ilo_dev *dev);
-
-static inline uint32_t
-ilo_state_ds_get_scratch_size(const struct ilo_state_ds *ds)
-{
- return ds->scratch_size;
-}
-
-bool
-ilo_state_gs_init(struct ilo_state_gs *gs,
- const struct ilo_dev *dev,
- const struct ilo_state_gs_info *info);
-
-bool
-ilo_state_gs_init_disabled(struct ilo_state_gs *gs,
- const struct ilo_dev *dev);
-
-static inline uint32_t
-ilo_state_gs_get_scratch_size(const struct ilo_state_gs *gs)
-{
- return gs->scratch_size;
-}
-
-bool
-ilo_state_ps_init(struct ilo_state_ps *ps,
- const struct ilo_dev *dev,
- const struct ilo_state_ps_info *info);
-
-bool
-ilo_state_ps_init_disabled(struct ilo_state_ps *ps,
- const struct ilo_dev *dev);
-
-bool
-ilo_state_ps_set_params(struct ilo_state_ps *ps,
- const struct ilo_dev *dev,
- const struct ilo_state_ps_params_info *params);
-
-static inline uint32_t
-ilo_state_ps_get_scratch_size(const struct ilo_state_ps *ps)
-{
- return ps->scratch_size;
-}
-
-#endif /* ILO_STATE_SHADER_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-#include "ilo_state_shader.h"
-
-struct pixel_ff {
- uint8_t dispatch_modes;
-
- uint32_t kernel_offsets[3];
- uint8_t grf_starts[3];
- bool pcb_enable;
- uint8_t per_thread_scratch_space;
- uint32_t per_thread_scratch_size;
-
- uint8_t sampler_count;
- uint8_t surface_count;
- bool has_uav;
-
- uint16_t thread_count;
-
- struct ilo_state_ps_dispatch_conds conds;
-
- bool kill_pixel;
- bool dispatch_enable;
- bool dual_source_blending;
- uint32_t sample_mask;
-};
-
-static bool
-ps_kernel_validate_gen6(const struct ilo_dev *dev,
- const struct ilo_state_shader_kernel_info *kernel)
-{
- /* "Dispatch GRF Start Register for Constant/Setup Data" is U7 */
- const uint8_t max_grf_start = 128;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* "Kernel Start Pointer" is 64-byte aligned */
- assert(kernel->offset % 64 == 0);
-
- assert(kernel->grf_start < max_grf_start);
-
- return true;
-}
-
-static bool
-ps_validate_gen6(const struct ilo_dev *dev,
- const struct ilo_state_ps_info *info)
-{
- const struct ilo_state_shader_kernel_info *kernel_8 = &info->kernel_8;
- const struct ilo_state_shader_kernel_info *kernel_16 = &info->kernel_16;
- const struct ilo_state_shader_kernel_info *kernel_32 = &info->kernel_32;
- const struct ilo_state_ps_io_info *io = &info->io;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (!ps_kernel_validate_gen6(dev, kernel_8) ||
- !ps_kernel_validate_gen6(dev, kernel_16) ||
- !ps_kernel_validate_gen6(dev, kernel_32))
- return false;
-
- /* unsupported on Gen6 */
- if (ilo_dev_gen(dev) == ILO_GEN(6))
- assert(!io->use_coverage_mask);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 275:
- *
- * "If a NULL Depth Buffer is selected, the Pixel Shader Computed Depth
- * field must be set to disabled."
- */
- if (ilo_dev_gen(dev) == ILO_GEN(6) && io->pscdepth != GEN7_PSCDEPTH_OFF)
- assert(info->cv_has_depth_buffer);
-
- if (!info->per_sample_dispatch) {
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 281:
- *
- * "MSDISPMODE_PERSAMPLE is required in order to select
- * POSOFFSET_SAMPLE."
- */
- assert(io->posoffset != GEN6_POSOFFSET_SAMPLE);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 282:
- *
- * "MSDISPMODE_PERSAMPLE is required in order to select
- * INTERP_SAMPLE."
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 283:
- *
- * "MSDISPMODE_PERSAMPLE is required in order to select Perspective
- * Sample or Non-perspective Sample barycentric coordinates."
- */
- assert(!info->cv_per_sample_interp);
- }
-
- /*
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 314:
- *
- * "Pixel Shader Dispatch, Alpha... must all be disabled."
- *
- * Simply disallow any valid kernel when there is early-z op. Also, when
- * there is no valid kernel, io should be zeroed.
- */
- if (info->valid_kernels)
- assert(!info->cv_has_earlyz_op);
- else
- assert(ilo_is_zeroed(io, sizeof(*io)));
-
- return true;
-}
-
-static uint8_t
-ps_get_gen6_dispatch_modes(const struct ilo_dev *dev,
- const struct ilo_state_ps_info *info)
-{
- const struct ilo_state_ps_io_info *io = &info->io;
- uint8_t dispatch_modes = info->valid_kernels;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (!dispatch_modes)
- return 0;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 334:
- *
- * "Not valid on [DevSNB] if 4x PERPIXEL mode with pixel shader
- * computed depth."
- *
- * "Valid on all products, except when in non-1x PERSAMPLE mode
- * (applies to [DevSNB+] only)"
- *
- * From the Sandy Bridge PRM, volume 4 part 1, page 239:
- *
- * "[DevSNB]: When Pixel Shader outputs oDepth and PS invocation mode
- * is PERPIXEL, Message Type for Render Target Write must be SIMD8.
- *
- * Errata: [DevSNB+]: When Pixel Shader outputs oMask, this message
- * type is not supported: SIMD8 (including SIMD8_DUALSRC_xx)."
- *
- * It is really hard to follow what combinations are valid on what
- * platforms. Judging from the restrictions on RT write messages on Gen6,
- * oDepth and oMask related issues should be Gen6-specific. PERSAMPLE
- * issue should be universal, and disallows multiple dispatch modes.
- */
- if (ilo_dev_gen(dev) == ILO_GEN(6)) {
- if (io->pscdepth != GEN7_PSCDEPTH_OFF && !info->per_sample_dispatch)
- dispatch_modes &= GEN6_PS_DISPATCH_8;
- if (io->write_omask)
- dispatch_modes &= ~GEN6_PS_DISPATCH_8;
- }
- if (info->per_sample_dispatch && !info->sample_count_one) {
- /* prefer 32 over 16 over 8 */
- if (dispatch_modes & GEN6_PS_DISPATCH_32)
- dispatch_modes &= GEN6_PS_DISPATCH_32;
- else if (dispatch_modes & GEN6_PS_DISPATCH_16)
- dispatch_modes &= GEN6_PS_DISPATCH_16;
- else
- dispatch_modes &= GEN6_PS_DISPATCH_8;
- }
-
- /*
- * From the Broadwell PRM, volume 2b, page 149:
- *
- * "When Render Target Fast Clear Enable is ENABLED or Render Target
- * Resolve Type = RESOLVE_PARTIAL or RESOLVE_FULL, this bit (8 Pixel
- * Dispatch or Dual-8 Pixel Dispatch Enable) must be DISABLED."
- */
- if (info->rt_clear_enable || info->rt_resolve_enable)
- dispatch_modes &= ~GEN6_PS_DISPATCH_8;
-
- assert(dispatch_modes);
-
- return dispatch_modes;
-}
-
-static uint16_t
-ps_get_gen6_thread_count(const struct ilo_dev *dev,
- const struct ilo_state_ps_info *info)
-{
- uint16_t thread_count;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* Maximum Number of Threads of 3DSTATE_PS */
- switch (ilo_dev_gen(dev)) {
- case ILO_GEN(8):
- /* scaled automatically */
- thread_count = 64 - 1;
- break;
- case ILO_GEN(7.5):
- thread_count = (dev->gt == 3) ? 408 :
- (dev->gt == 2) ? 204 : 102;
- break;
- case ILO_GEN(7):
- thread_count = (dev->gt == 2) ? 172 : 48;
- break;
- case ILO_GEN(6):
- default:
- /* from the classic driver instead of the PRM */
- thread_count = (dev->gt == 2) ? 80 : 40;
- break;
- }
-
- return thread_count - 1;
-}
-
-static bool
-ps_params_get_gen6_kill_pixel(const struct ilo_dev *dev,
- const struct ilo_state_ps_params_info *params,
- const struct ilo_state_ps_dispatch_conds *conds)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 275:
- *
- * "This bit (Pixel Shader Kill Pixel), if ENABLED, indicates that the
- * PS kernel or color calculator has the ability to kill (discard)
- * pixels or samples, other than due to depth or stencil testing.
- * This bit is required to be ENABLED in the following situations:
- *
- * The API pixel shader program contains "killpix" or "discard"
- * instructions, or other code in the pixel shader kernel that can
- * cause the final pixel mask to differ from the pixel mask received
- * on dispatch.
- *
- * A sampler with chroma key enabled with kill pixel mode is used by
- * the pixel shader.
- *
- * Any render target has Alpha Test Enable or AlphaToCoverage Enable
- * enabled.
- *
- * The pixel shader kernel generates and outputs oMask.
- *
- * Note: As ClipDistance clipping is fully supported in hardware and
- * therefore not via PS instructions, there should be no need to
- * ENABLE this bit due to ClipDistance clipping."
- */
- return (conds->ps_may_kill || params->alpha_may_kill);
-}
-
-static bool
-ps_params_get_gen6_dispatch_enable(const struct ilo_dev *dev,
- const struct ilo_state_ps_params_info *params,
- const struct ilo_state_ps_dispatch_conds *conds)
-{
- /*
- * We want to skip dispatching when EarlyZ suffices. The conditions that
- * require dispatching are
- *
- * - PS writes RTs and RTs are writeable
- * - PS changes depth value and depth test/write is enabled
- * - PS changes stencil value and stencil test is enabled
- * - PS writes UAVs
- * - PS or CC kills pixels
- * - EDSC is PSEXEC, and depth test/write or stencil test is enabled
- */
- bool dispatch_required =
- ((conds->has_rt_write && params->has_writeable_rt) ||
- conds->write_odepth ||
- conds->write_ostencil ||
- conds->has_uav_write ||
- ps_params_get_gen6_kill_pixel(dev, params, conds) ||
- params->earlyz_control_psexec);
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 280:
- *
- * "If EDSC_PSEXEC mode is selected, Thread Dispatch Enable must be
- * set."
- */
- if (ilo_dev_gen(dev) < ILO_GEN(8) && params->earlyz_control_psexec)
- dispatch_required = true;
-
- /* assert it is valid to dispatch */
- if (dispatch_required)
- assert(conds->ps_valid);
-
- return dispatch_required;
-}
-
-static bool
-ps_get_gen6_ff_kernels(const struct ilo_dev *dev,
- const struct ilo_state_ps_info *info,
- struct pixel_ff *ff)
-{
- const struct ilo_state_shader_kernel_info *kernel_8 = &info->kernel_8;
- const struct ilo_state_shader_kernel_info *kernel_16 = &info->kernel_16;
- const struct ilo_state_shader_kernel_info *kernel_32 = &info->kernel_32;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- ff->dispatch_modes = ps_get_gen6_dispatch_modes(dev, info);
-
- /* initialize kernel offsets and GRF starts */
- if (util_is_power_of_two(ff->dispatch_modes)) {
- if (ff->dispatch_modes & GEN6_PS_DISPATCH_8) {
- ff->kernel_offsets[0] = kernel_8->offset;
- ff->grf_starts[0] = kernel_8->grf_start;
- } else if (ff->dispatch_modes & GEN6_PS_DISPATCH_16) {
- ff->kernel_offsets[0] = kernel_16->offset;
- ff->grf_starts[0] = kernel_16->grf_start;
- } else if (ff->dispatch_modes & GEN6_PS_DISPATCH_32) {
- ff->kernel_offsets[0] = kernel_32->offset;
- ff->grf_starts[0] = kernel_32->grf_start;
- }
- } else {
- ff->kernel_offsets[0] = kernel_8->offset;
- ff->kernel_offsets[1] = kernel_32->offset;
- ff->kernel_offsets[2] = kernel_16->offset;
-
- ff->grf_starts[0] = kernel_8->grf_start;
- ff->grf_starts[1] = kernel_32->grf_start;
- ff->grf_starts[2] = kernel_16->grf_start;
- }
-
- /* we do not want to save it */
- assert(ff->kernel_offsets[0] == 0);
-
- ff->pcb_enable = (((ff->dispatch_modes & GEN6_PS_DISPATCH_8) &&
- kernel_8->pcb_attr_count) ||
- ((ff->dispatch_modes & GEN6_PS_DISPATCH_16) &&
- kernel_16->pcb_attr_count) ||
- ((ff->dispatch_modes & GEN6_PS_DISPATCH_32) &&
- kernel_32->pcb_attr_count));
-
- /* GPU hangs on Haswell if none of the dispatch mode bits is set */
- if (ilo_dev_gen(dev) == ILO_GEN(7.5) && !ff->dispatch_modes)
- ff->dispatch_modes |= GEN6_PS_DISPATCH_8;
-
- return true;
-}
-
-static bool
-ps_get_gen6_ff(const struct ilo_dev *dev,
- const struct ilo_state_ps_info *info,
- struct pixel_ff *ff)
-{
- const struct ilo_state_shader_resource_info *resource = &info->resource;
- const struct ilo_state_ps_io_info *io = &info->io;
- const struct ilo_state_ps_params_info *params = &info->params;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- memset(ff, 0, sizeof(*ff));
-
- if (!ps_validate_gen6(dev, info) || !ps_get_gen6_ff_kernels(dev, info, ff))
- return false;
-
- if (info->per_thread_scratch_size) {
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 271:
- *
- * "(Per-Thread Scratch Space)
- * Range [0,11] indicating [1k bytes, 2M bytes] in powers of two"
- */
- assert(info->per_thread_scratch_size <= 2 * 1024 * 1024);
-
- /* next power of two, starting from 1KB */
- ff->per_thread_scratch_space = (info->per_thread_scratch_size > 1024) ?
- (util_last_bit(info->per_thread_scratch_size - 1) - 10) : 0;
- ff->per_thread_scratch_size = 1 << (10 + ff->per_thread_scratch_space);
- }
-
- ff->sampler_count = (resource->sampler_count <= 12) ?
- (resource->sampler_count + 3) / 4 : 4;
- ff->surface_count = resource->surface_count;
- ff->has_uav = resource->has_uav;
-
- ff->thread_count = ps_get_gen6_thread_count(dev, info);
-
- ff->conds.ps_valid = (info->valid_kernels != 0x0);
- ff->conds.has_rt_write = io->has_rt_write;
- ff->conds.write_odepth = (io->pscdepth != GEN7_PSCDEPTH_OFF);
- ff->conds.write_ostencil = false;
- ff->conds.has_uav_write = resource->has_uav;
- ff->conds.ps_may_kill = (io->write_pixel_mask || io->write_omask);
-
- ff->kill_pixel = ps_params_get_gen6_kill_pixel(dev, params, &ff->conds);
- ff->dispatch_enable =
- ps_params_get_gen6_dispatch_enable(dev, params, &ff->conds);
- ff->dual_source_blending = params->dual_source_blending;
- ff->sample_mask = params->sample_mask;
-
- return true;
-}
-
-static bool
-ps_set_gen6_3dstate_wm(struct ilo_state_ps *ps,
- const struct ilo_dev *dev,
- const struct ilo_state_ps_info *info,
- const struct pixel_ff *ff)
-{
- const struct ilo_state_ps_io_info *io = &info->io;
- uint32_t dw2, dw3, dw4, dw5, dw6;
-
- ILO_DEV_ASSERT(dev, 6, 6);
-
- dw2 = ff->sampler_count << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT |
- ff->surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT;
-
- if (false)
- dw2 |= GEN6_THREADDISP_FP_MODE_ALT;
-
- dw3 = ff->per_thread_scratch_space <<
- GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT;
-
- dw4 = ff->grf_starts[0] << GEN6_WM_DW4_URB_GRF_START0__SHIFT |
- ff->grf_starts[1] << GEN6_WM_DW4_URB_GRF_START1__SHIFT |
- ff->grf_starts[2] << GEN6_WM_DW4_URB_GRF_START2__SHIFT;
-
- dw5 = ff->thread_count << GEN6_WM_DW5_MAX_THREADS__SHIFT |
- ff->dispatch_modes << GEN6_WM_DW5_PS_DISPATCH_MODE__SHIFT;
-
- if (ff->kill_pixel)
- dw5 |= GEN6_WM_DW5_PS_KILL_PIXEL;
-
- if (io->pscdepth != GEN7_PSCDEPTH_OFF)
- dw5 |= GEN6_WM_DW5_PS_COMPUTE_DEPTH;
- if (io->use_z)
- dw5 |= GEN6_WM_DW5_PS_USE_DEPTH;
-
- if (ff->dispatch_enable)
- dw5 |= GEN6_WM_DW5_PS_DISPATCH_ENABLE;
-
- if (io->write_omask)
- dw5 |= GEN6_WM_DW5_PS_COMPUTE_OMASK;
- if (io->use_w)
- dw5 |= GEN6_WM_DW5_PS_USE_W;
-
- if (ff->dual_source_blending)
- dw5 |= GEN6_WM_DW5_PS_DUAL_SOURCE_BLEND;
-
- dw6 = io->attr_count << GEN6_WM_DW6_SF_ATTR_COUNT__SHIFT |
- io->posoffset << GEN6_WM_DW6_PS_POSOFFSET__SHIFT;
-
- dw6 |= (info->per_sample_dispatch) ?
- GEN6_WM_DW6_MSDISPMODE_PERSAMPLE : GEN6_WM_DW6_MSDISPMODE_PERPIXEL;
-
- STATIC_ASSERT(ARRAY_SIZE(ps->ps) >= 7);
- ps->ps[0] = dw2;
- ps->ps[1] = dw3;
- ps->ps[2] = dw4;
- ps->ps[3] = dw5;
- ps->ps[4] = dw6;
- ps->ps[5] = ff->kernel_offsets[1];
- ps->ps[6] = ff->kernel_offsets[2];
-
- return true;
-}
-
-static bool
-ps_set_gen7_3dstate_wm(struct ilo_state_ps *ps,
- const struct ilo_dev *dev,
- const struct ilo_state_ps_info *info,
- const struct pixel_ff *ff)
-{
- const struct ilo_state_ps_io_info *io = &info->io;
- uint32_t dw1, dw2;
-
- ILO_DEV_ASSERT(dev, 7, 7.5);
-
- dw1 = io->pscdepth << GEN7_WM_DW1_PSCDEPTH__SHIFT;
-
- if (ff->dispatch_enable)
- dw1 |= GEN7_WM_DW1_PS_DISPATCH_ENABLE;
- if (ff->kill_pixel)
- dw1 |= GEN7_WM_DW1_PS_KILL_PIXEL;
-
- if (io->use_z)
- dw1 |= GEN7_WM_DW1_PS_USE_DEPTH;
- if (io->use_w)
- dw1 |= GEN7_WM_DW1_PS_USE_W;
- if (io->use_coverage_mask)
- dw1 |= GEN7_WM_DW1_PS_USE_COVERAGE_MASK;
-
- dw2 = (info->per_sample_dispatch) ?
- GEN7_WM_DW2_MSDISPMODE_PERSAMPLE : GEN7_WM_DW2_MSDISPMODE_PERPIXEL;
-
- STATIC_ASSERT(ARRAY_SIZE(ps->ps) >= 2);
- ps->ps[0] = dw1;
- ps->ps[1] = dw2;
-
- return true;
-}
-
-static bool
-ps_set_gen7_3DSTATE_PS(struct ilo_state_ps *ps,
- const struct ilo_dev *dev,
- const struct ilo_state_ps_info *info,
- const struct pixel_ff *ff)
-{
- const struct ilo_state_ps_io_info *io = &info->io;
- uint32_t dw2, dw3, dw4, dw5;
-
- ILO_DEV_ASSERT(dev, 7, 7.5);
-
- dw2 = ff->sampler_count << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT |
- ff->surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT;
-
- if (false)
- dw2 |= GEN6_THREADDISP_FP_MODE_ALT;
-
- dw3 = ff->per_thread_scratch_space <<
- GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT;
-
- dw4 = io->posoffset << GEN7_PS_DW4_POSOFFSET__SHIFT |
- ff->dispatch_modes << GEN7_PS_DW4_DISPATCH_MODE__SHIFT;
-
- if (ilo_dev_gen(dev) == ILO_GEN(7.5)) {
- dw4 |= ff->thread_count << GEN75_PS_DW4_MAX_THREADS__SHIFT |
- (ff->sample_mask & 0xff) << GEN75_PS_DW4_SAMPLE_MASK__SHIFT;
- } else {
- dw4 |= ff->thread_count << GEN7_PS_DW4_MAX_THREADS__SHIFT;
- }
-
- if (ff->pcb_enable)
- dw4 |= GEN7_PS_DW4_PUSH_CONSTANT_ENABLE;
- if (io->attr_count)
- dw4 |= GEN7_PS_DW4_ATTR_ENABLE;
- if (io->write_omask)
- dw4 |= GEN7_PS_DW4_COMPUTE_OMASK;
- if (info->rt_clear_enable)
- dw4 |= GEN7_PS_DW4_RT_FAST_CLEAR;
- if (ff->dual_source_blending)
- dw4 |= GEN7_PS_DW4_DUAL_SOURCE_BLEND;
- if (info->rt_resolve_enable)
- dw4 |= GEN7_PS_DW4_RT_RESOLVE;
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5) && ff->has_uav)
- dw4 |= GEN75_PS_DW4_ACCESS_UAV;
-
- dw5 = ff->grf_starts[0] << GEN7_PS_DW5_URB_GRF_START0__SHIFT |
- ff->grf_starts[1] << GEN7_PS_DW5_URB_GRF_START1__SHIFT |
- ff->grf_starts[2] << GEN7_PS_DW5_URB_GRF_START2__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(ps->ps) >= 8);
- ps->ps[2] = dw2;
- ps->ps[3] = dw3;
- ps->ps[4] = dw4;
- ps->ps[5] = dw5;
- ps->ps[6] = ff->kernel_offsets[1];
- ps->ps[7] = ff->kernel_offsets[2];
-
- return true;
-}
-
-static bool
-ps_set_gen8_3DSTATE_PS(struct ilo_state_ps *ps,
- const struct ilo_dev *dev,
- const struct ilo_state_ps_info *info,
- const struct pixel_ff *ff)
-{
- const struct ilo_state_ps_io_info *io = &info->io;
- uint32_t dw3, dw4, dw6, dw7;
-
- ILO_DEV_ASSERT(dev, 8, 8);
-
- /*
- * Set VME here for correct computation of LODs and others. Not sure why
- * it is needed now.
- */
- dw3 = GEN6_THREADDISP_VME |
- ff->sampler_count << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT |
- ff->surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT;
-
- if (false)
- dw3 |= GEN6_THREADDISP_FP_MODE_ALT;
-
- dw4 = ff->per_thread_scratch_space <<
- GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT;
-
- dw6 = ff->thread_count << GEN8_PS_DW6_MAX_THREADS__SHIFT |
- io->posoffset << GEN8_PS_DW6_POSOFFSET__SHIFT |
- ff->dispatch_modes << GEN8_PS_DW6_DISPATCH_MODE__SHIFT;
-
- if (ff->pcb_enable)
- dw6 |= GEN8_PS_DW6_PUSH_CONSTANT_ENABLE;
-
- if (info->rt_clear_enable)
- dw6 |= GEN8_PS_DW6_RT_FAST_CLEAR;
- if (info->rt_resolve_enable)
- dw6 |= GEN8_PS_DW6_RT_RESOLVE;
-
- dw7 = ff->grf_starts[0] << GEN8_PS_DW7_URB_GRF_START0__SHIFT |
- ff->grf_starts[1] << GEN8_PS_DW7_URB_GRF_START1__SHIFT |
- ff->grf_starts[2] << GEN8_PS_DW7_URB_GRF_START2__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(ps->ps) >= 6);
- ps->ps[0] = dw3;
- ps->ps[1] = dw4;
- ps->ps[2] = dw6;
- ps->ps[3] = dw7;
- ps->ps[4] = ff->kernel_offsets[1];
- ps->ps[5] = ff->kernel_offsets[2];
-
- return true;
-}
-
-static bool
-ps_set_gen8_3DSTATE_PS_EXTRA(struct ilo_state_ps *ps,
- const struct ilo_dev *dev,
- const struct ilo_state_ps_info *info,
- const struct pixel_ff *ff)
-{
- const struct ilo_state_ps_io_info *io = &info->io;
- uint32_t dw1;
-
- ILO_DEV_ASSERT(dev, 8, 8);
-
- dw1 = io->pscdepth << GEN8_PSX_DW1_PSCDEPTH__SHIFT;
-
- if (info->valid_kernels)
- dw1 |= GEN8_PSX_DW1_VALID;
- if (!io->has_rt_write)
- dw1 |= GEN8_PSX_DW1_UAV_ONLY;
- if (io->write_omask)
- dw1 |= GEN8_PSX_DW1_COMPUTE_OMASK;
- if (io->write_pixel_mask)
- dw1 |= GEN8_PSX_DW1_KILL_PIXEL;
-
- if (io->use_z)
- dw1 |= GEN8_PSX_DW1_USE_DEPTH;
- if (io->use_w)
- dw1 |= GEN8_PSX_DW1_USE_W;
- if (io->attr_count)
- dw1 |= GEN8_PSX_DW1_ATTR_ENABLE;
-
- if (info->per_sample_dispatch)
- dw1 |= GEN8_PSX_DW1_PER_SAMPLE;
- if (ff->has_uav)
- dw1 |= GEN8_PSX_DW1_ACCESS_UAV;
- if (io->use_coverage_mask)
- dw1 |= GEN8_PSX_DW1_USE_COVERAGE_MASK;
-
- /*
- * From the Broadwell PRM, volume 2b, page 151:
- *
- * "When this bit (Pixel Shader Valid) clear the rest of this command
- * should also be clear.
- */
- if (!info->valid_kernels)
- dw1 = 0;
-
- STATIC_ASSERT(ARRAY_SIZE(ps->ps) >= 5);
- ps->ps[4] = dw1;
-
- return true;
-}
-
-bool
-ilo_state_ps_init(struct ilo_state_ps *ps,
- const struct ilo_dev *dev,
- const struct ilo_state_ps_info *info)
-{
- struct pixel_ff ff;
- bool ret = true;
-
- assert(ilo_is_zeroed(ps, sizeof(*ps)));
-
- ret &= ps_get_gen6_ff(dev, info, &ff);
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- ret &= ps_set_gen8_3DSTATE_PS(ps, dev, info, &ff);
- ret &= ps_set_gen8_3DSTATE_PS_EXTRA(ps, dev, info, &ff);
- } else if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- ret &= ps_set_gen7_3dstate_wm(ps, dev, info, &ff);
- ret &= ps_set_gen7_3DSTATE_PS(ps, dev, info, &ff);
- } else {
- ret &= ps_set_gen6_3dstate_wm(ps, dev, info, &ff);
- }
-
- ps->scratch_size = ff.per_thread_scratch_size * ff.thread_count;
- /* save conditions */
- ps->conds = ff.conds;
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_ps_init_disabled(struct ilo_state_ps *ps,
- const struct ilo_dev *dev)
-{
- struct ilo_state_ps_info info;
-
- memset(&info, 0, sizeof(info));
-
- return ilo_state_ps_init(ps, dev, &info);
-}
-
-bool
-ilo_state_ps_set_params(struct ilo_state_ps *ps,
- const struct ilo_dev *dev,
- const struct ilo_state_ps_params_info *params)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* modify sample mask */
- if (ilo_dev_gen(dev) == ILO_GEN(7.5)) {
- ps->ps[4] = (ps->ps[4] & ~GEN75_PS_DW4_SAMPLE_MASK__MASK) |
- (params->sample_mask & 0xff) << GEN75_PS_DW4_SAMPLE_MASK__SHIFT;
- }
-
- /* modify dispatch enable, pixel kill, and dual source blending */
- if (ilo_dev_gen(dev) < ILO_GEN(8)) {
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- if (ps_params_get_gen6_dispatch_enable(dev, params, &ps->conds))
- ps->ps[0] |= GEN7_WM_DW1_PS_DISPATCH_ENABLE;
- else
- ps->ps[0] &= ~GEN7_WM_DW1_PS_DISPATCH_ENABLE;
-
- if (ps_params_get_gen6_kill_pixel(dev, params, &ps->conds))
- ps->ps[0] |= GEN7_WM_DW1_PS_KILL_PIXEL;
- else
- ps->ps[0] &= ~GEN7_WM_DW1_PS_KILL_PIXEL;
-
- if (params->dual_source_blending)
- ps->ps[4] |= GEN7_PS_DW4_DUAL_SOURCE_BLEND;
- else
- ps->ps[4] &= ~GEN7_PS_DW4_DUAL_SOURCE_BLEND;
- } else {
- if (ps_params_get_gen6_dispatch_enable(dev, params, &ps->conds))
- ps->ps[3] |= GEN6_WM_DW5_PS_DISPATCH_ENABLE;
- else
- ps->ps[3] &= ~GEN6_WM_DW5_PS_DISPATCH_ENABLE;
-
- if (ps_params_get_gen6_kill_pixel(dev, params, &ps->conds))
- ps->ps[3] |= GEN6_WM_DW5_PS_KILL_PIXEL;
- else
- ps->ps[3] &= ~GEN6_WM_DW5_PS_KILL_PIXEL;
-
- if (params->dual_source_blending)
- ps->ps[3] |= GEN6_WM_DW5_PS_DUAL_SOURCE_BLEND;
- else
- ps->ps[3] &= ~GEN6_WM_DW5_PS_DUAL_SOURCE_BLEND;
- }
- }
-
- return true;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-#include "ilo_vma.h"
-#include "ilo_state_sol.h"
-
-static bool
-sol_stream_validate_gen7(const struct ilo_dev *dev,
- const struct ilo_state_sol_stream_info *stream)
-{
- uint8_t i;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- assert(stream->vue_read_base + stream->vue_read_count <=
- stream->cv_vue_attr_count);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 200:
- *
- * "(Stream 0 Vertex Read Offset)
- * Format: U1 count of 256-bit units
- *
- * Specifies amount of data to skip over before reading back Stream 0
- * vertex data. Must be zero if the GS is enabled and the Output
- * Vertex Size field in 3DSTATE_GS is programmed to 0 (i.e., one 16B
- * unit)."
- *
- * "(Stream 0 Vertex Read Length)
- * Format: U5-1 count of 256-bit units
- *
- * Specifies amount of vertex data to read back for Stream 0 vertices,
- * starting at the Stream 0 Vertex Read Offset location. Maximum
- * readback is 17 256-bit units (34 128-bit vertex attributes). Read
- * data past the end of the valid vertex data has undefined contents,
- * and therefore shouldn't be used to source stream out data. Must be
- * zero (i.e., read length = 256b) if the GS is enabled and the Output
- * Vertex Size field in 3DSTATE_GS is programmed to 0 (i.e., one 16B
- * unit)."
- */
- assert(stream->vue_read_base == 0 || stream->vue_read_base == 2);
- assert(stream->vue_read_count <= 34);
-
- assert(stream->decl_count <= ILO_STATE_SOL_MAX_DECL_COUNT);
-
- for (i = 0; i < stream->decl_count; i++) {
- const struct ilo_state_sol_decl_info *decl = &stream->decls[i];
-
- assert(decl->is_hole || decl->attr < stream->vue_read_count);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 205:
- *
- * "There is only enough internal storage for the 128-bit vertex
- * header and 32 128-bit vertex attributes."
- */
- assert(decl->attr < 33);
-
- assert(decl->component_base < 4 &&
- decl->component_base + decl->component_count <= 4);
- assert(decl->buffer < ILO_STATE_SOL_MAX_BUFFER_COUNT);
- }
-
- return true;
-}
-
-static bool
-sol_validate_gen7(const struct ilo_dev *dev,
- const struct ilo_state_sol_info *info)
-{
- uint8_t i;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 198:
- *
- * "This bit (Render Stream Select) is used even if SO Function Enable
- * is DISABLED."
- *
- * From the Haswell PRM, volume 2b, page 796:
- *
- * "SO Function Enable must also be ENABLED in order for thiis field
- * (Render Stream Select) to select a stream for rendering. When SO
- * Function Enable is DISABLED and Rendering Disable is cleared (i.e.,
- * rendering is enabled), StreamID is ignored downstream of the SO
- * stage, allowing any stream to be rendered."
- *
- * We want Gen7 behavior, but we have to require users to follow Gen7.5
- * behavior: info->sol_enable must be set for info->render_stream to work.
- */
-
- for (i = 0; i < ARRAY_SIZE(info->streams); i++) {
- if (!sol_stream_validate_gen7(dev, &info->streams[i]))
- return false;
- }
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 208:
- *
- * "(Surface Pitch)
- * [0,2048] Must be 0 or a multiple of 4 Bytes."
- */
- for (i = 0; i < ARRAY_SIZE(info->buffer_strides); i++) {
- assert(info->buffer_strides[i] <= 2048 &&
- info->buffer_strides[i] % 4 == 0);
- }
-
- return true;
-}
-
-static bool
-sol_set_gen7_3DSTATE_STREAMOUT(struct ilo_state_sol *sol,
- const struct ilo_dev *dev,
- const struct ilo_state_sol_info *info)
-{
- struct {
- uint8_t offset;
- uint8_t len;
- } vue_read[ILO_STATE_SOL_MAX_STREAM_COUNT];
- uint8_t i;
- uint32_t dw1, dw2;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- if (!sol_validate_gen7(dev, info))
- return false;
-
- for (i = 0; i < ARRAY_SIZE(info->streams); i++) {
- const struct ilo_state_sol_stream_info *stream = &info->streams[i];
-
- vue_read[i].offset = stream->vue_read_base / 2;
- /*
- * In pairs minus 1. URB entries are aligned to 512-bits. There is no
- * need to worry about reading past entries.
- */
- vue_read[i].len = (stream->vue_read_count + 1) / 2;
- if (vue_read[i].len)
- vue_read[i].len--;
- }
-
- dw1 = info->render_stream << GEN7_SO_DW1_RENDER_STREAM_SELECT__SHIFT |
- info->tristrip_reorder << GEN7_SO_DW1_REORDER_MODE__SHIFT;
-
- if (info->sol_enable)
- dw1 |= GEN7_SO_DW1_SO_ENABLE;
-
- if (info->render_disable)
- dw1 |= GEN7_SO_DW1_RENDER_DISABLE;
-
- if (info->stats_enable)
- dw1 |= GEN7_SO_DW1_STATISTICS;
-
- if (ilo_dev_gen(dev) < ILO_GEN(8)) {
- const uint8_t buffer_enables = ((bool) info->buffer_strides[3]) << 3 |
- ((bool) info->buffer_strides[2]) << 2 |
- ((bool) info->buffer_strides[1]) << 1 |
- ((bool) info->buffer_strides[0]);
- dw1 |= buffer_enables << GEN7_SO_DW1_BUFFER_ENABLES__SHIFT;
- }
-
- dw2 = vue_read[3].offset << GEN7_SO_DW2_STREAM3_READ_OFFSET__SHIFT |
- vue_read[3].len << GEN7_SO_DW2_STREAM3_READ_LEN__SHIFT |
- vue_read[2].offset << GEN7_SO_DW2_STREAM2_READ_OFFSET__SHIFT |
- vue_read[2].len << GEN7_SO_DW2_STREAM2_READ_LEN__SHIFT |
- vue_read[1].offset << GEN7_SO_DW2_STREAM1_READ_OFFSET__SHIFT |
- vue_read[1].len << GEN7_SO_DW2_STREAM1_READ_LEN__SHIFT |
- vue_read[0].offset << GEN7_SO_DW2_STREAM0_READ_OFFSET__SHIFT |
- vue_read[0].len << GEN7_SO_DW2_STREAM0_READ_LEN__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(sol->streamout) >= 2);
- sol->streamout[0] = dw1;
- sol->streamout[1] = dw2;
-
- memcpy(sol->strides, info->buffer_strides, sizeof(sol->strides));
-
- return true;
-}
-
-static bool
-sol_set_gen7_3DSTATE_SO_DECL_LIST(struct ilo_state_sol *sol,
- const struct ilo_dev *dev,
- const struct ilo_state_sol_info *info,
- uint8_t max_decl_count)
-{
- uint64_t decl_list[ILO_STATE_SOL_MAX_DECL_COUNT];
- uint8_t decl_counts[ILO_STATE_SOL_MAX_STREAM_COUNT];
- uint8_t buffer_selects[ILO_STATE_SOL_MAX_STREAM_COUNT];
- uint32_t dw1, dw2;
- uint8_t i, j;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- memset(decl_list, 0, sizeof(decl_list[0]) * max_decl_count);
-
- for (i = 0; i < ARRAY_SIZE(info->streams); i++) {
- const struct ilo_state_sol_stream_info *stream = &info->streams[i];
-
- assert(stream->decl_count <= max_decl_count);
- decl_counts[i] = stream->decl_count;
- buffer_selects[i] = 0;
-
- for (j = 0; j < stream->decl_count; j++) {
- const struct ilo_state_sol_decl_info *decl = &stream->decls[j];
- const uint8_t mask = ((1 << decl->component_count) - 1) <<
- decl->component_base;
- uint16_t val;
-
- val = decl->buffer << GEN7_SO_DECL_OUTPUT_SLOT__SHIFT |
- mask << GEN7_SO_DECL_COMPONENT_MASK__SHIFT;
-
- if (decl->is_hole)
- val |= GEN7_SO_DECL_HOLE_FLAG;
- else
- val |= decl->attr << GEN7_SO_DECL_REG_INDEX__SHIFT;
-
- decl_list[j] |= (uint64_t) val << (16 * i);
- buffer_selects[i] |= 1 << decl->buffer;
- }
- }
-
- dw1 = buffer_selects[3] << GEN7_SO_DECL_DW1_STREAM3_BUFFER_SELECTS__SHIFT |
- buffer_selects[2] << GEN7_SO_DECL_DW1_STREAM2_BUFFER_SELECTS__SHIFT |
- buffer_selects[1] << GEN7_SO_DECL_DW1_STREAM1_BUFFER_SELECTS__SHIFT |
- buffer_selects[0] << GEN7_SO_DECL_DW1_STREAM0_BUFFER_SELECTS__SHIFT;
- dw2 = decl_counts[3] << GEN7_SO_DECL_DW2_STREAM3_ENTRY_COUNT__SHIFT |
- decl_counts[2] << GEN7_SO_DECL_DW2_STREAM2_ENTRY_COUNT__SHIFT |
- decl_counts[1] << GEN7_SO_DECL_DW2_STREAM1_ENTRY_COUNT__SHIFT |
- decl_counts[0] << GEN7_SO_DECL_DW2_STREAM0_ENTRY_COUNT__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(sol->so_decl) >= 2);
- sol->so_decl[0] = dw1;
- sol->so_decl[1] = dw2;
-
- STATIC_ASSERT(ARRAY_SIZE(sol->decl[0]) == 2);
- memcpy(sol->decl, decl_list, sizeof(sol->decl[0]) * max_decl_count);
- sol->decl_count = max_decl_count;
-
- return true;
-}
-
-static bool
-sol_buffer_validate_gen7(const struct ilo_dev *dev,
- const struct ilo_state_sol_buffer_info *info)
-{
- ILO_DEV_ASSERT(dev, 7, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 208:
- *
- * "(Surface Base Address) This field specifies the starting DWord
- * address..."
- */
- assert(info->offset % 4 == 0);
-
- if (info->vma) {
- assert(info->vma->vm_alignment % 4 == 0);
- assert(info->size && info->offset + info->size <= info->vma->vm_size);
- }
-
- /* Gen8+ only */
- if (info->write_offset_load || info->write_offset_save) {
- assert(ilo_dev_gen(dev) >= ILO_GEN(8) && info->write_offset_vma);
- assert(info->write_offset_offset + sizeof(uint32_t) <=
- info->write_offset_vma->vm_size);
- }
-
- /*
- * From the Broadwell PRM, volume 2b, page 206:
- *
- * "This field (Stream Offset) specifies the Offset in stream output
- * buffer to start at, or whether to append to the end of an existing
- * buffer. The Offset must be DWORD aligned."
- */
- if (info->write_offset_imm_enable) {
- assert(info->write_offset_load);
- assert(info->write_offset_imm % 4 == 0);
- }
-
- return true;
-}
-
-static uint32_t
-sol_buffer_get_gen6_size(const struct ilo_dev *dev,
- const struct ilo_state_sol_buffer_info *info)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 208:
- *
- * "(Surface End Address) This field specifies the ending DWord
- * address..."
- */
- return (info->vma) ? info->size & ~3 : 0;
-}
-
-static bool
-sol_buffer_set_gen7_3dstate_so_buffer(struct ilo_state_sol_buffer *sb,
- const struct ilo_dev *dev,
- const struct ilo_state_sol_buffer_info *info)
-{
- const uint32_t size = sol_buffer_get_gen6_size(dev, info);
-
- ILO_DEV_ASSERT(dev, 7, 7.5);
-
- if (!sol_buffer_validate_gen7(dev, info))
- return false;
-
- STATIC_ASSERT(ARRAY_SIZE(sb->so_buf) >= 2);
- sb->so_buf[0] = info->offset;
- sb->so_buf[1] = (size) ? info->offset + size : 0;
-
- return true;
-}
-
-static bool
-sol_buffer_set_gen8_3dstate_so_buffer(struct ilo_state_sol_buffer *sb,
- const struct ilo_dev *dev,
- const struct ilo_state_sol_buffer_info *info)
-{
- const uint32_t size = sol_buffer_get_gen6_size(dev, info);
- uint32_t dw1;
-
- ILO_DEV_ASSERT(dev, 8, 8);
-
- if (!sol_buffer_validate_gen7(dev, info))
- return false;
-
- dw1 = 0;
-
- if (info->vma)
- dw1 |= GEN8_SO_BUF_DW1_ENABLE;
- if (info->write_offset_load)
- dw1 |= GEN8_SO_BUF_DW1_OFFSET_WRITE_ENABLE;
- if (info->write_offset_save)
- dw1 |= GEN8_SO_BUF_DW1_OFFSET_ENABLE;
-
- STATIC_ASSERT(ARRAY_SIZE(sb->so_buf) >= 4);
- sb->so_buf[0] = dw1;
- sb->so_buf[1] = info->offset;
-
- /*
- * From the Broadwell PRM, volume 2b, page 205:
- *
- * "This field (Surface Size) specifies the size of buffer in number
- * DWords minus 1 of the buffer in Graphics Memory."
- */
- sb->so_buf[2] = (size) ? size / 4 - 1 : 0;
-
- /* load from imm or sb->write_offset_bo */
- sb->so_buf[3] = (info->write_offset_imm_enable) ?
- info->write_offset_imm : ~0u;
-
- return true;
-}
-
-bool
-ilo_state_sol_init(struct ilo_state_sol *sol,
- const struct ilo_dev *dev,
- const struct ilo_state_sol_info *info)
-{
- bool ret = true;
-
- assert(ilo_is_zeroed(sol, sizeof(*sol)));
- assert(ilo_is_zeroed(info->data, info->data_size));
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- uint8_t max_decl_count, i;
-
- max_decl_count = info->streams[0].decl_count;
- for (i = 1; i < ARRAY_SIZE(info->streams); i++) {
- if (max_decl_count < info->streams[i].decl_count)
- max_decl_count = info->streams[i].decl_count;
- }
-
- assert(ilo_state_sol_data_size(dev, max_decl_count) <= info->data_size);
- sol->decl = (uint32_t (*)[2]) info->data;
-
- ret &= sol_set_gen7_3DSTATE_STREAMOUT(sol, dev, info);
- ret &= sol_set_gen7_3DSTATE_SO_DECL_LIST(sol, dev, info, max_decl_count);
- }
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_sol_init_disabled(struct ilo_state_sol *sol,
- const struct ilo_dev *dev,
- bool render_disable)
-{
- struct ilo_state_sol_info info;
-
- memset(&info, 0, sizeof(info));
- info.render_disable = render_disable;
-
- return ilo_state_sol_init(sol, dev, &info);
-}
-
-uint32_t
-ilo_state_sol_buffer_size(const struct ilo_dev *dev, uint32_t size,
- uint32_t *alignment)
-{
- /* DWord aligned without padding */
- *alignment = 4;
- return size;
-}
-
-bool
-ilo_state_sol_buffer_init(struct ilo_state_sol_buffer *sb,
- const struct ilo_dev *dev,
- const struct ilo_state_sol_buffer_info *info)
-{
- bool ret = true;
-
- assert(ilo_is_zeroed(sb, sizeof(*sb)));
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- ret &= sol_buffer_set_gen8_3dstate_so_buffer(sb, dev, info);
- else
- ret &= sol_buffer_set_gen7_3dstate_so_buffer(sb, dev, info);
-
- sb->vma = info->vma;
- sb->write_offset_vma = info->write_offset_vma;
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_sol_buffer_init_disabled(struct ilo_state_sol_buffer *sb,
- const struct ilo_dev *dev)
-{
- struct ilo_state_sol_buffer_info info;
-
- memset(&info, 0, sizeof(info));
-
- return ilo_state_sol_buffer_init(sb, dev, &info);
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_STATE_SOL_H
-#define ILO_STATE_SOL_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-
-/*
- * From the Ivy Bridge PRM, volume 2 part 1, page 193:
- *
- * "Incoming topologies are tagged with a 2-bit StreamID."
- */
-#define ILO_STATE_SOL_MAX_STREAM_COUNT 4
-
-/*
- * From the Ivy Bridge PRM, volume 2 part 1, page 195:
- *
- * "Up to four SO buffers are supported."
- */
-#define ILO_STATE_SOL_MAX_BUFFER_COUNT 4
-
-/*
- * From the Ivy Bridge PRM, volume 2 part 1, page 201:
- *
- * "All 128 decls..."
- */
-#define ILO_STATE_SOL_MAX_DECL_COUNT 128
-
-/**
- * Output a vertex attribute.
- */
-struct ilo_state_sol_decl_info {
- /* select an attribute from read ones */
- uint8_t attr;
- bool is_hole;
-
- /* which components to write */
- uint8_t component_base;
- uint8_t component_count;
-
- /* destination buffer */
- uint8_t buffer;
-};
-
-struct ilo_state_sol_stream_info {
- /* which VUE attributes to read */
- uint8_t cv_vue_attr_count;
- uint8_t vue_read_base;
- uint8_t vue_read_count;
-
- uint8_t decl_count;
- const struct ilo_state_sol_decl_info *decls;
-};
-
-struct ilo_state_sol_info {
- void *data;
- size_t data_size;
-
- bool sol_enable;
- bool stats_enable;
- enum gen_reorder_mode tristrip_reorder;
-
- bool render_disable;
- /* ignored when SOL is disabled */
- uint8_t render_stream;
-
- /* a buffer is disabled when its stride is zero */
- uint16_t buffer_strides[ILO_STATE_SOL_MAX_BUFFER_COUNT];
-
- struct ilo_state_sol_stream_info streams[ILO_STATE_SOL_MAX_STREAM_COUNT];
-};
-
-struct ilo_state_sol {
- uint32_t streamout[2];
- uint16_t strides[4];
-
- uint32_t so_decl[2];
- uint32_t (*decl)[2];
- uint8_t decl_count;
-};
-
-struct ilo_vma;
-
-struct ilo_state_sol_buffer_info {
- const struct ilo_vma *vma;
- uint32_t offset;
- uint32_t size;
-
- /* Gen8+ only; at least sizeof(uint32_t) bytes */
- const struct ilo_vma *write_offset_vma;
- uint32_t write_offset_offset;
-
- bool write_offset_load;
- bool write_offset_save;
-
- bool write_offset_imm_enable;
- uint32_t write_offset_imm;
-};
-
-struct ilo_state_sol_buffer {
- uint32_t so_buf[5];
-
- const struct ilo_vma *vma;
- const struct ilo_vma *write_offset_vma;
-};
-
-static inline size_t
-ilo_state_sol_data_size(const struct ilo_dev *dev, uint8_t max_decl_count)
-{
- const struct ilo_state_sol *so = NULL;
- return (ilo_dev_gen(dev) >= ILO_GEN(7)) ?
- sizeof(so->decl[0]) * max_decl_count : 0;
-}
-
-bool
-ilo_state_sol_init(struct ilo_state_sol *sol,
- const struct ilo_dev *dev,
- const struct ilo_state_sol_info *info);
-
-bool
-ilo_state_sol_init_disabled(struct ilo_state_sol *sol,
- const struct ilo_dev *dev,
- bool render_disable);
-
-uint32_t
-ilo_state_sol_buffer_size(const struct ilo_dev *dev, uint32_t size,
- uint32_t *alignment);
-
-bool
-ilo_state_sol_buffer_init(struct ilo_state_sol_buffer *sb,
- const struct ilo_dev *dev,
- const struct ilo_state_sol_buffer_info *info);
-
-bool
-ilo_state_sol_buffer_init_disabled(struct ilo_state_sol_buffer *sb,
- const struct ilo_dev *dev);
-
-#endif /* ILO_STATE_SOL_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-#include "ilo_image.h"
-#include "ilo_vma.h"
-#include "ilo_state_surface.h"
-
-static bool
-surface_set_gen6_null_SURFACE_STATE(struct ilo_state_surface *surf,
- const struct ilo_dev *dev)
-{
- uint32_t dw0, dw3;
-
- ILO_DEV_ASSERT(dev, 6, 6);
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 71:
- *
- * "All of the remaining fields in surface state are ignored for null
- * surfaces, with the following exceptions:
- *
- * - [DevSNB+]: Width, Height, Depth, and LOD fields must match the
- * depth buffer's corresponding state for all render target
- * surfaces, including null.
- * - Surface Format must be R8G8B8A8_UNORM."
- *
- * From the Sandy Bridge PRM, volume 4 part 1, page 82:
- *
- * "If Surface Type is SURFTYPE_NULL, this field (Tiled Surface) must
- * be true"
- *
- * Note that we ignore the first exception for all surface types.
- */
- dw0 = GEN6_SURFTYPE_NULL << GEN6_SURFACE_DW0_TYPE__SHIFT |
- GEN6_FORMAT_R8G8B8A8_UNORM << GEN6_SURFACE_DW0_FORMAT__SHIFT;
- dw3 = GEN6_TILING_X << GEN6_SURFACE_DW3_TILING__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(surf->surface) >= 6);
- surf->surface[0] = dw0;
- surf->surface[1] = 0;
- surf->surface[2] = 0;
- surf->surface[3] = dw3;
- surf->surface[4] = 0;
- surf->surface[5] = 0;
-
- return true;
-}
-
-static bool
-surface_set_gen7_null_SURFACE_STATE(struct ilo_state_surface *surf,
- const struct ilo_dev *dev)
-{
- uint32_t dw0;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- dw0 = GEN6_SURFTYPE_NULL << GEN7_SURFACE_DW0_TYPE__SHIFT |
- GEN6_FORMAT_R8G8B8A8_UNORM << GEN7_SURFACE_DW0_FORMAT__SHIFT;
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- dw0 |= GEN6_TILING_X << GEN8_SURFACE_DW0_TILING__SHIFT;
- else
- dw0 |= GEN6_TILING_X << GEN7_SURFACE_DW0_TILING__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(surf->surface) >= 13);
- surf->surface[0] = dw0;
- memset(&surf->surface[1], 0, sizeof(uint32_t) *
- (((ilo_dev_gen(dev) >= ILO_GEN(8)) ? 13 : 8) - 1));
-
- return true;
-}
-
-static uint32_t
-surface_get_gen6_buffer_offset_alignment(const struct ilo_dev *dev,
- const struct ilo_state_surface_buffer_info *info)
-{
- uint32_t alignment;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 68:
- *
- * "The Base Address for linear render target surfaces and surfaces
- * accessed with the typed surface read/write data port messages must
- * be element-size aligned, for non-YUV surface formats, or a multiple
- * of 2 element-sizes for YUV surface formats. Other linear surfaces
- * have no alignment requirements (byte alignment is sufficient)."
- *
- * "Certain message types used to access surfaces have more stringent
- * alignment requirements. Please refer to the specific message
- * documentation for additional restrictions."
- */
- switch (info->access) {
- case ILO_STATE_SURFACE_ACCESS_SAMPLER:
- /* no alignment requirements */
- alignment = 1;
- break;
- case ILO_STATE_SURFACE_ACCESS_DP_RENDER:
- case ILO_STATE_SURFACE_ACCESS_DP_TYPED:
- /* element-size aligned */
- alignment = info->format_size;
-
- assert(info->struct_size % alignment == 0);
- break;
- case ILO_STATE_SURFACE_ACCESS_DP_UNTYPED:
- /*
- * Nothing is said about Untyped* messages, but I think they require the
- * base address to be DWord aligned.
- */
- alignment = 4;
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 70:
- *
- * "For linear surfaces with Surface Type of SURFTYPE_STRBUF, the
- * pitch must be a multiple of 4 bytes."
- */
- if (info->struct_size > 1)
- assert(info->struct_size % alignment == 0);
- break;
- case ILO_STATE_SURFACE_ACCESS_DP_DATA:
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 233, 235, and 237:
- *
- * "the surface base address must be OWord aligned"
- *
- * for OWord Block Read/Write, Unaligned OWord Block Read, and OWord
- * Dual Block Read/Write.
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 246 and 249:
- *
- * "The surface base address must be DWord aligned"
- *
- * for DWord Scattered Read/Write and Byte Scattered Read/Write.
- */
- alignment = (info->format_size > 4) ? 16 : 4;
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 233, 235, 237, and
- * 246:
- *
- * "the surface pitch is ignored, the surface is treated as a
- * 1-dimensional surface. An element size (pitch) of 16 bytes is
- * used to determine the size of the buffer for out-of-bounds
- * checking if using the surface state model."
- *
- * for OWord Block Read/Write, Unaligned OWord Block Read, OWord
- * Dual Block Read/Write, and DWord Scattered Read/Write.
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 248:
- *
- * "The surface pitch is ignored, the surface is treated as a
- * 1-dimensional surface. An element size (pitch) of 4 bytes is
- * used to determine the size of the buffer for out-of-bounds
- * checking if using the surface state model."
- *
- * for Byte Scattered Read/Write.
- *
- * It is programmable on Gen7.5+.
- */
- if (ilo_dev_gen(dev) < ILO_GEN(7.5)) {
- const int fixed = (info->format_size > 1) ? 16 : 4;
- assert(info->struct_size == fixed);
- }
- break;
- case ILO_STATE_SURFACE_ACCESS_DP_SVB:
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 259:
- *
- * "Both the surface base address and surface pitch must be DWord
- * aligned."
- */
- alignment = 4;
-
- assert(info->struct_size % alignment == 0);
- break;
- default:
- assert(!"unknown access");
- alignment = 1;
- break;
- }
-
- return alignment;
-}
-
-static bool
-surface_validate_gen6_buffer(const struct ilo_dev *dev,
- const struct ilo_state_surface_buffer_info *info)
-{
- uint32_t alignment;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (info->offset + info->size > info->vma->vm_size) {
- ilo_warn("invalid buffer range\n");
- return false;
- }
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 81:
- *
- * "For surfaces of type SURFTYPE_BUFFER: [0,2047] -> [1B, 2048B]
- * For surfaces of type SURFTYPE_STRBUF: [0,2047] -> [1B, 2048B]"
- */
- if (!info->struct_size || info->struct_size > 2048) {
- ilo_warn("invalid buffer struct size\n");
- return false;
- }
-
- alignment = surface_get_gen6_buffer_offset_alignment(dev, info);
- if (info->offset % alignment || info->vma->vm_alignment % alignment) {
- ilo_warn("bad buffer offset\n");
- return false;
- }
-
- /* no STRBUF on Gen6 */
- if (info->format == GEN6_FORMAT_RAW && info->struct_size > 1)
- assert(ilo_dev_gen(dev) >= ILO_GEN(7));
-
- /* SVB writes are Gen6 only */
- if (info->access == ILO_STATE_SURFACE_ACCESS_DP_SVB)
- assert(ilo_dev_gen(dev) == ILO_GEN(6));
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 83:
- *
- * "NOTE: "RAW" is supported only with buffers and structured buffers
- * accessed via the untyped surface read/write and untyped atomic
- * operation messages, which do not have a column in the table."
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 252:
- *
- * "For untyped messages, the Surface Format must be RAW and the
- * Surface Type must be SURFTYPE_BUFFER or SURFTYPE_STRBUF."
- */
- assert((info->access == ILO_STATE_SURFACE_ACCESS_DP_UNTYPED) ==
- (info->format == GEN6_FORMAT_RAW));
-
- return true;
-}
-
-static bool
-surface_get_gen6_buffer_struct_count(const struct ilo_dev *dev,
- const struct ilo_state_surface_buffer_info *info,
- uint32_t *count)
-{
- uint32_t max_struct, c;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- c = info->size / info->struct_size;
- if (info->format_size < info->size - info->struct_size * c)
- c++;
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 77:
- *
- * "For buffer surfaces, the number of entries in the buffer ranges
- * from 1 to 2^27."
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 68:
- *
- * "For typed buffer and structured buffer surfaces, the number of
- * entries in the buffer ranges from 1 to 2^27. For raw buffer
- * surfaces, the number of entries in the buffer is the number of
- * bytes which can range from 1 to 2^30."
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 69:
- *
- * For SURFTYPE_BUFFER: The low two bits of this field (Width) must be
- * 11 if the Surface Format is RAW (the size of the buffer must be a
- * multiple of 4 bytes)."
- */
- max_struct = 1 << 27;
- if (info->format == GEN6_FORMAT_RAW && info->struct_size == 1) {
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- max_struct = 1 << 30;
-
- c &= ~3;
- }
-
- if (!c || c > max_struct) {
- ilo_warn("too many or zero buffer structs\n");
- return false;
- }
-
- *count = c - 1;
-
- return true;
-}
-
-static bool
-surface_set_gen6_buffer_SURFACE_STATE(struct ilo_state_surface *surf,
- const struct ilo_dev *dev,
- const struct ilo_state_surface_buffer_info *info)
-{
- uint32_t dw0, dw1, dw2, dw3;
- uint32_t struct_count;
- int width, height, depth;
-
- ILO_DEV_ASSERT(dev, 6, 6);
-
- if (!surface_validate_gen6_buffer(dev, info) ||
- !surface_get_gen6_buffer_struct_count(dev, info, &struct_count))
- return false;
-
- /* bits [6:0] */
- width = (struct_count & 0x0000007f);
- /* bits [19:7] */
- height = (struct_count & 0x000fff80) >> 7;
- /* bits [26:20] */
- depth = (struct_count & 0x07f00000) >> 20;
-
- dw0 = GEN6_SURFTYPE_BUFFER << GEN6_SURFACE_DW0_TYPE__SHIFT |
- info->format << GEN6_SURFACE_DW0_FORMAT__SHIFT;
- dw1 = info->offset;
- dw2 = height << GEN6_SURFACE_DW2_HEIGHT__SHIFT |
- width << GEN6_SURFACE_DW2_WIDTH__SHIFT;
- dw3 = depth << GEN6_SURFACE_DW3_DEPTH__SHIFT |
- (info->struct_size - 1) << GEN6_SURFACE_DW3_PITCH__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(surf->surface) >= 6);
- surf->surface[0] = dw0;
- surf->surface[1] = dw1;
- surf->surface[2] = dw2;
- surf->surface[3] = dw3;
- surf->surface[4] = 0;
- surf->surface[5] = 0;
-
- surf->type = GEN6_SURFTYPE_BUFFER;
- surf->min_lod = 0;
- surf->mip_count = 0;
-
- return true;
-}
-
-static bool
-surface_set_gen7_buffer_SURFACE_STATE(struct ilo_state_surface *surf,
- const struct ilo_dev *dev,
- const struct ilo_state_surface_buffer_info *info)
-{
- uint32_t dw0, dw1, dw2, dw3, dw7;
- enum gen_surface_type type;
- uint32_t struct_count;
- int width, height, depth;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- if (!surface_validate_gen6_buffer(dev, info) ||
- !surface_get_gen6_buffer_struct_count(dev, info, &struct_count))
- return false;
-
- type = (info->format == GEN6_FORMAT_RAW && info->struct_size > 1) ?
- GEN7_SURFTYPE_STRBUF : GEN6_SURFTYPE_BUFFER;
-
- /* bits [6:0] */
- width = (struct_count & 0x0000007f);
- /* bits [20:7] */
- height = (struct_count & 0x001fff80) >> 7;
- /* bits [30:21] */
- depth = (struct_count & 0x7fe00000) >> 21;
-
- dw0 = type << GEN7_SURFACE_DW0_TYPE__SHIFT |
- info->format << GEN7_SURFACE_DW0_FORMAT__SHIFT;
- dw1 = (ilo_dev_gen(dev) >= ILO_GEN(8)) ? 0 : info->offset;
- dw2 = GEN_SHIFT32(height, GEN7_SURFACE_DW2_HEIGHT) |
- GEN_SHIFT32(width, GEN7_SURFACE_DW2_WIDTH);
- dw3 = GEN_SHIFT32(depth, GEN7_SURFACE_DW3_DEPTH) |
- GEN_SHIFT32(info->struct_size - 1, GEN7_SURFACE_DW3_PITCH);
-
- dw7 = 0;
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5)) {
- dw7 |= GEN_SHIFT32(GEN75_SCS_RED, GEN75_SURFACE_DW7_SCS_R) |
- GEN_SHIFT32(GEN75_SCS_GREEN, GEN75_SURFACE_DW7_SCS_G) |
- GEN_SHIFT32(GEN75_SCS_BLUE, GEN75_SURFACE_DW7_SCS_B) |
- GEN_SHIFT32(GEN75_SCS_ALPHA, GEN75_SURFACE_DW7_SCS_A);
- }
-
- STATIC_ASSERT(ARRAY_SIZE(surf->surface) >= 13);
- surf->surface[0] = dw0;
- surf->surface[1] = dw1;
- surf->surface[2] = dw2;
- surf->surface[3] = dw3;
- surf->surface[4] = 0;
- surf->surface[5] = 0;
- surf->surface[6] = 0;
- surf->surface[7] = dw7;
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- surf->surface[8] = info->offset;
- surf->surface[9] = 0;
- surf->surface[10] = 0;
- surf->surface[11] = 0;
- surf->surface[12] = 0;
- }
-
- surf->type = type;
- surf->min_lod = 0;
- surf->mip_count = 0;
-
- return true;
-}
-
-static bool
-surface_validate_gen6_image(const struct ilo_dev *dev,
- const struct ilo_state_surface_image_info *info)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- switch (info->access) {
- case ILO_STATE_SURFACE_ACCESS_SAMPLER:
- case ILO_STATE_SURFACE_ACCESS_DP_RENDER:
- break;
- case ILO_STATE_SURFACE_ACCESS_DP_TYPED:
- assert(ilo_dev_gen(dev) >= ILO_GEN(7));
- break;
- default:
- assert(!"unsupported surface access");
- break;
- }
-
- assert(info->img && info->vma);
-
- if (info->img->tiling != GEN6_TILING_NONE)
- assert(info->vma->vm_alignment % 4096 == 0);
-
- if (info->aux_vma) {
- assert(ilo_image_can_enable_aux(info->img, info->level_base));
- /* always tiled */
- assert(info->aux_vma->vm_alignment % 4096 == 0);
- }
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 78:
- *
- * "For surface types other than SURFTYPE_BUFFER, the Width specified
- * by this field must be less than or equal to the surface pitch
- * (specified in bytes via the Surface Pitch field)."
- */
- assert(info->img->bo_stride && info->img->bo_stride <= 512 * 1024 &&
- info->img->width0 <= info->img->bo_stride);
-
- if (info->type != info->img->type) {
- assert(info->type == GEN6_SURFTYPE_2D &&
- info->img->type == GEN6_SURFTYPE_CUBE);
- }
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 78:
- *
- * "For cube maps, Width must be set equal to the Height."
- */
- if (info->type == GEN6_SURFTYPE_CUBE)
- assert(info->img->width0 == info->img->height0);
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 72:
- *
- * "Tile Walk TILEWALK_YMAJOR is UNDEFINED for render target formats
- * that have 128 bits-per-element (BPE)."
- *
- * "If Number of Multisamples is set to a value other than
- * MULTISAMPLECOUNT_1, this field cannot be set to the following
- * formats:
- *
- * - any format with greater than 64 bits per element
- * - any compressed texture format (BC*)
- * - any YCRCB* format"
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 63:
- *
- * If Number of Multisamples is set to a value other than
- * MULTISAMPLECOUNT_1, this field cannot be set to the following
- * formats: any format with greater than 64 bits per element, if
- * Number of Multisamples is MULTISAMPLECOUNT_8, any compressed
- * texture format (BC*), and any YCRCB* format.
- *
- * TODO
- */
-
- if (ilo_dev_gen(dev) < ILO_GEN(8) && info->img->tiling == GEN8_TILING_W) {
- ilo_warn("tiling W is not supported\n");
- return false;
- }
-
- return true;
-}
-
-static void
-surface_get_gen6_image_max_extent(const struct ilo_dev *dev,
- const struct ilo_state_surface_image_info *info,
- uint16_t *max_w, uint16_t *max_h)
-{
- const uint16_t max_size = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 16384 : 8192;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- switch (info->type) {
- case GEN6_SURFTYPE_1D:
- *max_w = max_size;
- *max_h = 1;
- break;
- case GEN6_SURFTYPE_2D:
- case GEN6_SURFTYPE_CUBE:
- *max_w = max_size;
- *max_h = max_size;
- break;
- case GEN6_SURFTYPE_3D:
- *max_w = 2048;
- *max_h = 2048;
- break;
- default:
- assert(!"invalid surface type");
- *max_w = 1;
- *max_h = 1;
- break;
- }
-}
-
-static bool
-surface_get_gen6_image_extent(const struct ilo_dev *dev,
- const struct ilo_state_surface_image_info *info,
- uint16_t *width, uint16_t *height)
-{
- uint16_t w, h, max_w, max_h;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- w = info->img->width0;
- h = info->img->height0;
-
- surface_get_gen6_image_max_extent(dev, info, &max_w, &max_h);
- assert(w && h && w <= max_w && h <= max_h);
-
- *width = w - 1;
- *height = h - 1;
-
- return true;
-}
-
-static bool
-surface_get_gen6_image_slices(const struct ilo_dev *dev,
- const struct ilo_state_surface_image_info *info,
- uint16_t *depth, uint16_t *min_array_elem,
- uint16_t *rt_view_extent)
-{
- uint16_t max_slice, d;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 63:
- *
- * "If this field (Surface Array) is enabled, the Surface Type must be
- * SURFTYPE_1D, SURFTYPE_2D, or SURFTYPE_CUBE. If this field is
- * disabled and Surface Type is SURFTYPE_1D, SURFTYPE_2D, or
- * SURFTYPE_CUBE, the Depth field must be set to zero."
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 69:
- *
- * "This field (Depth) specifies the total number of levels for a
- * volume texture or the number of array elements allowed to be
- * accessed starting at the Minimum Array Element for arrayed
- * surfaces. If the volume texture is MIP-mapped, this field
- * specifies the depth of the base MIP level."
- *
- * "For SURFTYPE_CUBE:For Sampling Engine Surfaces, the range of this
- * field is [0,340], indicating the number of cube array elements
- * (equal to the number of underlying 2D array elements divided by 6).
- * For other surfaces, this field must be zero."
- *
- * "Errata: For SURFTYPE_CUBE sampling engine surfaces, the range of
- * this field is limited to [0,85].
- *
- * Errata: If Surface Array is enabled, and Depth is between 1024 and
- * 2047, an incorrect array slice may be accessed if the requested
- * array index in the message is greater than or equal to 4096."
- *
- * The errata are for Gen7-specific, and they limit the number of useable
- * layers to (86 * 6), about 512.
- */
-
- switch (info->type) {
- case GEN6_SURFTYPE_1D:
- case GEN6_SURFTYPE_2D:
- case GEN6_SURFTYPE_CUBE:
- max_slice = (ilo_dev_gen(dev) >= ILO_GEN(7.5)) ? 2048 : 512;
-
- assert(info->img->array_size <= max_slice);
- max_slice = info->img->array_size;
-
- d = info->slice_count;
- if (info->type == GEN6_SURFTYPE_CUBE) {
- if (info->access == ILO_STATE_SURFACE_ACCESS_SAMPLER) {
- if (!d || d % 6) {
- ilo_warn("invalid cube slice count\n");
- return false;
- }
-
- if (ilo_dev_gen(dev) == ILO_GEN(7) && d > 86 * 6) {
- ilo_warn("cube slice count exceeds Gen7 limit\n");
- return false;
- }
- } else {
- /*
- * Minumum Array Element and Depth must be 0; Render Target View
- * Extent is ignored.
- */
- if (info->slice_base || d != 6) {
- ilo_warn("no cube RT array support in data port\n");
- return false;
- }
- }
-
- d /= 6;
- }
-
- if (!info->is_array && d > 1) {
- ilo_warn("non-array surface with non-zero depth\n");
- return false;
- }
- break;
- case GEN6_SURFTYPE_3D:
- max_slice = 2048;
-
- assert(info->img->depth0 <= max_slice);
- max_slice = u_minify(info->img->depth0, info->level_base);
-
- d = info->img->depth0;
-
- if (info->is_array) {
- ilo_warn("3D surfaces cannot be arrays\n");
- return false;
- }
- break;
- default:
- assert(!"invalid surface type");
- return false;
- break;
- }
-
- if (!info->slice_count ||
- info->slice_base + info->slice_count > max_slice) {
- ilo_warn("invalid slice range\n");
- return false;
- }
-
- assert(d);
- *depth = d - 1;
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 84:
- *
- * "For Sampling Engine and Render Target 1D and 2D Surfaces:
- * This field (Minimum Array Element) indicates the minimum array
- * element that can be accessed as part of this surface. This field
- * is added to the delivered array index before it is used to address
- * the surface.
- *
- * For Render Target 3D Surfaces:
- * This field indicates the minimum `R' coordinate on the LOD
- * currently being rendered to. This field is added to the delivered
- * array index before it is used to address the surface.
- *
- * For Sampling Engine Cube Surfaces on [DevSNB+] only:
- * This field indicates the minimum array element in the underlying 2D
- * surface array that can be accessed as part of this surface (the
- * cube array index is multipled by 6 to compute this value, although
- * this field is not restricted to only multiples of 6). This field is
- * added to the delivered array index before it is used to address the
- * surface.
- *
- * For Other Surfaces:
- * This field must be set to zero."
- *
- * On Gen7+, typed sufaces are treated like sampling engine 1D and 2D
- * surfaces.
- */
- *min_array_elem = info->slice_base;
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 84:
- *
- * "For Render Target 3D Surfaces:
- * This field (Render Target View Extent) indicates the extent of the
- * accessible `R' coordinates minus 1 on the LOD currently being
- * rendered to.
- *
- * For Render Target 1D and 2D Surfaces:
- * This field must be set to the same value as the Depth field.
- *
- * For Other Surfaces:
- * This field is ignored."
- */
- *rt_view_extent = info->slice_count - 1;
-
- return true;
-}
-
-static bool
-surface_get_gen6_image_levels(const struct ilo_dev *dev,
- const struct ilo_state_surface_image_info *info,
- uint8_t *min_lod, uint8_t *mip_count)
-{
- uint8_t max_level = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 15 : 14;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(info->img->level_count <= max_level);
- max_level = info->img->level_count;
-
- if (!info->level_count ||
- info->level_base + info->level_count > max_level) {
- ilo_warn("invalid level range\n");
- return false;
- }
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 79:
- *
- * "For Sampling Engine Surfaces:
- * This field (MIP Count / LOD) indicates the number of MIP levels
- * allowed to be accessed starting at Surface Min LOD, which must be
- * less than or equal to the number of MIP levels actually stored in
- * memory for this surface.
- *
- * Force the mip map access to be between the mipmap specified by the
- * integer bits of the Min LOD and the ceiling of the value specified
- * here.
- *
- * For Render Target Surfaces:
- * This field defines the MIP level that is currently being rendered
- * into. This is the absolute MIP level on the surface and is not
- * relative to the Surface Min LOD field, which is ignored for render
- * target surfaces.
- *
- * For Other Surfaces:
- * This field is reserved : MBZ"
- *
- * From the Sandy Bridge PRM, volume 4 part 1, page 83:
- *
- * "For Sampling Engine Surfaces:
- *
- * This field (Surface Min LOD) indicates the most detailed LOD that
- * can be accessed as part of this surface. This field is added to
- * the delivered LOD (sample_l, ld, or resinfo message types) before
- * it is used to address the surface.
- *
- * For Other Surfaces:
- * This field is ignored."
- *
- * On Gen7+, typed sufaces are treated like sampling engine surfaces.
- */
- if (info->access == ILO_STATE_SURFACE_ACCESS_DP_RENDER) {
- assert(info->level_count == 1);
-
- *min_lod = 0;
- *mip_count = info->level_base;
- } else {
- *min_lod = info->level_base;
- *mip_count = info->level_count - 1;
- }
-
- return true;
-}
-
-static bool
-surface_get_gen6_image_sample_count(const struct ilo_dev *dev,
- const struct ilo_state_surface_image_info *info,
- enum gen_sample_count *sample_count)
-{
- int min_gen;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- switch (info->img->sample_count) {
- case 1:
- *sample_count = GEN6_NUMSAMPLES_1;
- min_gen = ILO_GEN(6);
- break;
- case 2:
- *sample_count = GEN8_NUMSAMPLES_2;
- min_gen = ILO_GEN(8);
- break;
- case 4:
- *sample_count = GEN6_NUMSAMPLES_4;
- min_gen = ILO_GEN(6);
- break;
- case 8:
- *sample_count = GEN7_NUMSAMPLES_8;
- min_gen = ILO_GEN(7);
- break;
- default:
- assert(!"invalid sample count");
- *sample_count = GEN6_NUMSAMPLES_1;
- break;
- }
-
- assert(ilo_dev_gen(dev) >= min_gen);
-
- return true;
-}
-
-static bool
-surface_get_gen6_image_alignments(const struct ilo_dev *dev,
- const struct ilo_state_surface_image_info *info,
- uint32_t *alignments)
-{
- uint32_t a = 0;
- bool err = false;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- switch (info->img->align_i) {
- case 4:
- a |= GEN8_SURFACE_DW0_HALIGN_4;
- break;
- case 8:
- a |= GEN8_SURFACE_DW0_HALIGN_8;
- break;
- case 16:
- a |= GEN8_SURFACE_DW0_HALIGN_16;
- break;
- default:
- err = true;
- break;
- }
-
- switch (info->img->align_j) {
- case 4:
- a |= GEN7_SURFACE_DW0_VALIGN_4;
- break;
- case 8:
- a |= GEN8_SURFACE_DW0_VALIGN_8;
- break;
- case 16:
- a |= GEN8_SURFACE_DW0_VALIGN_16;
- break;
- default:
- err = true;
- break;
- }
- } else if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- switch (info->img->align_i) {
- case 4:
- a |= GEN7_SURFACE_DW0_HALIGN_4;
- break;
- case 8:
- a |= GEN7_SURFACE_DW0_HALIGN_8;
- break;
- default:
- err = true;
- break;
- }
-
- switch (info->img->align_j) {
- case 2:
- a |= GEN7_SURFACE_DW0_VALIGN_2;
- break;
- case 4:
- a |= GEN7_SURFACE_DW0_VALIGN_4;
- break;
- default:
- err = true;
- break;
- }
- } else {
- if (info->img->align_i != 4)
- err = true;
-
- switch (info->img->align_j) {
- case 2:
- a |= GEN6_SURFACE_DW5_VALIGN_2;
- break;
- case 4:
- a |= GEN6_SURFACE_DW5_VALIGN_4;
- break;
- default:
- err = true;
- break;
- }
- }
-
- if (err)
- assert(!"invalid HALIGN or VALIGN");
-
- *alignments = a;
-
- return true;
-}
-
-static bool
-surface_set_gen6_image_SURFACE_STATE(struct ilo_state_surface *surf,
- const struct ilo_dev *dev,
- const struct ilo_state_surface_image_info *info)
-{
- uint16_t width, height, depth, array_base, view_extent;
- uint8_t min_lod, mip_count;
- enum gen_sample_count sample_count;
- uint32_t alignments;
- uint32_t dw0, dw2, dw3, dw4, dw5;
-
- ILO_DEV_ASSERT(dev, 6, 6);
-
- if (!surface_validate_gen6_image(dev, info) ||
- !surface_get_gen6_image_extent(dev, info, &width, &height) ||
- !surface_get_gen6_image_slices(dev, info, &depth, &array_base,
- &view_extent) ||
- !surface_get_gen6_image_levels(dev, info, &min_lod, &mip_count) ||
- !surface_get_gen6_image_sample_count(dev, info, &sample_count) ||
- !surface_get_gen6_image_alignments(dev, info, &alignments))
- return false;
-
- /* no ARYSPC_LOD0 */
- assert(info->img->walk != ILO_IMAGE_WALK_LOD);
- /* no UMS/CMS */
- if (info->img->sample_count > 1)
- assert(info->img->interleaved_samples);
-
- dw0 = info->type << GEN6_SURFACE_DW0_TYPE__SHIFT |
- info->format << GEN6_SURFACE_DW0_FORMAT__SHIFT |
- GEN6_SURFACE_DW0_MIPLAYOUT_BELOW;
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 74:
- *
- * "CUBE_AVERAGE may only be selected if all of the Cube Face Enable
- * fields are equal to one."
- *
- * From the Sandy Bridge PRM, volume 4 part 1, page 75-76:
- *
- * "For SURFTYPE_CUBE Surfaces accessed via the Sampling Engine:
- * Bits 5:0 of this field (Cube Face Enables) enable the individual
- * faces of a cube map. Enabling a face indicates that the face is
- * present in the cube map, while disabling it indicates that that
- * face is represented by the texture map's border color. Refer to
- * Memory Data Formats for the correlation between faces and the cube
- * map memory layout. Note that storage for disabled faces must be
- * provided.
- *
- * For other surfaces:
- * This field is reserved : MBZ"
- *
- * "When TEXCOORDMODE_CLAMP is used when accessing a cube map, this
- * field must be programmed to 111111b (all faces enabled)."
- */
- if (info->type == GEN6_SURFTYPE_CUBE &&
- info->access == ILO_STATE_SURFACE_ACCESS_SAMPLER) {
- dw0 |= GEN6_SURFACE_DW0_CUBE_MAP_CORNER_MODE_AVERAGE |
- GEN6_SURFACE_DW0_CUBE_FACE_ENABLES__MASK;
- }
-
- dw2 = height << GEN6_SURFACE_DW2_HEIGHT__SHIFT |
- width << GEN6_SURFACE_DW2_WIDTH__SHIFT |
- mip_count << GEN6_SURFACE_DW2_MIP_COUNT_LOD__SHIFT;
-
- dw3 = depth << GEN6_SURFACE_DW3_DEPTH__SHIFT |
- (info->img->bo_stride - 1) << GEN6_SURFACE_DW3_PITCH__SHIFT |
- info->img->tiling << GEN6_SURFACE_DW3_TILING__SHIFT;
-
- dw4 = min_lod << GEN6_SURFACE_DW4_MIN_LOD__SHIFT |
- array_base << GEN6_SURFACE_DW4_MIN_ARRAY_ELEMENT__SHIFT |
- view_extent << GEN6_SURFACE_DW4_RT_VIEW_EXTENT__SHIFT |
- sample_count << GEN6_SURFACE_DW4_MULTISAMPLECOUNT__SHIFT;
-
- dw5 = alignments;
-
- STATIC_ASSERT(ARRAY_SIZE(surf->surface) >= 6);
- surf->surface[0] = dw0;
- surf->surface[1] = 0;
- surf->surface[2] = dw2;
- surf->surface[3] = dw3;
- surf->surface[4] = dw4;
- surf->surface[5] = dw5;
-
- surf->type = info->type;
- surf->min_lod = min_lod;
- surf->mip_count = mip_count;
-
- return true;
-}
-
-static bool
-surface_set_gen7_image_SURFACE_STATE(struct ilo_state_surface *surf,
- const struct ilo_dev *dev,
- const struct ilo_state_surface_image_info *info)
-{
- uint16_t width, height, depth, array_base, view_extent;
- uint8_t min_lod, mip_count;
- uint32_t alignments;
- enum gen_sample_count sample_count;
- uint32_t dw0, dw1, dw2, dw3, dw4, dw5, dw7;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- if (!surface_validate_gen6_image(dev, info) ||
- !surface_get_gen6_image_extent(dev, info, &width, &height) ||
- !surface_get_gen6_image_slices(dev, info, &depth, &array_base,
- &view_extent) ||
- !surface_get_gen6_image_levels(dev, info, &min_lod, &mip_count) ||
- !surface_get_gen6_image_sample_count(dev, info, &sample_count) ||
- !surface_get_gen6_image_alignments(dev, info, &alignments))
- return false;
-
- dw0 = info->type << GEN7_SURFACE_DW0_TYPE__SHIFT |
- info->format << GEN7_SURFACE_DW0_FORMAT__SHIFT |
- alignments;
-
- if (info->is_array)
- dw0 |= GEN7_SURFACE_DW0_IS_ARRAY;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- dw0 |= info->img->tiling << GEN8_SURFACE_DW0_TILING__SHIFT;
- } else {
- dw0 |= info->img->tiling << GEN7_SURFACE_DW0_TILING__SHIFT;
-
- if (info->img->walk == ILO_IMAGE_WALK_LOD)
- dw0 |= GEN7_SURFACE_DW0_ARYSPC_LOD0;
- else
- dw0 |= GEN7_SURFACE_DW0_ARYSPC_FULL;
- }
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 67:
- *
- * "For SURFTYPE_CUBE Surfaces accessed via the Sampling Engine: Bits
- * 5:0 of this field (Cube Face Enables) enable the individual faces
- * of a cube map. Enabling a face indicates that the face is present
- * in the cube map, while disabling it indicates that that face is
- * represented by the texture map's border color. Refer to Memory Data
- * Formats for the correlation between faces and the cube map memory
- * layout. Note that storage for disabled faces must be provided. For
- * other surfaces this field is reserved and MBZ."
- *
- * "When TEXCOORDMODE_CLAMP is used when accessing a cube map, this
- * field must be programmed to 111111b (all faces enabled). This field
- * is ignored unless the Surface Type is SURFTYPE_CUBE."
- */
- if (info->type == GEN6_SURFTYPE_CUBE &&
- info->access == ILO_STATE_SURFACE_ACCESS_SAMPLER)
- dw0 |= GEN7_SURFACE_DW0_CUBE_FACE_ENABLES__MASK;
-
- dw1 = 0;
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- assert(info->img->walk_layer_height % 4 == 0);
- dw1 |= info->img->walk_layer_height / 4 <<
- GEN8_SURFACE_DW1_QPITCH__SHIFT;
- }
-
- dw2 = height << GEN7_SURFACE_DW2_HEIGHT__SHIFT |
- width << GEN7_SURFACE_DW2_WIDTH__SHIFT;
-
- dw3 = depth << GEN7_SURFACE_DW3_DEPTH__SHIFT |
- (info->img->bo_stride - 1) << GEN7_SURFACE_DW3_PITCH__SHIFT;
-
- if (ilo_dev_gen(dev) == ILO_GEN(7.5))
- dw3 |= 0 << GEN75_SURFACE_DW3_INTEGER_SURFACE_FORMAT__SHIFT;
-
- dw4 = array_base << GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT__SHIFT |
- view_extent << GEN7_SURFACE_DW4_RT_VIEW_EXTENT__SHIFT |
- sample_count << GEN7_SURFACE_DW4_MULTISAMPLECOUNT__SHIFT;
-
- /*
- * MSFMT_MSS means the samples are not interleaved and MSFMT_DEPTH_STENCIL
- * means the samples are interleaved. The layouts are the same when the
- * number of samples is 1.
- */
- if (info->img->interleaved_samples && info->img->sample_count > 1) {
- assert(info->access != ILO_STATE_SURFACE_ACCESS_DP_RENDER);
- dw4 |= GEN7_SURFACE_DW4_MSFMT_DEPTH_STENCIL;
- } else {
- dw4 |= GEN7_SURFACE_DW4_MSFMT_MSS;
- }
-
- dw5 = min_lod << GEN7_SURFACE_DW5_MIN_LOD__SHIFT |
- mip_count << GEN7_SURFACE_DW5_MIP_COUNT_LOD__SHIFT;
-
- dw7 = 0;
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5)) {
- dw7 |= GEN_SHIFT32(GEN75_SCS_RED, GEN75_SURFACE_DW7_SCS_R) |
- GEN_SHIFT32(GEN75_SCS_GREEN, GEN75_SURFACE_DW7_SCS_G) |
- GEN_SHIFT32(GEN75_SCS_BLUE, GEN75_SURFACE_DW7_SCS_B) |
- GEN_SHIFT32(GEN75_SCS_ALPHA, GEN75_SURFACE_DW7_SCS_A);
- }
-
- STATIC_ASSERT(ARRAY_SIZE(surf->surface) >= 13);
- surf->surface[0] = dw0;
- surf->surface[1] = dw1;
- surf->surface[2] = dw2;
- surf->surface[3] = dw3;
- surf->surface[4] = dw4;
- surf->surface[5] = dw5;
- surf->surface[6] = 0;
- surf->surface[7] = dw7;
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- surf->surface[8] = 0;
- surf->surface[9] = 0;
- surf->surface[10] = 0;
- surf->surface[11] = 0;
- surf->surface[12] = 0;
- }
-
- surf->type = info->type;
- surf->min_lod = min_lod;
- surf->mip_count = mip_count;
-
- return true;
-}
-
-uint32_t
-ilo_state_surface_buffer_size(const struct ilo_dev *dev,
- enum ilo_state_surface_access access,
- uint32_t size, uint32_t *alignment)
-{
- switch (access) {
- case ILO_STATE_SURFACE_ACCESS_SAMPLER:
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 118:
- *
- * "For buffers, which have no inherent "height," padding
- * requirements are different. A buffer must be padded to the next
- * multiple of 256 array elements, with an additional 16 bytes
- * added beyond that to account for the L1 cache line."
- *
- * Assuming tightly packed GEN6_FORMAT_R32G32B32A32_FLOAT, the size
- * needs to be padded to 4096 (= 16 * 256).
- */
- *alignment = 1;
- size = align(size, 4096) + 16;
- break;
- case ILO_STATE_SURFACE_ACCESS_DP_RENDER:
- case ILO_STATE_SURFACE_ACCESS_DP_TYPED:
- /* element-size aligned for worst cases */
- *alignment = 16;
- break;
- case ILO_STATE_SURFACE_ACCESS_DP_UNTYPED:
- /* DWord aligned? */
- *alignment = 4;
- break;
- case ILO_STATE_SURFACE_ACCESS_DP_DATA:
- /* OWord aligned */
- *alignment = 16;
- size = align(size, 16);
- break;
- case ILO_STATE_SURFACE_ACCESS_DP_SVB:
- /* always DWord aligned */
- *alignment = 4;
- break;
- default:
- assert(!"unknown access");
- *alignment = 1;
- break;
- }
-
- return size;
-}
-
-bool
-ilo_state_surface_init_for_null(struct ilo_state_surface *surf,
- const struct ilo_dev *dev)
-{
- bool ret = true;
-
- assert(ilo_is_zeroed(surf, sizeof(*surf)));
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- ret &= surface_set_gen7_null_SURFACE_STATE(surf, dev);
- else
- ret &= surface_set_gen6_null_SURFACE_STATE(surf, dev);
-
- surf->vma = NULL;
- surf->type = GEN6_SURFTYPE_NULL;
- surf->readonly = true;
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_surface_init_for_buffer(struct ilo_state_surface *surf,
- const struct ilo_dev *dev,
- const struct ilo_state_surface_buffer_info *info)
-{
- bool ret = true;
-
- assert(ilo_is_zeroed(surf, sizeof(*surf)));
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- ret &= surface_set_gen7_buffer_SURFACE_STATE(surf, dev, info);
- else
- ret &= surface_set_gen6_buffer_SURFACE_STATE(surf, dev, info);
-
- surf->vma = info->vma;
- surf->readonly = info->readonly;
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_surface_init_for_image(struct ilo_state_surface *surf,
- const struct ilo_dev *dev,
- const struct ilo_state_surface_image_info *info)
-{
- bool ret = true;
-
- assert(ilo_is_zeroed(surf, sizeof(*surf)));
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- ret &= surface_set_gen7_image_SURFACE_STATE(surf, dev, info);
- else
- ret &= surface_set_gen6_image_SURFACE_STATE(surf, dev, info);
-
- surf->vma = info->vma;
- surf->aux_vma = info->aux_vma;
-
- surf->is_integer = info->is_integer;
- surf->readonly = info->readonly;
- surf->scanout = info->img->scanout;
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_surface_set_scs(struct ilo_state_surface *surf,
- const struct ilo_dev *dev,
- enum gen_surface_scs rgba[4])
-{
- const uint32_t scs = GEN_SHIFT32(rgba[0], GEN75_SURFACE_DW7_SCS_R) |
- GEN_SHIFT32(rgba[1], GEN75_SURFACE_DW7_SCS_G) |
- GEN_SHIFT32(rgba[2], GEN75_SURFACE_DW7_SCS_B) |
- GEN_SHIFT32(rgba[3], GEN75_SURFACE_DW7_SCS_A);
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(ilo_dev_gen(dev) >= ILO_GEN(7.5));
-
- surf->surface[7] = (surf->surface[7] & ~GEN75_SURFACE_DW7_SCS__MASK) | scs;
-
- return true;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_STATE_SURFACE_H
-#define ILO_STATE_SURFACE_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-
-enum ilo_state_surface_access {
- ILO_STATE_SURFACE_ACCESS_SAMPLER, /* sampling engine surfaces */
- ILO_STATE_SURFACE_ACCESS_DP_RENDER, /* render target surfaces */
- ILO_STATE_SURFACE_ACCESS_DP_TYPED, /* typed surfaces */
- ILO_STATE_SURFACE_ACCESS_DP_UNTYPED, /* untyped surfaces */
- ILO_STATE_SURFACE_ACCESS_DP_DATA,
- ILO_STATE_SURFACE_ACCESS_DP_SVB,
-};
-
-struct ilo_vma;
-struct ilo_image;
-
-struct ilo_state_surface_buffer_info {
- const struct ilo_vma *vma;
- uint32_t offset;
- uint32_t size;
-
- enum ilo_state_surface_access access;
-
- /* format_size may be less than, equal to, or greater than struct_size */
- enum gen_surface_format format;
- uint8_t format_size;
-
- bool readonly;
- uint16_t struct_size;
-};
-
-struct ilo_state_surface_image_info {
- const struct ilo_image *img;
- uint8_t level_base;
- uint8_t level_count;
- uint16_t slice_base;
- uint16_t slice_count;
-
- const struct ilo_vma *vma;
- const struct ilo_vma *aux_vma;
-
- enum ilo_state_surface_access access;
-
- enum gen_surface_type type;
-
- enum gen_surface_format format;
- bool is_integer;
-
- bool readonly;
- bool is_array;
-};
-
-struct ilo_state_surface {
- uint32_t surface[13];
-
- const struct ilo_vma *vma;
- const struct ilo_vma *aux_vma;
-
- enum gen_surface_type type;
- uint8_t min_lod;
- uint8_t mip_count;
- bool is_integer;
-
- bool readonly;
- bool scanout;
-};
-
-bool
-ilo_state_surface_valid_format(const struct ilo_dev *dev,
- enum ilo_state_surface_access access,
- enum gen_surface_format format);
-
-uint32_t
-ilo_state_surface_buffer_size(const struct ilo_dev *dev,
- enum ilo_state_surface_access access,
- uint32_t size, uint32_t *alignment);
-
-bool
-ilo_state_surface_init_for_null(struct ilo_state_surface *surf,
- const struct ilo_dev *dev);
-
-bool
-ilo_state_surface_init_for_buffer(struct ilo_state_surface *surf,
- const struct ilo_dev *dev,
- const struct ilo_state_surface_buffer_info *info);
-
-bool
-ilo_state_surface_init_for_image(struct ilo_state_surface *surf,
- const struct ilo_dev *dev,
- const struct ilo_state_surface_image_info *info);
-
-bool
-ilo_state_surface_set_scs(struct ilo_state_surface *surf,
- const struct ilo_dev *dev,
- enum gen_surface_scs rgba[4]);
-
-#endif /* ILO_STATE_SURFACE_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "genhw/genhw.h"
-#include "ilo_state_surface.h"
-
-static bool
-surface_valid_sampler_format(const struct ilo_dev *dev,
- enum ilo_state_surface_access access,
- enum gen_surface_format format)
-{
- /*
- * This table is based on:
- *
- * - the Sandy Bridge PRM, volume 4 part 1, page 88-97
- * - the Ivy Bridge PRM, volume 4 part 1, page 84-87
- */
- static const struct sampler_cap {
- int sampling;
- int filtering;
- int shadow_map;
- int chroma_key;
- } caps[] = {
-#define CAP(sampling, filtering, shadow_map, chroma_key) \
- { ILO_GEN(sampling), ILO_GEN(filtering), ILO_GEN(shadow_map), ILO_GEN(chroma_key) }
- [GEN6_FORMAT_R32G32B32A32_FLOAT] = CAP( 1, 5, 0, 0),
- [GEN6_FORMAT_R32G32B32A32_SINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R32G32B32A32_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R32G32B32X32_FLOAT] = CAP( 1, 5, 0, 0),
- [GEN6_FORMAT_R32G32B32_FLOAT] = CAP( 1, 5, 0, 0),
- [GEN6_FORMAT_R32G32B32_SINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R32G32B32_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R16G16B16A16_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R16G16B16A16_SNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R16G16B16A16_SINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R16G16B16A16_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R16G16B16A16_FLOAT] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R32G32_FLOAT] = CAP( 1, 5, 0, 0),
- [GEN6_FORMAT_R32G32_SINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R32G32_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R32_FLOAT_X8X24_TYPELESS] = CAP( 1, 5, 1, 0),
- [GEN6_FORMAT_X32_TYPELESS_G8X24_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_L32A32_FLOAT] = CAP( 1, 5, 0, 0),
- [GEN6_FORMAT_R16G16B16X16_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R16G16B16X16_FLOAT] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_A32X32_FLOAT] = CAP( 1, 5, 0, 0),
- [GEN6_FORMAT_L32X32_FLOAT] = CAP( 1, 5, 0, 0),
- [GEN6_FORMAT_I32X32_FLOAT] = CAP( 1, 5, 0, 0),
- [GEN6_FORMAT_B8G8R8A8_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_B8G8R8A8_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R10G10B10A2_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R10G10B10A2_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R10G10B10A2_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R10G10B10_SNORM_A2_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R8G8B8A8_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R8G8B8A8_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R8G8B8A8_SNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R8G8B8A8_SINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R8G8B8A8_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R16G16_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R16G16_SNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R16G16_SINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R16G16_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R16G16_FLOAT] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_B10G10R10A2_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_B10G10R10A2_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R11G11B10_FLOAT] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R32_SINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R32_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R32_FLOAT] = CAP( 1, 5, 1, 0),
- [GEN6_FORMAT_R24_UNORM_X8_TYPELESS] = CAP( 1, 5, 1, 0),
- [GEN6_FORMAT_X24_TYPELESS_G8_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_L16A16_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_I24X8_UNORM] = CAP( 1, 5, 1, 0),
- [GEN6_FORMAT_L24X8_UNORM] = CAP( 1, 5, 1, 0),
- [GEN6_FORMAT_A24X8_UNORM] = CAP( 1, 5, 1, 0),
- [GEN6_FORMAT_I32_FLOAT] = CAP( 1, 5, 1, 0),
- [GEN6_FORMAT_L32_FLOAT] = CAP( 1, 5, 1, 0),
- [GEN6_FORMAT_A32_FLOAT] = CAP( 1, 5, 1, 0),
- [GEN6_FORMAT_B8G8R8X8_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_B8G8R8X8_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R8G8B8X8_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R8G8B8X8_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R9G9B9E5_SHAREDEXP] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_B10G10R10X2_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_L16A16_FLOAT] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_B5G6R5_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_B5G6R5_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_B5G5R5A1_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_B5G5R5A1_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_B4G4R4A4_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_B4G4R4A4_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R8G8_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R8G8_SNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_R8G8_SINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R8G8_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R16_UNORM] = CAP( 1, 1, 1, 0),
- [GEN6_FORMAT_R16_SNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R16_SINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R16_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R16_FLOAT] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_A8P8_UNORM_PALETTE0] = CAP( 5, 5, 0, 0),
- [GEN6_FORMAT_A8P8_UNORM_PALETTE1] = CAP( 5, 5, 0, 0),
- [GEN6_FORMAT_I16_UNORM] = CAP( 1, 1, 1, 0),
- [GEN6_FORMAT_L16_UNORM] = CAP( 1, 1, 1, 0),
- [GEN6_FORMAT_A16_UNORM] = CAP( 1, 1, 1, 0),
- [GEN6_FORMAT_L8A8_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_I16_FLOAT] = CAP( 1, 1, 1, 0),
- [GEN6_FORMAT_L16_FLOAT] = CAP( 1, 1, 1, 0),
- [GEN6_FORMAT_A16_FLOAT] = CAP( 1, 1, 1, 0),
- [GEN6_FORMAT_L8A8_UNORM_SRGB] = CAP(4.5, 4.5, 0, 0),
- [GEN6_FORMAT_R5G5_SNORM_B6_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_P8A8_UNORM_PALETTE0] = CAP( 5, 5, 0, 0),
- [GEN6_FORMAT_P8A8_UNORM_PALETTE1] = CAP( 5, 5, 0, 0),
- [GEN6_FORMAT_R8_UNORM] = CAP( 1, 1, 0, 4.5),
- [GEN6_FORMAT_R8_SNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R8_SINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R8_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_A8_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_I8_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_L8_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_P4A4_UNORM_PALETTE0] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_A4P4_UNORM_PALETTE0] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_P8_UNORM_PALETTE0] = CAP(4.5, 4.5, 0, 0),
- [GEN6_FORMAT_L8_UNORM_SRGB] = CAP(4.5, 4.5, 0, 0),
- [GEN6_FORMAT_P8_UNORM_PALETTE1] = CAP(4.5, 4.5, 0, 0),
- [GEN6_FORMAT_P4A4_UNORM_PALETTE1] = CAP(4.5, 4.5, 0, 0),
- [GEN6_FORMAT_A4P4_UNORM_PALETTE1] = CAP(4.5, 4.5, 0, 0),
- [GEN6_FORMAT_DXT1_RGB_SRGB] = CAP(4.5, 4.5, 0, 0),
- [GEN6_FORMAT_R1_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_YCRCB_NORMAL] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_YCRCB_SWAPUVY] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_P2_UNORM_PALETTE0] = CAP(4.5, 4.5, 0, 0),
- [GEN6_FORMAT_P2_UNORM_PALETTE1] = CAP(4.5, 4.5, 0, 0),
- [GEN6_FORMAT_BC1_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_BC2_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_BC3_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_BC4_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_BC5_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_BC1_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_BC2_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_BC3_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_MONO8] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_YCRCB_SWAPUV] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_YCRCB_SWAPY] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_DXT1_RGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_FXT1] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_BC4_SNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_BC5_SNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R16G16B16_FLOAT] = CAP( 5, 5, 0, 0),
- [GEN6_FORMAT_BC6H_SF16] = CAP( 7, 7, 0, 0),
- [GEN6_FORMAT_BC7_UNORM] = CAP( 7, 7, 0, 0),
- [GEN6_FORMAT_BC7_UNORM_SRGB] = CAP( 7, 7, 0, 0),
- [GEN6_FORMAT_BC6H_UF16] = CAP( 7, 7, 0, 0),
-#undef CAP
- };
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- return (format < ARRAY_SIZE(caps) && caps[format].sampling &&
- ilo_dev_gen(dev) >= caps[format].sampling);
-}
-
-static bool
-surface_valid_dp_format(const struct ilo_dev *dev,
- enum ilo_state_surface_access access,
- enum gen_surface_format format)
-{
- /*
- * This table is based on:
- *
- * - the Sandy Bridge PRM, volume 4 part 1, page 88-97
- * - the Ivy Bridge PRM, volume 4 part 1, page 172, 252-253, and 277-278
- * - the Haswell PRM, volume 7, page 262-264
- */
- static const struct dp_cap {
- int rt_write;
- int rt_write_blending;
- int typed_write;
- int media_color_processing;
- } caps[] = {
-#define CAP(rt_write, rt_write_blending, typed_write, media_color_processing) \
- { ILO_GEN(rt_write), ILO_GEN(rt_write_blending), ILO_GEN(typed_write), ILO_GEN(media_color_processing) }
- [GEN6_FORMAT_R32G32B32A32_FLOAT] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_R32G32B32A32_SINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R32G32B32A32_UINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R16G16B16A16_UNORM] = CAP( 1, 4.5, 7, 6),
- [GEN6_FORMAT_R16G16B16A16_SNORM] = CAP( 1, 6, 7, 0),
- [GEN6_FORMAT_R16G16B16A16_SINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R16G16B16A16_UINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R16G16B16A16_FLOAT] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_R32G32_FLOAT] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_R32G32_SINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R32G32_UINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_B8G8R8A8_UNORM] = CAP( 1, 1, 7, 6),
- [GEN6_FORMAT_B8G8R8A8_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R10G10B10A2_UNORM] = CAP( 1, 1, 7, 6),
- [GEN6_FORMAT_R10G10B10A2_UNORM_SRGB] = CAP( 0, 0, 0, 6),
- [GEN6_FORMAT_R10G10B10A2_UINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R8G8B8A8_UNORM] = CAP( 1, 1, 7, 6),
- [GEN6_FORMAT_R8G8B8A8_UNORM_SRGB] = CAP( 1, 1, 0, 6),
- [GEN6_FORMAT_R8G8B8A8_SNORM] = CAP( 1, 6, 7, 0),
- [GEN6_FORMAT_R8G8B8A8_SINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R8G8B8A8_UINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R16G16_UNORM] = CAP( 1, 4.5, 7, 0),
- [GEN6_FORMAT_R16G16_SNORM] = CAP( 1, 6, 7, 0),
- [GEN6_FORMAT_R16G16_SINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R16G16_UINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R16G16_FLOAT] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_B10G10R10A2_UNORM] = CAP( 1, 1, 7, 6),
- [GEN6_FORMAT_B10G10R10A2_UNORM_SRGB] = CAP( 1, 1, 0, 6),
- [GEN6_FORMAT_R11G11B10_FLOAT] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_R32_SINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R32_UINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R32_FLOAT] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_B8G8R8X8_UNORM] = CAP( 0, 0, 0, 6),
- [GEN6_FORMAT_B5G6R5_UNORM] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_B5G6R5_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_B5G5R5A1_UNORM] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_B5G5R5A1_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_B4G4R4A4_UNORM] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_B4G4R4A4_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R8G8_UNORM] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_R8G8_SNORM] = CAP( 1, 6, 7, 0),
- [GEN6_FORMAT_R8G8_SINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R8G8_UINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R16_UNORM] = CAP( 1, 4.5, 7, 7),
- [GEN6_FORMAT_R16_SNORM] = CAP( 1, 6, 7, 0),
- [GEN6_FORMAT_R16_SINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R16_UINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R16_FLOAT] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_B5G5R5X1_UNORM] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_B5G5R5X1_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R8_UNORM] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_R8_SNORM] = CAP( 1, 6, 7, 0),
- [GEN6_FORMAT_R8_SINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R8_UINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_A8_UNORM] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_YCRCB_NORMAL] = CAP( 1, 0, 0, 6),
- [GEN6_FORMAT_YCRCB_SWAPUVY] = CAP( 1, 0, 0, 6),
- [GEN6_FORMAT_YCRCB_SWAPUV] = CAP( 1, 0, 0, 6),
- [GEN6_FORMAT_YCRCB_SWAPY] = CAP( 1, 0, 0, 6),
-#undef CAP
- };
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (format >= ARRAY_SIZE(caps))
- return false;
-
- switch (access) {
- case ILO_STATE_SURFACE_ACCESS_DP_RENDER:
- return (caps[format].rt_write &&
- ilo_dev_gen(dev) >= caps[format].rt_write);
- case ILO_STATE_SURFACE_ACCESS_DP_TYPED:
- return (caps[format].typed_write &&
- ilo_dev_gen(dev) >= caps[format].typed_write);
- case ILO_STATE_SURFACE_ACCESS_DP_UNTYPED:
- return (format == GEN6_FORMAT_RAW);
- case ILO_STATE_SURFACE_ACCESS_DP_DATA:
- /* ignored, but can it be raw? */
- assert(format != GEN6_FORMAT_RAW);
- return true;
- default:
- return false;
- }
-}
-
-static bool
-surface_valid_svb_format(const struct ilo_dev *dev,
- enum gen_surface_format format)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * This table is based on:
- *
- * - the Sandy Bridge PRM, volume 4 part 1, page 88-97
- * - the Ivy Bridge PRM, volume 2 part 1, page 195
- * - the Haswell PRM, volume 7, page 535
- */
- switch (format) {
- case GEN6_FORMAT_R32G32B32A32_FLOAT:
- case GEN6_FORMAT_R32G32B32A32_SINT:
- case GEN6_FORMAT_R32G32B32A32_UINT:
- case GEN6_FORMAT_R32G32B32_FLOAT:
- case GEN6_FORMAT_R32G32B32_SINT:
- case GEN6_FORMAT_R32G32B32_UINT:
- case GEN6_FORMAT_R32G32_FLOAT:
- case GEN6_FORMAT_R32G32_SINT:
- case GEN6_FORMAT_R32G32_UINT:
- case GEN6_FORMAT_R32_SINT:
- case GEN6_FORMAT_R32_UINT:
- case GEN6_FORMAT_R32_FLOAT:
- return true;
- default:
- return false;
- }
-}
-
-bool
-ilo_state_surface_valid_format(const struct ilo_dev *dev,
- enum ilo_state_surface_access access,
- enum gen_surface_format format)
-{
- bool valid;
-
- switch (access) {
- case ILO_STATE_SURFACE_ACCESS_SAMPLER:
- valid = surface_valid_sampler_format(dev, access, format);
- break;
- case ILO_STATE_SURFACE_ACCESS_DP_RENDER:
- case ILO_STATE_SURFACE_ACCESS_DP_TYPED:
- case ILO_STATE_SURFACE_ACCESS_DP_UNTYPED:
- case ILO_STATE_SURFACE_ACCESS_DP_DATA:
- valid = surface_valid_dp_format(dev, access, format);
- break;
- case ILO_STATE_SURFACE_ACCESS_DP_SVB:
- valid = surface_valid_svb_format(dev, format);
- break;
- default:
- valid = false;
- break;
- }
-
- return valid;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-#include "ilo_state_urb.h"
-
-struct urb_configuration {
- uint8_t vs_pcb_alloc_kb;
- uint8_t hs_pcb_alloc_kb;
- uint8_t ds_pcb_alloc_kb;
- uint8_t gs_pcb_alloc_kb;
- uint8_t ps_pcb_alloc_kb;
-
- uint8_t urb_offset_8kb;
-
- uint8_t vs_urb_alloc_8kb;
- uint8_t hs_urb_alloc_8kb;
- uint8_t ds_urb_alloc_8kb;
- uint8_t gs_urb_alloc_8kb;
-
- uint8_t vs_entry_rows;
- uint8_t hs_entry_rows;
- uint8_t ds_entry_rows;
- uint8_t gs_entry_rows;
-
- int vs_entry_count;
- int hs_entry_count;
- int ds_entry_count;
- int gs_entry_count;
-};
-
-static void
-urb_alloc_gen7_pcb(const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info,
- struct urb_configuration *conf)
-{
- /*
- * From the Haswell PRM, volume 2b, page 940:
- *
- * "[0,16] (0KB - 16KB) Increments of 1KB DevHSW:GT1, DevHSW:GT2
- * [0,32] (0KB - 32KB) Increments of 2KB DevHSW:GT3"
- */
- const uint8_t increment_kb =
- (ilo_dev_gen(dev) >= ILO_GEN(8) ||
- (ilo_dev_gen(dev) == ILO_GEN(7.5) && dev->gt == 3)) ? 2 : 1;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- /*
- * Keep the strategy simple as we do not know the workloads and how
- * expensive it is to change the configuration frequently.
- */
- if (info->hs_const_data || info->ds_const_data) {
- conf->vs_pcb_alloc_kb = increment_kb * 4;
- conf->hs_pcb_alloc_kb = increment_kb * 3;
- conf->ds_pcb_alloc_kb = increment_kb * 3;
- conf->gs_pcb_alloc_kb = increment_kb * 3;
- conf->ps_pcb_alloc_kb = increment_kb * 3;
- } else if (info->gs_const_data) {
- conf->vs_pcb_alloc_kb = increment_kb * 6;
- conf->gs_pcb_alloc_kb = increment_kb * 5;
- conf->ps_pcb_alloc_kb = increment_kb * 5;
- } else {
- conf->vs_pcb_alloc_kb = increment_kb * 8;
- conf->ps_pcb_alloc_kb = increment_kb * 8;
- }
-
- conf->urb_offset_8kb = increment_kb * 16 / 8;
-}
-
-static void
-urb_alloc_gen6_urb(const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info,
- struct urb_configuration *conf)
-{
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 34:
- *
- * "(VS URB Starting Address) Offset from the start of the URB memory
- * where VS starts its allocation, specified in multiples of 8 KB."
- *
- * Same for other stages.
- */
- const int space_avail_8kb = dev->urb_size / 8192 - conf->urb_offset_8kb;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 173:
- *
- * "Programming Note: If the GS stage is enabled, software must always
- * allocate at least one GS URB Entry. This is true even if the GS
- * thread never needs to output vertices to the urb, e.g., when only
- * performing stream output. This is an artifact of the need to pass
- * the GS thread an initial destination URB handle."
- */
- const bool force_gs_alloc =
- (ilo_dev_gen(dev) == ILO_GEN(6) && info->gs_enable);
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (info->hs_entry_size || info->ds_entry_size) {
- conf->vs_urb_alloc_8kb = space_avail_8kb / 4;
- conf->hs_urb_alloc_8kb = space_avail_8kb / 4;
- conf->ds_urb_alloc_8kb = space_avail_8kb / 4;
- conf->gs_urb_alloc_8kb = space_avail_8kb / 4;
-
- if (space_avail_8kb % 4) {
- assert(space_avail_8kb % 2 == 0);
- conf->vs_urb_alloc_8kb++;
- conf->gs_urb_alloc_8kb++;
- }
- } else if (info->gs_entry_size || force_gs_alloc) {
- assert(space_avail_8kb % 2 == 0);
- conf->vs_urb_alloc_8kb = space_avail_8kb / 2;
- conf->gs_urb_alloc_8kb = space_avail_8kb / 2;
- } else {
- conf->vs_urb_alloc_8kb = space_avail_8kb;
- }
-}
-
-static bool
-urb_init_gen6_vs_entry(const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info,
- struct urb_configuration *conf)
-{
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 28:
- *
- * "(VS URB Entry Allocation Size)
- * Range [0,4] = [1,5] 1024-bit URB rows"
- *
- * "(VS Number of URB Entries)
- * Range [24,256] in multiples of 4
- * [24, 128] in multiples of 4[DevSNBGT1]"
- */
- const int max_entry_count = (dev->gt == 2) ? 256 : 252;
- const int row_size = 1024 / 8;
- int row_count, entry_count;
- int entry_size;
-
- ILO_DEV_ASSERT(dev, 6, 6);
-
- /* VE and VS share the same VUE for each vertex */
- entry_size = info->vs_entry_size;
- if (entry_size < info->ve_entry_size)
- entry_size = info->ve_entry_size;
-
- row_count = (entry_size + row_size - 1) / row_size;
- if (row_count > 5)
- return false;
- else if (!row_count)
- row_count++;
-
- entry_count = conf->vs_urb_alloc_8kb * 8192 / (row_size * row_count);
- if (entry_count > max_entry_count)
- entry_count = max_entry_count;
- entry_count &= ~3;
- assert(entry_count >= 24);
-
- conf->vs_entry_rows = row_count;
- conf->vs_entry_count = entry_count;
-
- return true;
-}
-
-static bool
-urb_init_gen6_gs_entry(const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info,
- struct urb_configuration *conf)
-{
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 29:
- *
- * "(GS Number of URB Entries)
- * Range [0,256] in multiples of 4
- * [0, 254] in multiples of 4[DevSNBGT1]"
- *
- * "(GS URB Entry Allocation Size)
- * Range [0,4] = [1,5] 1024-bit URB rows"
- */
- const int max_entry_count = (dev->gt == 2) ? 256 : 252;
- const int row_size = 1024 / 8;
- int row_count, entry_count;
-
- ILO_DEV_ASSERT(dev, 6, 6);
-
- row_count = (info->gs_entry_size + row_size - 1) / row_size;
- if (row_count > 5)
- return false;
- else if (!row_count)
- row_count++;
-
- entry_count = conf->gs_urb_alloc_8kb * 8192 / (row_size * row_count);
- if (entry_count > max_entry_count)
- entry_count = max_entry_count;
- entry_count &= ~3;
-
- conf->gs_entry_rows = row_count;
- conf->gs_entry_count = entry_count;
-
- return true;
-}
-
-static bool
-urb_init_gen7_vs_entry(const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info,
- struct urb_configuration *conf)
-{
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 34-35:
- *
- * "VS URB Entry Allocation Size equal to 4(5 512-bit URB rows) may
- * cause performance to decrease due to banking in the URB. Element
- * sizes of 16 to 20 should be programmed with six 512-bit URB rows."
- *
- * "(VS URB Entry Allocation Size)
- * Format: U9-1 count of 512-bit units"
- *
- * "(VS Number of URB Entries)
- * [32,704]
- * [32,512]
- *
- * Programming Restriction: VS Number of URB Entries must be divisible
- * by 8 if the VS URB Entry Allocation Size is less than 9 512-bit URB
- * entries."2:0" = reserved "000b""
- *
- * From the Haswell PRM, volume 2b, page 847:
- *
- * "(VS Number of URB Entries)
- * [64,1664] DevHSW:GT3
- * [64,1664] DevHSW:GT2
- * [32,640] DevHSW:GT1"
- */
- const int row_size = 512 / 8;
- int row_count, entry_count;
- int entry_size;
- int max_entry_count, min_entry_count;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 35:
- *
- * "Programming Restriction: As the VS URB entry serves as both the
- * per-vertex input and output of the VS shader, the VS URB Allocation
- * Size must be sized to the maximum of the vertex input and output
- * structures."
- *
- * From the Ivy Bridge PRM, volume 2 part 1, page 42:
- *
- * "If the VS function is enabled, the VF-written VUEs are not required
- * to have Vertex Headers, as the VS-incoming vertices are guaranteed
- * to be consumed by the VS (i.e., the VS thread is responsible for
- * overwriting the input vertex data)."
- *
- * VE and VS share the same VUE for each vertex.
- */
- entry_size = info->vs_entry_size;
- if (entry_size < info->ve_entry_size)
- entry_size = info->ve_entry_size;
-
- row_count = (entry_size + row_size - 1) / row_size;
- if (row_count == 5 || !row_count)
- row_count++;
-
- entry_count = conf->vs_urb_alloc_8kb * 8192 / (row_size * row_count);
- if (row_count < 9)
- entry_count &= ~7;
-
- switch (ilo_dev_gen(dev)) {
- case ILO_GEN(8):
- case ILO_GEN(7.5):
- max_entry_count = (dev->gt >= 2) ? 1664 : 640;
- min_entry_count = (dev->gt >= 2) ? 64 : 32;
- break;
- case ILO_GEN(7):
- max_entry_count = (dev->gt == 2) ? 704 : 512;
- min_entry_count = 32;
- break;
- default:
- assert(!"unexpected gen");
- return false;
- break;
- }
-
- if (entry_count > max_entry_count)
- entry_count = max_entry_count;
- else if (entry_count < min_entry_count)
- return false;
-
- conf->vs_entry_rows = row_count;
- conf->vs_entry_count = entry_count;
-
- return true;
-}
-
-static bool
-urb_init_gen7_hs_entry(const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info,
- struct urb_configuration *conf)
-{
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 37:
- *
- * "HS Number of URB Entries must be divisible by 8 if the HS URB Entry
- * Allocation Size is less than 9 512-bit URB
- * entries."2:0" = reserved "000"
- *
- * [0,64]
- * [0,32]"
- *
- * From the Haswell PRM, volume 2b, page 849:
- *
- * "(HS Number of URB Entries)
- * [0,128] DevHSW:GT2
- * [0,64] DevHSW:GT1"
- */
- const int row_size = 512 / 8;
- int row_count, entry_count;
- int max_entry_count;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- row_count = (info->hs_entry_size + row_size - 1) / row_size;
- if (!row_count)
- row_count++;
-
- entry_count = conf->hs_urb_alloc_8kb * 8192 / (row_size * row_count);
- if (row_count < 9)
- entry_count &= ~7;
-
- switch (ilo_dev_gen(dev)) {
- case ILO_GEN(8):
- case ILO_GEN(7.5):
- max_entry_count = (dev->gt >= 2) ? 128 : 64;
- break;
- case ILO_GEN(7):
- max_entry_count = (dev->gt == 2) ? 64 : 32;
- break;
- default:
- assert(!"unexpected gen");
- return false;
- break;
- }
-
- if (entry_count > max_entry_count)
- entry_count = max_entry_count;
- else if (info->hs_entry_size && !entry_count)
- return false;
-
- conf->hs_entry_rows = row_count;
- conf->hs_entry_count = entry_count;
-
- return true;
-}
-
-static bool
-urb_init_gen7_ds_entry(const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info,
- struct urb_configuration *conf)
-{
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 38:
- *
- * "(DS URB Entry Allocation Size)
- * [0,9]"
- *
- * "(DS Number of URB Entries) If Domain Shader Thread Dispatch is
- * Enabled then the minimum number handles that must be allocated is
- * 138 URB entries.
- * "2:0" = reserved "000"
- *
- * [0,448]
- * [0,288]
- *
- * DS Number of URB Entries must be divisible by 8 if the DS URB Entry
- * Allocation Size is less than 9 512-bit URB entries.If Domain Shader
- * Thread Dispatch is Enabled then the minimum number of handles that
- * must be allocated is 10 URB entries."
- *
- * From the Haswell PRM, volume 2b, page 851:
- *
- * "(DS Number of URB Entries)
- * [0,960] DevHSW:GT2
- * [0,384] DevHSW:GT1"
- */
- const int row_size = 512 / 8;
- int row_count, entry_count;
- int max_entry_count;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- row_count = (info->ds_entry_size + row_size - 1) / row_size;
- if (row_count > 10)
- return false;
- else if (!row_count)
- row_count++;
-
- entry_count = conf->ds_urb_alloc_8kb * 8192 / (row_size * row_count);
- if (row_count < 9)
- entry_count &= ~7;
-
- switch (ilo_dev_gen(dev)) {
- case ILO_GEN(8):
- case ILO_GEN(7.5):
- max_entry_count = (dev->gt >= 2) ? 960 : 384;
- break;
- case ILO_GEN(7):
- max_entry_count = (dev->gt == 2) ? 448 : 288;
- break;
- default:
- assert(!"unexpected gen");
- return false;
- break;
- }
-
- if (entry_count > max_entry_count)
- entry_count = max_entry_count;
- else if (info->ds_entry_size && entry_count < 10)
- return false;
-
- conf->ds_entry_rows = row_count;
- conf->ds_entry_count = entry_count;
-
- return true;
-}
-
-static bool
-urb_init_gen7_gs_entry(const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info,
- struct urb_configuration *conf)
-{
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 40:
- *
- * "(GS Number of URB Entries) GS Number of URB Entries must be
- * divisible by 8 if the GS URB Entry Allocation Size is less than 9
- * 512-bit URB entries.
- * "2:0" = reserved "000"
- *
- * [0,320]
- * [0,192]"
- *
- * From the Ivy Bridge PRM, volume 2 part 1, page 171:
- *
- * "(DUAL_INSTANCE and DUAL_OBJECT) The GS must be allocated at least
- * two URB handles or behavior is UNDEFINED."
- *
- * From the Haswell PRM, volume 2b, page 853:
- *
- * "(GS Number of URB Entries)
- * [0,640] DevHSW:GT2
- * [0,256] DevHSW:GT1
- *
- * Only if GS is disabled can this field be programmed to 0. If GS is
- * enabled this field shall be programmed to a value greater than 0.
- * For GS Dispatch Mode "Single", this field shall be programmed to a
- * value greater than or equal to 1. For other GS Dispatch Modes,
- * refer to the definition of Dispatch Mode (3DSTATE_GS) for minimum
- * values of this field."
- */
- const int row_size = 512 / 8;
- int row_count, entry_count;
- int max_entry_count;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- row_count = (info->gs_entry_size + row_size - 1) / row_size;
- if (!row_count)
- row_count++;
-
- entry_count = conf->gs_urb_alloc_8kb * 8192 / (row_size * row_count);
- if (row_count < 9)
- entry_count &= ~7;
-
- switch (ilo_dev_gen(dev)) {
- case ILO_GEN(8):
- case ILO_GEN(7.5):
- max_entry_count = (dev->gt >= 2) ? 640 : 256;
- break;
- case ILO_GEN(7):
- max_entry_count = (dev->gt == 2) ? 320 : 192;
- break;
- default:
- assert(!"unexpected gen");
- return false;
- break;
- }
-
- if (entry_count > max_entry_count)
- entry_count = max_entry_count;
- else if (info->gs_entry_size && entry_count < 2)
- return false;
-
- conf->gs_entry_rows = row_count;
- conf->gs_entry_count = entry_count;
-
- return true;
-}
-
-static bool
-urb_get_gen6_configuration(const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info,
- struct urb_configuration *conf)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- memset(conf, 0, sizeof(*conf));
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- urb_alloc_gen7_pcb(dev, info, conf);
-
- urb_alloc_gen6_urb(dev, info, conf);
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- if (!urb_init_gen7_vs_entry(dev, info, conf) ||
- !urb_init_gen7_hs_entry(dev, info, conf) ||
- !urb_init_gen7_ds_entry(dev, info, conf) ||
- !urb_init_gen7_gs_entry(dev, info, conf))
- return false;
- } else {
- if (!urb_init_gen6_vs_entry(dev, info, conf) ||
- !urb_init_gen6_gs_entry(dev, info, conf))
- return false;
- }
-
- return true;
-}
-
-static bool
-urb_set_gen7_3dstate_push_constant_alloc(struct ilo_state_urb *urb,
- const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info,
- const struct urb_configuration *conf)
-{
- uint32_t dw1[5];
- uint8_t sizes_kb[5], offset_kb;
- int i;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- sizes_kb[0] = conf->vs_pcb_alloc_kb;
- sizes_kb[1] = conf->hs_pcb_alloc_kb;
- sizes_kb[2] = conf->ds_pcb_alloc_kb;
- sizes_kb[3] = conf->gs_pcb_alloc_kb;
- sizes_kb[4] = conf->ps_pcb_alloc_kb;
- offset_kb = 0;
-
- for (i = 0; i < 5; i++) {
- /* careful for the valid range of offsets */
- if (sizes_kb[i]) {
- dw1[i] = offset_kb << GEN7_PCB_ALLOC_DW1_OFFSET__SHIFT |
- sizes_kb[i] << GEN7_PCB_ALLOC_DW1_SIZE__SHIFT;
- offset_kb += sizes_kb[i];
- } else {
- dw1[i] = 0;
- }
- }
-
- STATIC_ASSERT(ARRAY_SIZE(urb->pcb) >= 5);
- memcpy(urb->pcb, dw1, sizeof(dw1));
-
- return true;
-}
-
-static bool
-urb_set_gen6_3DSTATE_URB(struct ilo_state_urb *urb,
- const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info,
- const struct urb_configuration *conf)
-{
- uint32_t dw1, dw2;
-
- ILO_DEV_ASSERT(dev, 6, 6);
-
- assert(conf->vs_entry_rows && conf->gs_entry_rows);
-
- dw1 = (conf->vs_entry_rows - 1) << GEN6_URB_DW1_VS_ENTRY_SIZE__SHIFT |
- conf->vs_entry_count << GEN6_URB_DW1_VS_ENTRY_COUNT__SHIFT;
- dw2 = conf->gs_entry_count << GEN6_URB_DW2_GS_ENTRY_COUNT__SHIFT |
- (conf->gs_entry_rows - 1) << GEN6_URB_DW2_GS_ENTRY_SIZE__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(urb->urb) >= 2);
- urb->urb[0] = dw1;
- urb->urb[1] = dw2;
-
- return true;
-}
-
-static bool
-urb_set_gen7_3dstate_urb(struct ilo_state_urb *urb,
- const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info,
- const struct urb_configuration *conf)
-{
- uint32_t dw1[4];
- struct {
- uint8_t alloc_8kb;
- uint8_t entry_rows;
- int entry_count;
- } stages[4];
- uint8_t offset_8kb;
- int i;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- stages[0].alloc_8kb = conf->vs_urb_alloc_8kb;
- stages[1].alloc_8kb = conf->hs_urb_alloc_8kb;
- stages[2].alloc_8kb = conf->ds_urb_alloc_8kb;
- stages[3].alloc_8kb = conf->gs_urb_alloc_8kb;
-
- stages[0].entry_rows = conf->vs_entry_rows;
- stages[1].entry_rows = conf->hs_entry_rows;
- stages[2].entry_rows = conf->ds_entry_rows;
- stages[3].entry_rows = conf->gs_entry_rows;
-
- stages[0].entry_count = conf->vs_entry_count;
- stages[1].entry_count = conf->hs_entry_count;
- stages[2].entry_count = conf->ds_entry_count;
- stages[3].entry_count = conf->gs_entry_count;
-
- offset_8kb = conf->urb_offset_8kb;
-
- for (i = 0; i < 4; i++) {
- /* careful for the valid range of offsets */
- if (stages[i].alloc_8kb) {
- assert(stages[i].entry_rows);
- dw1[i] =
- offset_8kb << GEN7_URB_DW1_OFFSET__SHIFT |
- (stages[i].entry_rows - 1) << GEN7_URB_DW1_ENTRY_SIZE__SHIFT |
- stages[i].entry_count << GEN7_URB_DW1_ENTRY_COUNT__SHIFT;
- offset_8kb += stages[i].alloc_8kb;
- } else {
- dw1[i] = 0;
- }
- }
-
- STATIC_ASSERT(ARRAY_SIZE(urb->urb) >= 4);
- memcpy(urb->urb, dw1, sizeof(dw1));
-
- return true;
-}
-
-bool
-ilo_state_urb_init(struct ilo_state_urb *urb,
- const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info)
-{
- assert(ilo_is_zeroed(urb, sizeof(*urb)));
- return ilo_state_urb_set_info(urb, dev, info);
-}
-
-bool
-ilo_state_urb_init_for_rectlist(struct ilo_state_urb *urb,
- const struct ilo_dev *dev,
- uint8_t vf_attr_count)
-{
- struct ilo_state_urb_info info;
-
- memset(&info, 0, sizeof(info));
- info.ve_entry_size = sizeof(uint32_t) * 4 * vf_attr_count;
-
- return ilo_state_urb_init(urb, dev, &info);
-}
-
-bool
-ilo_state_urb_set_info(struct ilo_state_urb *urb,
- const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info)
-{
- struct urb_configuration conf;
- bool ret = true;
-
- ret &= urb_get_gen6_configuration(dev, info, &conf);
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- ret &= urb_set_gen7_3dstate_push_constant_alloc(urb, dev, info, &conf);
- ret &= urb_set_gen7_3dstate_urb(urb, dev, info, &conf);
- } else {
- ret &= urb_set_gen6_3DSTATE_URB(urb, dev, info, &conf);
- }
-
- assert(ret);
-
- return ret;
-}
-
-void
-ilo_state_urb_full_delta(const struct ilo_state_urb *urb,
- const struct ilo_dev *dev,
- struct ilo_state_urb_delta *delta)
-{
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- delta->dirty = ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_VS |
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_HS |
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_DS |
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_GS |
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_PS |
- ILO_STATE_URB_3DSTATE_URB_VS |
- ILO_STATE_URB_3DSTATE_URB_HS |
- ILO_STATE_URB_3DSTATE_URB_DS |
- ILO_STATE_URB_3DSTATE_URB_GS;
- } else {
- delta->dirty = ILO_STATE_URB_3DSTATE_URB_VS |
- ILO_STATE_URB_3DSTATE_URB_GS;
- }
-}
-
-void
-ilo_state_urb_get_delta(const struct ilo_state_urb *urb,
- const struct ilo_dev *dev,
- const struct ilo_state_urb *old,
- struct ilo_state_urb_delta *delta)
-{
- delta->dirty = 0;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- if (memcmp(urb->pcb, old->pcb, sizeof(urb->pcb))) {
- delta->dirty |= ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_VS |
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_HS |
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_DS |
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_GS |
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_PS;
- }
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 34:
- *
- * "3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
- * programmed in order for the programming of this state
- * (3DSTATE_URB_VS) to be valid."
- *
- * The same is true for the other three states.
- */
- if (memcmp(urb->urb, old->urb, sizeof(urb->urb))) {
- delta->dirty |= ILO_STATE_URB_3DSTATE_URB_VS |
- ILO_STATE_URB_3DSTATE_URB_HS |
- ILO_STATE_URB_3DSTATE_URB_DS |
- ILO_STATE_URB_3DSTATE_URB_GS;
- }
- } else {
- if (memcmp(urb->urb, old->urb, sizeof(uint32_t) * 2)) {
- delta->dirty |= ILO_STATE_URB_3DSTATE_URB_VS |
- ILO_STATE_URB_3DSTATE_URB_GS;
- }
- }
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_STATE_URB_H
-#define ILO_STATE_URB_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-
-enum ilo_state_urb_dirty_bits {
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_VS = (1 << 0),
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_HS = (1 << 1),
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_DS = (1 << 2),
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_GS = (1 << 3),
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_PS = (1 << 4),
- ILO_STATE_URB_3DSTATE_URB_VS = (1 << 5),
- ILO_STATE_URB_3DSTATE_URB_HS = (1 << 6),
- ILO_STATE_URB_3DSTATE_URB_DS = (1 << 7),
- ILO_STATE_URB_3DSTATE_URB_GS = (1 << 8),
-};
-
-/**
- * URB entry allocation sizes and sizes of constant data extracted from PCBs
- * to threads.
- */
-struct ilo_state_urb_info {
- bool gs_enable;
-
- bool vs_const_data;
- bool hs_const_data;
- bool ds_const_data;
- bool gs_const_data;
- bool ps_const_data;
-
- uint16_t ve_entry_size;
- uint16_t vs_entry_size;
- uint16_t hs_entry_size;
- uint16_t ds_entry_size;
- uint16_t gs_entry_size;
-};
-
-struct ilo_state_urb {
- uint32_t pcb[5];
- uint32_t urb[4];
-};
-
-struct ilo_state_urb_delta {
- uint32_t dirty;
-};
-
-bool
-ilo_state_urb_init(struct ilo_state_urb *urb,
- const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info);
-
-bool
-ilo_state_urb_init_for_rectlist(struct ilo_state_urb *urb,
- const struct ilo_dev *dev,
- uint8_t vf_attr_count);
-
-bool
-ilo_state_urb_set_info(struct ilo_state_urb *urb,
- const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info);
-
-void
-ilo_state_urb_full_delta(const struct ilo_state_urb *urb,
- const struct ilo_dev *dev,
- struct ilo_state_urb_delta *delta);
-
-void
-ilo_state_urb_get_delta(const struct ilo_state_urb *urb,
- const struct ilo_dev *dev,
- const struct ilo_state_urb *old,
- struct ilo_state_urb_delta *delta);
-
-#endif /* ILO_STATE_URB_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-#include "ilo_vma.h"
-#include "ilo_state_vf.h"
-
-static bool
-vf_validate_gen6_elements(const struct ilo_dev *dev,
- const struct ilo_state_vf_info *info)
-{
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 95:
- *
- * "(Source Element Offset (in bytes))
- * Format: U11
- * Range [0,2047"
- *
- * From the Haswell PRM, volume 2d, page 415:
- *
- * "(Source Element Offset)
- * Format: U12 byte offset
- * ...
- * [0,4095]"
- *
- * From the Broadwell PRM, volume 2d, page 469:
- *
- * "(Source Element Offset)
- * Format: U12 byte offset
- * ...
- * [0,2047]"
- */
- const uint16_t max_vertex_offset =
- (ilo_dev_gen(dev) == ILO_GEN(7.5)) ? 4096 : 2048;
- uint8_t i;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(info->element_count <= ILO_STATE_VF_MAX_ELEMENT_COUNT);
-
- for (i = 0; i < info->element_count; i++) {
- const struct ilo_state_vf_element_info *elem = &info->elements[i];
-
- assert(elem->buffer < ILO_STATE_VF_MAX_BUFFER_COUNT);
- assert(elem->vertex_offset < max_vertex_offset);
- assert(ilo_state_vf_valid_element_format(dev, elem->format));
- }
-
- return true;
-}
-
-static uint32_t
-get_gen6_component_controls(const struct ilo_dev *dev,
- enum gen_vf_component comp_x,
- enum gen_vf_component comp_y,
- enum gen_vf_component comp_z,
- enum gen_vf_component comp_w)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- return comp_x << GEN6_VE_DW1_COMP0__SHIFT |
- comp_y << GEN6_VE_DW1_COMP1__SHIFT |
- comp_z << GEN6_VE_DW1_COMP2__SHIFT |
- comp_w << GEN6_VE_DW1_COMP3__SHIFT;
-}
-
-static bool
-get_gen6_edge_flag_format(const struct ilo_dev *dev,
- const struct ilo_state_vf_element_info *elem,
- enum gen_surface_format *format)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 94:
- *
- * "The Source Element Format must be set to the UINT format."
- *
- * From the Haswell PRM, volume 2d, page 413:
- *
- * "The SourceElementFormat needs to be a single-component format with
- * an element which has edge flag enabled."
- */
- if (elem->component_count != 1)
- return false;
-
- /* pick the format we like */
- switch (elem->format_size) {
- case 1:
- *format = GEN6_FORMAT_R8_UINT;
- break;
- case 2:
- *format = GEN6_FORMAT_R16_UINT;
- break;
- case 4:
- *format = GEN6_FORMAT_R32_UINT;
- break;
- default:
- return false;
- break;
- }
-
- return true;
-}
-
-static bool
-vf_set_gen6_3DSTATE_VERTEX_ELEMENTS(struct ilo_state_vf *vf,
- const struct ilo_dev *dev,
- const struct ilo_state_vf_info *info)
-{
- enum gen_surface_format edge_flag_format;
- uint32_t dw0, dw1;
- uint8_t i;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (!vf_validate_gen6_elements(dev, info))
- return false;
-
- for (i = 0; i < info->element_count; i++) {
- const struct ilo_state_vf_element_info *elem = &info->elements[i];
- enum gen_vf_component components[4] = {
- GEN6_VFCOMP_STORE_0,
- GEN6_VFCOMP_STORE_0,
- GEN6_VFCOMP_STORE_0,
- (elem->is_integer) ? GEN6_VFCOMP_STORE_1_INT :
- GEN6_VFCOMP_STORE_1_FP,
- };
-
- switch (elem->component_count) {
- case 4: components[3] = GEN6_VFCOMP_STORE_SRC; /* fall through */
- case 3: components[2] = GEN6_VFCOMP_STORE_SRC; /* fall through */
- case 2: components[1] = GEN6_VFCOMP_STORE_SRC; /* fall through */
- case 1: components[0] = GEN6_VFCOMP_STORE_SRC; break;
- default:
- assert(!"unexpected component count");
- break;
- }
-
- dw0 = elem->buffer << GEN6_VE_DW0_VB_INDEX__SHIFT |
- GEN6_VE_DW0_VALID |
- elem->format << GEN6_VE_DW0_FORMAT__SHIFT |
- elem->vertex_offset << GEN6_VE_DW0_VB_OFFSET__SHIFT;
- dw1 = get_gen6_component_controls(dev,
- components[0], components[1],
- components[2], components[3]);
-
- STATIC_ASSERT(ARRAY_SIZE(vf->user_ve[i]) >= 2);
- vf->user_ve[i][0] = dw0;
- vf->user_ve[i][1] = dw1;
- }
-
- vf->user_ve_count = i;
-
- vf->edge_flag_supported = (i && get_gen6_edge_flag_format(dev,
- &info->elements[i - 1], &edge_flag_format));
- if (vf->edge_flag_supported) {
- const struct ilo_state_vf_element_info *elem = &info->elements[i - 1];
-
- /* without edge flag enable */
- vf->last_user_ve[0][0] = dw0;
- vf->last_user_ve[0][1] = dw1;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 94:
- *
- * "This bit (Edge Flag Enable) must only be ENABLED on the last
- * valid VERTEX_ELEMENT structure.
- *
- * When set, Component 0 Control must be set to
- * VFCOMP_STORE_SRC, and Component 1-3 Control must be set to
- * VFCOMP_NOSTORE."
- */
- dw0 = elem->buffer << GEN6_VE_DW0_VB_INDEX__SHIFT |
- GEN6_VE_DW0_VALID |
- edge_flag_format << GEN6_VE_DW0_FORMAT__SHIFT |
- GEN6_VE_DW0_EDGE_FLAG_ENABLE |
- elem->vertex_offset << GEN6_VE_DW0_VB_OFFSET__SHIFT;
- dw1 = get_gen6_component_controls(dev, GEN6_VFCOMP_STORE_SRC,
- GEN6_VFCOMP_NOSTORE, GEN6_VFCOMP_NOSTORE, GEN6_VFCOMP_NOSTORE);
-
- /* with edge flag enable */
- vf->last_user_ve[1][0] = dw0;
- vf->last_user_ve[1][1] = dw1;
- }
-
- return true;
-}
-
-static bool
-vf_set_gen6_vertex_buffer_state(struct ilo_state_vf *vf,
- const struct ilo_dev *dev,
- const struct ilo_state_vf_info *info)
-{
- uint8_t i;
-
- ILO_DEV_ASSERT(dev, 6, 7.5);
-
- memset(vf->vb_to_first_elem, -1, sizeof(vf->vb_to_first_elem));
-
- for (i = 0; i < info->element_count; i++) {
- const struct ilo_state_vf_element_info *elem = &info->elements[i];
-
- STATIC_ASSERT(ARRAY_SIZE(vf->user_instancing[i]) >= 2);
- /* instancing enable only */
- vf->user_instancing[i][0] = (elem->instancing_enable) ?
- GEN6_VB_DW0_ACCESS_INSTANCEDATA :
- GEN6_VB_DW0_ACCESS_VERTEXDATA;
- vf->user_instancing[i][1] = elem->instancing_step_rate;
-
- /*
- * Instancing is per VB, not per VE, before Gen8. Set up a VB-to-VE
- * mapping as well.
- */
- if (vf->vb_to_first_elem[elem->buffer] < 0) {
- vf->vb_to_first_elem[elem->buffer] = i;
- } else {
- const struct ilo_state_vf_element_info *first =
- &info->elements[vf->vb_to_first_elem[elem->buffer]];
-
- assert(elem->instancing_enable == first->instancing_enable &&
- elem->instancing_step_rate == first->instancing_step_rate);
- }
- }
-
- return true;
-}
-
-static bool
-vf_set_gen8_3DSTATE_VF_INSTANCING(struct ilo_state_vf *vf,
- const struct ilo_dev *dev,
- const struct ilo_state_vf_info *info)
-{
- uint8_t i;
-
- ILO_DEV_ASSERT(dev, 8, 8);
-
- for (i = 0; i < info->element_count; i++) {
- const struct ilo_state_vf_element_info *elem = &info->elements[i];
-
- STATIC_ASSERT(ARRAY_SIZE(vf->user_instancing[i]) >= 2);
- vf->user_instancing[i][0] = (elem->instancing_enable) ?
- GEN8_INSTANCING_DW1_ENABLE : 0;
- vf->user_instancing[i][1] = elem->instancing_step_rate;
- }
-
- return true;
-}
-
-static uint32_t
-get_gen6_component_zeros(const struct ilo_dev *dev)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- return get_gen6_component_controls(dev,
- GEN6_VFCOMP_STORE_0,
- GEN6_VFCOMP_STORE_0,
- GEN6_VFCOMP_STORE_0,
- GEN6_VFCOMP_STORE_0);
-}
-
-static uint32_t
-get_gen6_component_ids(const struct ilo_dev *dev,
- bool vertexid, bool instanceid)
-{
- ILO_DEV_ASSERT(dev, 6, 7.5);
-
- return get_gen6_component_controls(dev,
- (vertexid) ? GEN6_VFCOMP_STORE_VID : GEN6_VFCOMP_STORE_0,
- (instanceid) ? GEN6_VFCOMP_STORE_IID : GEN6_VFCOMP_STORE_0,
- GEN6_VFCOMP_STORE_0,
- GEN6_VFCOMP_STORE_0);
-}
-
-static bool
-vf_params_set_gen6_internal_ve(struct ilo_state_vf *vf,
- const struct ilo_dev *dev,
- const struct ilo_state_vf_params_info *params,
- uint8_t user_ve_count)
-{
- const bool prepend_ids =
- (params->prepend_vertexid || params->prepend_instanceid);
- uint8_t internal_ve_count = 0, i;
- uint32_t dw1[2];
-
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 92:
- *
- * "- At least one VERTEX_ELEMENT_STATE structure must be included.
- *
- * - Inclusion of partial VERTEX_ELEMENT_STATE structures is
- * UNDEFINED.
- *
- * - SW must ensure that at least one vertex element is defined prior
- * to issuing a 3DPRIMTIVE command, or operation is UNDEFINED.
- *
- * - There are no "holes" allowed in the destination vertex: NOSTORE
- * components must be overwritten by subsequent components unless
- * they are the trailing DWords of the vertex. Software must
- * explicitly chose some value (probably 0) to be written into
- * DWords that would otherwise be "holes"."
- *
- * - ...
- *
- * - [DevILK+] Element[0] must be valid."
- */
- if (params->prepend_zeros || (!user_ve_count && !prepend_ids))
- dw1[internal_ve_count++] = get_gen6_component_zeros(dev);
-
- if (prepend_ids) {
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- /* placeholder for 3DSTATE_VF_SGVS */
- dw1[internal_ve_count++] = get_gen6_component_zeros(dev);
- } else {
- dw1[internal_ve_count++] = get_gen6_component_ids(dev,
- params->prepend_vertexid, params->prepend_instanceid);
- }
- }
-
- for (i = 0; i < internal_ve_count; i++) {
- STATIC_ASSERT(ARRAY_SIZE(vf->internal_ve[i]) >= 2);
- vf->internal_ve[i][0] = GEN6_VE_DW0_VALID;
- vf->internal_ve[i][1] = dw1[i];
- }
-
- vf->internal_ve_count = internal_ve_count;
-
- return true;
-}
-
-static bool
-vf_params_set_gen8_3DSTATE_VF_SGVS(struct ilo_state_vf *vf,
- const struct ilo_dev *dev,
- const struct ilo_state_vf_params_info *params)
-{
- const uint8_t attr = (params->prepend_zeros) ? 1 : 0;
- uint32_t dw1;
-
- ILO_DEV_ASSERT(dev, 8, 8);
-
- dw1 = 0;
-
- if (params->prepend_instanceid) {
- dw1 |= GEN8_SGVS_DW1_IID_ENABLE |
- 1 << GEN8_SGVS_DW1_IID_COMP__SHIFT |
- attr << GEN8_SGVS_DW1_IID_OFFSET__SHIFT;
- }
-
- if (params->prepend_vertexid) {
- dw1 |= GEN8_SGVS_DW1_VID_ENABLE |
- 0 << GEN8_SGVS_DW1_VID_COMP__SHIFT |
- attr << GEN8_SGVS_DW1_VID_OFFSET__SHIFT;
- }
-
- STATIC_ASSERT(ARRAY_SIZE(vf->sgvs) >= 1);
- vf->sgvs[0] = dw1;
-
- return true;
-}
-
-static uint32_t
-get_gen6_fixed_cut_index(const struct ilo_dev *dev,
- enum gen_index_format format)
-{
- const uint32_t fixed = ~0u;
-
- ILO_DEV_ASSERT(dev, 6, 7);
-
- switch (format) {
- case GEN6_INDEX_BYTE: return (uint8_t) fixed;
- case GEN6_INDEX_WORD: return (uint16_t) fixed;
- case GEN6_INDEX_DWORD: return (uint32_t) fixed;
- default:
- assert(!"unknown index format");
- return fixed;
- }
-}
-
-static bool
-get_gen6_cut_index_supported(const struct ilo_dev *dev,
- enum gen_3dprim_type topology)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * See the Sandy Bridge PRM, volume 2 part 1, page 80 and the Haswell PRM,
- * volume 7, page 456.
- */
- switch (topology) {
- case GEN6_3DPRIM_TRIFAN:
- case GEN6_3DPRIM_QUADLIST:
- case GEN6_3DPRIM_QUADSTRIP:
- case GEN6_3DPRIM_POLYGON:
- case GEN6_3DPRIM_LINELOOP:
- return (ilo_dev_gen(dev) >= ILO_GEN(7.5));
- case GEN6_3DPRIM_RECTLIST:
- case GEN6_3DPRIM_TRIFAN_NOSTIPPLE:
- return false;
- default:
- return true;
- }
-}
-
-static bool
-vf_params_set_gen6_3dstate_index_buffer(struct ilo_state_vf *vf,
- const struct ilo_dev *dev,
- const struct ilo_state_vf_params_info *params)
-{
- uint32_t dw0 = 0;
-
- ILO_DEV_ASSERT(dev, 6, 7);
-
- /* cut index only, as in 3DSTATE_VF */
- if (params->cut_index_enable) {
- assert(get_gen6_cut_index_supported(dev, params->cv_topology));
- assert(get_gen6_fixed_cut_index(dev, params->cv_index_format) ==
- params->cut_index);
-
- dw0 |= GEN6_IB_DW0_CUT_INDEX_ENABLE;
- }
-
- STATIC_ASSERT(ARRAY_SIZE(vf->cut) >= 1);
- vf->cut[0] = dw0;
-
- return true;
-}
-
-static bool
-vf_params_set_gen75_3DSTATE_VF(struct ilo_state_vf *vf,
- const struct ilo_dev *dev,
- const struct ilo_state_vf_params_info *params)
-{
- uint32_t dw0 = 0;
-
- ILO_DEV_ASSERT(dev, 7.5, 8);
-
- if (params->cut_index_enable) {
- assert(get_gen6_cut_index_supported(dev, params->cv_topology));
- dw0 |= GEN75_VF_DW0_CUT_INDEX_ENABLE;
- }
-
- STATIC_ASSERT(ARRAY_SIZE(vf->cut) >= 2);
- vf->cut[0] = dw0;
- vf->cut[1] = params->cut_index;
-
- return true;
-}
-
-static bool
-vertex_buffer_validate_gen6(const struct ilo_dev *dev,
- const struct ilo_state_vertex_buffer_info *info)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (info->vma)
- assert(info->size && info->offset + info->size <= info->vma->vm_size);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 86:
- *
- * "(Buffer Pitch)
- * Range [DevCTG+]: [0,2048] Bytes"
- */
- assert(info->stride <= 2048);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 86:
- *
- * "64-bit floating point values must be 64-bit aligned in memory, or
- * UNPREDICTABLE data will be fetched. When accessing an element
- * containing 64-bit floating point values, the Buffer Starting
- * Address and Source Element Offset values must add to a 64-bit
- * aligned address, and BufferPitch must be a multiple of 64-bits."
- */
- if (info->cv_has_double) {
- if (info->vma)
- assert(info->vma->vm_alignment % 8 == 0);
-
- assert(info->stride % 8 == 0);
- assert((info->offset + info->cv_double_vertex_offset_mod_8) % 8 == 0);
- }
-
- return true;
-}
-
-static uint32_t
-vertex_buffer_get_gen6_size(const struct ilo_dev *dev,
- const struct ilo_state_vertex_buffer_info *info)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
- return (info->vma) ? info->size : 0;
-}
-
-static bool
-vertex_buffer_set_gen8_vertex_buffer_state(struct ilo_state_vertex_buffer *vb,
- const struct ilo_dev *dev,
- const struct ilo_state_vertex_buffer_info *info)
-{
- const uint32_t size = vertex_buffer_get_gen6_size(dev, info);
- uint32_t dw0;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (!vertex_buffer_validate_gen6(dev, info))
- return false;
-
- dw0 = info->stride << GEN6_VB_DW0_PITCH__SHIFT;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- dw0 |= GEN7_VB_DW0_ADDR_MODIFIED;
- if (!info->vma)
- dw0 |= GEN6_VB_DW0_IS_NULL;
-
- STATIC_ASSERT(ARRAY_SIZE(vb->vb) >= 3);
- vb->vb[0] = dw0;
- vb->vb[1] = info->offset;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- vb->vb[2] = size;
- } else {
- /* address of the last valid byte */
- vb->vb[2] = (size) ? info->offset + size - 1 : 0;
- }
-
- vb->vma = info->vma;
-
- return true;
-}
-
-static uint32_t
-get_index_format_size(enum gen_index_format format)
-{
- switch (format) {
- case GEN6_INDEX_BYTE: return 1;
- case GEN6_INDEX_WORD: return 2;
- case GEN6_INDEX_DWORD: return 4;
- default:
- assert(!"unknown index format");
- return 1;
- }
-}
-
-static bool
-index_buffer_validate_gen6(const struct ilo_dev *dev,
- const struct ilo_state_index_buffer_info *info)
-{
- const uint32_t format_size = get_index_format_size(info->format);
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 79:
- *
- * "This field (Buffer Starting Address) contains the size-aligned (as
- * specified by Index Format) Graphics Address of the first element of
- * interest within the index buffer."
- */
- assert(info->offset % format_size == 0);
-
- if (info->vma) {
- assert(info->vma->vm_alignment % format_size == 0);
- assert(info->size && info->offset + info->size <= info->vma->vm_size);
- }
-
- return true;
-}
-
-static uint32_t
-index_buffer_get_gen6_size(const struct ilo_dev *dev,
- const struct ilo_state_index_buffer_info *info)
-{
- uint32_t size;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (!info->vma)
- return 0;
-
- size = info->size;
- if (ilo_dev_gen(dev) < ILO_GEN(8)) {
- const uint32_t format_size = get_index_format_size(info->format);
- size -= (size % format_size);
- }
-
- return size;
-}
-
-static bool
-index_buffer_set_gen8_3DSTATE_INDEX_BUFFER(struct ilo_state_index_buffer *ib,
- const struct ilo_dev *dev,
- const struct ilo_state_index_buffer_info *info)
-{
- const uint32_t size = index_buffer_get_gen6_size(dev, info);
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (!index_buffer_validate_gen6(dev, info))
- return false;
-
- STATIC_ASSERT(ARRAY_SIZE(ib->ib) >= 3);
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- ib->ib[0] = info->format << GEN8_IB_DW1_FORMAT__SHIFT;
- ib->ib[1] = info->offset;
- ib->ib[2] = size;
- } else {
- ib->ib[0] = info->format << GEN6_IB_DW0_FORMAT__SHIFT;
- ib->ib[1] = info->offset;
- /* address of the last valid byte, or 0 */
- ib->ib[2] = (size) ? info->offset + size - 1 : 0;
- }
-
- ib->vma = info->vma;
-
- return true;
-}
-
-bool
-ilo_state_vf_valid_element_format(const struct ilo_dev *dev,
- enum gen_surface_format format)
-{
- /*
- * This table is based on:
- *
- * - the Sandy Bridge PRM, volume 4 part 1, page 88-97
- * - the Ivy Bridge PRM, volume 2 part 1, page 97-99
- * - the Haswell PRM, volume 7, page 467-470
- */
- static const int vf_element_formats[] = {
- [GEN6_FORMAT_R32G32B32A32_FLOAT] = ILO_GEN( 1),
- [GEN6_FORMAT_R32G32B32A32_SINT] = ILO_GEN( 1),
- [GEN6_FORMAT_R32G32B32A32_UINT] = ILO_GEN( 1),
- [GEN6_FORMAT_R32G32B32A32_UNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R32G32B32A32_SNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R64G64_FLOAT] = ILO_GEN( 1),
- [GEN6_FORMAT_R32G32B32A32_SSCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R32G32B32A32_USCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R32G32B32A32_SFIXED] = ILO_GEN(7.5),
- [GEN6_FORMAT_R32G32B32_FLOAT] = ILO_GEN( 1),
- [GEN6_FORMAT_R32G32B32_SINT] = ILO_GEN( 1),
- [GEN6_FORMAT_R32G32B32_UINT] = ILO_GEN( 1),
- [GEN6_FORMAT_R32G32B32_UNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R32G32B32_SNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R32G32B32_SSCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R32G32B32_USCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R32G32B32_SFIXED] = ILO_GEN(7.5),
- [GEN6_FORMAT_R16G16B16A16_UNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R16G16B16A16_SNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R16G16B16A16_SINT] = ILO_GEN( 1),
- [GEN6_FORMAT_R16G16B16A16_UINT] = ILO_GEN( 1),
- [GEN6_FORMAT_R16G16B16A16_FLOAT] = ILO_GEN( 1),
- [GEN6_FORMAT_R32G32_FLOAT] = ILO_GEN( 1),
- [GEN6_FORMAT_R32G32_SINT] = ILO_GEN( 1),
- [GEN6_FORMAT_R32G32_UINT] = ILO_GEN( 1),
- [GEN6_FORMAT_R32G32_UNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R32G32_SNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R64_FLOAT] = ILO_GEN( 1),
- [GEN6_FORMAT_R16G16B16A16_SSCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R16G16B16A16_USCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R32G32_SSCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R32G32_USCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R32G32_SFIXED] = ILO_GEN(7.5),
- [GEN6_FORMAT_B8G8R8A8_UNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R10G10B10A2_UNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R10G10B10A2_UINT] = ILO_GEN( 1),
- [GEN6_FORMAT_R10G10B10_SNORM_A2_UNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R8G8B8A8_UNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R8G8B8A8_SNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R8G8B8A8_SINT] = ILO_GEN( 1),
- [GEN6_FORMAT_R8G8B8A8_UINT] = ILO_GEN( 1),
- [GEN6_FORMAT_R16G16_UNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R16G16_SNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R16G16_SINT] = ILO_GEN( 1),
- [GEN6_FORMAT_R16G16_UINT] = ILO_GEN( 1),
- [GEN6_FORMAT_R16G16_FLOAT] = ILO_GEN( 1),
- [GEN6_FORMAT_B10G10R10A2_UNORM] = ILO_GEN(7.5),
- [GEN6_FORMAT_R11G11B10_FLOAT] = ILO_GEN( 1),
- [GEN6_FORMAT_R32_SINT] = ILO_GEN( 1),
- [GEN6_FORMAT_R32_UINT] = ILO_GEN( 1),
- [GEN6_FORMAT_R32_FLOAT] = ILO_GEN( 1),
- [GEN6_FORMAT_R32_UNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R32_SNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R10G10B10X2_USCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R8G8B8A8_SSCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R8G8B8A8_USCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R16G16_SSCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R16G16_USCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R32_SSCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R32_USCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R8G8_UNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R8G8_SNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R8G8_SINT] = ILO_GEN( 1),
- [GEN6_FORMAT_R8G8_UINT] = ILO_GEN( 1),
- [GEN6_FORMAT_R16_UNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R16_SNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R16_SINT] = ILO_GEN( 1),
- [GEN6_FORMAT_R16_UINT] = ILO_GEN( 1),
- [GEN6_FORMAT_R16_FLOAT] = ILO_GEN( 1),
- [GEN6_FORMAT_R8G8_SSCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R8G8_USCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R16_SSCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R16_USCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R8_UNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R8_SNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R8_SINT] = ILO_GEN( 1),
- [GEN6_FORMAT_R8_UINT] = ILO_GEN( 1),
- [GEN6_FORMAT_R8_SSCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R8_USCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R8G8B8_UNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R8G8B8_SNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R8G8B8_SSCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R8G8B8_USCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R64G64B64A64_FLOAT] = ILO_GEN( 1),
- [GEN6_FORMAT_R64G64B64_FLOAT] = ILO_GEN( 1),
- [GEN6_FORMAT_R16G16B16_FLOAT] = ILO_GEN( 6),
- [GEN6_FORMAT_R16G16B16_UNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R16G16B16_SNORM] = ILO_GEN( 1),
- [GEN6_FORMAT_R16G16B16_SSCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R16G16B16_USCALED] = ILO_GEN( 1),
- [GEN6_FORMAT_R16G16B16_UINT] = ILO_GEN(7.5),
- [GEN6_FORMAT_R16G16B16_SINT] = ILO_GEN(7.5),
- [GEN6_FORMAT_R32_SFIXED] = ILO_GEN(7.5),
- [GEN6_FORMAT_R10G10B10A2_SNORM] = ILO_GEN(7.5),
- [GEN6_FORMAT_R10G10B10A2_USCALED] = ILO_GEN(7.5),
- [GEN6_FORMAT_R10G10B10A2_SSCALED] = ILO_GEN(7.5),
- [GEN6_FORMAT_R10G10B10A2_SINT] = ILO_GEN(7.5),
- [GEN6_FORMAT_B10G10R10A2_SNORM] = ILO_GEN(7.5),
- [GEN6_FORMAT_B10G10R10A2_USCALED] = ILO_GEN(7.5),
- [GEN6_FORMAT_B10G10R10A2_SSCALED] = ILO_GEN(7.5),
- [GEN6_FORMAT_B10G10R10A2_UINT] = ILO_GEN(7.5),
- [GEN6_FORMAT_B10G10R10A2_SINT] = ILO_GEN(7.5),
- [GEN6_FORMAT_R8G8B8_UINT] = ILO_GEN(7.5),
- [GEN6_FORMAT_R8G8B8_SINT] = ILO_GEN(7.5),
- };
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- return (format < ARRAY_SIZE(vf_element_formats) &&
- vf_element_formats[format] &&
- ilo_dev_gen(dev) >= vf_element_formats[format]);
-}
-
-bool
-ilo_state_vf_init(struct ilo_state_vf *vf,
- const struct ilo_dev *dev,
- const struct ilo_state_vf_info *info)
-{
- bool ret = true;
-
- assert(ilo_is_zeroed(vf, sizeof(*vf)));
- assert(ilo_is_zeroed(info->data, info->data_size));
-
- assert(ilo_state_vf_data_size(dev, info->element_count) <=
- info->data_size);
- vf->user_ve = (uint32_t (*)[2]) info->data;
- vf->user_instancing =
- (uint32_t (*)[2]) (vf->user_ve + info->element_count);
-
- ret &= vf_set_gen6_3DSTATE_VERTEX_ELEMENTS(vf, dev, info);
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- ret &= vf_set_gen8_3DSTATE_VF_INSTANCING(vf, dev, info);
- else
- ret &= vf_set_gen6_vertex_buffer_state(vf, dev, info);
-
- ret &= ilo_state_vf_set_params(vf, dev, &info->params);
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_vf_init_for_rectlist(struct ilo_state_vf *vf,
- const struct ilo_dev *dev,
- void *data, size_t data_size,
- const struct ilo_state_vf_element_info *elements,
- uint8_t element_count)
-{
- struct ilo_state_vf_info info;
-
- memset(&info, 0, sizeof(info));
-
- info.data = data;
- info.data_size = data_size;
-
- info.elements = elements;
- info.element_count = element_count;
-
- /*
- * For VUE header,
- *
- * DW0: Reserved: MBZ
- * DW1: Render Target Array Index
- * DW2: Viewport Index
- * DW3: Point Width
- */
- info.params.prepend_zeros = true;
-
- return ilo_state_vf_init(vf, dev, &info);
-}
-
-bool
-ilo_state_vf_set_params(struct ilo_state_vf *vf,
- const struct ilo_dev *dev,
- const struct ilo_state_vf_params_info *params)
-{
- bool ret = true;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- ret &= vf_params_set_gen6_internal_ve(vf, dev, params, vf->user_ve_count);
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- ret &= vf_params_set_gen8_3DSTATE_VF_SGVS(vf, dev, params);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 94:
- *
- * "Edge flags are supported for the following primitive topology types
- * only, otherwise EdgeFlagEnable must not be ENABLED.
- *
- * - 3DPRIM_TRILIST*
- * - 3DPRIM_TRISTRIP*
- * - 3DPRIM_TRIFAN*
- * - 3DPRIM_POLYGON"
- *
- * "[DevSNB]: Edge Flags are not supported for QUADLIST primitives.
- * Software may elect to convert QUADLIST primitives to some set of
- * corresponding edge-flag-supported primitive types (e.g., POLYGONs)
- * prior to submission to the 3D vf."
- *
- * From the Ivy Bridge PRM, volume 2 part 1, page 86:
- *
- * "Edge flags are supported for all primitive topology types."
- *
- * Both PRMs are confusing...
- */
- if (params->last_element_edge_flag) {
- assert(vf->edge_flag_supported);
- if (ilo_dev_gen(dev) == ILO_GEN(6))
- assert(params->cv_topology != GEN6_3DPRIM_QUADLIST);
- }
-
- if (vf->edge_flag_supported) {
- assert(vf->user_ve_count);
- memcpy(vf->user_ve[vf->user_ve_count - 1],
- vf->last_user_ve[params->last_element_edge_flag],
- sizeof(vf->user_ve[vf->user_ve_count - 1]));
- }
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5))
- ret &= vf_params_set_gen75_3DSTATE_VF(vf, dev, params);
- else
- ret &= vf_params_set_gen6_3dstate_index_buffer(vf, dev, params);
-
- assert(ret);
-
- return ret;
-}
-
-void
-ilo_state_vf_full_delta(const struct ilo_state_vf *vf,
- const struct ilo_dev *dev,
- struct ilo_state_vf_delta *delta)
-{
- delta->dirty = ILO_STATE_VF_3DSTATE_VERTEX_ELEMENTS;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- delta->dirty |= ILO_STATE_VF_3DSTATE_VF_SGVS |
- ILO_STATE_VF_3DSTATE_VF_INSTANCING;
- } else {
- delta->dirty |= ILO_STATE_VF_3DSTATE_VERTEX_BUFFERS;
- }
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5))
- delta->dirty |= ILO_STATE_VF_3DSTATE_VF;
- else
- delta->dirty |= ILO_STATE_VF_3DSTATE_INDEX_BUFFER;
-}
-
-void
-ilo_state_vf_get_delta(const struct ilo_state_vf *vf,
- const struct ilo_dev *dev,
- const struct ilo_state_vf *old,
- struct ilo_state_vf_delta *delta)
-{
- /* no shallow copying */
- assert(vf->user_ve != old->user_ve &&
- vf->user_instancing != old->user_instancing);
-
- delta->dirty = 0;
-
- if (vf->internal_ve_count != old->internal_ve_count ||
- vf->user_ve_count != old->user_ve_count ||
- memcmp(vf->internal_ve, old->internal_ve,
- sizeof(vf->internal_ve[0]) * vf->internal_ve_count) ||
- memcmp(vf->user_ve, old->user_ve,
- sizeof(vf->user_ve[0]) * vf->user_ve_count))
- delta->dirty |= ILO_STATE_VF_3DSTATE_VERTEX_ELEMENTS;
-
- if (vf->user_ve_count != old->user_ve_count ||
- memcmp(vf->user_instancing, old->user_instancing,
- sizeof(vf->user_instancing[0]) * vf->user_ve_count)) {
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- delta->dirty |= ILO_STATE_VF_3DSTATE_VF_INSTANCING;
- else
- delta->dirty |= ILO_STATE_VF_3DSTATE_VERTEX_BUFFERS;
- }
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- if (vf->sgvs[0] != old->sgvs[0])
- delta->dirty |= ILO_STATE_VF_3DSTATE_VF_SGVS;
- }
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5)) {
- if (memcmp(vf->cut, old->cut, sizeof(vf->cut)))
- delta->dirty |= ILO_STATE_VF_3DSTATE_VF;
- } else {
- if (vf->cut[0] != old->cut[0])
- delta->dirty |= ILO_STATE_VF_3DSTATE_INDEX_BUFFER;
- }
-}
-
-uint32_t
-ilo_state_vertex_buffer_size(const struct ilo_dev *dev, uint32_t size,
- uint32_t *alignment)
-{
- /* align for doubles without padding */
- *alignment = 8;
- return size;
-}
-
-/**
- * No need to initialize first.
- */
-bool
-ilo_state_vertex_buffer_set_info(struct ilo_state_vertex_buffer *vb,
- const struct ilo_dev *dev,
- const struct ilo_state_vertex_buffer_info *info)
-{
- bool ret = true;
-
- ret &= vertex_buffer_set_gen8_vertex_buffer_state(vb, dev, info);
-
- assert(ret);
-
- return ret;
-}
-
-uint32_t
-ilo_state_index_buffer_size(const struct ilo_dev *dev, uint32_t size,
- uint32_t *alignment)
-{
- /* align for the worst case without padding */
- *alignment = get_index_format_size(GEN6_INDEX_DWORD);
- return size;
-}
-
-/**
- * No need to initialize first.
- */
-bool
-ilo_state_index_buffer_set_info(struct ilo_state_index_buffer *ib,
- const struct ilo_dev *dev,
- const struct ilo_state_index_buffer_info *info)
-{
- bool ret = true;
-
- ret &= index_buffer_set_gen8_3DSTATE_INDEX_BUFFER(ib, dev, info);
-
- assert(ret);
-
- return ret;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_STATE_VF_H
-#define ILO_STATE_VF_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-
-/*
- * From the Sandy Bridge PRM, volume 2 part 1, page 93:
- *
- * "Up to 34 (DevSNB+) vertex elements are supported."
- *
- * "Up to 33 VBs are supported"
- *
- * Reserve two VEs and one VB for internal use.
- */
-#define ILO_STATE_VF_MAX_ELEMENT_COUNT (34 - 2)
-#define ILO_STATE_VF_MAX_BUFFER_COUNT (33 - 1)
-
-enum ilo_state_vf_dirty_bits {
- ILO_STATE_VF_3DSTATE_VERTEX_ELEMENTS = (1 << 0),
- ILO_STATE_VF_3DSTATE_VF_SGVS = (1 << 1),
- ILO_STATE_VF_3DSTATE_VF_INSTANCING = (1 << 2),
- ILO_STATE_VF_3DSTATE_VERTEX_BUFFERS = (1 << 3),
- ILO_STATE_VF_3DSTATE_VF = (1 << 4),
- ILO_STATE_VF_3DSTATE_INDEX_BUFFER = (1 << 5),
-};
-
-/**
- * Fetch a 128-bit vertex attribute.
- */
-struct ilo_state_vf_element_info {
- uint8_t buffer;
- uint16_t vertex_offset;
- enum gen_surface_format format;
-
- uint8_t format_size;
- uint8_t component_count;
- bool is_integer;
-
- /* must be the same for those share the same buffer before Gen8 */
- bool instancing_enable;
- uint32_t instancing_step_rate;
-};
-
-/**
- * VF parameters.
- */
-struct ilo_state_vf_params_info {
- enum gen_3dprim_type cv_topology;
-
- /* prepend an attribute of zeros */
- bool prepend_zeros;
-
- /* prepend an attribute of VertexID and/or InstanceID */
- bool prepend_vertexid;
- bool prepend_instanceid;
-
- bool last_element_edge_flag;
-
- enum gen_index_format cv_index_format;
- bool cut_index_enable;
- uint32_t cut_index;
-};
-
-/**
- * Vertex fetch.
- */
-struct ilo_state_vf_info {
- void *data;
- size_t data_size;
-
- const struct ilo_state_vf_element_info *elements;
- uint8_t element_count;
-
- struct ilo_state_vf_params_info params;
-};
-
-struct ilo_state_vf {
- uint32_t (*user_ve)[2];
- uint32_t (*user_instancing)[2];
- int8_t vb_to_first_elem[ILO_STATE_VF_MAX_BUFFER_COUNT];
- uint8_t user_ve_count;
-
- bool edge_flag_supported;
- uint32_t last_user_ve[2][2];
-
- /* two VEs are reserved for internal use */
- uint32_t internal_ve[2][2];
- uint8_t internal_ve_count;
-
- uint32_t sgvs[1];
-
- uint32_t cut[2];
-};
-
-struct ilo_state_vf_delta {
- uint32_t dirty;
-};
-
-struct ilo_vma;
-
-struct ilo_state_vertex_buffer_info {
- const struct ilo_vma *vma;
- uint32_t offset;
- uint32_t size;
-
- uint16_t stride;
-
- /* doubles must be at 64-bit aligned addresses */
- bool cv_has_double;
- uint8_t cv_double_vertex_offset_mod_8;
-};
-
-struct ilo_state_vertex_buffer {
- uint32_t vb[3];
-
- const struct ilo_vma *vma;
-};
-
-struct ilo_state_index_buffer_info {
- const struct ilo_vma *vma;
- uint32_t offset;
- uint32_t size;
-
- enum gen_index_format format;
-};
-
-struct ilo_state_index_buffer {
- uint32_t ib[3];
-
- const struct ilo_vma *vma;
-};
-
-static inline size_t
-ilo_state_vf_data_size(const struct ilo_dev *dev, uint8_t element_count)
-{
- const struct ilo_state_vf *vf = NULL;
- return (sizeof(vf->user_ve[0]) +
- sizeof(vf->user_instancing[0])) * element_count;
-}
-
-bool
-ilo_state_vf_valid_element_format(const struct ilo_dev *dev,
- enum gen_surface_format format);
-
-bool
-ilo_state_vf_init(struct ilo_state_vf *vf,
- const struct ilo_dev *dev,
- const struct ilo_state_vf_info *info);
-
-bool
-ilo_state_vf_init_for_rectlist(struct ilo_state_vf *vf,
- const struct ilo_dev *dev,
- void *data, size_t data_size,
- const struct ilo_state_vf_element_info *elements,
- uint8_t element_count);
-
-bool
-ilo_state_vf_set_params(struct ilo_state_vf *vf,
- const struct ilo_dev *dev,
- const struct ilo_state_vf_params_info *params);
-
-/**
- * Return the number of attributes in the VUE.
- */
-static inline uint8_t
-ilo_state_vf_get_attr_count(const struct ilo_state_vf *vf)
-{
- return vf->internal_ve_count + vf->user_ve_count;
-}
-
-void
-ilo_state_vf_full_delta(const struct ilo_state_vf *vf,
- const struct ilo_dev *dev,
- struct ilo_state_vf_delta *delta);
-
-void
-ilo_state_vf_get_delta(const struct ilo_state_vf *vf,
- const struct ilo_dev *dev,
- const struct ilo_state_vf *old,
- struct ilo_state_vf_delta *delta);
-
-uint32_t
-ilo_state_vertex_buffer_size(const struct ilo_dev *dev, uint32_t size,
- uint32_t *alignment);
-
-bool
-ilo_state_vertex_buffer_set_info(struct ilo_state_vertex_buffer *vb,
- const struct ilo_dev *dev,
- const struct ilo_state_vertex_buffer_info *info);
-
-uint32_t
-ilo_state_index_buffer_size(const struct ilo_dev *dev, uint32_t size,
- uint32_t *alignment);
-
-bool
-ilo_state_index_buffer_set_info(struct ilo_state_index_buffer *ib,
- const struct ilo_dev *dev,
- const struct ilo_state_index_buffer_info *info);
-
-#endif /* ILO_STATE_VF_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-#include "ilo_state_viewport.h"
-
-static void
-viewport_matrix_get_gen6_guardband(const struct ilo_dev *dev,
- const struct ilo_state_viewport_matrix_info *mat,
- float *min_gbx, float *max_gbx,
- float *min_gby, float *max_gby)
-{
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 234:
- *
- * "Per-Device Guardband Extents
- *
- * - Supported X,Y ScreenSpace "Guardband" Extent: [-16K,16K-1]
- * - Maximum Post-Clamp Delta (X or Y): 16K"
- *
- * "In addition, in order to be correctly rendered, objects must have a
- * screenspace bounding box not exceeding 8K in the X or Y direction.
- * This additional restriction must also be comprehended by software,
- * i.e., enforced by use of clipping."
- *
- * From the Ivy Bridge PRM, volume 2 part 1, page 248:
- *
- * "Per-Device Guardband Extents
- *
- * - Supported X,Y ScreenSpace "Guardband" Extent: [-32K,32K-1]
- * - Maximum Post-Clamp Delta (X or Y): N/A"
- *
- * "In addition, in order to be correctly rendered, objects must have a
- * screenspace bounding box not exceeding 8K in the X or Y direction.
- * This additional restriction must also be comprehended by software,
- * i.e., enforced by use of clipping."
- *
- * Combined, the bounding box of any object can not exceed 8K in both
- * width and height.
- *
- * Below we set the guardband as a squre of length 8K, centered at where
- * the viewport is. This makes sure all objects passing the GB test are
- * valid to the renderer, and those failing the XY clipping have a
- * better chance of passing the GB test.
- */
- const int max_extent = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 32768 : 16384;
- const int half_len = 8192 / 2;
- int center_x = (int) mat->translate[0];
- int center_y = (int) mat->translate[1];
- float scale_x, scale_y;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* make sure the guardband is within the valid range */
- if (center_x - half_len < -max_extent)
- center_x = -max_extent + half_len;
- else if (center_x + half_len > max_extent - 1)
- center_x = max_extent - half_len;
-
- if (center_y - half_len < -max_extent)
- center_y = -max_extent + half_len;
- else if (center_y + half_len > max_extent - 1)
- center_y = max_extent - half_len;
-
- scale_x = fabsf(mat->scale[0]);
- scale_y = fabsf(mat->scale[1]);
- /*
- * From the Haswell PRM, volume 2d, page 292-293:
- *
- * "Note: Minimum allowed value for this field (X/Y Min Clip Guardband)
- * is -16384."
- *
- * "Note: Maximum allowed value for this field (X/Y Max Clip Guardband)
- * is 16383."
- *
- * Avoid small scales.
- */
- if (scale_x < 1.0f)
- scale_x = 1.0f;
- if (scale_y < 1.0f)
- scale_y = 1.0f;
-
- /* in NDC space */
- *min_gbx = ((float) (center_x - half_len) - mat->translate[0]) / scale_x;
- *max_gbx = ((float) (center_x + half_len) - mat->translate[0]) / scale_x;
- *min_gby = ((float) (center_y - half_len) - mat->translate[1]) / scale_y;
- *max_gby = ((float) (center_y + half_len) - mat->translate[1]) / scale_y;
-}
-
-static void
-viewport_matrix_get_extent(const struct ilo_state_viewport_matrix_info *mat,
- int axis, float *min, float *max)
-{
- const float scale_abs = fabsf(mat->scale[axis]);
-
- *min = -1.0f * scale_abs + mat->translate[axis];
- *max = 1.0f * scale_abs + mat->translate[axis];
-}
-
-static bool
-viewport_matrix_set_gen7_SF_CLIP_VIEWPORT(struct ilo_state_viewport *vp,
- const struct ilo_dev *dev,
- const struct ilo_state_viewport_matrix_info *matrices,
- uint8_t count)
-{
- uint8_t i;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- for (i = 0; i < count; i++) {
- const struct ilo_state_viewport_matrix_info *mat = &matrices[i];
- float min_gbx, max_gbx, min_gby, max_gby;
- uint32_t dw[16];
-
- viewport_matrix_get_gen6_guardband(dev, mat,
- &min_gbx, &max_gbx, &min_gby, &max_gby);
-
- dw[0] = fui(mat->scale[0]);
- dw[1] = fui(mat->scale[1]);
- dw[2] = fui(mat->scale[2]);
- dw[3] = fui(mat->translate[0]);
- dw[4] = fui(mat->translate[1]);
- dw[5] = fui(mat->translate[2]);
- dw[6] = 0;
- dw[7] = 0;
-
- dw[8] = fui(min_gbx);
- dw[9] = fui(max_gbx);
- dw[10] = fui(min_gby);
- dw[11] = fui(max_gby);
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- float min_x, max_x, min_y, max_y;
-
- viewport_matrix_get_extent(mat, 0, &min_x, &max_x);
- viewport_matrix_get_extent(mat, 1, &min_y, &max_y);
-
- dw[12] = fui(min_x);
- dw[13] = fui(max_x - 1.0f);
- dw[14] = fui(min_y);
- dw[15] = fui(max_y - 1.0f);
- } else {
- dw[12] = 0;
- dw[13] = 0;
- dw[14] = 0;
- dw[15] = 0;
- }
-
- STATIC_ASSERT(ARRAY_SIZE(vp->sf_clip[i]) >= 16);
- memcpy(vp->sf_clip[i], dw, sizeof(dw));
- }
-
- return true;
-}
-
-static bool
-viewport_matrix_set_gen6_CC_VIEWPORT(struct ilo_state_viewport *vp,
- const struct ilo_dev *dev,
- const struct ilo_state_viewport_matrix_info *matrices,
- uint8_t count)
-{
- uint8_t i;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- for (i = 0; i < count; i++) {
- const struct ilo_state_viewport_matrix_info *mat = &matrices[i];
- float min_z, max_z;
-
- viewport_matrix_get_extent(mat, 2, &min_z, &max_z);
-
- STATIC_ASSERT(ARRAY_SIZE(vp->cc[i]) >= 2);
- vp->cc[i][0] = fui(min_z);
- vp->cc[i][1] = fui(max_z);
- }
-
- return true;
-}
-
-static bool
-viewport_scissor_set_gen6_SCISSOR_RECT(struct ilo_state_viewport *vp,
- const struct ilo_dev *dev,
- const struct ilo_state_viewport_scissor_info *scissors,
- uint8_t count)
-{
- const uint16_t max_size = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 16384 : 8192;
- uint8_t i;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- for (i = 0; i < count; i++) {
- const struct ilo_state_viewport_scissor_info *scissor = &scissors[i];
- uint16_t min_x, min_y, max_x, max_y;
- uint32_t dw0, dw1;
-
- min_x = (scissor->min_x < max_size) ? scissor->min_x : max_size - 1;
- min_y = (scissor->min_y < max_size) ? scissor->min_y : max_size - 1;
- max_x = (scissor->max_x < max_size) ? scissor->max_x : max_size - 1;
- max_y = (scissor->max_y < max_size) ? scissor->max_y : max_size - 1;
-
- dw0 = min_y << GEN6_SCISSOR_DW0_MIN_Y__SHIFT |
- min_x << GEN6_SCISSOR_DW0_MIN_X__SHIFT;
- dw1 = max_y << GEN6_SCISSOR_DW1_MAX_Y__SHIFT |
- max_x << GEN6_SCISSOR_DW1_MAX_X__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(vp->scissor[i]) >= 2);
- vp->scissor[i][0] = dw0;
- vp->scissor[i][1] = dw1;
- }
-
- return true;
-}
-
-bool
-ilo_state_viewport_init(struct ilo_state_viewport *vp,
- const struct ilo_dev *dev,
- const struct ilo_state_viewport_info *info)
-{
- const size_t elem_size = ilo_state_viewport_data_size(dev, 1);
-
- assert(ilo_is_zeroed(vp, sizeof(*vp)));
- assert(ilo_is_zeroed(info->data, info->data_size));
-
- vp->data = info->data;
-
- if (info->data_size / elem_size < ILO_STATE_VIEWPORT_MAX_COUNT)
- vp->array_size = info->data_size / elem_size;
- else
- vp->array_size = ILO_STATE_VIEWPORT_MAX_COUNT;
-
- return ilo_state_viewport_set_params(vp, dev, &info->params, false);
-}
-
-bool
-ilo_state_viewport_init_data_only(struct ilo_state_viewport *vp,
- const struct ilo_dev *dev,
- void *data, size_t data_size)
-{
- struct ilo_state_viewport_info info;
-
- memset(&info, 0, sizeof(info));
- info.data = data;
- info.data_size = data_size;
-
- return ilo_state_viewport_init(vp, dev, &info);
-}
-
-bool
-ilo_state_viewport_init_for_rectlist(struct ilo_state_viewport *vp,
- const struct ilo_dev *dev,
- void *data, size_t data_size)
-{
- struct ilo_state_viewport_info info;
- struct ilo_state_viewport_matrix_info mat;
- struct ilo_state_viewport_scissor_info sci;
-
- memset(&info, 0, sizeof(info));
- memset(&mat, 0, sizeof(mat));
- memset(&sci, 0, sizeof(sci));
-
- info.data = data;
- info.data_size = data_size;
- info.params.matrices = &mat;
- info.params.scissors = &sci;
- info.params.count = 1;
-
- mat.scale[0] = 1.0f;
- mat.scale[1] = 1.0f;
- mat.scale[2] = 1.0f;
-
- return ilo_state_viewport_init(vp, dev, &info);
-}
-
-static void
-viewport_set_count(struct ilo_state_viewport *vp,
- const struct ilo_dev *dev,
- uint8_t count)
-{
- assert(count <= vp->array_size);
-
- vp->count = count;
- vp->sf_clip = (uint32_t (*)[16]) vp->data;
- vp->cc = (uint32_t (*)[ 2]) (vp->sf_clip + count);
- vp->scissor = (uint32_t (*)[ 2]) (vp->cc + count);
-}
-
-bool
-ilo_state_viewport_set_params(struct ilo_state_viewport *vp,
- const struct ilo_dev *dev,
- const struct ilo_state_viewport_params_info *params,
- bool scissors_only)
-{
- bool ret = true;
-
- if (scissors_only) {
- assert(vp->count == params->count);
-
- ret &= viewport_scissor_set_gen6_SCISSOR_RECT(vp, dev,
- params->scissors, params->count);
- } else {
- viewport_set_count(vp, dev, params->count);
-
- ret &= viewport_matrix_set_gen7_SF_CLIP_VIEWPORT(vp, dev,
- params->matrices, params->count);
- ret &= viewport_matrix_set_gen6_CC_VIEWPORT(vp, dev,
- params->matrices, params->count);
- ret &= viewport_scissor_set_gen6_SCISSOR_RECT(vp, dev,
- params->scissors, params->count);
- }
-
- assert(ret);
-
- return ret;
-}
-
-void
-ilo_state_viewport_full_delta(const struct ilo_state_viewport *vp,
- const struct ilo_dev *dev,
- struct ilo_state_viewport_delta *delta)
-{
- delta->dirty = ILO_STATE_VIEWPORT_SF_CLIP_VIEWPORT |
- ILO_STATE_VIEWPORT_CC_VIEWPORT |
- ILO_STATE_VIEWPORT_SCISSOR_RECT;
-}
-
-void
-ilo_state_viewport_get_delta(const struct ilo_state_viewport *vp,
- const struct ilo_dev *dev,
- const struct ilo_state_viewport *old,
- struct ilo_state_viewport_delta *delta)
-{
- const size_t sf_clip_size = sizeof(vp->sf_clip[0]) * vp->count;
- const size_t cc_size = sizeof(vp->cc[0]) * vp->count;
- const size_t scissor_size = sizeof(vp->scissor[0]) * vp->count;
-
- /* no shallow copying */
- assert(vp->data != old->data);
-
- if (vp->count != old->count) {
- ilo_state_viewport_full_delta(vp, dev, delta);
- return;
- }
-
- delta->dirty = 0;
-
- if (memcmp(vp->sf_clip, old->sf_clip, sf_clip_size))
- delta->dirty |= ILO_STATE_VIEWPORT_SF_CLIP_VIEWPORT;
-
- if (memcmp(vp->cc, old->cc, cc_size))
- delta->dirty |= ILO_STATE_VIEWPORT_CC_VIEWPORT;
-
- if (memcmp(vp->scissor, old->scissor, scissor_size))
- delta->dirty |= ILO_STATE_VIEWPORT_SCISSOR_RECT;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_STATE_VIEWPORT_H
-#define ILO_STATE_VIEWPORT_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-
-/*
- * From the Sandy Bridge PRM, volume 2 part 1, page 38:
- *
- * "... 16 sets of viewport (VP) state parameters in the Clip unit's
- * VertexClipTest function and in the SF unit's ViewportMapping and
- * Scissor functions."
- */
-#define ILO_STATE_VIEWPORT_MAX_COUNT 16
-
-enum ilo_state_viewport_dirty_bits {
- ILO_STATE_VIEWPORT_SF_CLIP_VIEWPORT = (1 << 0),
- ILO_STATE_VIEWPORT_CC_VIEWPORT = (1 << 1),
- ILO_STATE_VIEWPORT_SCISSOR_RECT = (1 << 2),
-};
-
-struct ilo_state_viewport_matrix_info {
- float scale[3];
- float translate[3];
-};
-
-struct ilo_state_viewport_scissor_info {
- /* all inclusive */
- uint16_t min_x;
- uint16_t min_y;
- uint16_t max_x;
- uint16_t max_y;
-};
-
-struct ilo_state_viewport_params_info {
- const struct ilo_state_viewport_matrix_info *matrices;
- const struct ilo_state_viewport_scissor_info *scissors;
- uint8_t count;
-};
-
-struct ilo_state_viewport_info {
- void *data;
- size_t data_size;
-
- struct ilo_state_viewport_params_info params;
-};
-
-struct ilo_state_viewport {
- void *data;
- uint8_t array_size;
-
- uint8_t count;
- uint32_t (*sf_clip)[16];
- uint32_t (*cc)[2];
- uint32_t (*scissor)[2];
-};
-
-struct ilo_state_viewport_delta {
- uint32_t dirty;
-};
-
-static inline size_t
-ilo_state_viewport_data_size(const struct ilo_dev *dev, uint8_t array_size)
-{
- const struct ilo_state_viewport *vp = NULL;
- return (sizeof(vp->sf_clip[0]) +
- sizeof(vp->cc[0]) +
- sizeof(vp->scissor[0])) * array_size;
-}
-
-bool
-ilo_state_viewport_init(struct ilo_state_viewport *vp,
- const struct ilo_dev *dev,
- const struct ilo_state_viewport_info *info);
-
-bool
-ilo_state_viewport_init_data_only(struct ilo_state_viewport *vp,
- const struct ilo_dev *dev,
- void *data, size_t data_size);
-
-bool
-ilo_state_viewport_init_for_rectlist(struct ilo_state_viewport *vp,
- const struct ilo_dev *dev,
- void *data, size_t data_size);
-
-bool
-ilo_state_viewport_set_params(struct ilo_state_viewport *vp,
- const struct ilo_dev *dev,
- const struct ilo_state_viewport_params_info *params,
- bool scissors_only);
-
-void
-ilo_state_viewport_full_delta(const struct ilo_state_viewport *vp,
- const struct ilo_dev *dev,
- struct ilo_state_viewport_delta *delta);
-
-void
-ilo_state_viewport_get_delta(const struct ilo_state_viewport *vp,
- const struct ilo_dev *dev,
- const struct ilo_state_viewport *old,
- struct ilo_state_viewport_delta *delta);
-
-#endif /* ILO_STATE_VIEWPORT_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-#include "ilo_image.h"
-#include "ilo_vma.h"
-#include "ilo_state_zs.h"
-
-static bool
-zs_set_gen6_null_3DSTATE_DEPTH_BUFFER(struct ilo_state_zs *zs,
- const struct ilo_dev *dev)
-{
- const enum gen_depth_format format = GEN6_ZFORMAT_D32_FLOAT;
- uint32_t dw1;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- dw1 = GEN6_SURFTYPE_NULL << GEN7_DEPTH_DW1_TYPE__SHIFT |
- format << GEN7_DEPTH_DW1_FORMAT__SHIFT;
- } else {
- dw1 = GEN6_SURFTYPE_NULL << GEN6_DEPTH_DW1_TYPE__SHIFT |
- GEN6_TILING_Y << GEN6_DEPTH_DW1_TILING__SHIFT |
- format << GEN6_DEPTH_DW1_FORMAT__SHIFT;
- }
-
- STATIC_ASSERT(ARRAY_SIZE(zs->depth) >= 5);
- zs->depth[0] = dw1;
- zs->depth[1] = 0;
- zs->depth[2] = 0;
- zs->depth[3] = 0;
- zs->depth[4] = 0;
-
- return true;
-}
-
-static bool
-zs_validate_gen6(const struct ilo_dev *dev,
- const struct ilo_state_zs_info *info)
-{
- const struct ilo_image *img = (info->z_img) ? info->z_img : info->s_img;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(!info->z_img == !info->z_vma);
- assert(!info->s_img == !info->s_vma);
-
- /* all tiled */
- if (info->z_img) {
- assert(info->z_img->tiling == GEN6_TILING_Y);
- assert(info->z_vma->vm_alignment % 4096 == 0);
- }
- if (info->s_img) {
- assert(info->s_img->tiling == GEN8_TILING_W);
- assert(info->s_vma->vm_alignment % 4096 == 0);
- }
- if (info->hiz_vma) {
- assert(info->z_img &&
- ilo_image_can_enable_aux(info->z_img, info->level));
- assert(info->z_vma->vm_alignment % 4096 == 0);
- }
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 315:
- *
- * "The stencil buffer has a format of S8_UINT, and shares Surface
- * Type, Height, Width, and Depth, Minimum Array Element, Render
- * Target View Extent, Depth Coordinate Offset X/Y, LOD, and Depth
- * Buffer Object Control State fields of the depth buffer."
- */
- if (info->z_img && info->s_img && info->z_img != info->s_img) {
- assert(info->z_img->type == info->s_img->type &&
- info->z_img->height0 == info->s_img->height0 &&
- info->z_img->depth0 == info->s_img->depth0);
- }
-
- if (info->type != img->type) {
- assert(info->type == GEN6_SURFTYPE_2D &&
- img->type == GEN6_SURFTYPE_CUBE);
- }
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- switch (info->format) {
- case GEN6_ZFORMAT_D32_FLOAT:
- case GEN6_ZFORMAT_D24_UNORM_X8_UINT:
- case GEN6_ZFORMAT_D16_UNORM:
- break;
- default:
- assert(!"unknown depth format");
- break;
- }
- } else {
- /*
- * From the Ironlake PRM, volume 2 part 1, page 330:
- *
- * "If this field (Separate Stencil Buffer Enable) is disabled, the
- * Surface Format of the depth buffer cannot be D24_UNORM_X8_UINT."
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 321:
- *
- * "[DevSNB]: This field (Separate Stencil Buffer Enable) must be
- * set to the same value (enabled or disabled) as Hierarchical
- * Depth Buffer Enable."
- */
- if (info->hiz_vma)
- assert(info->format != GEN6_ZFORMAT_D24_UNORM_S8_UINT);
- else
- assert(info->format != GEN6_ZFORMAT_D24_UNORM_X8_UINT);
- }
-
- assert(info->level < img->level_count);
- assert(img->bo_stride);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 323:
- *
- * "For cube maps, Width must be set equal to Height."
- */
- if (info->type == GEN6_SURFTYPE_CUBE)
- assert(img->width0 == img->height0);
-
- return true;
-}
-
-static void
-zs_get_gen6_max_extent(const struct ilo_dev *dev,
- const struct ilo_state_zs_info *info,
- uint16_t *max_w, uint16_t *max_h)
-{
- const uint16_t max_size = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 16384 : 8192;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- switch (info->type) {
- case GEN6_SURFTYPE_1D:
- *max_w = max_size;
- *max_h = 1;
- break;
- case GEN6_SURFTYPE_2D:
- case GEN6_SURFTYPE_CUBE:
- *max_w = max_size;
- *max_h = max_size;
- break;
- case GEN6_SURFTYPE_3D:
- *max_w = 2048;
- *max_h = 2048;
- break;
- default:
- assert(!"invalid surface type");
- *max_w = 1;
- *max_h = 1;
- break;
- }
-}
-
-static void
-get_gen6_hiz_alignments(const struct ilo_dev *dev,
- const struct ilo_image *img,
- uint16_t *align_w, uint16_t *align_h)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 313:
- *
- * "A rectangle primitive representing the clear area is delivered. The
- * primitive must adhere to the following restrictions on size:
- *
- * - If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
- * aligned to an 8x4 pixel block relative to the upper left corner
- * of the depth buffer, and contain an integer number of these pixel
- * blocks, and all 8x4 pixels must be lit.
- * - If Number of Multisamples is NUMSAMPLES_4, the rectangle must be
- * aligned to a 4x2 pixel block (8x4 sample block) relative to the
- * upper left corner of the depth buffer, and contain an integer
- * number of these pixel blocks, and all samples of the 4x2 pixels
- * must be lit
- * - If Number of Multisamples is NUMSAMPLES_8, the rectangle must be
- * aligned to a 2x2 pixel block (8x4 sample block) relative to the
- * upper left corner of the depth buffer, and contain an integer
- * number of these pixel blocks, and all samples of the 2x2 pixels
- * must be list."
- *
- * Experiments on Gen7.5 show that HiZ resolve also requires the rectangle
- * to be aligned to 8x4 sample blocks. But to be on the safe side, we
- * always require a level to be aligned when HiZ is enabled.
- */
- switch (img->sample_count) {
- case 1:
- *align_w = 8;
- *align_h = 4;
- break;
- case 2:
- *align_w = 4;
- *align_h = 4;
- break;
- case 4:
- *align_w = 4;
- *align_h = 2;
- break;
- case 8:
- *align_w = 2;
- *align_h = 2;
- break;
- case 16:
- *align_w = 2;
- *align_h = 1;
- break;
- default:
- assert(!"unknown sample count");
- *align_w = 1;
- *align_h = 1;
- break;
- }
-}
-
-static bool
-zs_get_gen6_depth_extent(const struct ilo_dev *dev,
- const struct ilo_state_zs_info *info,
- uint16_t *width, uint16_t *height)
-{
- const struct ilo_image *img = (info->z_img) ? info->z_img : info->s_img;
- uint16_t w, h, max_w, max_h;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- w = img->width0;
- h = img->height0;
-
- if (info->hiz_vma) {
- uint16_t align_w, align_h;
-
- get_gen6_hiz_alignments(dev, info->z_img, &align_w, &align_h);
-
- /*
- * We want to force 8x4 alignment, but we can do so only for level 0 and
- * only when it is padded. ilo_image should know all these.
- */
- if (info->level)
- assert(w % align_w == 0 && h % align_h == 0);
-
- w = align(w, align_w);
- h = align(h, align_h);
- }
-
- zs_get_gen6_max_extent(dev, info, &max_w, &max_h);
- assert(w && h && w <= max_w && h <= max_h);
-
- *width = w - 1;
- *height = h - 1;
-
- return true;
-}
-
-static bool
-zs_get_gen6_depth_slices(const struct ilo_dev *dev,
- const struct ilo_state_zs_info *info,
- uint16_t *depth, uint16_t *min_array_elem,
- uint16_t *rt_view_extent)
-{
- const struct ilo_image *img = (info->z_img) ? info->z_img : info->s_img;
- uint16_t max_slice, d;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 325:
- *
- * "This field (Depth) specifies the total number of levels for a
- * volume texture or the number of array elements allowed to be
- * accessed starting at the Minimum Array Element for arrayed
- * surfaces. If the volume texture is MIP-mapped, this field specifies
- * the depth of the base MIP level."
- */
- switch (info->type) {
- case GEN6_SURFTYPE_1D:
- case GEN6_SURFTYPE_2D:
- case GEN6_SURFTYPE_CUBE:
- max_slice = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 2048 : 512;
-
- assert(img->array_size <= max_slice);
- max_slice = img->array_size;
-
- d = info->slice_count;
- if (info->type == GEN6_SURFTYPE_CUBE) {
- /*
- * Minumum Array Element and Depth must be 0; Render Target View
- * Extent is ignored.
- */
- if (info->slice_base || d != 6) {
- ilo_warn("no cube array dpeth buffer\n");
- return false;
- }
-
- d /= 6;
- }
- break;
- case GEN6_SURFTYPE_3D:
- max_slice = 2048;
-
- assert(img->depth0 <= max_slice);
- max_slice = u_minify(img->depth0, info->level);
-
- d = img->depth0;
- break;
- default:
- assert(!"invalid surface type");
- return false;
- break;
- }
-
- if (!info->slice_count ||
- info->slice_base + info->slice_count > max_slice) {
- ilo_warn("invalid slice range\n");
- return false;
- }
-
- assert(d);
- *depth = d - 1;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 325:
- *
- * "For 1D and 2D Surfaces:
- * This field (Minimum Array Element) indicates the minimum array
- * element that can be accessed as part of this surface. The delivered
- * array index is added to this field before being used to address the
- * surface.
- *
- * For 3D Surfaces:
- * This field indicates the minimum `R' coordinate on the LOD
- * currently being rendered to. This field is added to the delivered
- * array index before it is used to address the surface.
- *
- * For Other Surfaces:
- * This field is ignored."
- */
- *min_array_elem = info->slice_base;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 326:
- *
- * "For 3D Surfaces:
- * This field (Render Target View Extent) indicates the extent of the
- * accessible `R' coordinates minus 1 on the LOD currently being
- * rendered to.
- *
- * For 1D and 2D Surfaces:
- * This field must be set to the same value as the Depth field.
- *
- * For Other Surfaces:
- * This field is ignored."
- */
- *rt_view_extent = info->slice_count - 1;
-
- return true;
-}
-
-static bool
-zs_set_gen6_3DSTATE_DEPTH_BUFFER(struct ilo_state_zs *zs,
- const struct ilo_dev *dev,
- const struct ilo_state_zs_info *info)
-{
- uint16_t width, height, depth, array_base, view_extent;
- uint32_t dw1, dw2, dw3, dw4;
-
- ILO_DEV_ASSERT(dev, 6, 6);
-
- if (!zs_validate_gen6(dev, info) ||
- !zs_get_gen6_depth_extent(dev, info, &width, &height) ||
- !zs_get_gen6_depth_slices(dev, info, &depth, &array_base,
- &view_extent))
- return false;
-
- /* info->z_readonly and info->s_readonly are ignored on Gen6 */
- dw1 = info->type << GEN6_DEPTH_DW1_TYPE__SHIFT |
- GEN6_TILING_Y << GEN6_DEPTH_DW1_TILING__SHIFT |
- info->format << GEN6_DEPTH_DW1_FORMAT__SHIFT;
-
- if (info->z_img)
- dw1 |= (info->z_img->bo_stride - 1) << GEN6_DEPTH_DW1_PITCH__SHIFT;
-
- if (info->hiz_vma || !info->z_img) {
- dw1 |= GEN6_DEPTH_DW1_HIZ_ENABLE |
- GEN6_DEPTH_DW1_SEPARATE_STENCIL;
- }
-
- dw2 = 0;
- dw3 = height << GEN6_DEPTH_DW3_HEIGHT__SHIFT |
- width << GEN6_DEPTH_DW3_WIDTH__SHIFT |
- info->level << GEN6_DEPTH_DW3_LOD__SHIFT |
- GEN6_DEPTH_DW3_MIPLAYOUT_BELOW;
- dw4 = depth << GEN6_DEPTH_DW4_DEPTH__SHIFT |
- array_base << GEN6_DEPTH_DW4_MIN_ARRAY_ELEMENT__SHIFT |
- view_extent << GEN6_DEPTH_DW4_RT_VIEW_EXTENT__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(zs->depth) >= 5);
- zs->depth[0] = dw1;
- zs->depth[1] = dw2;
- zs->depth[2] = dw3;
- zs->depth[3] = dw4;
- zs->depth[4] = 0;
-
- return true;
-}
-
-static bool
-zs_set_gen7_3DSTATE_DEPTH_BUFFER(struct ilo_state_zs *zs,
- const struct ilo_dev *dev,
- const struct ilo_state_zs_info *info)
-{
- uint16_t width, height, depth;
- uint16_t array_base, view_extent;
- uint32_t dw1, dw2, dw3, dw4, dw6;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- if (!zs_validate_gen6(dev, info) ||
- !zs_get_gen6_depth_extent(dev, info, &width, &height) ||
- !zs_get_gen6_depth_slices(dev, info, &depth, &array_base,
- &view_extent))
- return false;
-
- dw1 = info->type << GEN7_DEPTH_DW1_TYPE__SHIFT |
- info->format << GEN7_DEPTH_DW1_FORMAT__SHIFT;
-
- if (info->z_img) {
- if (!info->z_readonly)
- dw1 |= GEN7_DEPTH_DW1_DEPTH_WRITE_ENABLE;
- if (info->hiz_vma)
- dw1 |= GEN7_DEPTH_DW1_HIZ_ENABLE;
-
- dw1 |= (info->z_img->bo_stride - 1) << GEN7_DEPTH_DW1_PITCH__SHIFT;
- }
-
- if (info->s_img && !info->s_readonly)
- dw1 |= GEN7_DEPTH_DW1_STENCIL_WRITE_ENABLE;
-
- dw2 = 0;
- dw3 = height << GEN7_DEPTH_DW3_HEIGHT__SHIFT |
- width << GEN7_DEPTH_DW3_WIDTH__SHIFT |
- info->level << GEN7_DEPTH_DW3_LOD__SHIFT;
- dw4 = depth << GEN7_DEPTH_DW4_DEPTH__SHIFT |
- array_base << GEN7_DEPTH_DW4_MIN_ARRAY_ELEMENT__SHIFT;
- dw6 = view_extent << GEN7_DEPTH_DW6_RT_VIEW_EXTENT__SHIFT;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8) && info->z_img) {
- assert(info->z_img->walk_layer_height % 4 == 0);
- /* note that DW is off-by-one for Gen8+ */
- dw6 |= (info->z_img->walk_layer_height / 4) <<
- GEN8_DEPTH_DW7_QPITCH__SHIFT;
- }
-
- STATIC_ASSERT(ARRAY_SIZE(zs->depth) >= 5);
- zs->depth[0] = dw1;
- zs->depth[1] = dw2;
- zs->depth[2] = dw3;
- zs->depth[3] = dw4;
- zs->depth[4] = dw6;
-
- return true;
-}
-
-static bool
-zs_set_gen6_null_3DSTATE_STENCIL_BUFFER(struct ilo_state_zs *zs,
- const struct ilo_dev *dev)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- STATIC_ASSERT(ARRAY_SIZE(zs->stencil) >= 3);
- zs->stencil[0] = 0;
- zs->stencil[1] = 0;
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- zs->stencil[2] = 0;
-
- return true;
-}
-
-static bool
-zs_set_gen6_3DSTATE_STENCIL_BUFFER(struct ilo_state_zs *zs,
- const struct ilo_dev *dev,
- const struct ilo_state_zs_info *info)
-{
- const struct ilo_image *img = info->s_img;
- uint32_t dw1, dw2;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(img->bo_stride);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 329:
- *
- * "The pitch must be set to 2x the value computed based on width, as
- * the stencil buffer is stored with two rows interleaved."
- *
- * For Gen7+, we still dobule the stride because we did not double the
- * slice widths when initializing ilo_image.
- */
- dw1 = (img->bo_stride * 2 - 1) << GEN6_STENCIL_DW1_PITCH__SHIFT;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5))
- dw1 |= GEN75_STENCIL_DW1_STENCIL_BUFFER_ENABLE;
-
- dw2 = 0;
- /* offset to the level as Gen6 does not support mipmapped stencil */
- if (ilo_dev_gen(dev) == ILO_GEN(6)) {
- unsigned x, y;
-
- ilo_image_get_slice_pos(img, info->level, 0, &x, &y);
- ilo_image_pos_to_mem(img, x, y, &x, &y);
- dw2 |= ilo_image_mem_to_raw(img, x, y);
- }
-
- STATIC_ASSERT(ARRAY_SIZE(zs->stencil) >= 3);
- zs->stencil[0] = dw1;
- zs->stencil[1] = dw2;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- uint32_t dw4;
-
- assert(img->walk_layer_height % 4 == 0);
- dw4 = (img->walk_layer_height / 4) << GEN8_STENCIL_DW4_QPITCH__SHIFT;
-
- zs->stencil[2] = dw4;
- }
-
- return true;
-}
-
-static bool
-zs_set_gen6_null_3DSTATE_HIER_DEPTH_BUFFER(struct ilo_state_zs *zs,
- const struct ilo_dev *dev)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- STATIC_ASSERT(ARRAY_SIZE(zs->hiz) >= 3);
- zs->hiz[0] = 0;
- zs->hiz[1] = 0;
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- zs->hiz[2] = 0;
-
- return true;
-}
-
-static bool
-zs_set_gen6_3DSTATE_HIER_DEPTH_BUFFER(struct ilo_state_zs *zs,
- const struct ilo_dev *dev,
- const struct ilo_state_zs_info *info)
-{
- const struct ilo_image *img = info->z_img;
- uint32_t dw1, dw2;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(img->aux.bo_stride);
-
- dw1 = (img->aux.bo_stride - 1) << GEN6_HIZ_DW1_PITCH__SHIFT;
-
- dw2 = 0;
- /* offset to the level as Gen6 does not support mipmapped HiZ */
- if (ilo_dev_gen(dev) == ILO_GEN(6))
- dw2 |= img->aux.walk_lod_offsets[info->level];
-
- STATIC_ASSERT(ARRAY_SIZE(zs->hiz) >= 3);
- zs->hiz[0] = dw1;
- zs->hiz[1] = dw2;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- uint32_t dw4;
-
- assert(img->aux.walk_layer_height % 4 == 0);
- dw4 = (img->aux.walk_layer_height / 4) << GEN8_HIZ_DW4_QPITCH__SHIFT;
-
- zs->hiz[2] = dw4;
- }
-
- return true;
-}
-
-bool
-ilo_state_zs_init(struct ilo_state_zs *zs, const struct ilo_dev *dev,
- const struct ilo_state_zs_info *info)
-{
- bool ret = true;
-
- assert(ilo_is_zeroed(zs, sizeof(*zs)));
-
- if (info->z_img || info->s_img) {
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- ret &= zs_set_gen7_3DSTATE_DEPTH_BUFFER(zs, dev, info);
- else
- ret &= zs_set_gen6_3DSTATE_DEPTH_BUFFER(zs, dev, info);
- } else {
- ret &= zs_set_gen6_null_3DSTATE_DEPTH_BUFFER(zs, dev);
- }
-
- if (info->s_img)
- ret &= zs_set_gen6_3DSTATE_STENCIL_BUFFER(zs, dev, info);
- else
- ret &= zs_set_gen6_null_3DSTATE_STENCIL_BUFFER(zs, dev);
-
- if (info->z_img && info->hiz_vma)
- ret &= zs_set_gen6_3DSTATE_HIER_DEPTH_BUFFER(zs, dev, info);
- else
- ret &= zs_set_gen6_null_3DSTATE_HIER_DEPTH_BUFFER(zs, dev);
-
- zs->z_vma = info->z_vma;
- zs->s_vma = info->s_vma;
- zs->hiz_vma = info->hiz_vma;
-
- zs->z_readonly = info->z_readonly;
- zs->s_readonly = info->s_readonly;
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_zs_init_for_null(struct ilo_state_zs *zs,
- const struct ilo_dev *dev)
-{
- struct ilo_state_zs_info info;
-
- memset(&info, 0, sizeof(info));
- info.type = GEN6_SURFTYPE_NULL;
- info.format = GEN6_ZFORMAT_D32_FLOAT;
-
- return ilo_state_zs_init(zs, dev, &info);
-}
-
-bool
-ilo_state_zs_disable_hiz(struct ilo_state_zs *zs,
- const struct ilo_dev *dev)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * Separate stencil must be disabled simultaneously on Gen6. We can make
- * it work when there is no stencil buffer, but it is probably not worth
- * it.
- */
- assert(ilo_dev_gen(dev) >= ILO_GEN(7));
-
- if (zs->hiz_vma) {
- zs->depth[0] &= ~GEN7_DEPTH_DW1_HIZ_ENABLE;
- zs_set_gen6_null_3DSTATE_HIER_DEPTH_BUFFER(zs, dev);
- zs->hiz_vma = NULL;
- }
-
- return true;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_STATE_ZS_H
-#define ILO_STATE_ZS_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-
-struct ilo_vma;
-struct ilo_image;
-
-struct ilo_state_zs_info {
- /* both optional */
- const struct ilo_image *z_img;
- const struct ilo_image *s_img;
- uint8_t level;
- uint16_t slice_base;
- uint16_t slice_count;
-
- const struct ilo_vma *z_vma;
- const struct ilo_vma *s_vma;
- const struct ilo_vma *hiz_vma;
-
- enum gen_surface_type type;
- enum gen_depth_format format;
-
- /* ignored prior to Gen7 */
- bool z_readonly;
- bool s_readonly;
-};
-
-struct ilo_state_zs {
- uint32_t depth[5];
- uint32_t stencil[3];
- uint32_t hiz[3];
-
- const struct ilo_vma *z_vma;
- const struct ilo_vma *s_vma;
- const struct ilo_vma *hiz_vma;
-
- bool z_readonly;
- bool s_readonly;
-};
-
-bool
-ilo_state_zs_init(struct ilo_state_zs *zs,
- const struct ilo_dev *dev,
- const struct ilo_state_zs_info *info);
-
-bool
-ilo_state_zs_init_for_null(struct ilo_state_zs *zs,
- const struct ilo_dev *dev);
-
-bool
-ilo_state_zs_disable_hiz(struct ilo_state_zs *zs,
- const struct ilo_dev *dev);
-
-#endif /* ILO_STATE_ZS_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_VMA_H
-#define ILO_VMA_H
-
-#include "ilo_core.h"
-#include "ilo_debug.h"
-#include "ilo_dev.h"
-
-struct intel_bo;
-
-/**
- * A virtual memory area.
- */
-struct ilo_vma {
- /* address space */
- uint32_t vm_size;
- uint32_t vm_alignment;
-
- /* backing storage */
- struct intel_bo *bo;
- uint32_t bo_offset;
-};
-
-static inline bool
-ilo_vma_init(struct ilo_vma *vma, const struct ilo_dev *dev,
- uint32_t size, uint32_t alignment)
-{
- assert(ilo_is_zeroed(vma, sizeof(*vma)));
- assert(size && alignment);
-
- vma->vm_alignment = alignment;
- vma->vm_size = size;
-
- return true;
-}
-
-static inline void
-ilo_vma_set_bo(struct ilo_vma *vma, const struct ilo_dev *dev,
- struct intel_bo *bo, uint32_t offset)
-{
- assert(offset % vma->vm_alignment == 0);
-
- vma->bo = bo;
- vma->bo_offset = offset;
-}
-
-#endif /* ILO_VMA_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef INTEL_WINSYS_H
-#define INTEL_WINSYS_H
-
-#include "pipe/p_compiler.h"
-
-/* this is compatible with i915_drm.h's definitions */
-enum intel_ring_type {
- INTEL_RING_RENDER = 1,
- INTEL_RING_BSD = 2,
- INTEL_RING_BLT = 3,
- INTEL_RING_VEBOX = 4,
-};
-
-/* this is compatible with i915_drm.h's definitions */
-enum intel_exec_flag {
- INTEL_EXEC_GEN7_SOL_RESET = 1 << 8,
-};
-
-/* this is compatible with i915_drm.h's definitions */
-enum intel_reloc_flag {
- INTEL_RELOC_FENCE = 1 << 0,
- INTEL_RELOC_GGTT = 1 << 1,
- INTEL_RELOC_WRITE = 1 << 2,
-};
-
-/* this is compatible with i915_drm.h's definitions */
-enum intel_tiling_mode {
- INTEL_TILING_NONE = 0,
- INTEL_TILING_X = 1,
- INTEL_TILING_Y = 2,
-};
-
-struct winsys_handle;
-struct intel_winsys;
-struct intel_context;
-struct intel_bo;
-
-struct intel_winsys_info {
- int devid;
-
- /* the sizes of the aperture in bytes */
- size_t aperture_total;
- size_t aperture_mappable;
-
- bool has_llc;
- bool has_address_swizzling;
- bool has_logical_context;
- bool has_ppgtt;
-
- /* valid registers for intel_winsys_read_reg() */
- bool has_timestamp;
-
- /* valid flags for intel_winsys_submit_bo() */
- bool has_gen7_sol_reset;
-};
-
-void
-intel_winsys_destroy(struct intel_winsys *winsys);
-
-const struct intel_winsys_info *
-intel_winsys_get_info(const struct intel_winsys *winsys);
-
-/**
- * Create a logical context for use with the render ring.
- */
-struct intel_context *
-intel_winsys_create_context(struct intel_winsys *winsys);
-
-/**
- * Destroy a logical context.
- */
-void
-intel_winsys_destroy_context(struct intel_winsys *winsys,
- struct intel_context *ctx);
-
-/**
- * Read a register. Only registers that are considered safe, such as
- *
- * TIMESTAMP (0x2358)
- *
- * can be read.
- */
-int
-intel_winsys_read_reg(struct intel_winsys *winsys,
- uint32_t reg, uint64_t *val);
-
-/**
- * Return the numbers of submissions lost due to GPU reset.
- *
- * \param active_lost Number of lost active/guilty submissions
- * \param pending_lost Number of lost pending/innocent submissions
- */
-int
-intel_winsys_get_reset_stats(struct intel_winsys *winsys,
- struct intel_context *ctx,
- uint32_t *active_lost,
- uint32_t *pending_lost);
-/**
- * Allocate a buffer object.
- *
- * \param name Informative description of the bo.
- * \param size Size of the bo.
- * \param cpu_init Will be initialized by CPU.
- */
-struct intel_bo *
-intel_winsys_alloc_bo(struct intel_winsys *winsys,
- const char *name,
- unsigned long size,
- bool cpu_init);
-
-/**
- * Create a bo from a user memory pointer. Both \p userptr and \p size must
- * be page aligned.
- */
-struct intel_bo *
-intel_winsys_import_userptr(struct intel_winsys *winsys,
- const char *name,
- void *userptr,
- unsigned long size,
- unsigned long flags);
-
-/**
- * Create a bo from a winsys handle.
- */
-struct intel_bo *
-intel_winsys_import_handle(struct intel_winsys *winsys,
- const char *name,
- const struct winsys_handle *handle,
- unsigned long height,
- enum intel_tiling_mode *tiling,
- unsigned long *pitch);
-
-/**
- * Export \p bo as a winsys handle for inter-process sharing. \p tiling and
- * \p pitch must match those set by \p intel_bo_set_tiling().
- */
-int
-intel_winsys_export_handle(struct intel_winsys *winsys,
- struct intel_bo *bo,
- enum intel_tiling_mode tiling,
- unsigned long pitch,
- unsigned long height,
- struct winsys_handle *handle);
-
-/**
- * Return true when buffer objects directly specified in \p bo_array, and
- * those indirectly referenced by them, can fit in the aperture space.
- */
-bool
-intel_winsys_can_submit_bo(struct intel_winsys *winsys,
- struct intel_bo **bo_array,
- int count);
-
-/**
- * Submit \p bo for execution.
- *
- * \p bo and all bos referenced by \p bo will be considered busy until all
- * commands are parsed and executed. \p ctx is ignored when the bo is not
- * submitted to the render ring.
- */
-int
-intel_winsys_submit_bo(struct intel_winsys *winsys,
- enum intel_ring_type ring,
- struct intel_bo *bo, int used,
- struct intel_context *ctx,
- unsigned long flags);
-
-/**
- * Decode the commands contained in \p bo. For debugging.
- *
- * \param bo Batch buffer to decode.
- * \param used Size of the commands in bytes.
- */
-void
-intel_winsys_decode_bo(struct intel_winsys *winsys,
- struct intel_bo *bo, int used);
-
-/**
- * Increase the reference count of \p bo. No-op when \p bo is NULL.
- */
-struct intel_bo *
-intel_bo_ref(struct intel_bo *bo);
-
-/**
- * Decrease the reference count of \p bo. When the reference count reaches
- * zero, \p bo is destroyed. No-op when \p bo is NULL.
- */
-void
-intel_bo_unref(struct intel_bo *bo);
-
-/**
- * Set the tiling of \p bo. The info is used by GTT mapping and bo export.
- */
-int
-intel_bo_set_tiling(struct intel_bo *bo,
- enum intel_tiling_mode tiling,
- unsigned long pitch);
-
-/**
- * Map \p bo for CPU access. Recursive mapping is allowed.
- *
- * map() maps the backing store into CPU address space, cached. It will block
- * if the bo is busy. This variant allows fastest random reads and writes,
- * but the caller needs to handle tiling or swizzling manually if the bo is
- * tiled or swizzled. If write is enabled and there is no shared last-level
- * cache (LLC), the CPU cache will be flushed, which is expensive.
- *
- * map_gtt() maps the bo for MMIO access, uncached but write-combined. It
- * will block if the bo is busy. This variant promises a reasonable speed for
- * sequential writes, but reads would be very slow. Callers always have a
- * linear view of the bo.
- *
- * map_async() and map_gtt_async() work similar to map() and map_gtt()
- * respectively, except that they do not block.
- */
-void *
-intel_bo_map(struct intel_bo *bo, bool write_enable);
-
-void *
-intel_bo_map_async(struct intel_bo *bo);
-
-void *
-intel_bo_map_gtt(struct intel_bo *bo);
-
-void *
-intel_bo_map_gtt_async(struct intel_bo *bo);
-
-/**
- * Unmap \p bo.
- */
-void
-intel_bo_unmap(struct intel_bo *bo);
-
-/**
- * Write data to \p bo.
- */
-int
-intel_bo_pwrite(struct intel_bo *bo, unsigned long offset,
- unsigned long size, const void *data);
-
-/**
- * Read data from the bo.
- */
-int
-intel_bo_pread(struct intel_bo *bo, unsigned long offset,
- unsigned long size, void *data);
-
-/**
- * Add \p target_bo to the relocation list.
- *
- * When \p bo is submitted for execution, and if \p target_bo has moved,
- * the kernel will patch \p bo at \p offset to \p target_bo->offset plus
- * \p target_offset.
- *
- * \p presumed_offset should be written to \p bo at \p offset.
- */
-int
-intel_bo_add_reloc(struct intel_bo *bo, uint32_t offset,
- struct intel_bo *target_bo, uint32_t target_offset,
- uint32_t flags, uint64_t *presumed_offset);
-
-/**
- * Return the current number of relocations.
- */
-int
-intel_bo_get_reloc_count(struct intel_bo *bo);
-
-/**
- * Truncate all relocations except the first \p start ones.
- *
- * Combined with \p intel_bo_get_reloc_count(), they can be used to undo the
- * \p intel_bo_add_reloc() calls that were just made.
- */
-void
-intel_bo_truncate_relocs(struct intel_bo *bo, int start);
-
-/**
- * Return true if \p target_bo is on the relocation list of \p bo, or on
- * the relocation list of some bo that is referenced by \p bo.
- */
-bool
-intel_bo_has_reloc(struct intel_bo *bo, struct intel_bo *target_bo);
-
-/**
- * Wait until \bo is idle, or \p timeout nanoseconds have passed. A
- * negative timeout means to wait indefinitely.
- *
- * \return 0 only when \p bo is idle
- */
-int
-intel_bo_wait(struct intel_bo *bo, int64_t timeout);
-
-/**
- * Return true if \p bo is busy.
- */
-static inline bool
-intel_bo_is_busy(struct intel_bo *bo)
-{
- return (intel_bo_wait(bo, 0) != 0);
-}
-
-#endif /* INTEL_WINSYS_H */
+++ /dev/null
-#ifndef GEN_BLITTER_XML
-#define GEN_BLITTER_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-https://github.com/olvaffe/envytools/
-git clone https://github.com/olvaffe/envytools.git
-
-Copyright (C) 2014-2015 by the following authors:
-- Chia-I Wu <olvaffe@gmail.com> (olv)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-#define GEN6_BLITTER_TYPE__MASK 0xe0000000
-#define GEN6_BLITTER_TYPE__SHIFT 29
-#define GEN6_BLITTER_TYPE_BLITTER (0x2 << 29)
-#define GEN6_BLITTER_OPCODE__MASK 0x1fc00000
-#define GEN6_BLITTER_OPCODE__SHIFT 22
-#define GEN6_BLITTER_OPCODE_COLOR_BLT (0x40 << 22)
-#define GEN6_BLITTER_OPCODE_SRC_COPY_BLT (0x43 << 22)
-#define GEN6_BLITTER_OPCODE_XY_COLOR_BLT (0x50 << 22)
-#define GEN6_BLITTER_OPCODE_XY_SRC_COPY_BLT (0x53 << 22)
-#define GEN6_BLITTER_BR00_WRITE_A (0x1 << 21)
-#define GEN6_BLITTER_BR00_WRITE_RGB (0x1 << 20)
-#define GEN6_BLITTER_BR00_SRC_TILED (0x1 << 15)
-#define GEN6_BLITTER_BR00_DST_TILED (0x1 << 11)
-#define GEN6_BLITTER_LENGTH__MASK 0x0000003f
-#define GEN6_BLITTER_LENGTH__SHIFT 0
-#define GEN6_BLITTER_BR13_DIR_RTL (0x1 << 30)
-#define GEN6_BLITTER_BR13_CLIP_ENABLE (0x1 << 30)
-#define GEN6_BLITTER_BR13_FORMAT__MASK 0x03000000
-#define GEN6_BLITTER_BR13_FORMAT__SHIFT 24
-#define GEN6_BLITTER_BR13_FORMAT_8 (0x0 << 24)
-#define GEN6_BLITTER_BR13_FORMAT_565 (0x1 << 24)
-#define GEN6_BLITTER_BR13_FORMAT_1555 (0x2 << 24)
-#define GEN6_BLITTER_BR13_FORMAT_8888 (0x3 << 24)
-#define GEN6_BLITTER_BR13_ROP__MASK 0x00ff0000
-#define GEN6_BLITTER_BR13_ROP__SHIFT 16
-#define GEN6_BLITTER_BR13_ROP_SRCCOPY (0xcc << 16)
-#define GEN6_BLITTER_BR13_ROP_PATCOPY (0xf0 << 16)
-#define GEN6_BLITTER_BR13_DST_PITCH__MASK 0x0000ffff
-#define GEN6_BLITTER_BR13_DST_PITCH__SHIFT 0
-#define GEN6_BLITTER_BR11_SRC_PITCH__MASK 0x0000ffff
-#define GEN6_BLITTER_BR11_SRC_PITCH__SHIFT 0
-#define GEN6_BLITTER_BR14_DST_HEIGHT__MASK 0xffff0000
-#define GEN6_BLITTER_BR14_DST_HEIGHT__SHIFT 16
-#define GEN6_BLITTER_BR14_DST_WIDTH__MASK 0x0000ffff
-#define GEN6_BLITTER_BR14_DST_WIDTH__SHIFT 0
-#define GEN6_BLITTER_BR22_DST_Y1__MASK 0xffff0000
-#define GEN6_BLITTER_BR22_DST_Y1__SHIFT 16
-#define GEN6_BLITTER_BR22_DST_X1__MASK 0x0000ffff
-#define GEN6_BLITTER_BR22_DST_X1__SHIFT 0
-#define GEN6_BLITTER_BR23_DST_Y2__MASK 0xffff0000
-#define GEN6_BLITTER_BR23_DST_Y2__SHIFT 16
-#define GEN6_BLITTER_BR23_DST_X2__MASK 0x0000ffff
-#define GEN6_BLITTER_BR23_DST_X2__SHIFT 0
-#define GEN6_BLITTER_BR26_SRC_Y1__MASK 0xffff0000
-#define GEN6_BLITTER_BR26_SRC_Y1__SHIFT 16
-#define GEN6_BLITTER_BR26_SRC_X1__MASK 0x0000ffff
-#define GEN6_BLITTER_BR26_SRC_X1__SHIFT 0
-#define GEN6_COLOR_BLT__SIZE 6
-
-
-
-
-
-
-
-
-#define GEN6_SRC_COPY_BLT__SIZE 8
-
-
-
-
-
-
-
-
-
-
-
-#define GEN6_XY_COLOR_BLT__SIZE 7
-
-
-
-
-
-
-
-
-
-#define GEN6_XY_SRC_COPY_BLT__SIZE 10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-#endif /* GEN_BLITTER_XML */
+++ /dev/null
-#ifndef GEN_EU_ISA_XML
-#define GEN_EU_ISA_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-https://github.com/olvaffe/envytools/
-git clone https://github.com/olvaffe/envytools.git
-
-Copyright (C) 2014-2015 by the following authors:
-- Chia-I Wu <olvaffe@gmail.com> (olv)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-enum gen_eu_opcode {
- GEN6_OPCODE_ILLEGAL = 0x0,
- GEN6_OPCODE_MOV = 0x1,
- GEN6_OPCODE_SEL = 0x2,
- GEN6_OPCODE_MOVI = 0x3,
- GEN6_OPCODE_NOT = 0x4,
- GEN6_OPCODE_AND = 0x5,
- GEN6_OPCODE_OR = 0x6,
- GEN6_OPCODE_XOR = 0x7,
- GEN6_OPCODE_SHR = 0x8,
- GEN6_OPCODE_SHL = 0x9,
- GEN6_OPCODE_DIM = 0xa,
- GEN6_OPCODE_ASR = 0xc,
- GEN6_OPCODE_CMP = 0x10,
- GEN6_OPCODE_CMPN = 0x11,
- GEN7_OPCODE_CSEL = 0x12,
- GEN7_OPCODE_F32TO16 = 0x13,
- GEN7_OPCODE_F16TO32 = 0x14,
- GEN7_OPCODE_BFREV = 0x17,
- GEN7_OPCODE_BFE = 0x18,
- GEN7_OPCODE_BFI1 = 0x19,
- GEN7_OPCODE_BFI2 = 0x1a,
- GEN6_OPCODE_JMPI = 0x20,
- GEN7_OPCODE_BRD = 0x21,
- GEN6_OPCODE_IF = 0x22,
- GEN7_OPCODE_BRC = 0x23,
- GEN6_OPCODE_ELSE = 0x24,
- GEN6_OPCODE_ENDIF = 0x25,
- GEN6_OPCODE_CASE = 0x26,
- GEN6_OPCODE_WHILE = 0x27,
- GEN6_OPCODE_BREAK = 0x28,
- GEN6_OPCODE_CONT = 0x29,
- GEN6_OPCODE_HALT = 0x2a,
- GEN75_OPCODE_CALLA = 0x2b,
- GEN6_OPCODE_CALL = 0x2c,
- GEN6_OPCODE_RETURN = 0x2d,
- GEN8_OPCODE_GOTO = 0x2e,
- GEN6_OPCODE_WAIT = 0x30,
- GEN6_OPCODE_SEND = 0x31,
- GEN6_OPCODE_SENDC = 0x32,
- GEN6_OPCODE_MATH = 0x38,
- GEN6_OPCODE_ADD = 0x40,
- GEN6_OPCODE_MUL = 0x41,
- GEN6_OPCODE_AVG = 0x42,
- GEN6_OPCODE_FRC = 0x43,
- GEN6_OPCODE_RNDU = 0x44,
- GEN6_OPCODE_RNDD = 0x45,
- GEN6_OPCODE_RNDE = 0x46,
- GEN6_OPCODE_RNDZ = 0x47,
- GEN6_OPCODE_MAC = 0x48,
- GEN6_OPCODE_MACH = 0x49,
- GEN6_OPCODE_LZD = 0x4a,
- GEN7_OPCODE_FBH = 0x4b,
- GEN7_OPCODE_FBL = 0x4c,
- GEN7_OPCODE_CBIT = 0x4d,
- GEN7_OPCODE_ADDC = 0x4e,
- GEN7_OPCODE_SUBB = 0x4f,
- GEN6_OPCODE_SAD2 = 0x50,
- GEN6_OPCODE_SADA2 = 0x51,
- GEN6_OPCODE_DP4 = 0x54,
- GEN6_OPCODE_DPH = 0x55,
- GEN6_OPCODE_DP3 = 0x56,
- GEN6_OPCODE_DP2 = 0x57,
- GEN6_OPCODE_LINE = 0x59,
- GEN6_OPCODE_PLN = 0x5a,
- GEN6_OPCODE_MAD = 0x5b,
- GEN6_OPCODE_LRP = 0x5c,
- GEN6_OPCODE_NOP = 0x7e,
-};
-
-enum gen_eu_access_mode {
- GEN6_ALIGN_1 = 0x0,
- GEN6_ALIGN_16 = 0x1,
-};
-
-enum gen_eu_mask_control {
- GEN6_MASKCTRL_NORMAL = 0x0,
- GEN6_MASKCTRL_NOMASK = 0x1,
-};
-
-enum gen_eu_dependency_control {
- GEN6_DEPCTRL_NORMAL = 0x0,
- GEN6_DEPCTRL_NODDCLR = 0x1,
- GEN6_DEPCTRL_NODDCHK = 0x2,
- GEN6_DEPCTRL_NEITHER = 0x3,
-};
-
-enum gen_eu_quarter_control {
- GEN6_QTRCTRL_1Q = 0x0,
- GEN6_QTRCTRL_2Q = 0x1,
- GEN6_QTRCTRL_3Q = 0x2,
- GEN6_QTRCTRL_4Q = 0x3,
- GEN6_QTRCTRL_1H = 0x0,
- GEN6_QTRCTRL_2H = 0x2,
-};
-
-enum gen_eu_thread_control {
- GEN6_THREADCTRL_NORMAL = 0x0,
- GEN6_THREADCTRL_ATOMIC = 0x1,
- GEN6_THREADCTRL_SWITCH = 0x2,
-};
-
-enum gen_eu_predicate_control {
- GEN6_PREDCTRL_NONE = 0x0,
- GEN6_PREDCTRL_NORMAL = 0x1,
- GEN6_PREDCTRL_ANYV = 0x2,
- GEN6_PREDCTRL_ALLV = 0x3,
- GEN6_PREDCTRL_ANY2H = 0x4,
- GEN6_PREDCTRL_ALL2H = 0x5,
- GEN6_PREDCTRL_X = 0x2,
- GEN6_PREDCTRL_Y = 0x3,
- GEN6_PREDCTRL_Z = 0x4,
- GEN6_PREDCTRL_W = 0x5,
- GEN6_PREDCTRL_ANY4H = 0x6,
- GEN6_PREDCTRL_ALL4H = 0x7,
- GEN6_PREDCTRL_ANY8H = 0x8,
- GEN6_PREDCTRL_ALL8H = 0x9,
- GEN6_PREDCTRL_ANY16H = 0xa,
- GEN6_PREDCTRL_ALL16H = 0xb,
- GEN7_PREDCTRL_ANY32H = 0xc,
- GEN7_PREDCTRL_ALL32H = 0xd,
-};
-
-enum gen_eu_exec_size {
- GEN6_EXECSIZE_1 = 0x0,
- GEN6_EXECSIZE_2 = 0x1,
- GEN6_EXECSIZE_4 = 0x2,
- GEN6_EXECSIZE_8 = 0x3,
- GEN6_EXECSIZE_16 = 0x4,
- GEN6_EXECSIZE_32 = 0x5,
-};
-
-enum gen_eu_condition_modifier {
- GEN6_COND_NONE = 0x0,
- GEN6_COND_Z = 0x1,
- GEN6_COND_NZ = 0x2,
- GEN6_COND_G = 0x3,
- GEN6_COND_GE = 0x4,
- GEN6_COND_L = 0x5,
- GEN6_COND_LE = 0x6,
- GEN6_COND_O = 0x8,
- GEN6_COND_U = 0x9,
-};
-
-enum gen_eu_math_function_control {
- GEN6_MATH_INV = 0x1,
- GEN6_MATH_LOG = 0x2,
- GEN6_MATH_EXP = 0x3,
- GEN6_MATH_SQRT = 0x4,
- GEN6_MATH_RSQ = 0x5,
- GEN6_MATH_SIN = 0x6,
- GEN6_MATH_COS = 0x7,
- GEN6_MATH_FDIV = 0x9,
- GEN6_MATH_POW = 0xa,
- GEN6_MATH_INT_DIV = 0xb,
- GEN6_MATH_INT_DIV_QUOTIENT = 0xc,
- GEN6_MATH_INT_DIV_REMAINDER = 0xd,
- GEN8_MATH_INVM = 0xe,
- GEN8_MATH_RSQRTM = 0xf,
-};
-
-enum gen_eu_shared_function_id {
- GEN6_SFID_NULL = 0x0,
- GEN6_SFID_SAMPLER = 0x2,
- GEN6_SFID_GATEWAY = 0x3,
- GEN6_SFID_DP_SAMPLER = 0x4,
- GEN6_SFID_DP_RC = 0x5,
- GEN6_SFID_URB = 0x6,
- GEN6_SFID_SPAWNER = 0x7,
- GEN6_SFID_VME = 0x8,
- GEN6_SFID_DP_CC = 0x9,
- GEN7_SFID_DP_DC0 = 0xa,
- GEN7_SFID_PI = 0xb,
- GEN75_SFID_DP_DC1 = 0xc,
-};
-
-enum gen_eu_reg_file {
- GEN6_FILE_ARF = 0x0,
- GEN6_FILE_GRF = 0x1,
- GEN6_FILE_MRF = 0x2,
- GEN6_FILE_IMM = 0x3,
-};
-
-enum gen_eu_reg_type {
- GEN6_TYPE_UD = 0x0,
- GEN6_TYPE_D = 0x1,
- GEN6_TYPE_UW = 0x2,
- GEN6_TYPE_W = 0x3,
- GEN6_TYPE_UB = 0x4,
- GEN6_TYPE_B = 0x5,
- GEN7_TYPE_DF = 0x6,
- GEN6_TYPE_F = 0x7,
- GEN8_TYPE_UQ = 0x8,
- GEN8_TYPE_Q = 0x9,
- GEN8_TYPE_HF = 0xa,
- GEN6_TYPE_UV_IMM = 0x4,
- GEN6_TYPE_VF_IMM = 0x5,
- GEN6_TYPE_V_IMM = 0x6,
- GEN8_TYPE_DF_IMM = 0xa,
- GEN8_TYPE_HF_IMM = 0xb,
- GEN7_TYPE_F_3SRC = 0x0,
- GEN7_TYPE_D_3SRC = 0x1,
- GEN7_TYPE_UD_3SRC = 0x2,
- GEN7_TYPE_DF_3SRC = 0x3,
-};
-
-enum gen_eu_vertical_stride {
- GEN6_VERTSTRIDE_0 = 0x0,
- GEN6_VERTSTRIDE_1 = 0x1,
- GEN6_VERTSTRIDE_2 = 0x2,
- GEN6_VERTSTRIDE_4 = 0x3,
- GEN6_VERTSTRIDE_8 = 0x4,
- GEN6_VERTSTRIDE_16 = 0x5,
- GEN6_VERTSTRIDE_32 = 0x6,
- GEN6_VERTSTRIDE_VXH = 0xf,
-};
-
-enum gen_eu_width {
- GEN6_WIDTH_1 = 0x0,
- GEN6_WIDTH_2 = 0x1,
- GEN6_WIDTH_4 = 0x2,
- GEN6_WIDTH_8 = 0x3,
- GEN6_WIDTH_16 = 0x4,
-};
-
-enum gen_eu_horizontal_stride {
- GEN6_HORZSTRIDE_0 = 0x0,
- GEN6_HORZSTRIDE_1 = 0x1,
- GEN6_HORZSTRIDE_2 = 0x2,
- GEN6_HORZSTRIDE_4 = 0x3,
-};
-
-enum gen_eu_addressing_mode {
- GEN6_ADDRMODE_DIRECT = 0x0,
- GEN6_ADDRMODE_INDIRECT = 0x1,
-};
-
-enum gen_eu_swizzle {
- GEN6_SWIZZLE_X = 0x0,
- GEN6_SWIZZLE_Y = 0x1,
- GEN6_SWIZZLE_Z = 0x2,
- GEN6_SWIZZLE_W = 0x3,
-};
-
-enum gen_eu_arf_reg {
- GEN6_ARF_NULL = 0x0,
- GEN6_ARF_A0 = 0x10,
- GEN6_ARF_ACC0 = 0x20,
- GEN6_ARF_F0 = 0x30,
- GEN6_ARF_SR0 = 0x70,
- GEN6_ARF_CR0 = 0x80,
- GEN6_ARF_N0 = 0x90,
- GEN6_ARF_IP = 0xa0,
- GEN6_ARF_TDR = 0xb0,
- GEN7_ARF_TM0 = 0xc0,
-};
-
-#define GEN6_INST_SATURATE (0x1 << 31)
-#define GEN6_INST_DEBUGCTRL (0x1 << 30)
-#define GEN6_INST_CMPTCTRL (0x1 << 29)
-#define GEN8_INST_BRANCHCTRL (0x1 << 28)
-#define GEN6_INST_ACCWRCTRL (0x1 << 28)
-#define GEN6_INST_CONDMODIFIER__MASK 0x0f000000
-#define GEN6_INST_CONDMODIFIER__SHIFT 24
-#define GEN6_INST_SFID__MASK 0x0f000000
-#define GEN6_INST_SFID__SHIFT 24
-#define GEN6_INST_FC__MASK 0x0f000000
-#define GEN6_INST_FC__SHIFT 24
-#define GEN6_INST_EXECSIZE__MASK 0x00e00000
-#define GEN6_INST_EXECSIZE__SHIFT 21
-#define GEN6_INST_PREDINV (0x1 << 20)
-#define GEN6_INST_PREDCTRL__MASK 0x000f0000
-#define GEN6_INST_PREDCTRL__SHIFT 16
-#define GEN6_INST_THREADCTRL__MASK 0x0000c000
-#define GEN6_INST_THREADCTRL__SHIFT 14
-#define GEN6_INST_QTRCTRL__MASK 0x00003000
-#define GEN6_INST_QTRCTRL__SHIFT 12
-#define GEN6_INST_DEPCTRL__MASK 0x00000c00
-#define GEN6_INST_DEPCTRL__SHIFT 10
-#define GEN6_INST_MASKCTRL__MASK 0x00000200
-#define GEN6_INST_MASKCTRL__SHIFT 9
-#define GEN8_INST_NIBCTRL (0x1 << 11)
-#define GEN8_INST_DEPCTRL__MASK 0x00000600
-#define GEN8_INST_DEPCTRL__SHIFT 9
-#define GEN6_INST_ACCESSMODE__MASK 0x00000100
-#define GEN6_INST_ACCESSMODE__SHIFT 8
-#define GEN6_INST_OPCODE__MASK 0x0000007f
-#define GEN6_INST_OPCODE__SHIFT 0
-#define GEN6_INST_DST_ADDRMODE__MASK 0x80000000
-#define GEN6_INST_DST_ADDRMODE__SHIFT 31
-#define GEN6_INST_DST_HORZSTRIDE__MASK 0x60000000
-#define GEN6_INST_DST_HORZSTRIDE__SHIFT 29
-#define GEN6_INST_DST_REG__MASK 0x1fe00000
-#define GEN6_INST_DST_REG__SHIFT 21
-#define GEN6_INST_DST_SUBREG__MASK 0x001f0000
-#define GEN6_INST_DST_SUBREG__SHIFT 16
-#define GEN6_INST_DST_ADDR_SUBREG__MASK 0x1c000000
-#define GEN6_INST_DST_ADDR_SUBREG__SHIFT 26
-#define GEN6_INST_DST_ADDR_IMM__MASK 0x03ff0000
-#define GEN6_INST_DST_ADDR_IMM__SHIFT 16
-#define GEN8_INST_DST_ADDR_SUBREG__MASK 0x1e000000
-#define GEN8_INST_DST_ADDR_SUBREG__SHIFT 25
-#define GEN8_INST_DST_ADDR_IMM__MASK 0x01ff0000
-#define GEN8_INST_DST_ADDR_IMM__SHIFT 16
-#define GEN6_INST_DST_SUBREG_ALIGN16__MASK 0x00100000
-#define GEN6_INST_DST_SUBREG_ALIGN16__SHIFT 20
-#define GEN6_INST_DST_SUBREG_ALIGN16__SHR 4
-#define GEN6_INST_DST_ADDR_IMM_ALIGN16__MASK 0x03f00000
-#define GEN6_INST_DST_ADDR_IMM_ALIGN16__SHIFT 20
-#define GEN6_INST_DST_ADDR_IMM_ALIGN16__SHR 4
-#define GEN8_INST_DST_ADDR_IMM_ALIGN16__MASK 0x01f00000
-#define GEN8_INST_DST_ADDR_IMM_ALIGN16__SHIFT 20
-#define GEN8_INST_DST_ADDR_IMM_ALIGN16__SHR 4
-#define GEN6_INST_DST_WRITEMASK__MASK 0x000f0000
-#define GEN6_INST_DST_WRITEMASK__SHIFT 16
-#define GEN7_INST_NIBCTRL (0x1 << 15)
-#define GEN6_INST_SRC1_TYPE__MASK 0x00007000
-#define GEN6_INST_SRC1_TYPE__SHIFT 12
-#define GEN6_INST_SRC1_FILE__MASK 0x00000c00
-#define GEN6_INST_SRC1_FILE__SHIFT 10
-#define GEN6_INST_SRC0_TYPE__MASK 0x00000380
-#define GEN6_INST_SRC0_TYPE__SHIFT 7
-#define GEN6_INST_SRC0_FILE__MASK 0x00000060
-#define GEN6_INST_SRC0_FILE__SHIFT 5
-#define GEN6_INST_DST_TYPE__MASK 0x0000001c
-#define GEN6_INST_DST_TYPE__SHIFT 2
-#define GEN6_INST_DST_FILE__MASK 0x00000003
-#define GEN6_INST_DST_FILE__SHIFT 0
-#define GEN8_INST_DST_ADDR_IMM_BIT9__MASK 0x00008000
-#define GEN8_INST_DST_ADDR_IMM_BIT9__SHIFT 15
-#define GEN8_INST_DST_ADDR_IMM_BIT9__SHR 9
-#define GEN8_INST_SRC0_TYPE__MASK 0x00007800
-#define GEN8_INST_SRC0_TYPE__SHIFT 11
-#define GEN8_INST_SRC0_FILE__MASK 0x00000600
-#define GEN8_INST_SRC0_FILE__SHIFT 9
-#define GEN8_INST_DST_TYPE__MASK 0x000001e0
-#define GEN8_INST_DST_TYPE__SHIFT 5
-#define GEN8_INST_DST_FILE__MASK 0x00000018
-#define GEN8_INST_DST_FILE__SHIFT 3
-#define GEN8_INST_MASKCTRL__MASK 0x00000004
-#define GEN8_INST_MASKCTRL__SHIFT 2
-#define GEN8_INST_FLAG_REG__MASK 0x00000002
-#define GEN8_INST_FLAG_REG__SHIFT 1
-#define GEN8_INST_FLAG_SUBREG__MASK 0x00000001
-#define GEN8_INST_FLAG_SUBREG__SHIFT 0
-#define GEN7_INST_FLAG_REG__MASK 0x04000000
-#define GEN7_INST_FLAG_REG__SHIFT 26
-#define GEN6_INST_FLAG_SUBREG__MASK 0x02000000
-#define GEN6_INST_FLAG_SUBREG__SHIFT 25
-#define GEN8_INST_SRC0_ADDR_IMM_BIT9__MASK 0x80000000
-#define GEN8_INST_SRC0_ADDR_IMM_BIT9__SHIFT 31
-#define GEN8_INST_SRC0_ADDR_IMM_BIT9__SHR 9
-#define GEN8_INST_SRC1_TYPE__MASK 0x78000000
-#define GEN8_INST_SRC1_TYPE__SHIFT 27
-#define GEN8_INST_SRC1_FILE__MASK 0x06000000
-#define GEN8_INST_SRC1_FILE__SHIFT 25
-#define GEN8_INST_SRC1_ADDR_IMM_BIT9__MASK 0x02000000
-#define GEN8_INST_SRC1_ADDR_IMM_BIT9__SHIFT 25
-#define GEN8_INST_SRC1_ADDR_IMM_BIT9__SHR 9
-#define GEN6_INST_SRC_VERTSTRIDE__MASK 0x01e00000
-#define GEN6_INST_SRC_VERTSTRIDE__SHIFT 21
-#define GEN6_INST_SRC_WIDTH__MASK 0x001c0000
-#define GEN6_INST_SRC_WIDTH__SHIFT 18
-#define GEN6_INST_SRC_HORZSTRIDE__MASK 0x00030000
-#define GEN6_INST_SRC_HORZSTRIDE__SHIFT 16
-#define GEN6_INST_SRC_SWIZZLE_W__MASK 0x000c0000
-#define GEN6_INST_SRC_SWIZZLE_W__SHIFT 18
-#define GEN6_INST_SRC_SWIZZLE_Z__MASK 0x00030000
-#define GEN6_INST_SRC_SWIZZLE_Z__SHIFT 16
-#define GEN6_INST_SRC_ADDRMODE__MASK 0x00008000
-#define GEN6_INST_SRC_ADDRMODE__SHIFT 15
-#define GEN6_INST_SRC_NEGATE (0x1 << 14)
-#define GEN6_INST_SRC_ABSOLUTE (0x1 << 13)
-#define GEN6_INST_SRC_REG__MASK 0x00001fe0
-#define GEN6_INST_SRC_REG__SHIFT 5
-#define GEN6_INST_SRC_SUBREG__MASK 0x0000001f
-#define GEN6_INST_SRC_SUBREG__SHIFT 0
-#define GEN6_INST_SRC_ADDR_SUBREG__MASK 0x00001c00
-#define GEN6_INST_SRC_ADDR_SUBREG__SHIFT 10
-#define GEN6_INST_SRC_ADDR_IMM__MASK 0x000003ff
-#define GEN6_INST_SRC_ADDR_IMM__SHIFT 0
-#define GEN8_INST_SRC_ADDR_SUBREG__MASK 0x00001e00
-#define GEN8_INST_SRC_ADDR_SUBREG__SHIFT 9
-#define GEN8_INST_SRC_ADDR_IMM__MASK 0x000001ff
-#define GEN8_INST_SRC_ADDR_IMM__SHIFT 0
-#define GEN6_INST_SRC_SUBREG_ALIGN16__MASK 0x00000010
-#define GEN6_INST_SRC_SUBREG_ALIGN16__SHIFT 4
-#define GEN6_INST_SRC_SUBREG_ALIGN16__SHR 4
-#define GEN6_INST_SRC_ADDR_IMM_ALIGN16__MASK 0x000003f0
-#define GEN6_INST_SRC_ADDR_IMM_ALIGN16__SHIFT 4
-#define GEN6_INST_SRC_ADDR_IMM_ALIGN16__SHR 4
-#define GEN8_INST_SRC_ADDR_IMM_ALIGN16__MASK 0x000001f0
-#define GEN8_INST_SRC_ADDR_IMM_ALIGN16__SHIFT 4
-#define GEN8_INST_SRC_ADDR_IMM_ALIGN16__SHR 4
-#define GEN6_INST_SRC_SWIZZLE_Y__MASK 0x0000000c
-#define GEN6_INST_SRC_SWIZZLE_Y__SHIFT 2
-#define GEN6_INST_SRC_SWIZZLE_X__MASK 0x00000003
-#define GEN6_INST_SRC_SWIZZLE_X__SHIFT 0
-#define GEN6_3SRC_DST_REG__MASK 0xff000000
-#define GEN6_3SRC_DST_REG__SHIFT 24
-#define GEN6_3SRC_DST_SUBREG__MASK 0x00e00000
-#define GEN6_3SRC_DST_SUBREG__SHIFT 21
-#define GEN6_3SRC_DST_SUBREG__SHR 2
-#define GEN6_3SRC_DST_WRITEMASK__MASK 0x001e0000
-#define GEN6_3SRC_DST_WRITEMASK__SHIFT 17
-#define GEN7_3SRC_NIBCTRL (0x1 << 15)
-#define GEN7_3SRC_DST_TYPE__MASK 0x00003000
-#define GEN7_3SRC_DST_TYPE__SHIFT 12
-#define GEN7_3SRC_SRC_TYPE__MASK 0x00000c00
-#define GEN7_3SRC_SRC_TYPE__SHIFT 10
-#define GEN6_3SRC_SRC2_NEGATE (0x1 << 9)
-#define GEN6_3SRC_SRC2_ABSOLUTE (0x1 << 8)
-#define GEN6_3SRC_SRC1_NEGATE (0x1 << 7)
-#define GEN6_3SRC_SRC1_ABSOLUTE (0x1 << 6)
-#define GEN6_3SRC_SRC0_NEGATE (0x1 << 5)
-#define GEN6_3SRC_SRC0_ABSOLUTE (0x1 << 4)
-#define GEN7_3SRC_FLAG_REG__MASK 0x00000004
-#define GEN7_3SRC_FLAG_REG__SHIFT 2
-#define GEN6_3SRC_FLAG_SUBREG__MASK 0x00000002
-#define GEN6_3SRC_FLAG_SUBREG__SHIFT 1
-#define GEN6_3SRC_DST_FILE_MRF (0x1 << 0)
-#define GEN8_3SRC_DST_TYPE__MASK 0x0001c000
-#define GEN8_3SRC_DST_TYPE__SHIFT 14
-#define GEN8_3SRC_SRC_TYPE__MASK 0x00003800
-#define GEN8_3SRC_SRC_TYPE__SHIFT 11
-#define GEN8_3SRC_SRC2_NEGATE (0x1 << 10)
-#define GEN8_3SRC_SRC2_ABSOLUTE (0x1 << 9)
-#define GEN8_3SRC_SRC1_NEGATE (0x1 << 8)
-#define GEN8_3SRC_SRC1_ABSOLUTE (0x1 << 7)
-#define GEN8_3SRC_SRC0_NEGATE (0x1 << 6)
-#define GEN8_3SRC_SRC0_ABSOLUTE (0x1 << 5)
-#define GEN8_3SRC_MASKCTRL__MASK 0x00000004
-#define GEN8_3SRC_MASKCTRL__SHIFT 2
-#define GEN8_3SRC_FLAG_REG__MASK 0x00000002
-#define GEN8_3SRC_FLAG_REG__SHIFT 1
-#define GEN8_3SRC_FLAG_SUBREG__MASK 0x00000001
-#define GEN8_3SRC_FLAG_SUBREG__SHIFT 0
-#define GEN6_3SRC_SRC_REG__MASK 0x000ff000
-#define GEN6_3SRC_SRC_REG__SHIFT 12
-#define GEN6_3SRC_SRC_SUBREG__MASK 0x00000e00
-#define GEN6_3SRC_SRC_SUBREG__SHIFT 9
-#define GEN6_3SRC_SRC_SUBREG__SHR 2
-#define GEN6_3SRC_SRC_SWIZZLE_W__MASK 0x00000180
-#define GEN6_3SRC_SRC_SWIZZLE_W__SHIFT 7
-#define GEN6_3SRC_SRC_SWIZZLE_Z__MASK 0x00000060
-#define GEN6_3SRC_SRC_SWIZZLE_Z__SHIFT 5
-#define GEN6_3SRC_SRC_SWIZZLE_Y__MASK 0x00000018
-#define GEN6_3SRC_SRC_SWIZZLE_Y__SHIFT 3
-#define GEN6_3SRC_SRC_SWIZZLE_X__MASK 0x00000006
-#define GEN6_3SRC_SRC_SWIZZLE_X__SHIFT 1
-#define GEN6_3SRC_SRC_REPCTRL (0x1 << 0)
-#define GEN6_COMPACT_SRC1_REG__MASK 0xff00000000000000ULL
-#define GEN6_COMPACT_SRC1_REG__SHIFT 56
-#define GEN6_COMPACT_SRC0_REG__MASK 0x00ff000000000000ULL
-#define GEN6_COMPACT_SRC0_REG__SHIFT 48
-#define GEN6_COMPACT_DST_REG__MASK 0x0000ff0000000000ULL
-#define GEN6_COMPACT_DST_REG__SHIFT 40
-#define GEN6_COMPACT_SRC1_INDEX__MASK 0x000000f800000000ULL
-#define GEN6_COMPACT_SRC1_INDEX__SHIFT 35
-#define GEN6_COMPACT_SRC0_INDEX__MASK 0x00000007c0000000ULL
-#define GEN6_COMPACT_SRC0_INDEX__SHIFT 30
-#define GEN6_COMPACT_CMPTCTRL (0x1 << 29)
-#define GEN6_COMPACT_FLAG_SUBREG__MASK 0x10000000
-#define GEN6_COMPACT_FLAG_SUBREG__SHIFT 28
-#define GEN6_COMPACT_CONDMODIFIER__MASK 0x0f000000
-#define GEN6_COMPACT_CONDMODIFIER__SHIFT 24
-#define GEN6_COMPACT_ACCWRCTRL (0x1 << 23)
-#define GEN6_COMPACT_SUBREG_INDEX__MASK 0x007c0000
-#define GEN6_COMPACT_SUBREG_INDEX__SHIFT 18
-#define GEN6_COMPACT_DATATYPE_INDEX__MASK 0x0003e000
-#define GEN6_COMPACT_DATATYPE_INDEX__SHIFT 13
-#define GEN6_COMPACT_CONTROL_INDEX__MASK 0x00001f00
-#define GEN6_COMPACT_CONTROL_INDEX__SHIFT 8
-#define GEN6_COMPACT_DEBUGCTRL (0x1 << 7)
-#define GEN6_COMPACT_OPCODE__MASK 0x0000007f
-#define GEN6_COMPACT_OPCODE__SHIFT 0
-#define GEN8_COMPACT_3SRC_SRC2_REG__MASK 0xfe00000000000000ULL
-#define GEN8_COMPACT_3SRC_SRC2_REG__SHIFT 57
-#define GEN8_COMPACT_3SRC_SRC2_REG__SHR 1
-#define GEN8_COMPACT_3SRC_SRC1_REG__MASK 0x01fc000000000000ULL
-#define GEN8_COMPACT_3SRC_SRC1_REG__SHIFT 50
-#define GEN8_COMPACT_3SRC_SRC1_REG__SHR 1
-#define GEN8_COMPACT_3SRC_SRC0_REG__MASK 0x0003f80000000000ULL
-#define GEN8_COMPACT_3SRC_SRC0_REG__SHIFT 43
-#define GEN8_COMPACT_3SRC_SRC0_REG__SHR 1
-#define GEN8_COMPACT_3SRC_SRC2_SUBREG__MASK 0x0000070000000000ULL
-#define GEN8_COMPACT_3SRC_SRC2_SUBREG__SHIFT 40
-#define GEN8_COMPACT_3SRC_SRC2_SUBREG__SHR 2
-#define GEN8_COMPACT_3SRC_SRC1_SUBREG__MASK 0x000000e000000000ULL
-#define GEN8_COMPACT_3SRC_SRC1_SUBREG__SHIFT 37
-#define GEN8_COMPACT_3SRC_SRC1_SUBREG__SHR 2
-#define GEN8_COMPACT_3SRC_SRC0_SUBREG__MASK 0x0000001c00000000ULL
-#define GEN8_COMPACT_3SRC_SRC0_SUBREG__SHIFT 34
-#define GEN8_COMPACT_3SRC_SRC0_SUBREG__SHR 2
-#define GEN8_COMPACT_3SRC_SRC2_REPCTRL (0x1ULL << 33)
-#define GEN8_COMPACT_3SRC_SRC1_REPCTRL (0x1ULL << 32)
-#define GEN8_COMPACT_3SRC_SATURATE (0x1 << 31)
-#define GEN8_COMPACT_3SRC_DEBUGCTRL (0x1 << 30)
-#define GEN8_COMPACT_3SRC_CMPTCTRL (0x1 << 29)
-#define GEN8_COMPACT_3SRC_SRC0_REPCTRL (0x1 << 28)
-#define GEN8_COMPACT_3SRC_DST_REG__MASK 0x0007f000
-#define GEN8_COMPACT_3SRC_DST_REG__SHIFT 12
-#define GEN8_COMPACT_3SRC_SOURCE_INDEX__MASK 0x00000c00
-#define GEN8_COMPACT_3SRC_SOURCE_INDEX__SHIFT 10
-#define GEN8_COMPACT_3SRC_CONTROL_INDEX__MASK 0x00000300
-#define GEN8_COMPACT_3SRC_CONTROL_INDEX__SHIFT 8
-#define GEN8_COMPACT_3SRC_OPCODE__MASK 0x0000007f
-#define GEN8_COMPACT_3SRC_OPCODE__SHIFT 0
-
-
-
-
-
-
-
-
-#define GEN6_3SRC_SRC_2__MASK 0x7ffffc0000000000ULL
-#define GEN6_3SRC_SRC_2__SHIFT 42
-#define GEN6_3SRC_SRC_1__MASK 0x000003ffffe00000ULL
-#define GEN6_3SRC_SRC_1__SHIFT 21
-#define GEN6_3SRC_SRC_0__MASK 0x001fffff
-#define GEN6_3SRC_SRC_0__SHIFT 0
-
-
-
-
-
-
-#endif /* GEN_EU_ISA_XML */
+++ /dev/null
-#ifndef GEN_EU_MESSAGE_XML
-#define GEN_EU_MESSAGE_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-https://github.com/olvaffe/envytools/
-git clone https://github.com/olvaffe/envytools.git
-
-Copyright (C) 2014-2015 by the following authors:
-- Chia-I Wu <olvaffe@gmail.com> (olv)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-enum gen_eu_urb_op {
- GEN6_MSG_URB_WRITE = 0x0,
- GEN6_MSG_URB_FF_SYNC = 0x1,
- GEN7_MSG_URB_WRITE_HWORD = 0x0,
- GEN7_MSG_URB_WRITE_OWORD = 0x1,
- GEN7_MSG_URB_READ_HWORD = 0x2,
- GEN7_MSG_URB_READ_OWORD = 0x3,
- GEN7_MSG_URB_ATOMIC_MOV = 0x4,
- GEN7_MSG_URB_ATOMIC_INC = 0x5,
- GEN75_MSG_URB_ATOMIC_ADD = 0x6,
- GEN8_MSG_URB_SIMD8_WRITE = 0x7,
- GEN8_MSG_URB_SIMD8_READ = 0x8,
-};
-
-enum gen_eu_pi_simd {
- GEN7_MSG_PI_SIMD8 = 0x0,
- GEN7_MSG_PI_SIMD16 = 0x1,
-};
-
-enum gen_eu_pi_op {
- GEN7_MSG_PI_EVAL_SNAPPED_IMM = 0x0,
- GEN7_MSG_PI_EVAL_SINDEX = 0x1,
- GEN7_MSG_PI_EVAL_CENTROID = 0x2,
- GEN7_MSG_PI_EVAL_SNAPPED = 0x3,
-};
-
-enum gen_eu_sampler_simd {
- GEN6_MSG_SAMPLER_SIMD4X2 = 0x0,
- GEN9_MSG_SAMPLER_SIMD8D = 0x0,
- GEN6_MSG_SAMPLER_SIMD8 = 0x1,
- GEN6_MSG_SAMPLER_SIMD16 = 0x2,
- GEN6_MSG_SAMPLER_SIMD32_64 = 0x3,
-};
-
-enum gen_eu_sampler_op {
- GEN6_MSG_SAMPLER_SAMPLE = 0x0,
- GEN6_MSG_SAMPLER_SAMPLE_B = 0x1,
- GEN6_MSG_SAMPLER_SAMPLE_L = 0x2,
- GEN6_MSG_SAMPLER_SAMPLE_C = 0x3,
- GEN6_MSG_SAMPLER_SAMPLE_D = 0x4,
- GEN6_MSG_SAMPLER_SAMPLE_B_C = 0x5,
- GEN6_MSG_SAMPLER_SAMPLE_L_C = 0x6,
- GEN6_MSG_SAMPLER_LD = 0x7,
- GEN6_MSG_SAMPLER_GATHER4 = 0x8,
- GEN6_MSG_SAMPLER_LOD = 0x9,
- GEN6_MSG_SAMPLER_RESINFO = 0xa,
- GEN6_MSG_SAMPLER_SAMPLEINFO = 0xb,
- GEN7_MSG_SAMPLER_GATHER4_C = 0x10,
- GEN7_MSG_SAMPLER_GATHER4_PO = 0x11,
- GEN7_MSG_SAMPLER_GATHER4_PO_C = 0x12,
- GEN7_MSG_SAMPLER_SAMPLE_D_C = 0x14,
- GEN7_MSG_SAMPLER_SAMPLE_LZ = 0x18,
- GEN7_MSG_SAMPLER_SAMPLE_C_LC = 0x19,
- GEN7_MSG_SAMPLER_LD_LZ = 0x1a,
- GEN7_MSG_SAMPLER_LD_MCS = 0x1d,
- GEN7_MSG_SAMPLER_LD2DMS = 0x1e,
- GEN7_MSG_SAMPLER_LD2DSS = 0x1f,
-};
-
-enum gen_eu_dp_op {
- GEN6_MSG_DP_OWORD_BLOCK_READ = 0x0,
- GEN6_MSG_DP_RT_UNORM_READ = 0x1,
- GEN6_MSG_DP_OWORD_DUAL_BLOCK_READ = 0x2,
- GEN6_MSG_DP_MEDIA_BLOCK_READ = 0x4,
- GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_READ = 0x5,
- GEN6_MSG_DP_DWORD_SCATTERED_READ = 0x6,
- GEN6_MSG_DP_DWORD_ATOMIC_WRITE = 0x7,
- GEN6_MSG_DP_OWORD_BLOCK_WRITE = 0x8,
- GEN6_MSG_DP_OWORD_DUAL_BLOCK_WRITE = 0x9,
- GEN6_MSG_DP_MEDIA_BLOCK_WRITE = 0xa,
- GEN6_MSG_DP_DWORD_SCATTERED_WRITE = 0xb,
- GEN6_MSG_DP_RT_WRITE = 0xc,
- GEN6_MSG_DP_SVB_WRITE = 0xd,
- GEN6_MSG_DP_RT_UNORM_WRITE = 0xe,
- GEN7_MSG_DP_SAMPLER_UNALIGNED_OWORD_BLOCK_READ = 0x1,
- GEN7_MSG_DP_SAMPLER_MEDIA_BLOCK_READ = 0x4,
- GEN7_MSG_DP_RC_MEDIA_BLOCK_READ = 0x4,
- GEN7_MSG_DP_RC_TYPED_SURFACE_READ = 0x5,
- GEN7_MSG_DP_RC_TYPED_ATOMIC_OP = 0x6,
- GEN7_MSG_DP_RC_MEMORY_FENCE = 0x7,
- GEN7_MSG_DP_RC_MEDIA_BLOCK_WRITE = 0xa,
- GEN7_MSG_DP_RC_RT_WRITE = 0xc,
- GEN7_MSG_DP_RC_TYPED_SURFACE_WRITE = 0xd,
- GEN7_MSG_DP_CC_OWORD_BLOCK_READ = 0x0,
- GEN7_MSG_DP_CC_UNALIGNED_OWORD_BLOCK_READ = 0x1,
- GEN7_MSG_DP_CC_OWORD_DUAL_BLOCK_READ = 0x2,
- GEN7_MSG_DP_CC_DWORD_SCATTERED_READ = 0x3,
- GEN7_MSG_DP_DC0_OWORD_BLOCK_READ = 0x0,
- GEN7_MSG_DP_DC0_UNALIGNED_OWORD_BLOCK_READ = 0x1,
- GEN7_MSG_DP_DC0_OWORD_DUAL_BLOCK_READ = 0x2,
- GEN7_MSG_DP_DC0_DWORD_SCATTERED_READ = 0x3,
- GEN7_MSG_DP_DC0_BYTE_SCATTERED_READ = 0x4,
- GEN7_MSG_DP_DC0_UNTYPED_SURFACE_READ = 0x5,
- GEN7_MSG_DP_DC0_UNTYPED_ATOMIC_OP = 0x6,
- GEN7_MSG_DP_DC0_MEMORY_FENCE = 0x7,
- GEN7_MSG_DP_DC0_OWORD_BLOCK_WRITE = 0x8,
- GEN7_MSG_DP_DC0_OWORD_DUAL_BLOCK_WRITE = 0xa,
- GEN7_MSG_DP_DC0_DWORD_SCATTERED_WRITE = 0xb,
- GEN7_MSG_DP_DC0_BYTE_SCATTERED_WRITE = 0xc,
- GEN7_MSG_DP_DC0_UNTYPED_SURFACE_WRITE = 0xd,
- GEN75_MSG_DP_SAMPLER_READ_SURFACE_INFO = 0x0,
- GEN75_MSG_DP_SAMPLER_UNALIGNED_OWORD_BLOCK_READ = 0x1,
- GEN75_MSG_DP_SAMPLER_MEDIA_BLOCK_READ = 0x4,
- GEN75_MSG_DP_RC_MEDIA_BLOCK_READ = 0x4,
- GEN75_MSG_DP_RC_MEMORY_FENCE = 0x7,
- GEN75_MSG_DP_RC_MEDIA_BLOCK_WRITE = 0xa,
- GEN75_MSG_DP_RC_RT_WRITE = 0xc,
- GEN8_MSG_DP_RC_RT_READ = 0xd,
- GEN75_MSG_DP_CC_OWORD_BLOCK_READ = 0x0,
- GEN75_MSG_DP_CC_UNALIGNED_OWORD_BLOCK_READ = 0x1,
- GEN75_MSG_DP_CC_OWORD_DUAL_BLOCK_READ = 0x2,
- GEN75_MSG_DP_CC_DWORD_SCATTERED_READ = 0x3,
- GEN75_MSG_DP_DC0_OWORD_BLOCK_READ = 0x0,
- GEN75_MSG_DP_DC0_UNALIGNED_OWORD_BLOCK_READ = 0x1,
- GEN75_MSG_DP_DC0_OWORD_DUAL_BLOCK_READ = 0x2,
- GEN75_MSG_DP_DC0_DWORD_SCATTERED_READ = 0x3,
- GEN75_MSG_DP_DC0_BYTE_SCATTERED_READ = 0x4,
- GEN75_MSG_DP_DC0_MEMORY_FENCE = 0x7,
- GEN75_MSG_DP_DC0_OWORD_BLOCK_WRITE = 0x8,
- GEN75_MSG_DP_DC0_OWORD_DUAL_BLOCK_WRITE = 0xa,
- GEN75_MSG_DP_DC0_DWORD_SCATTERED_WRITE = 0xb,
- GEN75_MSG_DP_DC0_BYTE_SCATTERED_WRITE = 0xc,
- GEN75_MSG_DP_DC1_UNTYPED_SURFACE_READ = 0x1,
- GEN75_MSG_DP_DC1_UNTYPED_ATOMIC_OP = 0x2,
- GEN75_MSG_DP_DC1_UNTYPED_ATOMIC_OP_SIMD4X2 = 0x3,
- GEN75_MSG_DP_DC1_MEDIA_BLOCK_READ = 0x4,
- GEN75_MSG_DP_DC1_TYPED_SURFACE_READ = 0x5,
- GEN75_MSG_DP_DC1_TYPED_ATOMIC_OP = 0x6,
- GEN75_MSG_DP_DC1_TYPED_ATOMIC_OP_SIMD4X2 = 0x7,
- GEN75_MSG_DP_DC1_UNTYPED_SURFACE_WRITE = 0x9,
- GEN75_MSG_DP_DC1_MEDIA_BLOCK_WRITE = 0xa,
- GEN75_MSG_DP_DC1_ATOMIC_COUNTER_OP = 0xb,
- GEN75_MSG_DP_DC1_ATOMIC_COUNTER_OP_SIMD4X2 = 0xc,
- GEN75_MSG_DP_DC1_TYPED_SURFACE_WRITE = 0xd,
-};
-
-enum gen_eu_dp_aop {
- GEN7_MSG_DP_AOP_CMPWR8B = 0x0,
- GEN7_MSG_DP_AOP_AND = 0x1,
- GEN7_MSG_DP_AOP_OR = 0x2,
- GEN7_MSG_DP_AOP_XOR = 0x3,
- GEN7_MSG_DP_AOP_MOV = 0x4,
- GEN7_MSG_DP_AOP_INC = 0x5,
- GEN7_MSG_DP_AOP_DEC = 0x6,
- GEN7_MSG_DP_AOP_ADD = 0x7,
- GEN7_MSG_DP_AOP_SUB = 0x8,
- GEN7_MSG_DP_AOP_REVSUB = 0x9,
- GEN7_MSG_DP_AOP_IMAX = 0xa,
- GEN7_MSG_DP_AOP_IMIN = 0xb,
- GEN7_MSG_DP_AOP_UMAX = 0xc,
- GEN7_MSG_DP_AOP_UMIN = 0xd,
- GEN7_MSG_DP_AOP_CMPWR = 0xe,
- GEN7_MSG_DP_AOP_PREDEC = 0xf,
-};
-
-#define GEN6_MSG_EOT (0x1 << 31)
-#define GEN6_MSG_MLEN__MASK 0x1e000000
-#define GEN6_MSG_MLEN__SHIFT 25
-#define GEN6_MSG_RLEN__MASK 0x01f00000
-#define GEN6_MSG_RLEN__SHIFT 20
-#define GEN6_MSG_HEADER_PRESENT (0x1 << 19)
-#define GEN6_MSG_FUNCTION_CONTROL__MASK 0x0007ffff
-#define GEN6_MSG_FUNCTION_CONTROL__SHIFT 0
-#define GEN6_MSG_URB_COMPLETE (0x1 << 15)
-#define GEN6_MSG_URB_USED (0x1 << 14)
-#define GEN6_MSG_URB_ALLOCATE (0x1 << 13)
-#define GEN6_MSG_URB_INTERLEAVED (0x1 << 10)
-#define GEN6_MSG_URB_OFFSET__MASK 0x000003f0
-#define GEN6_MSG_URB_OFFSET__SHIFT 4
-#define GEN6_MSG_URB_OP__MASK 0x0000000f
-#define GEN6_MSG_URB_OP__SHIFT 0
-#define GEN7_MSG_URB_PER_SLOT_OFFSET (0x1 << 16)
-#define GEN7_MSG_URB_COMPLETE (0x1 << 15)
-#define GEN7_MSG_URB_INTERLEAVED (0x1 << 14)
-#define GEN7_MSG_URB_GLOBAL_OFFSET__MASK 0x00003ff8
-#define GEN7_MSG_URB_GLOBAL_OFFSET__SHIFT 3
-#define GEN7_MSG_URB_OP__MASK 0x00000007
-#define GEN7_MSG_URB_OP__SHIFT 0
-#define GEN8_MSG_URB_PER_SLOT_OFFSET (0x1 << 17)
-#define GEN8_MSG_URB_INTERLEAVED (0x1 << 15)
-#define GEN8_MSG_URB_GLOBAL_OFFSET__MASK 0x00007ff0
-#define GEN8_MSG_URB_GLOBAL_OFFSET__SHIFT 4
-#define GEN8_MSG_URB_OP__MASK 0x0000000f
-#define GEN8_MSG_URB_OP__SHIFT 0
-#define GEN7_MSG_PI_SIMD__MASK 0x00010000
-#define GEN7_MSG_PI_SIMD__SHIFT 16
-#define GEN7_MSG_PI_LINEAR_INTERP (0x1 << 14)
-#define GEN7_MSG_PI_OP__MASK 0x00003000
-#define GEN7_MSG_PI_OP__SHIFT 12
-#define GEN7_MSG_PI_SLOTGRP_HI (0x1 << 11)
-#define GEN7_MSG_PI_OFFSET_Y__MASK 0x000000f0
-#define GEN7_MSG_PI_OFFSET_Y__SHIFT 4
-#define GEN7_MSG_PI_OFFSET_X__MASK 0x0000000f
-#define GEN7_MSG_PI_OFFSET_X__SHIFT 0
-#define GEN7_MSG_PI_SAMPLE_INDEX__MASK 0x000000f0
-#define GEN7_MSG_PI_SAMPLE_INDEX__SHIFT 4
-#define GEN6_MSG_SAMPLER_SIMD__MASK 0x00030000
-#define GEN6_MSG_SAMPLER_SIMD__SHIFT 16
-#define GEN6_MSG_SAMPLER_OP__MASK 0x0000f000
-#define GEN6_MSG_SAMPLER_OP__SHIFT 12
-#define GEN7_MSG_SAMPLER_SIMD__MASK 0x00060000
-#define GEN7_MSG_SAMPLER_SIMD__SHIFT 17
-#define GEN7_MSG_SAMPLER_OP__MASK 0x0001f000
-#define GEN7_MSG_SAMPLER_OP__SHIFT 12
-#define GEN6_MSG_SAMPLER_INDEX__MASK 0x00000f00
-#define GEN6_MSG_SAMPLER_INDEX__SHIFT 8
-#define GEN6_MSG_SAMPLER_SURFACE__MASK 0x000000ff
-#define GEN6_MSG_SAMPLER_SURFACE__SHIFT 0
-#define GEN6_MSG_DP_SEND_WRITE_COMMIT (0x1 << 17)
-#define GEN6_MSG_DP_OP__MASK 0x0001e000
-#define GEN6_MSG_DP_OP__SHIFT 13
-#define GEN6_MSG_DP_CTRL__MASK 0x00001f00
-#define GEN6_MSG_DP_CTRL__SHIFT 8
-#define GEN7_MSG_DP_CATEGORY (0x1 << 18)
-#define GEN7_MSG_DP_OP__MASK 0x0003c000
-#define GEN7_MSG_DP_OP__SHIFT 14
-#define GEN7_MSG_DP_CTRL__MASK 0x00003f00
-#define GEN7_MSG_DP_CTRL__SHIFT 8
-#define GEN7_MSG_DP_OWORD_BLOCK_READ_INVALIDATE (0x1 << 13)
-#define GEN6_MSG_DP_OWORD_BLOCK_SIZE__MASK 0x00000700
-#define GEN6_MSG_DP_OWORD_BLOCK_SIZE__SHIFT 8
-#define GEN6_MSG_DP_OWORD_BLOCK_SIZE_1_LO (0x0 << 8)
-#define GEN6_MSG_DP_OWORD_BLOCK_SIZE_1_HI (0x1 << 8)
-#define GEN6_MSG_DP_OWORD_BLOCK_SIZE_2 (0x2 << 8)
-#define GEN6_MSG_DP_OWORD_BLOCK_SIZE_4 (0x3 << 8)
-#define GEN6_MSG_DP_OWORD_BLOCK_SIZE_8 (0x4 << 8)
-#define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE__MASK 0x00000700
-#define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE__SHIFT 8
-#define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE_1_LO (0x0 << 8)
-#define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE_1_HI (0x1 << 8)
-#define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE_2 (0x2 << 8)
-#define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE_4 (0x3 << 8)
-#define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE_8 (0x4 << 8)
-#define GEN7_MSG_DP_OWORD_DUAL_BLOCK_READ_INVALIDATE (0x1 << 13)
-#define GEN6_MSG_DP_OWORD_DUAL_BLOCK_SIZE__MASK 0x00000300
-#define GEN6_MSG_DP_OWORD_DUAL_BLOCK_SIZE__SHIFT 8
-#define GEN6_MSG_DP_OWORD_DUAL_BLOCK_SIZE_1 (0x0 << 8)
-#define GEN6_MSG_DP_OWORD_DUAL_BLOCK_SIZE_4 (0x2 << 8)
-#define GEN7_MSG_DP_DWORD_SCATTERED_READ_INVALIDATE (0x1 << 13)
-#define GEN6_MSG_DP_DWORD_SCATTERED_BLOCK_SIZE__MASK 0x00000300
-#define GEN6_MSG_DP_DWORD_SCATTERED_BLOCK_SIZE__SHIFT 8
-#define GEN6_MSG_DP_DWORD_SCATTERED_BLOCK_SIZE_8 (0x2 << 8)
-#define GEN6_MSG_DP_DWORD_SCATTERED_BLOCK_SIZE_16 (0x3 << 8)
-#define GEN6_MSG_DP_BYTE_SCATTERED_DATA_SIZE__MASK 0x00000600
-#define GEN6_MSG_DP_BYTE_SCATTERED_DATA_SIZE__SHIFT 9
-#define GEN6_MSG_DP_BYTE_SCATTERED_DATA_SIZE_1 (0x0 << 9)
-#define GEN6_MSG_DP_BYTE_SCATTERED_DATA_SIZE_2 (0x1 << 9)
-#define GEN6_MSG_DP_BYTE_SCATTERED_DATA_SIZE_4 (0x2 << 9)
-#define GEN6_MSG_DP_BYTE_SCATTERED_MODE__MASK 0x00000100
-#define GEN6_MSG_DP_BYTE_SCATTERED_MODE__SHIFT 8
-#define GEN6_MSG_DP_BYTE_SCATTERED_MODE_SIMD8 (0x0 << 8)
-#define GEN6_MSG_DP_BYTE_SCATTERED_MODE_SIMD16 (0x1 << 8)
-#define GEN6_MSG_DP_RT_LAST (0x1 << 12)
-#define GEN6_MSG_DP_RT_SLOTGRP_HI (0x1 << 11)
-#define GEN6_MSG_DP_RT_MODE__MASK 0x00000700
-#define GEN6_MSG_DP_RT_MODE__SHIFT 8
-#define GEN6_MSG_DP_RT_MODE_SIMD16 (0x0 << 8)
-#define GEN6_MSG_DP_RT_MODE_SIMD16_REPDATA (0x1 << 8)
-#define GEN6_MSG_DP_RT_MODE_SIMD8_DUALSRC_LO (0x2 << 8)
-#define GEN6_MSG_DP_RT_MODE_SIMD8_DUALSRC_HI (0x3 << 8)
-#define GEN6_MSG_DP_RT_MODE_SIMD8_LO (0x4 << 8)
-#define GEN6_MSG_DP_RT_MODE_SIMD8_IMAGE_WR (0x5 << 8)
-#define GEN7_MSG_DP_TYPED_SLOTGRP_HI (0x1 << 13)
-#define GEN7_MSG_DP_TYPED_MASK__MASK 0x00000f00
-#define GEN7_MSG_DP_TYPED_MASK__SHIFT 8
-#define GEN7_MSG_DP_UNTYPED_MODE__MASK 0x00003000
-#define GEN7_MSG_DP_UNTYPED_MODE__SHIFT 12
-#define GEN7_MSG_DP_UNTYPED_MODE_SIMD4X2 (0x0 << 12)
-#define GEN7_MSG_DP_UNTYPED_MODE_SIMD16 (0x1 << 12)
-#define GEN7_MSG_DP_UNTYPED_MODE_SIMD8 (0x2 << 12)
-#define GEN7_MSG_DP_UNTYPED_MASK__MASK 0x00000f00
-#define GEN7_MSG_DP_UNTYPED_MASK__SHIFT 8
-#define GEN7_MSG_DP_ATOMIC_RETURN_DATA_ENABLE (0x1 << 13)
-#define GEN7_MSG_DP_ATOMIC_TYPED_SLOTGRP_HI (0x1 << 12)
-#define GEN7_MSG_DP_ATOMIC_UNTYPED_MODE__MASK 0x00001000
-#define GEN7_MSG_DP_ATOMIC_UNTYPED_MODE__SHIFT 12
-#define GEN7_MSG_DP_ATOMIC_UNTYPED_MODE_SIMD16 (0x0 << 12)
-#define GEN7_MSG_DP_ATOMIC_UNTYPED_MODE_SIMD8 (0x1 << 12)
-#define GEN7_MSG_DP_ATOMIC_OP__MASK 0x00000f00
-#define GEN7_MSG_DP_ATOMIC_OP__SHIFT 8
-#define GEN6_MSG_DP_SURFACE__MASK 0x000000ff
-#define GEN6_MSG_DP_SURFACE__SHIFT 0
-#define GEN6_MSG_TS_RESOURCE_SELECT__MASK 0x00000010
-#define GEN6_MSG_TS_RESOURCE_SELECT__SHIFT 4
-#define GEN6_MSG_TS_RESOURCE_SELECT_CHILD (0x0 << 4)
-#define GEN6_MSG_TS_RESOURCE_SELECT_ROOT (0x1 << 4)
-#define GEN6_MSG_TS_RESOURCE_SELECT_DEREF (0x0 << 4)
-#define GEN6_MSG_TS_RESOURCE_SELECT_NO_DEREF (0x1 << 4)
-#define GEN6_MSG_TS_REQUESTER_TYPE__MASK 0x00000002
-#define GEN6_MSG_TS_REQUESTER_TYPE__SHIFT 1
-#define GEN6_MSG_TS_REQUESTER_TYPE_ROOT (0x0 << 1)
-#define GEN6_MSG_TS_REQUESTER_TYPE_CHILD (0x1 << 1)
-#define GEN6_MSG_TS_OPCODE__MASK 0x00000001
-#define GEN6_MSG_TS_OPCODE__SHIFT 0
-#define GEN6_MSG_TS_OPCODE_DEREF 0x0
-#define GEN6_MSG_TS_OPCODE_SPAWN 0x1
-
-#endif /* GEN_EU_MESSAGE_XML */
+++ /dev/null
-#ifndef GEN_MI_XML
-#define GEN_MI_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-https://github.com/olvaffe/envytools/
-git clone https://github.com/olvaffe/envytools.git
-
-Copyright (C) 2014-2015 by the following authors:
-- Chia-I Wu <olvaffe@gmail.com> (olv)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-enum gen_mi_alu_opcode {
- GEN75_MI_ALU_NOOP = 0x0,
- GEN75_MI_ALU_LOAD = 0x80,
- GEN75_MI_ALU_LOADINV = 0x480,
- GEN75_MI_ALU_LOAD0 = 0x81,
- GEN75_MI_ALU_LOAD1 = 0x481,
- GEN75_MI_ALU_ADD = 0x100,
- GEN75_MI_ALU_SUB = 0x101,
- GEN75_MI_ALU_AND = 0x102,
- GEN75_MI_ALU_OR = 0x103,
- GEN75_MI_ALU_XOR = 0x104,
- GEN75_MI_ALU_STORE = 0x180,
- GEN75_MI_ALU_STOREINV = 0x580,
-};
-
-enum gen_mi_alu_operand {
- GEN75_MI_ALU_R0 = 0x0,
- GEN75_MI_ALU_R1 = 0x1,
- GEN75_MI_ALU_R2 = 0x2,
- GEN75_MI_ALU_R3 = 0x3,
- GEN75_MI_ALU_R4 = 0x4,
- GEN75_MI_ALU_R5 = 0x5,
- GEN75_MI_ALU_R6 = 0x6,
- GEN75_MI_ALU_R7 = 0x7,
- GEN75_MI_ALU_R8 = 0x8,
- GEN75_MI_ALU_R9 = 0x9,
- GEN75_MI_ALU_R10 = 0xa,
- GEN75_MI_ALU_R11 = 0xb,
- GEN75_MI_ALU_R12 = 0xc,
- GEN75_MI_ALU_R13 = 0xd,
- GEN75_MI_ALU_R14 = 0xe,
- GEN75_MI_ALU_R15 = 0xf,
- GEN75_MI_ALU_SRCA = 0x20,
- GEN75_MI_ALU_SRCB = 0x21,
- GEN75_MI_ALU_ACCU = 0x31,
- GEN75_MI_ALU_ZF = 0x32,
- GEN75_MI_ALU_CF = 0x33,
-};
-
-#define GEN6_MI_TYPE__MASK 0xe0000000
-#define GEN6_MI_TYPE__SHIFT 29
-#define GEN6_MI_TYPE_MI (0x0 << 29)
-#define GEN6_MI_OPCODE__MASK 0x1f800000
-#define GEN6_MI_OPCODE__SHIFT 23
-#define GEN6_MI_OPCODE_MI_NOOP (0x0 << 23)
-#define GEN75_MI_OPCODE_MI_SET_PREDICATE (0x1 << 23)
-#define GEN75_MI_OPCODE_MI_RS_CONTROL (0x6 << 23)
-#define GEN75_MI_OPCODE_MI_URB_ATOMIC_ALLOC (0x9 << 23)
-#define GEN6_MI_OPCODE_MI_BATCH_BUFFER_END (0xa << 23)
-#define GEN7_MI_OPCODE_MI_PREDICATE (0xc << 23)
-#define GEN7_MI_OPCODE_MI_URB_CLEAR (0x19 << 23)
-#define GEN75_MI_OPCODE_MI_MATH (0x1a << 23)
-#define GEN8_MI_OPCODE_MI_SEMAPHORE_SIGNAL (0x1b << 23)
-#define GEN8_MI_OPCODE_MI_SEMAPHORE_WAIT (0x1c << 23)
-#define GEN6_MI_OPCODE_MI_STORE_DATA_IMM (0x20 << 23)
-#define GEN6_MI_OPCODE_MI_LOAD_REGISTER_IMM (0x22 << 23)
-#define GEN6_MI_OPCODE_MI_STORE_REGISTER_MEM (0x24 << 23)
-#define GEN6_MI_OPCODE_MI_FLUSH_DW (0x26 << 23)
-#define GEN6_MI_OPCODE_MI_REPORT_PERF_COUNT (0x28 << 23)
-#define GEN7_MI_OPCODE_MI_LOAD_REGISTER_MEM (0x29 << 23)
-#define GEN75_MI_OPCODE_MI_LOAD_REGISTER_REG (0x2a << 23)
-#define GEN75_MI_OPCODE_MI_RS_STORE_DATA_IMM (0x2b << 23)
-#define GEN75_MI_OPCODE_MI_LOAD_URB_MEM (0x2c << 23)
-#define GEN75_MI_OPCODE_MI_STORE_URB_MEM (0x2d << 23)
-#define GEN8_MI_OPCODE_MI_COPY_MEM_MEM (0x2e << 23)
-#define GEN8_MI_OPCODE_MI_ATOMIC (0x2f << 23)
-#define GEN6_MI_OPCODE_MI_BATCH_BUFFER_START (0x31 << 23)
-#define GEN6_MI_LENGTH__MASK 0x0000003f
-#define GEN6_MI_LENGTH__SHIFT 0
-#define GEN6_MI_NOOP__SIZE 1
-#define GEN6_MI_NOOP_DW0_WRITE_NOPID (0x1 << 22)
-#define GEN6_MI_NOOP_DW0_VALUE__MASK 0x003fffff
-#define GEN6_MI_NOOP_DW0_VALUE__SHIFT 0
-
-#define GEN75_MI_SET_PREDICATE__SIZE 1
-#define GEN75_MI_SET_PREDICATE_DW0_PREDICATE__MASK 0x00000003
-#define GEN75_MI_SET_PREDICATE_DW0_PREDICATE__SHIFT 0
-#define GEN75_MI_SET_PREDICATE_DW0_PREDICATE_ALWAYS 0x0
-#define GEN75_MI_SET_PREDICATE_DW0_PREDICATE_ON_CLEAR 0x1
-#define GEN75_MI_SET_PREDICATE_DW0_PREDICATE_ON_SET 0x2
-#define GEN75_MI_SET_PREDICATE_DW0_PREDICATE_DISABLE 0x3
-
-#define GEN75_MI_RS_CONTROL__SIZE 1
-#define GEN75_MI_RS_CONTROL_DW0_ENABLE (0x1 << 0)
-
-#define GEN75_MI_URB_ATOMIC_ALLOC__SIZE 1
-#define GEN75_MI_URB_ATOMIC_ALLOC_DW0_OFFSET__MASK 0x000ff000
-#define GEN75_MI_URB_ATOMIC_ALLOC_DW0_OFFSET__SHIFT 12
-#define GEN75_MI_URB_ATOMIC_ALLOC_DW0_SIZE__MASK 0x000001ff
-#define GEN75_MI_URB_ATOMIC_ALLOC_DW0_SIZE__SHIFT 0
-
-#define GEN6_MI_BATCH_BUFFER_END__SIZE 1
-
-#define GEN7_MI_PREDICATE__SIZE 1
-#define GEN7_MI_PREDICATE_DW0_LOADOP__MASK 0x000000c0
-#define GEN7_MI_PREDICATE_DW0_LOADOP__SHIFT 6
-#define GEN7_MI_PREDICATE_DW0_LOADOP_KEEP (0x0 << 6)
-#define GEN7_MI_PREDICATE_DW0_LOADOP_LOAD (0x2 << 6)
-#define GEN7_MI_PREDICATE_DW0_LOADOP_LOADINV (0x3 << 6)
-#define GEN7_MI_PREDICATE_DW0_COMBINEOP__MASK 0x00000018
-#define GEN7_MI_PREDICATE_DW0_COMBINEOP__SHIFT 3
-#define GEN7_MI_PREDICATE_DW0_COMBINEOP_SET (0x0 << 3)
-#define GEN7_MI_PREDICATE_DW0_COMBINEOP_AND (0x1 << 3)
-#define GEN7_MI_PREDICATE_DW0_COMBINEOP_OR (0x2 << 3)
-#define GEN7_MI_PREDICATE_DW0_COMBINEOP_XOR (0x3 << 3)
-#define GEN7_MI_PREDICATE_DW0_COMPAREOP__MASK 0x00000003
-#define GEN7_MI_PREDICATE_DW0_COMPAREOP__SHIFT 0
-#define GEN7_MI_PREDICATE_DW0_COMPAREOP_TRUE 0x0
-#define GEN7_MI_PREDICATE_DW0_COMPAREOP_FALSE 0x1
-#define GEN7_MI_PREDICATE_DW0_COMPAREOP_SRCS_EQUAL 0x2
-#define GEN7_MI_PREDICATE_DW0_COMPAREOP_DELTAS_EQUAL 0x3
-
-#define GEN7_MI_URB_CLEAR__SIZE 2
-
-#define GEN7_MI_URB_CLEAR_DW1_LENGTH__MASK 0x3fff0000
-#define GEN7_MI_URB_CLEAR_DW1_LENGTH__SHIFT 16
-#define GEN7_MI_URB_CLEAR_DW1_OFFSET__MASK 0x00007fff
-#define GEN7_MI_URB_CLEAR_DW1_OFFSET__SHIFT 0
-
-#define GEN75_MI_MATH__SIZE 65
-
-#define GEN75_MI_MATH_DW_OP__MASK 0xfff00000
-#define GEN75_MI_MATH_DW_OP__SHIFT 20
-#define GEN75_MI_MATH_DW_SRC1__MASK 0x000ffc00
-#define GEN75_MI_MATH_DW_SRC1__SHIFT 10
-#define GEN75_MI_MATH_DW_SRC2__MASK 0x000007ff
-#define GEN75_MI_MATH_DW_SRC2__SHIFT 0
-
-#define GEN8_MI_SEMAPHORE_SIGNAL__SIZE 2
-#define GEN8_MI_SEMAPHORE_SIGNAL_DW0_POST_SYNC_OP (0x1 << 21)
-#define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE__MASK 0x00038000
-#define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE__SHIFT 15
-#define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE_RCS (0x0 << 15)
-#define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE_VCS0 (0x1 << 15)
-#define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE_BCS (0x2 << 15)
-#define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE_VECS (0x3 << 15)
-#define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE_VCS1 (0x4 << 15)
-
-
-#define GEN8_MI_SEMAPHORE_WAIT__SIZE 4
-#define GEN8_MI_SEMAPHORE_WAIT_DW0_USE_GGTT (0x1 << 22)
-#define GEN8_MI_SEMAPHORE_WAIT_DW0_WAIT_MODE__MASK 0x00008000
-#define GEN8_MI_SEMAPHORE_WAIT_DW0_WAIT_MODE__SHIFT 15
-#define GEN8_MI_SEMAPHORE_WAIT_DW0_WAIT_MODE_SIGNAL (0x0 << 15)
-#define GEN8_MI_SEMAPHORE_WAIT_DW0_WAIT_MODE_POLL (0x1 << 15)
-#define GEN8_MI_SEMAPHORE_WAIT_DW0_OP__MASK 0x00007000
-#define GEN8_MI_SEMAPHORE_WAIT_DW0_OP__SHIFT 12
-#define GEN8_MI_SEMAPHORE_WAIT_DW0_OP_SAD_GREATER_THAN_SDD (0x0 << 12)
-#define GEN8_MI_SEMAPHORE_WAIT_DW0_OP_SAD_GREATER_THAN_OR_EQUAL_SDD (0x1 << 12)
-#define GEN8_MI_SEMAPHORE_WAIT_DW0_OP_SAD_LESS_THAN_SDD (0x2 << 12)
-#define GEN8_MI_SEMAPHORE_WAIT_DW0_OP_SAD_LESS_THAN_OR_EQUAL_SDD (0x3 << 12)
-#define GEN8_MI_SEMAPHORE_WAIT_DW0_OP_SAD_EQUAL_SDD (0x4 << 12)
-#define GEN8_MI_SEMAPHORE_WAIT_DW0_OP_SAD_NO_EQUAL_SDD (0x5 << 12)
-
-
-#define GEN8_MI_SEMAPHORE_WAIT_DW2_ADDR_ADDR__MASK 0xfffffffc
-#define GEN8_MI_SEMAPHORE_WAIT_DW2_ADDR_ADDR__SHIFT 2
-#define GEN8_MI_SEMAPHORE_WAIT_DW2_ADDR_ADDR__SHR 2
-
-
-#define GEN6_MI_STORE_DATA_IMM__SIZE 6
-#define GEN6_MI_STORE_DATA_IMM_DW0_USE_GGTT (0x1 << 22)
-#define GEN8_MI_STORE_DATA_IMM_DW0_STORE_QWORD (0x1 << 21)
-
-
-#define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__MASK 0xfffffffc
-#define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__SHIFT 2
-#define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__SHR 2
-
-
-
-
-#define GEN6_MI_LOAD_REGISTER_IMM__SIZE 3
-#define GEN6_MI_LOAD_REGISTER_IMM_DW0_WRITE_DISABLES__MASK 0x00000f00
-#define GEN6_MI_LOAD_REGISTER_IMM_DW0_WRITE_DISABLES__SHIFT 8
-
-#define GEN6_MI_LOAD_REGISTER_IMM_DW1_REG__MASK 0x007ffffc
-#define GEN6_MI_LOAD_REGISTER_IMM_DW1_REG__SHIFT 2
-#define GEN6_MI_LOAD_REGISTER_IMM_DW1_REG__SHR 2
-
-
-#define GEN6_MI_STORE_REGISTER_MEM__SIZE 4
-#define GEN6_MI_STORE_REGISTER_MEM_DW0_USE_GGTT (0x1 << 22)
-#define GEN75_MI_STORE_REGISTER_MEM_DW0_PREDICATE_ENABLE (0x1 << 21)
-
-#define GEN6_MI_STORE_REGISTER_MEM_DW1_REG__MASK 0x007ffffc
-#define GEN6_MI_STORE_REGISTER_MEM_DW1_REG__SHIFT 2
-#define GEN6_MI_STORE_REGISTER_MEM_DW1_REG__SHR 2
-
-#define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__MASK 0xfffffffc
-#define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__SHIFT 2
-#define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__SHR 2
-
-
-#define GEN6_MI_FLUSH_DW__SIZE 5
-#define GEN6_MI_FLUSH_DW_DW0_WRITE__MASK 0x0000c000
-#define GEN6_MI_FLUSH_DW_DW0_WRITE__SHIFT 14
-#define GEN6_MI_FLUSH_DW_DW0_WRITE_NONE (0x0 << 14)
-#define GEN6_MI_FLUSH_DW_DW0_WRITE_IMM (0x1 << 14)
-#define GEN6_MI_FLUSH_DW_DW0_WRITE_TIMESTAMP (0x3 << 14)
-
-#define GEN6_MI_FLUSH_DW_DW1_USE_GGTT (0x1 << 2)
-#define GEN6_MI_FLUSH_DW_DW1_ADDR__MASK 0xfffffff8
-#define GEN6_MI_FLUSH_DW_DW1_ADDR__SHIFT 3
-#define GEN6_MI_FLUSH_DW_DW1_ADDR__SHR 3
-
-
-
-
-#define GEN6_MI_REPORT_PERF_COUNT__SIZE 3
-
-#define GEN6_MI_REPORT_PERF_COUNT_DW1_CORE_MODE_ENABLE (0x1 << 4)
-#define GEN6_MI_REPORT_PERF_COUNT_DW1_USE_GGTT (0x1 << 0)
-#define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__MASK 0xffffffc0
-#define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__SHIFT 6
-#define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__SHR 6
-
-
-#define GEN7_MI_LOAD_REGISTER_MEM__SIZE 4
-#define GEN7_MI_LOAD_REGISTER_MEM_DW0_USE_GGTT (0x1 << 22)
-#define GEN7_MI_LOAD_REGISTER_MEM_DW0_ASYNC_MODE_ENABLE (0x1 << 21)
-
-#define GEN7_MI_LOAD_REGISTER_MEM_DW1_REG__MASK 0x007ffffc
-#define GEN7_MI_LOAD_REGISTER_MEM_DW1_REG__SHIFT 2
-#define GEN7_MI_LOAD_REGISTER_MEM_DW1_REG__SHR 2
-
-#define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__MASK 0xfffffffc
-#define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__SHIFT 2
-#define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__SHR 2
-
-
-#define GEN75_MI_LOAD_REGISTER_REG__SIZE 3
-
-#define GEN75_MI_LOAD_REGISTER_REG_DW1_SRC_REG__MASK 0x007ffffc
-#define GEN75_MI_LOAD_REGISTER_REG_DW1_SRC_REG__SHIFT 2
-#define GEN75_MI_LOAD_REGISTER_REG_DW1_SRC_REG__SHR 2
-
-#define GEN75_MI_LOAD_REGISTER_REG_DW2_DST_REG__MASK 0x007ffffc
-#define GEN75_MI_LOAD_REGISTER_REG_DW2_DST_REG__SHIFT 2
-#define GEN75_MI_LOAD_REGISTER_REG_DW2_DST_REG__SHR 2
-
-#define GEN75_MI_RS_STORE_DATA_IMM__SIZE 6
-#define GEN75_MI_RS_STORE_DATA_IMM_DW0_USE_GGTT (0x1 << 22)
-
-
-#define GEN75_MI_RS_STORE_DATA_IMM_DW2_ADDR__MASK 0xfffffffc
-#define GEN75_MI_RS_STORE_DATA_IMM_DW2_ADDR__SHIFT 2
-#define GEN75_MI_RS_STORE_DATA_IMM_DW2_ADDR__SHR 2
-
-
-
-
-#define GEN75_MI_LOAD_URB_MEM__SIZE 4
-
-#define GEN75_MI_LOAD_URB_MEM_DW1_ADDR__MASK 0x00007ffc
-#define GEN75_MI_LOAD_URB_MEM_DW1_ADDR__SHIFT 2
-#define GEN75_MI_LOAD_URB_MEM_DW1_ADDR__SHR 2
-
-#define GEN75_MI_LOAD_URB_MEM_DW2_ADDR__MASK 0xffffffc0
-#define GEN75_MI_LOAD_URB_MEM_DW2_ADDR__SHIFT 6
-#define GEN75_MI_LOAD_URB_MEM_DW2_ADDR__SHR 6
-
-
-#define GEN75_MI_STORE_URB_MEM__SIZE 4
-
-#define GEN75_MI_STORE_URB_MEM_DW1_ADDR__MASK 0x00007ffc
-#define GEN75_MI_STORE_URB_MEM_DW1_ADDR__SHIFT 2
-#define GEN75_MI_STORE_URB_MEM_DW1_ADDR__SHR 2
-
-#define GEN75_MI_STORE_URB_MEM_DW2_ADDR__MASK 0xffffffc0
-#define GEN75_MI_STORE_URB_MEM_DW2_ADDR__SHIFT 6
-#define GEN75_MI_STORE_URB_MEM_DW2_ADDR__SHR 6
-
-
-#define GEN8_MI_COPY_MEM_MEM__SIZE 5
-#define GEN8_MI_COPY_MEM_MEM_DW0_USE_GGTT_SRC (0x1 << 22)
-#define GEN8_MI_COPY_MEM_MEM_DW0_USE_GGTT_DST (0x1 << 21)
-
-#define GEN8_MI_COPY_MEM_MEM_DW1_DST_ADDR__MASK 0xfffffffc
-#define GEN8_MI_COPY_MEM_MEM_DW1_DST_ADDR__SHIFT 2
-#define GEN8_MI_COPY_MEM_MEM_DW1_DST_ADDR__SHR 2
-
-
-#define GEN8_MI_COPY_MEM_MEM_DW3_SRC_ADDR__MASK 0xfffffffc
-#define GEN8_MI_COPY_MEM_MEM_DW3_SRC_ADDR__SHIFT 2
-#define GEN8_MI_COPY_MEM_MEM_DW3_SRC_ADDR__SHR 2
-
-
-#define GEN8_MI_ATOMIC__SIZE 11
-#define GEN8_MI_ATOMIC_DW0_USE_GGTT (0x1 << 22)
-#define GEN8_MI_ATOMIC_DW0_POST_SYNC_OP (0x1 << 21)
-#define GEN8_MI_ATOMIC_DW0_SIZE__MASK 0x00180000
-#define GEN8_MI_ATOMIC_DW0_SIZE__SHIFT 19
-#define GEN8_MI_ATOMIC_DW0_SIZE_DWORD (0x0 << 19)
-#define GEN8_MI_ATOMIC_DW0_SIZE_QWORD (0x1 << 19)
-#define GEN8_MI_ATOMIC_DW0_SIZE_OWORD (0x2 << 19)
-#define GEN8_MI_ATOMIC_DW0_INLINE_DATA (0x1 << 18)
-#define GEN8_MI_ATOMIC_DW0_CS_STALL (0x1 << 17)
-#define GEN8_MI_ATOMIC_DW0_RETURN_DATA_CONTROL (0x1 << 16)
-#define GEN8_MI_ATOMIC_DW0_OP__MASK 0x0000ff00
-#define GEN8_MI_ATOMIC_DW0_OP__SHIFT 8
-
-#define GEN8_MI_ATOMIC_DW1_ADDR__MASK 0xfffffffc
-#define GEN8_MI_ATOMIC_DW1_ADDR__SHIFT 2
-#define GEN8_MI_ATOMIC_DW1_ADDR__SHR 2
-
-
-
-#define GEN6_MI_BATCH_BUFFER_START__SIZE 3
-#define GEN75_MI_BATCH_BUFFER_START_DW0_SECOND_LEVEL (0x1 << 22)
-#define GEN75_MI_BATCH_BUFFER_START_DW0_ADD_OFFSET_ENABLE (0x1 << 16)
-#define GEN75_MI_BATCH_BUFFER_START_DW0_PREDICATION_ENABLE (0x1 << 15)
-#define GEN75_MI_BATCH_BUFFER_START_DW0_NON_PRIVILEGED (0x1 << 13)
-#define GEN6_MI_BATCH_BUFFER_START_DW0_CLEAR_COMMAND_BUFFER (0x1 << 11)
-#define GEN75_MI_BATCH_BUFFER_START_DW0_RS_ENABLE (0x1 << 10)
-#define GEN6_MI_BATCH_BUFFER_START_DW0_USE_PPGTT (0x1 << 8)
-
-#define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__MASK 0xfffffffc
-#define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__SHIFT 2
-#define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__SHR 2
-
-
-
-#endif /* GEN_MI_XML */
+++ /dev/null
-#ifndef GEN_REGS_XML
-#define GEN_REGS_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-https://github.com/olvaffe/envytools/
-git clone https://github.com/olvaffe/envytools.git
-
-Copyright (C) 2014-2015 by the following authors:
-- Chia-I Wu <olvaffe@gmail.com> (olv)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-#define GEN6_REG_MASK__MASK 0xffff0000
-#define GEN6_REG_MASK__SHIFT 16
-#define GEN6_REG__SIZE 0x400000
-#define GEN6_REG_NOPID 0x2094
-
-
-#define GEN6_REG_SO_PRIM_STORAGE_NEEDED 0x2280
-
-#define GEN6_REG_SO_NUM_PRIMS_WRITTEN 0x2288
-
-
-#define GEN7_REG_TS_GPGPU_THREADS_DISPATCHED 0x2290
-
-#define GEN7_REG_HS_INVOCATION_COUNT 0x2300
-
-#define GEN7_REG_DS_INVOCATION_COUNT 0x2308
-
-#define GEN6_REG_IA_VERTICES_COUNT 0x2310
-
-#define GEN6_REG_IA_PRIMITIVES_COUNT 0x2318
-
-#define GEN6_REG_VS_INVOCATION_COUNT 0x2320
-
-#define GEN6_REG_GS_INVOCATION_COUNT 0x2328
-
-#define GEN6_REG_GS_PRIMITIVES_COUNT 0x2330
-
-#define GEN6_REG_CL_INVOCATION_COUNT 0x2338
-
-#define GEN6_REG_CL_PRIMITIVES_COUNT 0x2340
-
-#define GEN6_REG_PS_INVOCATION_COUNT 0x2348
-
-#define GEN6_REG_PS_DEPTH_COUNT 0x2350
-
-#define GEN6_REG_TIMESTAMP 0x2358
-
-#define GEN6_REG_OACONTROL 0x2360
-#define GEN6_REG_OACONTROL_COUNTER_SELECT__MASK 0x0000001c
-#define GEN6_REG_OACONTROL_COUNTER_SELECT__SHIFT 2
-#define GEN6_REG_OACONTROL_PERFORMANCE_COUNTER_ENABLE (0x1 << 0)
-
-
-#define GEN7_REG_MI_PREDICATE_SRC0 0x2400
-
-#define GEN7_REG_MI_PREDICATE_SRC1 0x2408
-
-#define GEN7_REG_MI_PREDICATE_DATA 0x2410
-
-#define GEN7_REG_MI_PREDICATE_RESULT 0x2418
-
-#define GEN75_REG_MI_PREDICATE_RESULT_1 0x241c
-
-#define GEN75_REG_MI_PREDICATE_RESULT_2 0x2214
-
-#define GEN7_REG_3DPRIM_END_OFFSET 0x2420
-
-#define GEN7_REG_3DPRIM_START_VERTEX 0x2430
-
-#define GEN7_REG_3DPRIM_VERTEX_COUNT 0x2434
-
-#define GEN7_REG_3DPRIM_INSTANCE_COUNT 0x2438
-
-#define GEN7_REG_3DPRIM_START_INSTANCE 0x243c
-
-#define GEN7_REG_3DPRIM_BASE_VERTEX 0x2440
-
-#define GEN75_REG_CS_GPR(i0) (0x2600 + 0x8*(i0))
-#define GEN75_REG_CS_GPR__ESIZE 0x8
-#define GEN75_REG_CS_GPR__LEN 0x10
-
-#define GEN7_REG_GPGPU_DISPATCHDIMX 0x2500
-
-#define GEN7_REG_GPGPU_DISPATCHDIMY 0x2504
-
-#define GEN7_REG_GPGPU_DISPATCHDIMZ 0x2508
-
-
-#define GEN7_REG_SO_NUM_PRIMS_WRITTEN(i0) (0x5200 + 0x8*(i0))
-#define GEN7_REG_SO_NUM_PRIMS_WRITTEN__ESIZE 0x8
-#define GEN7_REG_SO_NUM_PRIMS_WRITTEN__LEN 0x4
-
-#define GEN7_REG_SO_PRIM_STORAGE_NEEDED(i0) (0x5240 + 0x8*(i0))
-#define GEN7_REG_SO_PRIM_STORAGE_NEEDED__ESIZE 0x8
-#define GEN7_REG_SO_PRIM_STORAGE_NEEDED__LEN 0x4
-
-#define GEN7_REG_SO_WRITE_OFFSET(i0) (0x5280 + 0x8*(i0))
-#define GEN7_REG_SO_WRITE_OFFSET__ESIZE 0x8
-#define GEN7_REG_SO_WRITE_OFFSET__LEN 0x4
-
-
-#define GEN7_REG_CACHE_MODE_0 0x7000
-#define GEN7_REG_CACHE_MODE_0_HIZ_RAW_STALL_OPT_DISABLE (0x1 << 2)
-
-#define GEN7_REG_CACHE_MODE_1 0x7004
-#define GEN8_REG_CACHE_MODE_1_NP_EARLY_Z_FAILS_DISABLE (0x1 << 13)
-#define GEN8_REG_CACHE_MODE_1_NP_PMA_FIX_ENABLE (0x1 << 11)
-
-
-#define GEN8_REG_L3CNTLREG 0x7034
-
-
-#define GEN7_REG_L3SQCREG1 0xb010
-#define GEN7_REG_L3SQCREG1_CON4DCUNC (0x1 << 24)
-#define GEN7_REG_L3SQCREG1_SQGHPCI__MASK 0x00ff0000
-#define GEN7_REG_L3SQCREG1_SQGHPCI__SHIFT 16
-#define GEN7_REG_L3SQCREG1_SQGHPCI_18_6 (0x73 << 16)
-#define GEN75_REG_L3SQCREG1_SQGPCI__MASK 0x00f80000
-#define GEN75_REG_L3SQCREG1_SQGPCI__SHIFT 19
-#define GEN75_REG_L3SQCREG1_SQGPCI_24 (0xc << 19)
-#define GEN75_REG_L3SQCREG1_SQHPCI__MASK 0x0007c000
-#define GEN75_REG_L3SQCREG1_SQHPCI__SHIFT 14
-#define GEN75_REG_L3SQCREG1_SQHPCI_8 (0x4 << 14)
-
-#define GEN7_REG_L3SQCREG2 0xb014
-
-#define GEN7_REG_L3SQCREG3 0xb018
-
-#define GEN7_REG_L3CNTLREG1 0xb01c
-
-#define GEN7_REG_L3CNTLREG2 0xb020
-#define GEN7_REG_L3CNTLREG2_DCWASLMB (0x1 << 27)
-#define GEN7_REG_L3CNTLREG2_DCWASS__MASK 0x07e00000
-#define GEN7_REG_L3CNTLREG2_DCWASS__SHIFT 21
-#define GEN7_REG_L3CNTLREG2_ROCPSLMB (0x1 << 20)
-#define GEN7_REG_L3CNTLREG2_RDOCPL__MASK 0x000fc000
-#define GEN7_REG_L3CNTLREG2_RDOCPL__SHIFT 14
-#define GEN7_REG_L3CNTLREG2_URBSLMB (0x1 << 7)
-#define GEN7_REG_L3CNTLREG2_URBALL__MASK 0x0000007e
-#define GEN7_REG_L3CNTLREG2_URBALL__SHIFT 1
-#define GEN7_REG_L3CNTLREG2_SLMMENB (0x1 << 0)
-
-#define GEN7_REG_L3CNTLREG3 0xb024
-#define GEN7_REG_L3CNTLREG3_TWALSLMB (0x1 << 21)
-#define GEN7_REG_L3CNTLREG3_TXWYALL__MASK 0x001f8000
-#define GEN7_REG_L3CNTLREG3_TXWYALL__SHIFT 15
-#define GEN7_REG_L3CNTLREG3_CWASLMB (0x1 << 14)
-#define GEN7_REG_L3CNTLREG3_CTWYALL__MASK 0x00003f00
-#define GEN7_REG_L3CNTLREG3_CTWYALL__SHIFT 8
-#define GEN7_REG_L3CNTLREG3_ISWYSLMB (0x1 << 7)
-#define GEN7_REG_L3CNTLREG3_ISWYALL__MASK 0x0000007e
-#define GEN7_REG_L3CNTLREG3_ISWYALL__SHIFT 1
-
-#define GEN6_REG_BCS_SWCTRL 0x22200
-#define GEN6_REG_BCS_SWCTRL_DST_TILING_Y (0x1 << 1)
-#define GEN6_REG_BCS_SWCTRL_SRC_TILING_Y (0x1 << 0)
-
-
-#endif /* GEN_REGS_XML */
+++ /dev/null
-#ifndef GEN_RENDER_XML
-#define GEN_RENDER_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-https://github.com/olvaffe/envytools/
-git clone https://github.com/olvaffe/envytools.git
-
-Copyright (C) 2014-2015 by the following authors:
-- Chia-I Wu <olvaffe@gmail.com> (olv)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-#define GEN6_RENDER_TYPE__MASK 0xe0000000
-#define GEN6_RENDER_TYPE__SHIFT 29
-#define GEN6_RENDER_TYPE_RENDER (0x3 << 29)
-#define GEN6_RENDER_SUBTYPE__MASK 0x18000000
-#define GEN6_RENDER_SUBTYPE__SHIFT 27
-#define GEN6_RENDER_SUBTYPE_COMMON (0x0 << 27)
-#define GEN6_RENDER_SUBTYPE_SINGLE_DW (0x1 << 27)
-#define GEN6_RENDER_SUBTYPE_MEDIA (0x2 << 27)
-#define GEN6_RENDER_SUBTYPE_3D (0x3 << 27)
-#define GEN6_RENDER_OPCODE__MASK 0x07ff0000
-#define GEN6_RENDER_OPCODE__SHIFT 16
-#define GEN6_RENDER_OPCODE_STATE_BASE_ADDRESS (0x101 << 16)
-#define GEN6_RENDER_OPCODE_STATE_SIP (0x102 << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_VF_STATISTICS (0xb << 16)
-#define GEN6_RENDER_OPCODE_PIPELINE_SELECT (0x104 << 16)
-#define GEN6_RENDER_OPCODE_MEDIA_VFE_STATE (0x0 << 16)
-#define GEN6_RENDER_OPCODE_MEDIA_CURBE_LOAD (0x1 << 16)
-#define GEN6_RENDER_OPCODE_MEDIA_INTERFACE_DESCRIPTOR_LOAD (0x2 << 16)
-#define GEN6_RENDER_OPCODE_MEDIA_STATE_FLUSH (0x4 << 16)
-#define GEN7_RENDER_OPCODE_GPGPU_WALKER (0x105 << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS (0x1 << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS (0x2 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_CLEAR_PARAMS (0x4 << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_URB (0x5 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_DEPTH_BUFFER (0x5 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_STENCIL_BUFFER (0x6 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_HIER_DEPTH_BUFFER (0x7 << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_VERTEX_BUFFERS (0x8 << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_VERTEX_ELEMENTS (0x9 << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_INDEX_BUFFER (0xa << 16)
-#define GEN75_RENDER_OPCODE_3DSTATE_VF (0xc << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS (0xd << 16)
-#define GEN8_RENDER_OPCODE_3DSTATE_MULTISAMPLE (0xd << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_CC_STATE_POINTERS (0xe << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_SCISSOR_STATE_POINTERS (0xf << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_VS (0x10 << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_GS (0x11 << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_CLIP (0x12 << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_SF (0x13 << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_WM (0x14 << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_VS (0x15 << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_GS (0x16 << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_PS (0x17 << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_SAMPLE_MASK (0x18 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_CONSTANT_HS (0x19 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_CONSTANT_DS (0x1a << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_HS (0x1b << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_TE (0x1c << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_DS (0x1d << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_STREAMOUT (0x1e << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_SBE (0x1f << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_PS (0x20 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP (0x21 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_CC (0x23 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_BLEND_STATE_POINTERS (0x24 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_DEPTH_STENCIL_STATE_POINTERS (0x25 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_VS (0x26 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_HS (0x27 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_DS (0x28 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_GS (0x29 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_PS (0x2a << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_VS (0x2b << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_HS (0x2c << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_DS (0x2d << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_GS (0x2e << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_PS (0x2f << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_URB_VS (0x30 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_URB_HS (0x31 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_URB_DS (0x32 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_URB_GS (0x33 << 16)
-#define GEN75_RENDER_OPCODE_3DSTATE_GATHER_CONSTANT_VS (0x34 << 16)
-#define GEN75_RENDER_OPCODE_3DSTATE_GATHER_CONSTANT_GS (0x35 << 16)
-#define GEN75_RENDER_OPCODE_3DSTATE_GATHER_CONSTANT_HS (0x36 << 16)
-#define GEN75_RENDER_OPCODE_3DSTATE_GATHER_CONSTANT_DS (0x37 << 16)
-#define GEN75_RENDER_OPCODE_3DSTATE_GATHER_CONSTANT_PS (0x38 << 16)
-#define GEN75_RENDER_OPCODE_3DSTATE_BINDING_TABLE_EDIT_VS (0x43 << 16)
-#define GEN75_RENDER_OPCODE_3DSTATE_BINDING_TABLE_EDIT_GS (0x44 << 16)
-#define GEN75_RENDER_OPCODE_3DSTATE_BINDING_TABLE_EDIT_HS (0x45 << 16)
-#define GEN75_RENDER_OPCODE_3DSTATE_BINDING_TABLE_EDIT_DS (0x45 << 16)
-#define GEN75_RENDER_OPCODE_3DSTATE_BINDING_TABLE_EDIT_PS (0x46 << 16)
-#define GEN8_RENDER_OPCODE_3DSTATE_VF_INSTANCING (0x49 << 16)
-#define GEN8_RENDER_OPCODE_3DSTATE_VF_SGVS (0x4a << 16)
-#define GEN8_RENDER_OPCODE_3DSTATE_VF_TOPOLOGY (0x4b << 16)
-#define GEN8_RENDER_OPCODE_3DSTATE_WM_CHROMAKEY (0x4c << 16)
-#define GEN8_RENDER_OPCODE_3DSTATE_PS_BLEND (0x4d << 16)
-#define GEN8_RENDER_OPCODE_3DSTATE_WM_DEPTH_STENCIL (0x4e << 16)
-#define GEN8_RENDER_OPCODE_3DSTATE_PS_EXTRA (0x4f << 16)
-#define GEN8_RENDER_OPCODE_3DSTATE_RASTER (0x50 << 16)
-#define GEN8_RENDER_OPCODE_3DSTATE_SBE_SWIZ (0x51 << 16)
-#define GEN8_RENDER_OPCODE_3DSTATE_WM_HZ_OP (0x52 << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_DRAWING_RECTANGLE (0x100 << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_DEPTH_BUFFER (0x105 << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_POLY_STIPPLE_OFFSET (0x106 << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_POLY_STIPPLE_PATTERN (0x107 << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_LINE_STIPPLE (0x108 << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_AA_LINE_PARAMETERS (0x10a << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_GS_SVB_INDEX (0x10b << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_MULTISAMPLE (0x10d << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_STENCIL_BUFFER (0x10e << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_HIER_DEPTH_BUFFER (0x10f << 16)
-#define GEN6_RENDER_OPCODE_3DSTATE_CLEAR_PARAMS (0x110 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_VS (0x112 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_HS (0x113 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_DS (0x114 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_GS (0x115 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_PS (0x116 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_SO_DECL_LIST (0x117 << 16)
-#define GEN7_RENDER_OPCODE_3DSTATE_SO_BUFFER (0x118 << 16)
-#define GEN75_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POOL_ALLOC (0x119 << 16)
-#define GEN75_RENDER_OPCODE_3DSTATE_GATHER_POOL_ALLOC (0x11a << 16)
-#define GEN8_RENDER_OPCODE_3DSTATE_SAMPLE_PATTERN (0x11c << 16)
-#define GEN6_RENDER_OPCODE_PIPE_CONTROL (0x200 << 16)
-#define GEN6_RENDER_OPCODE_3DPRIMITIVE (0x300 << 16)
-#define GEN6_RENDER_LENGTH__MASK 0x000000ff
-#define GEN6_RENDER_LENGTH__SHIFT 0
-#define GEN6_MOCS_LLC__MASK 0x00000003
-#define GEN6_MOCS_LLC__SHIFT 0
-#define GEN6_MOCS_LLC_PTE 0x0
-#define GEN6_MOCS_LLC_UC 0x1
-#define GEN6_MOCS_LLC_WB 0x2
-#define GEN7_MOCS_LLC__MASK 0x00000002
-#define GEN7_MOCS_LLC__SHIFT 1
-#define GEN7_MOCS_LLC_PTE (0x0 << 1)
-#define GEN7_MOCS_LLC_WB (0x1 << 1)
-#define GEN75_MOCS_LLC__MASK 0x00000006
-#define GEN75_MOCS_LLC__SHIFT 1
-#define GEN75_MOCS_LLC_PTE (0x0 << 1)
-#define GEN75_MOCS_LLC_UC (0x1 << 1)
-#define GEN75_MOCS_LLC_WB (0x2 << 1)
-#define GEN75_MOCS_LLC_ELLC (0x3 << 1)
-#define GEN7_MOCS_L3__MASK 0x00000001
-#define GEN7_MOCS_L3__SHIFT 0
-#define GEN7_MOCS_L3_UC 0x0
-#define GEN7_MOCS_L3_WB 0x1
-#define GEN8_MOCS_MT__MASK 0x00000060
-#define GEN8_MOCS_MT__SHIFT 5
-#define GEN8_MOCS_MT_PTE (0x0 << 5)
-#define GEN8_MOCS_MT_UC (0x1 << 5)
-#define GEN8_MOCS_MT_WT (0x2 << 5)
-#define GEN8_MOCS_MT_WB (0x3 << 5)
-#define GEN8_MOCS_CT__MASK 0x00000018
-#define GEN8_MOCS_CT__SHIFT 3
-#define GEN8_MOCS_CT_ELLC (0x0 << 3)
-#define GEN8_MOCS_CT_LLC_ONLY (0x1 << 3)
-#define GEN8_MOCS_CT_LLC (0x2 << 3)
-#define GEN8_MOCS_CT_L3 (0x3 << 3)
-#define GEN9_MOCS__MASK 0x0000007f
-#define GEN9_MOCS__SHIFT 0
-#define GEN9_MOCS_MT_WT_CT_L3 0x5
-#define GEN9_MOCS_MT_WB_CT_L3 0x9
-#define GEN6_SBA_ADDR__MASK 0xfffff000
-#define GEN6_SBA_ADDR__SHIFT 12
-#define GEN6_SBA_ADDR__SHR 12
-#define GEN6_SBA_MOCS__MASK 0x00000f00
-#define GEN6_SBA_MOCS__SHIFT 8
-#define GEN8_SBA_MOCS__MASK 0x000007f0
-#define GEN8_SBA_MOCS__SHIFT 4
-#define GEN6_SBA_ADDR_MODIFIED (0x1 << 0)
-#define GEN8_SBA_SIZE__MASK 0xfffff000
-#define GEN8_SBA_SIZE__SHIFT 12
-#define GEN8_SBA_SIZE__SHR 12
-#define GEN8_SBA_SIZE_MODIFIED (0x1 << 0)
-#define GEN6_BINDING_TABLE_ADDR__MASK 0x0000ffe0
-#define GEN6_BINDING_TABLE_ADDR__SHIFT 5
-#define GEN6_BINDING_TABLE_ADDR__SHR 5
-#define GEN6_STATE_BASE_ADDRESS__SIZE 19
-
-
-#define GEN6_SBA_DW1_GENERAL_STATELESS_MOCS__MASK 0x000000f0
-#define GEN6_SBA_DW1_GENERAL_STATELESS_MOCS__SHIFT 4
-#define GEN6_SBA_DW1_GENERAL_STATELESS_FORCE_WRITE_THRU (0x1 << 3)
-
-
-
-
-
-
-
-
-
-
-
-
-
-#define GEN8_SBA_DW3_STATELESS_MOCS__MASK 0x007f0000
-#define GEN8_SBA_DW3_STATELESS_MOCS__SHIFT 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-#define GEN6_STATE_SIP__SIZE 3
-
-
-#define GEN6_SIP_DW1_KERNEL_ADDR__MASK 0xfffffff0
-#define GEN6_SIP_DW1_KERNEL_ADDR__SHIFT 4
-#define GEN6_SIP_DW1_KERNEL_ADDR__SHR 4
-
-
-#define GEN6_PIPELINE_SELECT__SIZE 1
-
-#define GEN6_PIPELINE_SELECT_DW0_SELECT__MASK 0x00000003
-#define GEN6_PIPELINE_SELECT_DW0_SELECT__SHIFT 0
-#define GEN6_PIPELINE_SELECT_DW0_SELECT_3D 0x0
-#define GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA 0x1
-#define GEN7_PIPELINE_SELECT_DW0_SELECT_GPGPU 0x2
-#define GEN9_PIPELINE_SELECT_DW0_SELECT__MASK 0x00000700
-#define GEN9_PIPELINE_SELECT_DW0_SELECT__SHIFT 8
-#define GEN9_PIPELINE_SELECT_DW0_SELECT_3D (0x3 << 8)
-
-#define GEN6_PIPE_CONTROL__SIZE 6
-
-
-#define GEN7_PIPE_CONTROL_USE_GGTT (0x1 << 24)
-#define GEN7_PIPE_CONTROL_LRI_WRITE__MASK 0x00800000
-#define GEN7_PIPE_CONTROL_LRI_WRITE__SHIFT 23
-#define GEN7_PIPE_CONTROL_LRI_WRITE_NONE (0x0 << 23)
-#define GEN7_PIPE_CONTROL_LRI_WRITE_IMM (0x1 << 23)
-#define GEN6_PIPE_CONTROL_PROTECTED_MEMORY_ENABLE (0x1 << 22)
-#define GEN6_PIPE_CONTROL_STORE_DATA_INDEX (0x1 << 21)
-#define GEN6_PIPE_CONTROL_CS_STALL (0x1 << 20)
-#define GEN6_PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET (0x1 << 19)
-#define GEN6_PIPE_CONTROL_TLB_INVALIDATE (0x1 << 18)
-#define GEN6_PIPE_CONTROL_SYNC_GFDT_SURFACE (0x1 << 17)
-#define GEN6_PIPE_CONTROL_GENERIC_MEDIA_STATE_CLEAR (0x1 << 16)
-#define GEN6_PIPE_CONTROL_WRITE__MASK 0x0000c000
-#define GEN6_PIPE_CONTROL_WRITE__SHIFT 14
-#define GEN6_PIPE_CONTROL_WRITE_NONE (0x0 << 14)
-#define GEN6_PIPE_CONTROL_WRITE_IMM (0x1 << 14)
-#define GEN6_PIPE_CONTROL_WRITE_PS_DEPTH_COUNT (0x2 << 14)
-#define GEN6_PIPE_CONTROL_WRITE_TIMESTAMP (0x3 << 14)
-#define GEN6_PIPE_CONTROL_DEPTH_STALL (0x1 << 13)
-#define GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH (0x1 << 12)
-#define GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (0x1 << 11)
-#define GEN6_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (0x1 << 10)
-#define GEN6_PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE (0x1 << 9)
-#define GEN6_PIPE_CONTROL_NOTIFY_ENABLE (0x1 << 8)
-#define GEN7_PIPE_CONTROL_WRITE_IMM_FLUSH (0x1 << 7)
-#define GEN6_PIPE_CONTROL_PROTECTED_MEMORY_APP_ID__MASK 0x00000040
-#define GEN6_PIPE_CONTROL_PROTECTED_MEMORY_APP_ID__SHIFT 6
-#define GEN7_PIPE_CONTROL_DC_FLUSH (0x1 << 5)
-#define GEN6_PIPE_CONTROL_VF_CACHE_INVALIDATE (0x1 << 4)
-#define GEN6_PIPE_CONTROL_CONSTANT_CACHE_INVALIDATE (0x1 << 3)
-#define GEN6_PIPE_CONTROL_STATE_CACHE_INVALIDATE (0x1 << 2)
-#define GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL (0x1 << 1)
-#define GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH (0x1 << 0)
-
-#define GEN6_PIPE_CONTROL_DW2_USE_GGTT (0x1 << 2)
-#define GEN6_PIPE_CONTROL_DW2_ADDR__MASK 0xfffffff8
-#define GEN6_PIPE_CONTROL_DW2_ADDR__SHIFT 3
-#define GEN6_PIPE_CONTROL_DW2_ADDR__SHR 3
-
-#define GEN7_PIPE_CONTROL_DW2_ADDR__MASK 0xfffffffc
-#define GEN7_PIPE_CONTROL_DW2_ADDR__SHIFT 2
-#define GEN7_PIPE_CONTROL_DW2_ADDR__SHR 2
-
-#define GEN8_PIPE_CONTROL_DW2_ADDR__MASK 0xfffffffc
-#define GEN8_PIPE_CONTROL_DW2_ADDR__SHIFT 2
-#define GEN8_PIPE_CONTROL_DW2_ADDR__SHR 2
-
-
-
-
-
-#endif /* GEN_RENDER_XML */
+++ /dev/null
-#ifndef GEN_RENDER_3D_XML
-#define GEN_RENDER_3D_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-https://github.com/olvaffe/envytools/
-git clone https://github.com/olvaffe/envytools.git
-
-Copyright (C) 2014-2015 by the following authors:
-- Chia-I Wu <olvaffe@gmail.com> (olv)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-enum gen_3dprim_type {
- GEN6_3DPRIM_POINTLIST = 0x1,
- GEN6_3DPRIM_LINELIST = 0x2,
- GEN6_3DPRIM_LINESTRIP = 0x3,
- GEN6_3DPRIM_TRILIST = 0x4,
- GEN6_3DPRIM_TRISTRIP = 0x5,
- GEN6_3DPRIM_TRIFAN = 0x6,
- GEN6_3DPRIM_QUADLIST = 0x7,
- GEN6_3DPRIM_QUADSTRIP = 0x8,
- GEN6_3DPRIM_LINELIST_ADJ = 0x9,
- GEN6_3DPRIM_LINESTRIP_ADJ = 0xa,
- GEN6_3DPRIM_TRILIST_ADJ = 0xb,
- GEN6_3DPRIM_TRISTRIP_ADJ = 0xc,
- GEN6_3DPRIM_TRISTRIP_REVERSE = 0xd,
- GEN6_3DPRIM_POLYGON = 0xe,
- GEN6_3DPRIM_RECTLIST = 0xf,
- GEN6_3DPRIM_LINELOOP = 0x10,
- GEN6_3DPRIM_POINTLIST_BF = 0x11,
- GEN6_3DPRIM_LINESTRIP_CONT = 0x12,
- GEN6_3DPRIM_LINESTRIP_BF = 0x13,
- GEN6_3DPRIM_LINESTRIP_CONT_BF = 0x14,
- GEN6_3DPRIM_TRIFAN_NOSTIPPLE = 0x16,
- GEN7_3DPRIM_PATCHLIST_1 = 0x20,
- GEN7_3DPRIM_PATCHLIST_2 = 0x21,
- GEN7_3DPRIM_PATCHLIST_3 = 0x22,
- GEN7_3DPRIM_PATCHLIST_4 = 0x23,
- GEN7_3DPRIM_PATCHLIST_5 = 0x24,
- GEN7_3DPRIM_PATCHLIST_6 = 0x25,
- GEN7_3DPRIM_PATCHLIST_7 = 0x26,
- GEN7_3DPRIM_PATCHLIST_8 = 0x27,
- GEN7_3DPRIM_PATCHLIST_9 = 0x28,
- GEN7_3DPRIM_PATCHLIST_10 = 0x29,
- GEN7_3DPRIM_PATCHLIST_11 = 0x2a,
- GEN7_3DPRIM_PATCHLIST_12 = 0x2b,
- GEN7_3DPRIM_PATCHLIST_13 = 0x2c,
- GEN7_3DPRIM_PATCHLIST_14 = 0x2d,
- GEN7_3DPRIM_PATCHLIST_15 = 0x2e,
- GEN7_3DPRIM_PATCHLIST_16 = 0x2f,
- GEN7_3DPRIM_PATCHLIST_17 = 0x30,
- GEN7_3DPRIM_PATCHLIST_18 = 0x31,
- GEN7_3DPRIM_PATCHLIST_19 = 0x32,
- GEN7_3DPRIM_PATCHLIST_20 = 0x33,
- GEN7_3DPRIM_PATCHLIST_21 = 0x34,
- GEN7_3DPRIM_PATCHLIST_22 = 0x35,
- GEN7_3DPRIM_PATCHLIST_23 = 0x36,
- GEN7_3DPRIM_PATCHLIST_24 = 0x37,
- GEN7_3DPRIM_PATCHLIST_25 = 0x38,
- GEN7_3DPRIM_PATCHLIST_26 = 0x39,
- GEN7_3DPRIM_PATCHLIST_27 = 0x3a,
- GEN7_3DPRIM_PATCHLIST_28 = 0x3b,
- GEN7_3DPRIM_PATCHLIST_29 = 0x3c,
- GEN7_3DPRIM_PATCHLIST_30 = 0x3d,
- GEN7_3DPRIM_PATCHLIST_31 = 0x3e,
- GEN7_3DPRIM_PATCHLIST_32 = 0x3f,
-};
-
-enum gen_state_alignment {
- GEN6_ALIGNMENT_COLOR_CALC_STATE = 0x40,
- GEN6_ALIGNMENT_DEPTH_STENCIL_STATE = 0x40,
- GEN6_ALIGNMENT_BLEND_STATE = 0x40,
- GEN6_ALIGNMENT_CLIP_VIEWPORT = 0x20,
- GEN6_ALIGNMENT_SF_VIEWPORT = 0x20,
- GEN7_ALIGNMENT_SF_CLIP_VIEWPORT = 0x40,
- GEN6_ALIGNMENT_CC_VIEWPORT = 0x20,
- GEN6_ALIGNMENT_SCISSOR_RECT = 0x20,
- GEN6_ALIGNMENT_BINDING_TABLE_STATE = 0x20,
- GEN6_ALIGNMENT_SAMPLER_BORDER_COLOR_STATE = 0x20,
- GEN8_ALIGNMENT_SAMPLER_BORDER_COLOR_STATE = 0x40,
- GEN6_ALIGNMENT_SAMPLER_STATE = 0x20,
- GEN6_ALIGNMENT_SURFACE_STATE = 0x20,
- GEN8_ALIGNMENT_SURFACE_STATE = 0x40,
-};
-
-enum gen_index_format {
- GEN6_INDEX_BYTE = 0x0,
- GEN6_INDEX_WORD = 0x1,
- GEN6_INDEX_DWORD = 0x2,
-};
-
-enum gen_vf_component {
- GEN6_VFCOMP_NOSTORE = 0x0,
- GEN6_VFCOMP_STORE_SRC = 0x1,
- GEN6_VFCOMP_STORE_0 = 0x2,
- GEN6_VFCOMP_STORE_1_FP = 0x3,
- GEN6_VFCOMP_STORE_1_INT = 0x4,
- GEN6_VFCOMP_STORE_VID = 0x5,
- GEN6_VFCOMP_STORE_IID = 0x6,
-};
-
-enum gen_depth_format {
- GEN6_ZFORMAT_D32_FLOAT_S8X24_UINT = 0x0,
- GEN6_ZFORMAT_D32_FLOAT = 0x1,
- GEN6_ZFORMAT_D24_UNORM_S8_UINT = 0x2,
- GEN6_ZFORMAT_D24_UNORM_X8_UINT = 0x3,
- GEN6_ZFORMAT_D16_UNORM = 0x5,
-};
-
-enum gen_reorder_mode {
- GEN7_REORDER_LEADING = 0x0,
- GEN7_REORDER_TRAILING = 0x1,
-};
-
-enum gen_clip_mode {
- GEN6_CLIPMODE_NORMAL = 0x0,
- GEN6_CLIPMODE_REJECT_ALL = 0x3,
- GEN6_CLIPMODE_ACCEPT_ALL = 0x4,
-};
-
-enum gen_front_winding {
- GEN6_FRONTWINDING_CW = 0x0,
- GEN6_FRONTWINDING_CCW = 0x1,
-};
-
-enum gen_fill_mode {
- GEN6_FILLMODE_SOLID = 0x0,
- GEN6_FILLMODE_WIREFRAME = 0x1,
- GEN6_FILLMODE_POINT = 0x2,
-};
-
-enum gen_cull_mode {
- GEN6_CULLMODE_BOTH = 0x0,
- GEN6_CULLMODE_NONE = 0x1,
- GEN6_CULLMODE_FRONT = 0x2,
- GEN6_CULLMODE_BACK = 0x3,
-};
-
-enum gen_pixel_location {
- GEN6_PIXLOC_CENTER = 0x0,
- GEN6_PIXLOC_UL_CORNER = 0x1,
-};
-
-enum gen_sample_count {
- GEN6_NUMSAMPLES_1 = 0x0,
- GEN8_NUMSAMPLES_2 = 0x1,
- GEN6_NUMSAMPLES_4 = 0x2,
- GEN7_NUMSAMPLES_8 = 0x3,
-};
-
-enum gen_inputattr_select {
- GEN6_INPUTATTR_NORMAL = 0x0,
- GEN6_INPUTATTR_FACING = 0x1,
- GEN6_INPUTATTR_W = 0x2,
- GEN6_INPUTATTR_FACING_W = 0x3,
-};
-
-enum gen_zw_interp {
- GEN6_ZW_INTERP_PIXEL = 0x0,
- GEN6_ZW_INTERP_CENTROID = 0x2,
- GEN6_ZW_INTERP_SAMPLE = 0x3,
-};
-
-enum gen_position_offset {
- GEN6_POSOFFSET_NONE = 0x0,
- GEN6_POSOFFSET_CENTROID = 0x2,
- GEN6_POSOFFSET_SAMPLE = 0x3,
-};
-
-enum gen_edsc_mode {
- GEN7_EDSC_NORMAL = 0x0,
- GEN7_EDSC_PSEXEC = 0x1,
- GEN7_EDSC_PREPS = 0x2,
-};
-
-enum gen_pscdepth_mode {
- GEN7_PSCDEPTH_OFF = 0x0,
- GEN7_PSCDEPTH_ON = 0x1,
- GEN7_PSCDEPTH_ON_GE = 0x2,
- GEN7_PSCDEPTH_ON_LE = 0x3,
-};
-
-enum gen_msrast_mode {
- GEN6_MSRASTMODE_OFF_PIXEL = 0x0,
- GEN6_MSRASTMODE_OFF_PATTERN = 0x1,
- GEN6_MSRASTMODE_ON_PIXEL = 0x2,
- GEN6_MSRASTMODE_ON_PATTERN = 0x3,
-};
-
-#define GEN6_INTERP_NONPERSPECTIVE_SAMPLE (0x1 << 5)
-#define GEN6_INTERP_NONPERSPECTIVE_CENTROID (0x1 << 4)
-#define GEN6_INTERP_NONPERSPECTIVE_PIXEL (0x1 << 3)
-#define GEN6_INTERP_PERSPECTIVE_SAMPLE (0x1 << 2)
-#define GEN6_INTERP_PERSPECTIVE_CENTROID (0x1 << 1)
-#define GEN6_INTERP_PERSPECTIVE_PIXEL (0x1 << 0)
-#define GEN6_PS_DISPATCH_32 (0x1 << 2)
-#define GEN6_PS_DISPATCH_16 (0x1 << 1)
-#define GEN6_PS_DISPATCH_8 (0x1 << 0)
-#define GEN6_THREADDISP_SPF (0x1 << 31)
-#define GEN6_THREADDISP_VME (0x1 << 30)
-#define GEN6_THREADDISP_SAMPLER_COUNT__MASK 0x38000000
-#define GEN6_THREADDISP_SAMPLER_COUNT__SHIFT 27
-#define GEN7_THREADDISP_DENORMAL__MASK 0x04000000
-#define GEN7_THREADDISP_DENORMAL__SHIFT 26
-#define GEN7_THREADDISP_DENORMAL_FTZ (0x0 << 26)
-#define GEN7_THREADDISP_DENORMAL_RET (0x1 << 26)
-#define GEN6_THREADDISP_BINDING_TABLE_SIZE__MASK 0x03fc0000
-#define GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT 18
-#define GEN6_THREADDISP_PRIORITY_HIGH (0x1 << 17)
-#define GEN6_THREADDISP_FP_MODE_ALT (0x1 << 16)
-#define GEN7_ROUNDING_MODE__MASK 0x0000c000
-#define GEN7_ROUNDING_MODE__SHIFT 14
-#define GEN7_ROUNDING_MODE_RTNE (0x0 << 14)
-#define GEN7_ROUNDING_MODE_RU (0x1 << 14)
-#define GEN7_ROUNDING_MODE_RD (0x2 << 14)
-#define GEN7_ROUNDING_MODE_RTZ (0x3 << 14)
-#define GEN6_THREADDISP_ILLEGAL_CODE_EXCEPTION (0x1 << 13)
-#define GEN75_THREADDISP_ACCESS_UAV (0x1 << 12)
-#define GEN6_THREADDISP_MASK_STACK_EXCEPTION (0x1 << 11)
-#define GEN6_THREADDISP_SOFTWARE_EXCEPTION (0x1 << 7)
-#define GEN6_THREADSCRATCH_ADDR__MASK 0xfffffc00
-#define GEN6_THREADSCRATCH_ADDR__SHIFT 10
-#define GEN6_THREADSCRATCH_ADDR__SHR 10
-#define GEN6_THREADSCRATCH_SPACE_PER_THREAD__MASK 0x0000000f
-#define GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT 0
-#define GEN6_3DSTATE_VF_STATISTICS__SIZE 1
-
-#define GEN6_VF_STATS_DW0_ENABLE (0x1 << 0)
-
-#define GEN6_3DSTATE_BINDING_TABLE_POINTERS__SIZE 4
-
-#define GEN6_BINDING_TABLE_PTR_DW0_PS_CHANGED (0x1 << 12)
-#define GEN6_BINDING_TABLE_PTR_DW0_GS_CHANGED (0x1 << 9)
-#define GEN6_BINDING_TABLE_PTR_DW0_VS_CHANGED (0x1 << 8)
-
-
-
-
-#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS__SIZE 4
-
-#define GEN6_SAMPLER_PTR_DW0_PS_CHANGED (0x1 << 12)
-#define GEN6_SAMPLER_PTR_DW0_GS_CHANGED (0x1 << 9)
-#define GEN6_SAMPLER_PTR_DW0_VS_CHANGED (0x1 << 8)
-
-#define GEN6_SAMPLER_PTR_DW1_VS_ADDR__MASK 0xffffffe0
-#define GEN6_SAMPLER_PTR_DW1_VS_ADDR__SHIFT 5
-#define GEN6_SAMPLER_PTR_DW1_VS_ADDR__SHR 5
-
-#define GEN6_SAMPLER_PTR_DW2_GS_ADDR__MASK 0xffffffe0
-#define GEN6_SAMPLER_PTR_DW2_GS_ADDR__SHIFT 5
-#define GEN6_SAMPLER_PTR_DW2_GS_ADDR__SHR 5
-
-#define GEN6_SAMPLER_PTR_DW3_PS_ADDR__MASK 0xffffffe0
-#define GEN6_SAMPLER_PTR_DW3_PS_ADDR__SHIFT 5
-#define GEN6_SAMPLER_PTR_DW3_PS_ADDR__SHR 5
-
-#define GEN6_3DSTATE_URB__SIZE 3
-
-
-#define GEN6_URB_DW1_VS_ENTRY_SIZE__MASK 0x00ff0000
-#define GEN6_URB_DW1_VS_ENTRY_SIZE__SHIFT 16
-#define GEN6_URB_DW1_VS_ENTRY_COUNT__MASK 0x0000ffff
-#define GEN6_URB_DW1_VS_ENTRY_COUNT__SHIFT 0
-#define GEN6_URB_DW1_VS_ENTRY_COUNT__ALIGN 4
-
-#define GEN6_URB_DW2_GS_ENTRY_COUNT__MASK 0x0003ff00
-#define GEN6_URB_DW2_GS_ENTRY_COUNT__SHIFT 8
-#define GEN6_URB_DW2_GS_ENTRY_COUNT__ALIGN 4
-#define GEN6_URB_DW2_GS_ENTRY_SIZE__MASK 0x00000007
-#define GEN6_URB_DW2_GS_ENTRY_SIZE__SHIFT 0
-
-#define GEN7_3DSTATE_URB_ANY__SIZE 2
-
-
-#define GEN7_URB_DW1_OFFSET__MASK 0x3e000000
-#define GEN7_URB_DW1_OFFSET__SHIFT 25
-#define GEN75_URB_DW1_OFFSET__MASK 0x7e000000
-#define GEN75_URB_DW1_OFFSET__SHIFT 25
-#define GEN8_URB_DW1_OFFSET__MASK 0xfe000000
-#define GEN8_URB_DW1_OFFSET__SHIFT 25
-#define GEN7_URB_DW1_ENTRY_SIZE__MASK 0x01ff0000
-#define GEN7_URB_DW1_ENTRY_SIZE__SHIFT 16
-#define GEN7_URB_DW1_ENTRY_COUNT__MASK 0x0000ffff
-#define GEN7_URB_DW1_ENTRY_COUNT__SHIFT 0
-
-#define GEN75_3DSTATE_GATHER_CONSTANT_ANY__SIZE 130
-
-
-#define GEN75_GATHER_CONST_DW1_BT_VALID__MASK 0xffff0000
-#define GEN75_GATHER_CONST_DW1_BT_VALID__SHIFT 16
-#define GEN75_GATHER_CONST_DW1_BT_BLOCK__MASK 0x0000f000
-#define GEN75_GATHER_CONST_DW1_BT_BLOCK__SHIFT 12
-
-#define GEN75_GATHER_CONST_DW2_GATHER_BUFFER_OFFSET__MASK 0x007fffc0
-#define GEN75_GATHER_CONST_DW2_GATHER_BUFFER_OFFSET__SHIFT 6
-#define GEN75_GATHER_CONST_DW2_GATHER_BUFFER_OFFSET__SHR 6
-#define GEN8_GATHER_CONST_DW2_DX9_STALL (0x1 << 5)
-#define GEN75_GATHER_CONST_DW2_DX9_ENABLE (0x1 << 4)
-
-#define GEN75_GATHER_CONST_DW_ENTRY_HIGH__MASK 0xffff0000
-#define GEN75_GATHER_CONST_DW_ENTRY_HIGH__SHIFT 16
-#define GEN75_GATHER_CONST_DW_ENTRY_OFFSET__MASK 0x0000ff00
-#define GEN75_GATHER_CONST_DW_ENTRY_OFFSET__SHIFT 8
-#define GEN75_GATHER_CONST_DW_ENTRY_CHANNEL_MASK__MASK 0x000000f0
-#define GEN75_GATHER_CONST_DW_ENTRY_CHANNEL_MASK__SHIFT 4
-#define GEN75_GATHER_CONST_DW_ENTRY_BT_INDEX__MASK 0x0000001f
-#define GEN75_GATHER_CONST_DW_ENTRY_BT_INDEX__SHIFT 0
-
-#define GEN75_3DSTATE_BINDING_TABLE_EDIT_ANY__SIZE 258
-
-
-#define GEN75_BT_EDIT_DW1_BT_BLOCK_CLEAR__MASK 0xffff0000
-#define GEN75_BT_EDIT_DW1_BT_BLOCK_CLEAR__SHIFT 16
-#define GEN75_BT_EDIT_DW1_TARGET__MASK 0x00000003
-#define GEN75_BT_EDIT_DW1_TARGET__SHIFT 0
-#define GEN75_BT_EDIT_DW1_TARGET_CORE0 0x1
-#define GEN75_BT_EDIT_DW1_TARGET_CORE1 0x2
-#define GEN75_BT_EDIT_DW1_TARGET_ALL 0x3
-
-#define GEN75_BT_EDIT_DW_ENTRY_BT_INDEX__MASK 0x00ff0000
-#define GEN75_BT_EDIT_DW_ENTRY_BT_INDEX__SHIFT 16
-#define GEN75_BT_EDIT_DW_ENTRY_SURFACE_STATE_ADDR__MASK 0x0000ffff
-#define GEN75_BT_EDIT_DW_ENTRY_SURFACE_STATE_ADDR__SHIFT 0
-#define GEN75_BT_EDIT_DW_ENTRY_SURFACE_STATE_ADDR__SHR 5
-#define GEN8_BT_EDIT_DW_ENTRY_SURFACE_STATE_ADDR__MASK 0x0000ffff
-#define GEN8_BT_EDIT_DW_ENTRY_SURFACE_STATE_ADDR__SHIFT 0
-#define GEN8_BT_EDIT_DW_ENTRY_SURFACE_STATE_ADDR__SHR 6
-
-#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_ANY__SIZE 2
-
-
-#define GEN7_PCB_ALLOC_DW1_OFFSET__MASK 0x000f0000
-#define GEN7_PCB_ALLOC_DW1_OFFSET__SHIFT 16
-#define GEN7_PCB_ALLOC_DW1_SIZE__MASK 0x0000001f
-#define GEN7_PCB_ALLOC_DW1_SIZE__SHIFT 0
-
-#define GEN75_PCB_ALLOC_DW1_OFFSET__MASK 0x001f0000
-#define GEN75_PCB_ALLOC_DW1_OFFSET__SHIFT 16
-#define GEN75_PCB_ALLOC_DW1_SIZE__MASK 0x0000003f
-#define GEN75_PCB_ALLOC_DW1_SIZE__SHIFT 0
-
-#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC__SIZE 3
-
-
-#define GEN75_BT_POOL_ALLOC_DW1_ADDR__MASK 0xfffff000
-#define GEN75_BT_POOL_ALLOC_DW1_ADDR__SHIFT 12
-#define GEN75_BT_POOL_ALLOC_DW1_ADDR__SHR 12
-#define GEN75_BT_POOL_ALLOC_DW1_ENABLE (0x1 << 11)
-#define GEN75_BT_POOL_ALLOC_DW1_MOCS__MASK 0x00000780
-#define GEN75_BT_POOL_ALLOC_DW1_MOCS__SHIFT 7
-#define GEN8_BT_POOL_ALLOC_DW1_MOCS__MASK 0x0000007f
-#define GEN8_BT_POOL_ALLOC_DW1_MOCS__SHIFT 0
-
-#define GEN75_BT_POOL_ALLOC_DW2_END_ADDR__MASK 0xfffff000
-#define GEN75_BT_POOL_ALLOC_DW2_END_ADDR__SHIFT 12
-#define GEN75_BT_POOL_ALLOC_DW2_END_ADDR__SHR 12
-
-
-#define GEN8_BT_POOL_ALLOC_DW3_SIZE__MASK 0xfffff000
-#define GEN8_BT_POOL_ALLOC_DW3_SIZE__SHIFT 12
-#define GEN8_BT_POOL_ALLOC_DW3_SIZE__SHR 12
-
-#define GEN75_3DSTATE_GATHER_POOL_ALLOC__SIZE 3
-
-
-#define GEN75_GATHER_POOL_ALLOC_DW1_ADDR__MASK 0xfffff000
-#define GEN75_GATHER_POOL_ALLOC_DW1_ADDR__SHIFT 12
-#define GEN75_GATHER_POOL_ALLOC_DW1_ADDR__SHR 12
-#define GEN75_GATHER_POOL_ALLOC_DW1_ENABLE (0x1 << 11)
-#define GEN75_GATHER_POOL_ALLOC_DW1_MOCS__MASK 0x0000000f
-#define GEN75_GATHER_POOL_ALLOC_DW1_MOCS__SHIFT 0
-#define GEN8_GATHER_POOL_ALLOC_DW1_MOCS__MASK 0x0000007f
-#define GEN8_GATHER_POOL_ALLOC_DW1_MOCS__SHIFT 0
-
-#define GEN75_GATHER_POOL_ALLOC_DW2_END_ADDR__MASK 0xfffff000
-#define GEN75_GATHER_POOL_ALLOC_DW2_END_ADDR__SHIFT 12
-#define GEN75_GATHER_POOL_ALLOC_DW2_END_ADDR__SHR 12
-
-
-#define GEN8_GATHER_POOL_ALLOC_DW3_SIZE__MASK 0xfffff000
-#define GEN8_GATHER_POOL_ALLOC_DW3_SIZE__SHIFT 12
-#define GEN8_GATHER_POOL_ALLOC_DW3_SIZE__SHR 12
-
-#define GEN6_3DSTATE_VERTEX_BUFFERS__SIZE 133
-
-
-
-#define GEN6_VB_DW0_INDEX__MASK 0xfc000000
-#define GEN6_VB_DW0_INDEX__SHIFT 26
-#define GEN8_VB_DW0_MOCS__MASK 0x007f0000
-#define GEN8_VB_DW0_MOCS__SHIFT 16
-#define GEN6_VB_DW0_ACCESS__MASK 0x00100000
-#define GEN6_VB_DW0_ACCESS__SHIFT 20
-#define GEN6_VB_DW0_ACCESS_VERTEXDATA (0x0 << 20)
-#define GEN6_VB_DW0_ACCESS_INSTANCEDATA (0x1 << 20)
-#define GEN6_VB_DW0_MOCS__MASK 0x000f0000
-#define GEN6_VB_DW0_MOCS__SHIFT 16
-#define GEN7_VB_DW0_ADDR_MODIFIED (0x1 << 14)
-#define GEN6_VB_DW0_IS_NULL (0x1 << 13)
-#define GEN6_VB_DW0_CACHE_INVALIDATE (0x1 << 12)
-#define GEN6_VB_DW0_PITCH__MASK 0x00000fff
-#define GEN6_VB_DW0_PITCH__SHIFT 0
-
-
-
-
-
-
-
-#define GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE 69
-
-
-
-#define GEN6_VE_DW0_VB_INDEX__MASK 0xfc000000
-#define GEN6_VE_DW0_VB_INDEX__SHIFT 26
-#define GEN6_VE_DW0_VALID (0x1 << 25)
-#define GEN6_VE_DW0_FORMAT__MASK 0x01ff0000
-#define GEN6_VE_DW0_FORMAT__SHIFT 16
-#define GEN6_VE_DW0_EDGE_FLAG_ENABLE (0x1 << 15)
-#define GEN6_VE_DW0_VB_OFFSET__MASK 0x000007ff
-#define GEN6_VE_DW0_VB_OFFSET__SHIFT 0
-#define GEN75_VE_DW0_VB_OFFSET__MASK 0x00000fff
-#define GEN75_VE_DW0_VB_OFFSET__SHIFT 0
-
-#define GEN6_VE_DW1_COMP0__MASK 0x70000000
-#define GEN6_VE_DW1_COMP0__SHIFT 28
-#define GEN6_VE_DW1_COMP1__MASK 0x07000000
-#define GEN6_VE_DW1_COMP1__SHIFT 24
-#define GEN6_VE_DW1_COMP2__MASK 0x00700000
-#define GEN6_VE_DW1_COMP2__SHIFT 20
-#define GEN6_VE_DW1_COMP3__MASK 0x00070000
-#define GEN6_VE_DW1_COMP3__SHIFT 16
-
-#define GEN6_3DSTATE_INDEX_BUFFER__SIZE 5
-
-#define GEN6_IB_DW0_MOCS__MASK 0x0000f000
-#define GEN6_IB_DW0_MOCS__SHIFT 12
-#define GEN6_IB_DW0_CUT_INDEX_ENABLE (0x1 << 10)
-#define GEN6_IB_DW0_FORMAT__MASK 0x00000300
-#define GEN6_IB_DW0_FORMAT__SHIFT 8
-
-
-
-
-
-#define GEN8_IB_DW1_FORMAT__MASK 0x00000300
-#define GEN8_IB_DW1_FORMAT__SHIFT 8
-#define GEN8_IB_DW1_MOCS__MASK 0x0000007f
-#define GEN8_IB_DW1_MOCS__SHIFT 0
-
-
-
-
-#define GEN75_3DSTATE_VF__SIZE 2
-
-#define GEN75_VF_DW0_CUT_INDEX_ENABLE (0x1 << 8)
-
-
-#define GEN8_3DSTATE_VF_INSTANCING__SIZE 3
-
-
-#define GEN8_INSTANCING_DW1_ENABLE (0x1 << 8)
-#define GEN8_INSTANCING_DW1_VE_INDEX__MASK 0x0000003f
-#define GEN8_INSTANCING_DW1_VE_INDEX__SHIFT 0
-
-
-#define GEN8_3DSTATE_VF_SGVS__SIZE 2
-
-
-#define GEN8_SGVS_DW1_IID_ENABLE (0x1 << 31)
-#define GEN8_SGVS_DW1_IID_COMP__MASK 0x60000000
-#define GEN8_SGVS_DW1_IID_COMP__SHIFT 29
-#define GEN8_SGVS_DW1_IID_OFFSET__MASK 0x003f0000
-#define GEN8_SGVS_DW1_IID_OFFSET__SHIFT 16
-#define GEN8_SGVS_DW1_VID_ENABLE (0x1 << 15)
-#define GEN8_SGVS_DW1_VID_COMP__MASK 0x00006000
-#define GEN8_SGVS_DW1_VID_COMP__SHIFT 13
-#define GEN8_SGVS_DW1_VID_OFFSET__MASK 0x0000003f
-#define GEN8_SGVS_DW1_VID_OFFSET__SHIFT 0
-
-#define GEN8_3DSTATE_VF_TOPOLOGY__SIZE 2
-
-
-#define GEN8_TOPOLOGY_DW1_TYPE__MASK 0x0000003f
-#define GEN8_TOPOLOGY_DW1_TYPE__SHIFT 0
-
-#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS__SIZE 4
-
-#define GEN6_VP_PTR_DW0_CC_CHANGED (0x1 << 12)
-#define GEN6_VP_PTR_DW0_SF_CHANGED (0x1 << 11)
-#define GEN6_VP_PTR_DW0_CLIP_CHANGED (0x1 << 10)
-
-#define GEN6_VP_PTR_DW1_CLIP_ADDR__MASK 0xffffffe0
-#define GEN6_VP_PTR_DW1_CLIP_ADDR__SHIFT 5
-#define GEN6_VP_PTR_DW1_CLIP_ADDR__SHR 5
-
-#define GEN6_VP_PTR_DW2_SF_ADDR__MASK 0xffffffe0
-#define GEN6_VP_PTR_DW2_SF_ADDR__SHIFT 5
-#define GEN6_VP_PTR_DW2_SF_ADDR__SHR 5
-
-#define GEN6_VP_PTR_DW3_CC_ADDR__MASK 0xffffffe0
-#define GEN6_VP_PTR_DW3_CC_ADDR__SHIFT 5
-#define GEN6_VP_PTR_DW3_CC_ADDR__SHR 5
-
-#define GEN6_3DSTATE_CC_STATE_POINTERS__SIZE 4
-
-
-#define GEN6_CC_PTR_DW1_BLEND_CHANGED (0x1 << 0)
-#define GEN6_CC_PTR_DW1_BLEND_ADDR__MASK 0xffffffc0
-#define GEN6_CC_PTR_DW1_BLEND_ADDR__SHIFT 6
-#define GEN6_CC_PTR_DW1_BLEND_ADDR__SHR 6
-
-#define GEN6_CC_PTR_DW2_ZS_CHANGED (0x1 << 0)
-#define GEN6_CC_PTR_DW2_ZS_ADDR__MASK 0xffffffc0
-#define GEN6_CC_PTR_DW2_ZS_ADDR__SHIFT 6
-#define GEN6_CC_PTR_DW2_ZS_ADDR__SHR 6
-
-#define GEN6_CC_PTR_DW3_CC_CHANGED (0x1 << 0)
-#define GEN6_CC_PTR_DW3_CC_ADDR__MASK 0xffffffc0
-#define GEN6_CC_PTR_DW3_CC_ADDR__SHIFT 6
-#define GEN6_CC_PTR_DW3_CC_ADDR__SHR 6
-
-#define GEN6_3DSTATE_SCISSOR_STATE_POINTERS__SIZE 2
-
-
-#define GEN6_SCISSOR_PTR_DW1_ADDR__MASK 0xffffffe0
-#define GEN6_SCISSOR_PTR_DW1_ADDR__SHIFT 5
-#define GEN6_SCISSOR_PTR_DW1_ADDR__SHR 5
-
-#define GEN7_3DSTATE_POINTERS_ANY__SIZE 2
-
-
-#define GEN7_PTR_DW1_ADDR__MASK 0xffffffe0
-#define GEN7_PTR_DW1_ADDR__SHIFT 5
-#define GEN7_PTR_DW1_ADDR__SHR 5
-#define GEN8_PTR_DW1_CHANGED (0x1 << 0)
-
-#define GEN6_3DSTATE_VS__SIZE 9
-
-
-#define GEN6_VS_DW1_KERNEL_ADDR__MASK 0xffffffc0
-#define GEN6_VS_DW1_KERNEL_ADDR__SHIFT 6
-#define GEN6_VS_DW1_KERNEL_ADDR__SHR 6
-
-
-
-#define GEN6_VS_DW4_URB_GRF_START__MASK 0x01f00000
-#define GEN6_VS_DW4_URB_GRF_START__SHIFT 20
-#define GEN6_VS_DW4_URB_READ_LEN__MASK 0x0001f800
-#define GEN6_VS_DW4_URB_READ_LEN__SHIFT 11
-#define GEN6_VS_DW4_URB_READ_OFFSET__MASK 0x000003f0
-#define GEN6_VS_DW4_URB_READ_OFFSET__SHIFT 4
-
-#define GEN6_VS_DW5_MAX_THREADS__MASK 0xfe000000
-#define GEN6_VS_DW5_MAX_THREADS__SHIFT 25
-#define GEN75_VS_DW5_MAX_THREADS__MASK 0xff800000
-#define GEN75_VS_DW5_MAX_THREADS__SHIFT 23
-#define GEN6_VS_DW5_STATISTICS (0x1 << 10)
-#define GEN6_VS_DW5_CACHE_DISABLE (0x1 << 1)
-#define GEN6_VS_DW5_VS_ENABLE (0x1 << 0)
-
-
-
-#define GEN8_VS_DW1_KERNEL_ADDR__MASK 0xffffffc0
-#define GEN8_VS_DW1_KERNEL_ADDR__SHIFT 6
-#define GEN8_VS_DW1_KERNEL_ADDR__SHR 6
-
-
-
-
-
-#define GEN8_VS_DW6_URB_GRF_START__MASK 0x01f00000
-#define GEN8_VS_DW6_URB_GRF_START__SHIFT 20
-#define GEN8_VS_DW6_URB_READ_LEN__MASK 0x0001f800
-#define GEN8_VS_DW6_URB_READ_LEN__SHIFT 11
-#define GEN8_VS_DW6_URB_READ_OFFSET__MASK 0x000003f0
-#define GEN8_VS_DW6_URB_READ_OFFSET__SHIFT 4
-
-#define GEN8_VS_DW7_MAX_THREADS__MASK 0xff800000
-#define GEN8_VS_DW7_MAX_THREADS__SHIFT 23
-#define GEN8_VS_DW7_STATISTICS (0x1 << 10)
-#define GEN8_VS_DW7_SIMD8_ENABLE (0x1 << 2)
-#define GEN8_VS_DW7_CACHE_DISABLE (0x1 << 1)
-#define GEN8_VS_DW7_VS_ENABLE (0x1 << 0)
-
-#define GEN8_VS_DW8_VUE_OUT_READ_OFFSET__MASK 0x07e00000
-#define GEN8_VS_DW8_VUE_OUT_READ_OFFSET__SHIFT 21
-#define GEN8_VS_DW8_VUE_OUT_LEN__MASK 0x001f0000
-#define GEN8_VS_DW8_VUE_OUT_LEN__SHIFT 16
-#define GEN8_VS_DW8_UCP_CLIP_ENABLES__MASK 0x0000ff00
-#define GEN8_VS_DW8_UCP_CLIP_ENABLES__SHIFT 8
-#define GEN8_VS_DW8_UCP_CULL_ENABLES__MASK 0x000000ff
-#define GEN8_VS_DW8_UCP_CULL_ENABLES__SHIFT 0
-
-#define GEN7_3DSTATE_HS__SIZE 9
-
-
-#define GEN7_HS_DW1_DISPATCH_MAX_THREADS__MASK 0x0000007f
-#define GEN7_HS_DW1_DISPATCH_MAX_THREADS__SHIFT 0
-#define GEN75_HS_DW1_DISPATCH_MAX_THREADS__MASK 0x000000ff
-#define GEN75_HS_DW1_DISPATCH_MAX_THREADS__SHIFT 0
-
-#define GEN7_HS_DW2_HS_ENABLE (0x1 << 31)
-#define GEN7_HS_DW2_STATISTICS (0x1 << 29)
-#define GEN7_HS_DW2_INSTANCE_COUNT__MASK 0x0000000f
-#define GEN7_HS_DW2_INSTANCE_COUNT__SHIFT 0
-
-#define GEN7_HS_DW3_KERNEL_ADDR__MASK 0xffffffc0
-#define GEN7_HS_DW3_KERNEL_ADDR__SHIFT 6
-#define GEN7_HS_DW3_KERNEL_ADDR__SHR 6
-
-
-#define GEN7_HS_DW5_SPF (0x1 << 27)
-#define GEN7_HS_DW5_VME (0x1 << 26)
-#define GEN75_HS_DW5_ACCESS_UAV (0x1 << 25)
-#define GEN7_HS_DW5_INCLUDE_VERTEX_HANDLES (0x1 << 24)
-#define GEN7_HS_DW5_URB_GRF_START__MASK 0x00f80000
-#define GEN7_HS_DW5_URB_GRF_START__SHIFT 19
-#define GEN7_HS_DW5_URB_READ_LEN__MASK 0x0001f800
-#define GEN7_HS_DW5_URB_READ_LEN__SHIFT 11
-#define GEN7_HS_DW5_URB_READ_OFFSET__MASK 0x000003f0
-#define GEN7_HS_DW5_URB_READ_OFFSET__SHIFT 4
-
-#define GEN7_HS_DW6_URB_SEMAPHORE_ADDR__MASK 0x00000fff
-#define GEN7_HS_DW6_URB_SEMAPHORE_ADDR__SHIFT 0
-#define GEN7_HS_DW6_URB_SEMAPHORE_ADDR__SHR 6
-#define GEN75_HS_DW6_URB_SEMAPHORE_ADDR__MASK 0x00001fff
-#define GEN75_HS_DW6_URB_SEMAPHORE_ADDR__SHIFT 0
-#define GEN75_HS_DW6_URB_SEMAPHORE_ADDR__SHR 6
-
-
-
-
-#define GEN8_HS_DW2_HS_ENABLE (0x1 << 31)
-#define GEN8_HS_DW2_STATISTICS (0x1 << 29)
-#define GEN8_HS_DW2_MAX_THREADS__MASK 0x0001ff00
-#define GEN8_HS_DW2_MAX_THREADS__SHIFT 8
-#define GEN8_HS_DW2_INSTANCE_COUNT__MASK 0x0000000f
-#define GEN8_HS_DW2_INSTANCE_COUNT__SHIFT 0
-
-#define GEN8_HS_DW3_KERNEL_ADDR__MASK 0xffffffc0
-#define GEN8_HS_DW3_KERNEL_ADDR__SHIFT 6
-#define GEN8_HS_DW3_KERNEL_ADDR__SHR 6
-
-
-
-
-#define GEN8_HS_DW7_SPF (0x1 << 27)
-#define GEN8_HS_DW7_VME (0x1 << 26)
-#define GEN8_HS_DW7_ACCESS_UAV (0x1 << 25)
-#define GEN8_HS_DW7_INCLUDE_VERTEX_HANDLES (0x1 << 24)
-#define GEN8_HS_DW7_URB_GRF_START__MASK 0x00f80000
-#define GEN8_HS_DW7_URB_GRF_START__SHIFT 19
-#define GEN8_HS_DW7_URB_READ_LEN__MASK 0x0001f800
-#define GEN8_HS_DW7_URB_READ_LEN__SHIFT 11
-#define GEN8_HS_DW7_URB_READ_OFFSET__MASK 0x000003f0
-#define GEN8_HS_DW7_URB_READ_OFFSET__SHIFT 4
-
-
-#define GEN7_3DSTATE_TE__SIZE 4
-
-
-#define GEN7_TE_DW1_PARTITIONING__MASK 0x00003000
-#define GEN7_TE_DW1_PARTITIONING__SHIFT 12
-#define GEN7_TE_DW1_PARTITIONING_INTEGER (0x0 << 12)
-#define GEN7_TE_DW1_PARTITIONING_ODD_FRACTIONAL (0x1 << 12)
-#define GEN7_TE_DW1_PARTITIONING_EVEN_FRACTIONAL (0x2 << 12)
-#define GEN7_TE_DW1_OUTPUT_TOPO__MASK 0x00000300
-#define GEN7_TE_DW1_OUTPUT_TOPO__SHIFT 8
-#define GEN7_TE_DW1_OUTPUT_TOPO_POINT (0x0 << 8)
-#define GEN7_TE_DW1_OUTPUT_TOPO_LINE (0x1 << 8)
-#define GEN7_TE_DW1_OUTPUT_TOPO_TRI_CW (0x2 << 8)
-#define GEN7_TE_DW1_OUTPUT_TOPO_TRI_CCW (0x3 << 8)
-#define GEN7_TE_DW1_DOMAIN__MASK 0x00000030
-#define GEN7_TE_DW1_DOMAIN__SHIFT 4
-#define GEN7_TE_DW1_DOMAIN_QUAD (0x0 << 4)
-#define GEN7_TE_DW1_DOMAIN_TRI (0x1 << 4)
-#define GEN7_TE_DW1_DOMAIN_ISOLINE (0x2 << 4)
-#define GEN7_TE_DW1_MODE__MASK 0x00000006
-#define GEN7_TE_DW1_MODE__SHIFT 1
-#define GEN7_TE_DW1_MODE_HW (0x0 << 1)
-#define GEN7_TE_DW1_MODE_SW (0x1 << 1)
-#define GEN7_TE_DW1_TE_ENABLE (0x1 << 0)
-
-
-
-#define GEN7_3DSTATE_DS__SIZE 11
-
-
-#define GEN7_DS_DW1_KERNEL_ADDR__MASK 0xffffffc0
-#define GEN7_DS_DW1_KERNEL_ADDR__SHIFT 6
-#define GEN7_DS_DW1_KERNEL_ADDR__SHR 6
-
-
-
-#define GEN7_DS_DW4_URB_GRF_START__MASK 0x01f00000
-#define GEN7_DS_DW4_URB_GRF_START__SHIFT 20
-#define GEN7_DS_DW4_URB_READ_LEN__MASK 0x0003f800
-#define GEN7_DS_DW4_URB_READ_LEN__SHIFT 11
-#define GEN7_DS_DW4_URB_READ_OFFSET__MASK 0x000003f0
-#define GEN7_DS_DW4_URB_READ_OFFSET__SHIFT 4
-
-#define GEN7_DS_DW5_MAX_THREADS__MASK 0xfe000000
-#define GEN7_DS_DW5_MAX_THREADS__SHIFT 25
-#define GEN75_DS_DW5_MAX_THREADS__MASK 0x3fe00000
-#define GEN75_DS_DW5_MAX_THREADS__SHIFT 21
-#define GEN7_DS_DW5_STATISTICS (0x1 << 10)
-#define GEN7_DS_DW5_COMPUTE_W (0x1 << 2)
-#define GEN7_DS_DW5_CACHE_DISABLE (0x1 << 1)
-#define GEN7_DS_DW5_DS_ENABLE (0x1 << 0)
-
-
-
-#define GEN8_DS_DW1_KERNEL_ADDR__MASK 0xffffffc0
-#define GEN8_DS_DW1_KERNEL_ADDR__SHIFT 6
-#define GEN8_DS_DW1_KERNEL_ADDR__SHR 6
-
-
-
-
-
-#define GEN8_DS_DW6_URB_GRF_START__MASK 0x01f00000
-#define GEN8_DS_DW6_URB_GRF_START__SHIFT 20
-#define GEN8_DS_DW6_URB_READ_LEN__MASK 0x0003f800
-#define GEN8_DS_DW6_URB_READ_LEN__SHIFT 11
-#define GEN8_DS_DW6_URB_READ_OFFSET__MASK 0x000003f0
-#define GEN8_DS_DW6_URB_READ_OFFSET__SHIFT 4
-
-#define GEN8_DS_DW7_MAX_THREADS__MASK 0x3fe00000
-#define GEN8_DS_DW7_MAX_THREADS__SHIFT 21
-#define GEN8_DS_DW7_STATISTICS (0x1 << 10)
-#define GEN8_DS_DW7_SIMD8_ENABLE (0x1 << 3)
-#define GEN8_DS_DW7_COMPUTE_W (0x1 << 2)
-#define GEN8_DS_DW7_CACHE_DISABLE (0x1 << 1)
-#define GEN8_DS_DW7_DS_ENABLE (0x1 << 0)
-
-#define GEN8_DS_DW8_VUE_OUT_READ_OFFSET__MASK 0x07e00000
-#define GEN8_DS_DW8_VUE_OUT_READ_OFFSET__SHIFT 21
-#define GEN8_DS_DW8_VUE_OUT_LEN__MASK 0x001f0000
-#define GEN8_DS_DW8_VUE_OUT_LEN__SHIFT 16
-#define GEN8_DS_DW8_UCP_CLIP_ENABLES__MASK 0x0000ff00
-#define GEN8_DS_DW8_UCP_CLIP_ENABLES__SHIFT 8
-#define GEN8_DS_DW8_UCP_CULL_ENABLES__MASK 0x000000ff
-#define GEN8_DS_DW8_UCP_CULL_ENABLES__SHIFT 0
-
-
-
-#define GEN6_3DSTATE_GS__SIZE 10
-
-
-#define GEN6_GS_DW1_KERNEL_ADDR__MASK 0xffffffc0
-#define GEN6_GS_DW1_KERNEL_ADDR__SHIFT 6
-#define GEN6_GS_DW1_KERNEL_ADDR__SHR 6
-
-
-
-#define GEN6_GS_DW4_URB_READ_LEN__MASK 0x0001f800
-#define GEN6_GS_DW4_URB_READ_LEN__SHIFT 11
-#define GEN6_GS_DW4_URB_READ_OFFSET__MASK 0x000003f0
-#define GEN6_GS_DW4_URB_READ_OFFSET__SHIFT 4
-#define GEN6_GS_DW4_URB_GRF_START__MASK 0x0000000f
-#define GEN6_GS_DW4_URB_GRF_START__SHIFT 0
-
-#define GEN6_GS_DW5_MAX_THREADS__MASK 0xfe000000
-#define GEN6_GS_DW5_MAX_THREADS__SHIFT 25
-#define GEN6_GS_DW5_STATISTICS (0x1 << 10)
-#define GEN6_GS_DW5_SO_STATISTICS (0x1 << 9)
-#define GEN6_GS_DW5_RENDER_ENABLE (0x1 << 8)
-
-#define GEN6_GS_DW6_REORDER_LEADING_ENABLE (0x1 << 30)
-#define GEN6_GS_DW6_DISCARD_ADJACENCY (0x1 << 29)
-#define GEN6_GS_DW6_SVBI_PAYLOAD_ENABLE (0x1 << 28)
-#define GEN6_GS_DW6_SVBI_POST_INC_ENABLE (0x1 << 27)
-#define GEN6_GS_DW6_SVBI_POST_INC_VAL__MASK 0x03ff0000
-#define GEN6_GS_DW6_SVBI_POST_INC_VAL__SHIFT 16
-#define GEN6_GS_DW6_GS_ENABLE (0x1 << 15)
-
-
-
-#define GEN7_GS_DW1_KERNEL_ADDR__MASK 0xffffffc0
-#define GEN7_GS_DW1_KERNEL_ADDR__SHIFT 6
-#define GEN7_GS_DW1_KERNEL_ADDR__SHR 6
-
-
-
-#define GEN7_GS_DW4_OUTPUT_SIZE__MASK 0x1f800000
-#define GEN7_GS_DW4_OUTPUT_SIZE__SHIFT 23
-#define GEN7_GS_DW4_OUTPUT_TOPO__MASK 0x007e0000
-#define GEN7_GS_DW4_OUTPUT_TOPO__SHIFT 17
-#define GEN7_GS_DW4_URB_READ_LEN__MASK 0x0001f800
-#define GEN7_GS_DW4_URB_READ_LEN__SHIFT 11
-#define GEN7_GS_DW4_INCLUDE_VERTEX_HANDLES (0x1 << 10)
-#define GEN7_GS_DW4_URB_READ_OFFSET__MASK 0x000003f0
-#define GEN7_GS_DW4_URB_READ_OFFSET__SHIFT 4
-#define GEN7_GS_DW4_URB_GRF_START__MASK 0x0000000f
-#define GEN7_GS_DW4_URB_GRF_START__SHIFT 0
-
-#define GEN7_GS_DW5_MAX_THREADS__MASK 0xfe000000
-#define GEN7_GS_DW5_MAX_THREADS__SHIFT 25
-#define GEN7_GS_DW5_GSCTRL__MASK 0x01000000
-#define GEN7_GS_DW5_GSCTRL__SHIFT 24
-#define GEN7_GS_DW5_GSCTRL_CUT (0x0 << 24)
-#define GEN7_GS_DW5_GSCTRL_SID (0x1 << 24)
-#define GEN75_GS_DW5_MAX_THREADS__MASK 0xff000000
-#define GEN75_GS_DW5_MAX_THREADS__SHIFT 24
-#define GEN7_GS_DW5_CONTROL_DATA_HEADER_SIZE__MASK 0x00f00000
-#define GEN7_GS_DW5_CONTROL_DATA_HEADER_SIZE__SHIFT 20
-#define GEN7_GS_DW5_INSTANCE_CONTROL__MASK 0x000f8000
-#define GEN7_GS_DW5_INSTANCE_CONTROL__SHIFT 15
-#define GEN7_GS_DW5_DEFAULT_STREAM_ID__MASK 0x00006000
-#define GEN7_GS_DW5_DEFAULT_STREAM_ID__SHIFT 13
-#define GEN7_GS_DW5_DISPATCH_MODE__MASK 0x00001800
-#define GEN7_GS_DW5_DISPATCH_MODE__SHIFT 11
-#define GEN7_GS_DW5_DISPATCH_MODE_SINGLE (0x0 << 11)
-#define GEN7_GS_DW5_DISPATCH_MODE_DUAL_INSTANCE (0x1 << 11)
-#define GEN7_GS_DW5_DISPATCH_MODE_DUAL_OBJECT (0x2 << 11)
-#define GEN7_GS_DW5_STATISTICS (0x1 << 10)
-#define GEN7_GS_DW5_INVOCATION_INCR__MASK 0x000003e0
-#define GEN7_GS_DW5_INVOCATION_INCR__SHIFT 5
-#define GEN7_GS_DW5_INCLUDE_PRIMITIVE_ID (0x1 << 4)
-#define GEN7_GS_DW5_HINT (0x1 << 3)
-#define GEN7_GS_DW5_REORDER_LEADING_ENABLE (0x1 << 2)
-#define GEN75_GS_DW5_REORDER_MODE__MASK 0x00000004
-#define GEN75_GS_DW5_REORDER_MODE__SHIFT 2
-#define GEN7_GS_DW5_DISCARD_ADJACENCY (0x1 << 1)
-#define GEN7_GS_DW5_GS_ENABLE (0x1 << 0)
-
-#define GEN75_GS_DW6_GSCTRL__MASK 0x80000000
-#define GEN75_GS_DW6_GSCTRL__SHIFT 31
-#define GEN75_GS_DW6_GSCTRL_CUT (0x0 << 31)
-#define GEN75_GS_DW6_GSCTRL_SID (0x1 << 31)
-#define GEN7_GS_DW6_URB_SEMAPHORE_ADDR__MASK 0x00000fff
-#define GEN7_GS_DW6_URB_SEMAPHORE_ADDR__SHIFT 0
-#define GEN7_GS_DW6_URB_SEMAPHORE_ADDR__SHR 6
-#define GEN75_GS_DW6_URB_SEMAPHORE_ADDR__MASK 0x00001fff
-#define GEN75_GS_DW6_URB_SEMAPHORE_ADDR__SHIFT 0
-#define GEN75_GS_DW6_URB_SEMAPHORE_ADDR__SHR 6
-
-
-
-#define GEN8_GS_DW1_KERNEL_ADDR__MASK 0xffffffc0
-#define GEN8_GS_DW1_KERNEL_ADDR__SHIFT 6
-#define GEN8_GS_DW1_KERNEL_ADDR__SHR 6
-
-
-#define GEN8_GS_DW3_EXPECTED_VERTEX_COUNT__MASK 0x0000003f
-#define GEN8_GS_DW3_EXPECTED_VERTEX_COUNT__SHIFT 0
-
-
-
-#define GEN8_GS_DW6_OUTPUT_SIZE__MASK 0x1f800000
-#define GEN8_GS_DW6_OUTPUT_SIZE__SHIFT 23
-#define GEN8_GS_DW6_OUTPUT_TOPO__MASK 0x007e0000
-#define GEN8_GS_DW6_OUTPUT_TOPO__SHIFT 17
-#define GEN8_GS_DW6_URB_READ_LEN__MASK 0x0001f800
-#define GEN8_GS_DW6_URB_READ_LEN__SHIFT 11
-#define GEN8_GS_DW6_INCLUDE_VERTEX_HANDLES (0x1 << 10)
-#define GEN8_GS_DW6_URB_READ_OFFSET__MASK 0x000003f0
-#define GEN8_GS_DW6_URB_READ_OFFSET__SHIFT 4
-#define GEN8_GS_DW6_URB_GRF_START__MASK 0x0000000f
-#define GEN8_GS_DW6_URB_GRF_START__SHIFT 0
-
-#define GEN8_GS_DW7_MAX_THREADS__MASK 0xff000000
-#define GEN8_GS_DW7_MAX_THREADS__SHIFT 24
-#define GEN8_GS_DW7_CONTROL_DATA_HEADER_SIZE__MASK 0x00f00000
-#define GEN8_GS_DW7_CONTROL_DATA_HEADER_SIZE__SHIFT 20
-#define GEN8_GS_DW7_INSTANCE_CONTROL__MASK 0x000f8000
-#define GEN8_GS_DW7_INSTANCE_CONTROL__SHIFT 15
-#define GEN8_GS_DW7_DEFAULT_STREAM_ID__MASK 0x00006000
-#define GEN8_GS_DW7_DEFAULT_STREAM_ID__SHIFT 13
-#define GEN8_GS_DW7_DISPATCH_MODE__MASK 0x00001800
-#define GEN8_GS_DW7_DISPATCH_MODE__SHIFT 11
-#define GEN8_GS_DW7_DISPATCH_MODE_SINGLE (0x0 << 11)
-#define GEN8_GS_DW7_DISPATCH_MODE_DUAL_INSTANCE (0x1 << 11)
-#define GEN8_GS_DW7_DISPATCH_MODE_DUAL_OBJECT (0x2 << 11)
-#define GEN8_GS_DW7_STATISTICS (0x1 << 10)
-#define GEN8_GS_DW7_INVOCATION_INCR__MASK 0x000003e0
-#define GEN8_GS_DW7_INVOCATION_INCR__SHIFT 5
-#define GEN8_GS_DW7_INCLUDE_PRIMITIVE_ID (0x1 << 4)
-#define GEN8_GS_DW7_HINT (0x1 << 3)
-#define GEN8_GS_DW7_REORDER_MODE__MASK 0x00000004
-#define GEN8_GS_DW7_REORDER_MODE__SHIFT 2
-#define GEN8_GS_DW7_DISCARD_ADJACENCY (0x1 << 1)
-#define GEN8_GS_DW7_GS_ENABLE (0x1 << 0)
-
-#define GEN8_GS_DW8_GSCTRL__MASK 0x80000000
-#define GEN8_GS_DW8_GSCTRL__SHIFT 31
-#define GEN8_GS_DW8_GSCTRL_CUT (0x0 << 31)
-#define GEN8_GS_DW8_GSCTRL_SID (0x1 << 31)
-#define GEN8_GS_DW8_STATIC_OUTPUT (0x1 << 30)
-#define GEN8_GS_DW8_STATIC_OUTPUT_VERTEX_COUNT__MASK 0x07ff0000
-#define GEN8_GS_DW8_STATIC_OUTPUT_VERTEX_COUNT__SHIFT 16
-#define GEN9_GS_DW8_MAX_THREADS__MASK 0x000001ff
-#define GEN9_GS_DW8_MAX_THREADS__SHIFT 0
-
-#define GEN8_GS_DW9_VUE_OUT_READ_OFFSET__MASK 0x07e00000
-#define GEN8_GS_DW9_VUE_OUT_READ_OFFSET__SHIFT 21
-#define GEN8_GS_DW9_VUE_OUT_LEN__MASK 0x001f0000
-#define GEN8_GS_DW9_VUE_OUT_LEN__SHIFT 16
-#define GEN8_GS_DW9_UCP_CLIP_ENABLES__MASK 0x0000ff00
-#define GEN8_GS_DW9_UCP_CLIP_ENABLES__SHIFT 8
-#define GEN8_GS_DW9_UCP_CULL_ENABLES__MASK 0x000000ff
-#define GEN8_GS_DW9_UCP_CULL_ENABLES__SHIFT 0
-
-#define GEN7_3DSTATE_STREAMOUT__SIZE 5
-
-
-#define GEN7_SO_DW1_SO_ENABLE (0x1 << 31)
-#define GEN7_SO_DW1_RENDER_DISABLE (0x1 << 30)
-#define GEN7_SO_DW1_RENDER_STREAM_SELECT__MASK 0x18000000
-#define GEN7_SO_DW1_RENDER_STREAM_SELECT__SHIFT 27
-#define GEN7_SO_DW1_REORDER_MODE__MASK 0x04000000
-#define GEN7_SO_DW1_REORDER_MODE__SHIFT 26
-#define GEN7_SO_DW1_STATISTICS (0x1 << 25)
-#define GEN8_SO_DW1_FORCE_RENDERING__MASK 0x01800000
-#define GEN8_SO_DW1_FORCE_RENDERING__SHIFT 23
-#define GEN8_SO_DW1_FORCE_RENDERING_NORMAL (0x0 << 23)
-#define GEN8_SO_DW1_FORCE_RENDERING_OFF (0x2 << 23)
-#define GEN8_SO_DW1_FORCE_RENDERING_ON (0x3 << 23)
-#define GEN7_SO_DW1_BUFFER_ENABLES__MASK 0x00000f00
-#define GEN7_SO_DW1_BUFFER_ENABLES__SHIFT 8
-
-#define GEN7_SO_DW2_STREAM3_READ_OFFSET__MASK 0x20000000
-#define GEN7_SO_DW2_STREAM3_READ_OFFSET__SHIFT 29
-#define GEN7_SO_DW2_STREAM3_READ_LEN__MASK 0x1f000000
-#define GEN7_SO_DW2_STREAM3_READ_LEN__SHIFT 24
-#define GEN7_SO_DW2_STREAM2_READ_OFFSET__MASK 0x00200000
-#define GEN7_SO_DW2_STREAM2_READ_OFFSET__SHIFT 21
-#define GEN7_SO_DW2_STREAM2_READ_LEN__MASK 0x001f0000
-#define GEN7_SO_DW2_STREAM2_READ_LEN__SHIFT 16
-#define GEN7_SO_DW2_STREAM1_READ_OFFSET__MASK 0x00002000
-#define GEN7_SO_DW2_STREAM1_READ_OFFSET__SHIFT 13
-#define GEN7_SO_DW2_STREAM1_READ_LEN__MASK 0x00001f00
-#define GEN7_SO_DW2_STREAM1_READ_LEN__SHIFT 8
-#define GEN7_SO_DW2_STREAM0_READ_OFFSET__MASK 0x00000020
-#define GEN7_SO_DW2_STREAM0_READ_OFFSET__SHIFT 5
-#define GEN7_SO_DW2_STREAM0_READ_LEN__MASK 0x0000001f
-#define GEN7_SO_DW2_STREAM0_READ_LEN__SHIFT 0
-
-#define GEN8_SO_DW3_BUFFER1_PITCH__MASK 0x0fff0000
-#define GEN8_SO_DW3_BUFFER1_PITCH__SHIFT 16
-#define GEN8_SO_DW3_BUFFER0_PITCH__MASK 0x00000fff
-#define GEN8_SO_DW3_BUFFER0_PITCH__SHIFT 0
-
-#define GEN8_SO_DW4_BUFFER3_PITCH__MASK 0x0fff0000
-#define GEN8_SO_DW4_BUFFER3_PITCH__SHIFT 16
-#define GEN8_SO_DW4_BUFFER2_PITCH__MASK 0x00000fff
-#define GEN8_SO_DW4_BUFFER2_PITCH__SHIFT 0
-
-#define GEN7_3DSTATE_SO_DECL_LIST__SIZE 259
-
-
-#define GEN7_SO_DECL_DW1_STREAM3_BUFFER_SELECTS__MASK 0x0000f000
-#define GEN7_SO_DECL_DW1_STREAM3_BUFFER_SELECTS__SHIFT 12
-#define GEN7_SO_DECL_DW1_STREAM2_BUFFER_SELECTS__MASK 0x00000f00
-#define GEN7_SO_DECL_DW1_STREAM2_BUFFER_SELECTS__SHIFT 8
-#define GEN7_SO_DECL_DW1_STREAM1_BUFFER_SELECTS__MASK 0x000000f0
-#define GEN7_SO_DECL_DW1_STREAM1_BUFFER_SELECTS__SHIFT 4
-#define GEN7_SO_DECL_DW1_STREAM0_BUFFER_SELECTS__MASK 0x0000000f
-#define GEN7_SO_DECL_DW1_STREAM0_BUFFER_SELECTS__SHIFT 0
-
-#define GEN7_SO_DECL_DW2_STREAM3_ENTRY_COUNT__MASK 0xff000000
-#define GEN7_SO_DECL_DW2_STREAM3_ENTRY_COUNT__SHIFT 24
-#define GEN7_SO_DECL_DW2_STREAM2_ENTRY_COUNT__MASK 0x00ff0000
-#define GEN7_SO_DECL_DW2_STREAM2_ENTRY_COUNT__SHIFT 16
-#define GEN7_SO_DECL_DW2_STREAM1_ENTRY_COUNT__MASK 0x0000ff00
-#define GEN7_SO_DECL_DW2_STREAM1_ENTRY_COUNT__SHIFT 8
-#define GEN7_SO_DECL_DW2_STREAM0_ENTRY_COUNT__MASK 0x000000ff
-#define GEN7_SO_DECL_DW2_STREAM0_ENTRY_COUNT__SHIFT 0
-
-#define GEN7_SO_DECL_HIGH__MASK 0xffff0000
-#define GEN7_SO_DECL_HIGH__SHIFT 16
-#define GEN7_SO_DECL_OUTPUT_SLOT__MASK 0x00003000
-#define GEN7_SO_DECL_OUTPUT_SLOT__SHIFT 12
-#define GEN7_SO_DECL_HOLE_FLAG (0x1 << 11)
-#define GEN7_SO_DECL_REG_INDEX__MASK 0x000003f0
-#define GEN7_SO_DECL_REG_INDEX__SHIFT 4
-#define GEN7_SO_DECL_COMPONENT_MASK__MASK 0x0000000f
-#define GEN7_SO_DECL_COMPONENT_MASK__SHIFT 0
-
-#define GEN7_3DSTATE_SO_BUFFER__SIZE 8
-
-
-#define GEN8_SO_BUF_DW1_ENABLE (0x1 << 31)
-#define GEN7_SO_BUF_DW1_INDEX__MASK 0x60000000
-#define GEN7_SO_BUF_DW1_INDEX__SHIFT 29
-#define GEN7_SO_BUF_DW1_MOCS__MASK 0x1e000000
-#define GEN7_SO_BUF_DW1_MOCS__SHIFT 25
-#define GEN8_SO_BUF_DW1_MOCS__MASK 0x1fc00000
-#define GEN8_SO_BUF_DW1_MOCS__SHIFT 22
-#define GEN8_SO_BUF_DW1_OFFSET_WRITE_ENABLE (0x1 << 21)
-#define GEN8_SO_BUF_DW1_OFFSET_ENABLE (0x1 << 20)
-#define GEN7_SO_BUF_DW1_PITCH__MASK 0x00000fff
-#define GEN7_SO_BUF_DW1_PITCH__SHIFT 0
-
-#define GEN7_SO_BUF_DW2_START_ADDR__MASK 0xfffffffc
-#define GEN7_SO_BUF_DW2_START_ADDR__SHIFT 2
-#define GEN7_SO_BUF_DW2_START_ADDR__SHR 2
-
-#define GEN7_SO_BUF_DW3_END_ADDR__MASK 0xfffffffc
-#define GEN7_SO_BUF_DW3_END_ADDR__SHIFT 2
-#define GEN7_SO_BUF_DW3_END_ADDR__SHR 2
-
-#define GEN8_SO_BUF_DW2_ADDR__MASK 0xfffffffc
-#define GEN8_SO_BUF_DW2_ADDR__SHIFT 2
-#define GEN8_SO_BUF_DW2_ADDR__SHR 2
-
-
-
-#define GEN8_SO_BUF_DW5_OFFSET_ADDR_ADDR__MASK 0xfffffffc
-#define GEN8_SO_BUF_DW5_OFFSET_ADDR_ADDR__SHIFT 2
-#define GEN8_SO_BUF_DW5_OFFSET_ADDR_ADDR__SHR 2
-
-
-
-#define GEN6_3DSTATE_CLIP__SIZE 4
-
-
-#define GEN7_CLIP_DW1_FRONT_WINDING__MASK 0x00100000
-#define GEN7_CLIP_DW1_FRONT_WINDING__SHIFT 20
-#define GEN8_CLIP_DW1_FORCE_UCP_CULL_ENABLES (0x1 << 20)
-#define GEN7_CLIP_DW1_SUBPIXEL__MASK 0x00080000
-#define GEN7_CLIP_DW1_SUBPIXEL__SHIFT 19
-#define GEN7_CLIP_DW1_SUBPIXEL_8BITS (0x0 << 19)
-#define GEN7_CLIP_DW1_SUBPIXEL_4BITS (0x1 << 19)
-#define GEN7_CLIP_DW1_EARLY_CULL_ENABLE (0x1 << 18)
-#define GEN7_CLIP_DW1_CULL_MODE__MASK 0x00030000
-#define GEN7_CLIP_DW1_CULL_MODE__SHIFT 16
-#define GEN8_CLIP_DW1_FORCE_UCP_CLIP_ENABLES (0x1 << 17)
-#define GEN8_CLIP_DW1_FORCE_CLIP_MODE (0x1 << 16)
-#define GEN6_CLIP_DW1_STATISTICS (0x1 << 10)
-#define GEN6_CLIP_DW1_UCP_CULL_ENABLES__MASK 0x000000ff
-#define GEN6_CLIP_DW1_UCP_CULL_ENABLES__SHIFT 0
-
-#define GEN6_CLIP_DW2_CLIP_ENABLE (0x1 << 31)
-#define GEN6_CLIP_DW2_APIMODE__MASK 0x40000000
-#define GEN6_CLIP_DW2_APIMODE__SHIFT 30
-#define GEN6_CLIP_DW2_APIMODE_OGL (0x0 << 30)
-#define GEN6_CLIP_DW2_APIMODE_D3D (0x1 << 30)
-#define GEN6_CLIP_DW2_XY_TEST_ENABLE (0x1 << 28)
-#define GEN6_CLIP_DW2_Z_TEST_ENABLE (0x1 << 27)
-#define GEN6_CLIP_DW2_GB_TEST_ENABLE (0x1 << 26)
-#define GEN6_CLIP_DW2_UCP_CLIP_ENABLES__MASK 0x00ff0000
-#define GEN6_CLIP_DW2_UCP_CLIP_ENABLES__SHIFT 16
-#define GEN6_CLIP_DW2_CLIP_MODE__MASK 0x0000e000
-#define GEN6_CLIP_DW2_CLIP_MODE__SHIFT 13
-#define GEN6_CLIP_DW2_PERSPECTIVE_DIVIDE_DISABLE (0x1 << 9)
-#define GEN6_CLIP_DW2_NONPERSPECTIVE_BARYCENTRIC_ENABLE (0x1 << 8)
-#define GEN6_CLIP_DW2_TRI_PROVOKE__MASK 0x00000030
-#define GEN6_CLIP_DW2_TRI_PROVOKE__SHIFT 4
-#define GEN6_CLIP_DW2_LINE_PROVOKE__MASK 0x0000000c
-#define GEN6_CLIP_DW2_LINE_PROVOKE__SHIFT 2
-#define GEN6_CLIP_DW2_TRIFAN_PROVOKE__MASK 0x00000003
-#define GEN6_CLIP_DW2_TRIFAN_PROVOKE__SHIFT 0
-
-#define GEN6_CLIP_DW3_MIN_POINT_WIDTH__MASK 0x0ffe0000
-#define GEN6_CLIP_DW3_MIN_POINT_WIDTH__SHIFT 17
-#define GEN6_CLIP_DW3_MIN_POINT_WIDTH__RADIX 3
-#define GEN6_CLIP_DW3_MAX_POINT_WIDTH__MASK 0x0001ffc0
-#define GEN6_CLIP_DW3_MAX_POINT_WIDTH__SHIFT 6
-#define GEN6_CLIP_DW3_MAX_POINT_WIDTH__RADIX 3
-#define GEN6_CLIP_DW3_FORCE_RTAINDEX_ZERO (0x1 << 5)
-#define GEN6_CLIP_DW3_MAX_VPINDEX__MASK 0x0000000f
-#define GEN6_CLIP_DW3_MAX_VPINDEX__SHIFT 0
-
-#define GEN6_3DSTATE_SF_DW1_DW3__SIZE 3
-
-#define GEN7_SF_DW1_DEPTH_FORMAT__MASK 0x00007000
-#define GEN7_SF_DW1_DEPTH_FORMAT__SHIFT 12
-#define GEN9_SF_DW1_LINE_WIDTH__MASK 0x3ffff000
-#define GEN9_SF_DW1_LINE_WIDTH__SHIFT 12
-#define GEN9_SF_DW1_LINE_WIDTH__RADIX 7
-#define GEN7_SF_DW1_LEGACY_DEPTH_OFFSET (0x1 << 11)
-#define GEN7_SF_DW1_STATISTICS (0x1 << 10)
-#define GEN7_SF_DW1_DEPTH_OFFSET_SOLID (0x1 << 9)
-#define GEN7_SF_DW1_DEPTH_OFFSET_WIREFRAME (0x1 << 8)
-#define GEN7_SF_DW1_DEPTH_OFFSET_POINT (0x1 << 7)
-#define GEN7_SF_DW1_FILL_MODE_FRONT__MASK 0x00000060
-#define GEN7_SF_DW1_FILL_MODE_FRONT__SHIFT 5
-#define GEN7_SF_DW1_FILL_MODE_BACK__MASK 0x00000018
-#define GEN7_SF_DW1_FILL_MODE_BACK__SHIFT 3
-#define GEN7_SF_DW1_VIEWPORT_TRANSFORM (0x1 << 1)
-#define GEN7_SF_DW1_FRONT_WINDING__MASK 0x00000001
-#define GEN7_SF_DW1_FRONT_WINDING__SHIFT 0
-
-#define GEN7_SF_DW2_AA_LINE_ENABLE (0x1 << 31)
-#define GEN7_SF_DW2_CULL_MODE__MASK 0x60000000
-#define GEN7_SF_DW2_CULL_MODE__SHIFT 29
-#define GEN7_SF_DW2_LINE_WIDTH__MASK 0x0ffc0000
-#define GEN7_SF_DW2_LINE_WIDTH__SHIFT 18
-#define GEN7_SF_DW2_LINE_WIDTH__RADIX 7
-#define GEN7_SF_DW2_AA_LINE_CAP__MASK 0x00030000
-#define GEN7_SF_DW2_AA_LINE_CAP__SHIFT 16
-#define GEN7_SF_DW2_AA_LINE_CAP_0_5 (0x0 << 16)
-#define GEN7_SF_DW2_AA_LINE_CAP_1_0 (0x1 << 16)
-#define GEN7_SF_DW2_AA_LINE_CAP_2_0 (0x2 << 16)
-#define GEN7_SF_DW2_AA_LINE_CAP_4_0 (0x3 << 16)
-#define GEN75_SF_DW2_LINE_STIPPLE_ENABLE (0x1 << 14)
-#define GEN7_SF_DW2_SCISSOR_ENABLE (0x1 << 11)
-#define GEN7_SF_DW2_MSRASTMODE__MASK 0x00000300
-#define GEN7_SF_DW2_MSRASTMODE__SHIFT 8
-
-#define GEN7_SF_DW3_LINE_LAST_PIXEL_ENABLE (0x1 << 31)
-#define GEN7_SF_DW3_TRI_PROVOKE__MASK 0x60000000
-#define GEN7_SF_DW3_TRI_PROVOKE__SHIFT 29
-#define GEN7_SF_DW3_LINE_PROVOKE__MASK 0x18000000
-#define GEN7_SF_DW3_LINE_PROVOKE__SHIFT 27
-#define GEN7_SF_DW3_TRIFAN_PROVOKE__MASK 0x06000000
-#define GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT 25
-#define GEN7_SF_DW3_TRUE_AA_LINE_DISTANCE (0x1 << 14)
-#define GEN8_SF_DW3_SMOOTH_POINT_ENABLE (0x1 << 13)
-#define GEN7_SF_DW3_SUBPIXEL__MASK 0x00001000
-#define GEN7_SF_DW3_SUBPIXEL__SHIFT 12
-#define GEN7_SF_DW3_SUBPIXEL_8BITS (0x0 << 12)
-#define GEN7_SF_DW3_SUBPIXEL_4BITS (0x1 << 12)
-#define GEN7_SF_DW3_USE_POINT_WIDTH (0x1 << 11)
-#define GEN7_SF_DW3_POINT_WIDTH__MASK 0x000007ff
-#define GEN7_SF_DW3_POINT_WIDTH__SHIFT 0
-#define GEN7_SF_DW3_POINT_WIDTH__RADIX 3
-
-#define GEN7_3DSTATE_SBE_DW1__SIZE 13
-
-#define GEN8_SBE_DW1_FORCE_URB_READ_LEN (0x1 << 29)
-#define GEN8_SBE_DW1_FORCE_URB_READ_OFFSET (0x1 << 28)
-#define GEN7_SBE_DW1_ATTR_SWIZZLE__MASK 0x10000000
-#define GEN7_SBE_DW1_ATTR_SWIZZLE__SHIFT 28
-#define GEN7_SBE_DW1_ATTR_SWIZZLE_0_15 (0x0 << 28)
-#define GEN7_SBE_DW1_ATTR_SWIZZLE_16_31 (0x1 << 28)
-#define GEN7_SBE_DW1_ATTR_COUNT__MASK 0x0fc00000
-#define GEN7_SBE_DW1_ATTR_COUNT__SHIFT 22
-#define GEN7_SBE_DW1_ATTR_SWIZZLE_ENABLE (0x1 << 21)
-#define GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD__MASK 0x00100000
-#define GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD__SHIFT 20
-#define GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD_UPPERLEFT (0x0 << 20)
-#define GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD_LOWERLEFT (0x1 << 20)
-#define GEN8_SBE_DW1_PID_OVERRIDE_W (0x1 << 19)
-#define GEN8_SBE_DW1_PID_OVERRIDE_Z (0x1 << 18)
-#define GEN8_SBE_DW1_PID_OVERRIDE_Y (0x1 << 17)
-#define GEN8_SBE_DW1_PID_OVERRIDE_X (0x1 << 16)
-#define GEN7_SBE_DW1_URB_READ_LEN__MASK 0x0000f800
-#define GEN7_SBE_DW1_URB_READ_LEN__SHIFT 11
-#define GEN7_SBE_DW1_URB_READ_OFFSET__MASK 0x000003f0
-#define GEN7_SBE_DW1_URB_READ_OFFSET__SHIFT 4
-#define GEN8_SBE_DW1_URB_READ_OFFSET__MASK 0x000007e0
-#define GEN8_SBE_DW1_URB_READ_OFFSET__SHIFT 5
-#define GEN8_SBE_DW1_PID_OVERRIDE_ATTR__MASK 0x0000001f
-#define GEN8_SBE_DW1_PID_OVERRIDE_ATTR__SHIFT 0
-
-#define GEN8_3DSTATE_SBE_SWIZ_DW1_DW8__SIZE 8
-
-#define GEN8_SBE_SWIZ_HIGH__MASK 0xffff0000
-#define GEN8_SBE_SWIZ_HIGH__SHIFT 16
-#define GEN8_SBE_SWIZ_CONST_OVERRIDE_W (0x1 << 15)
-#define GEN8_SBE_SWIZ_CONST_OVERRIDE_Z (0x1 << 14)
-#define GEN8_SBE_SWIZ_CONST_OVERRIDE_Y (0x1 << 13)
-#define GEN8_SBE_SWIZ_CONST_OVERRIDE_X (0x1 << 12)
-#define GEN8_SBE_SWIZ_SWIZZLE_CONTROL (0x1 << 11)
-#define GEN8_SBE_SWIZ_CONST__MASK 0x00000600
-#define GEN8_SBE_SWIZ_CONST__SHIFT 9
-#define GEN8_SBE_SWIZ_CONST_0000 (0x0 << 9)
-#define GEN8_SBE_SWIZ_CONST_0001_FLOAT (0x1 << 9)
-#define GEN8_SBE_SWIZ_CONST_1111_FLOAT (0x2 << 9)
-#define GEN8_SBE_SWIZ_CONST_PRIM_ID (0x3 << 9)
-#define GEN8_SBE_SWIZ_SWIZZLE_SELECT__MASK 0x000000c0
-#define GEN8_SBE_SWIZ_SWIZZLE_SELECT__SHIFT 6
-#define GEN8_SBE_SWIZ_SRC_ATTR__MASK 0x0000001f
-#define GEN8_SBE_SWIZ_SRC_ATTR__SHIFT 0
-
-#define GEN6_3DSTATE_SF__SIZE 20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-#define GEN7_3DSTATE_SBE__SIZE 14
-
-
-
-
-
-
-
-
-
-
-
-
-#define GEN9_SBE_DW_ACTIVE_COMPONENT__MASK 0x00000003
-#define GEN9_SBE_DW_ACTIVE_COMPONENT__SHIFT 0
-#define GEN9_SBE_DW_ACTIVE_COMPONENT_NONE 0x0
-#define GEN9_SBE_DW_ACTIVE_COMPONENT_XY 0x1
-#define GEN9_SBE_DW_ACTIVE_COMPONENT_XYZ 0x2
-#define GEN9_SBE_DW_ACTIVE_COMPONENT_XYZW 0x3
-
-#define GEN8_3DSTATE_SBE_SWIZ__SIZE 11
-
-
-
-
-#define GEN8_3DSTATE_RASTER__SIZE 5
-
-
-#define GEN9_RASTER_DW1_Z_TEST_FAR_ENABLE (0x1 << 26)
-#define GEN8_RASTER_DW1_API__MASK 0x00c00000
-#define GEN8_RASTER_DW1_API__SHIFT 22
-#define GEN8_RASTER_DW1_API_DX9_OGL (0x0 << 22)
-#define GEN8_RASTER_DW1_API_DX10 (0x1 << 22)
-#define GEN8_RASTER_DW1_API_DX10_1 (0x2 << 22)
-#define GEN8_RASTER_DW1_FRONT_WINDING__MASK 0x00200000
-#define GEN8_RASTER_DW1_FRONT_WINDING__SHIFT 21
-#define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT__MASK 0x001c0000
-#define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT__SHIFT 18
-#define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT_NUMRASTSAMPLES_0 (0x0 << 18)
-#define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT_NUMRASTSAMPLES_1 (0x1 << 18)
-#define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT_NUMRASTSAMPLES_2 (0x2 << 18)
-#define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT_NUMRASTSAMPLES_4 (0x3 << 18)
-#define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT_NUMRASTSAMPLES_8 (0x4 << 18)
-#define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT_NUMRASTSAMPLES_16 (0x5 << 18)
-#define GEN8_RASTER_DW1_CULL_MODE__MASK 0x00030000
-#define GEN8_RASTER_DW1_CULL_MODE__SHIFT 16
-#define GEN8_RASTER_DW1_FORCE_MULTISAMPLE_ENABLE (0x1 << 14)
-#define GEN8_RASTER_DW1_SMOOTH_POINT_ENABLE (0x1 << 13)
-#define GEN8_RASTER_DW1_DX_MULTISAMPLE_ENABLE (0x1 << 12)
-#define GEN8_RASTER_DW1_DX_MSRASTMODE__MASK 0x00000c00
-#define GEN8_RASTER_DW1_DX_MSRASTMODE__SHIFT 10
-#define GEN8_RASTER_DW1_DEPTH_OFFSET_SOLID (0x1 << 9)
-#define GEN8_RASTER_DW1_DEPTH_OFFSET_WIREFRAME (0x1 << 8)
-#define GEN8_RASTER_DW1_DEPTH_OFFSET_POINT (0x1 << 7)
-#define GEN8_RASTER_DW1_FILL_MODE_FRONT__MASK 0x00000060
-#define GEN8_RASTER_DW1_FILL_MODE_FRONT__SHIFT 5
-#define GEN8_RASTER_DW1_FILL_MODE_BACK__MASK 0x00000018
-#define GEN8_RASTER_DW1_FILL_MODE_BACK__SHIFT 3
-#define GEN8_RASTER_DW1_AA_LINE_ENABLE (0x1 << 2)
-#define GEN8_RASTER_DW1_SCISSOR_ENABLE (0x1 << 1)
-#define GEN8_RASTER_DW1_Z_TEST_ENABLE (0x1 << 0)
-#define GEN9_RASTER_DW1_Z_TEST_NEAR_ENABLE (0x1 << 0)
-
-
-
-
-#define GEN6_3DSTATE_WM__SIZE 9
-
-
-#define GEN6_WM_DW1_KERNEL0_ADDR__MASK 0xffffffc0
-#define GEN6_WM_DW1_KERNEL0_ADDR__SHIFT 6
-#define GEN6_WM_DW1_KERNEL0_ADDR__SHR 6
-
-
-
-#define GEN6_WM_DW4_STATISTICS (0x1 << 31)
-#define GEN6_WM_DW4_DEPTH_CLEAR (0x1 << 30)
-#define GEN6_WM_DW4_DEPTH_RESOLVE (0x1 << 28)
-#define GEN6_WM_DW4_HIZ_RESOLVE (0x1 << 27)
-#define GEN6_WM_DW4_URB_GRF_START0__MASK 0x007f0000
-#define GEN6_WM_DW4_URB_GRF_START0__SHIFT 16
-#define GEN6_WM_DW4_URB_GRF_START1__MASK 0x00007f00
-#define GEN6_WM_DW4_URB_GRF_START1__SHIFT 8
-#define GEN6_WM_DW4_URB_GRF_START2__MASK 0x0000007f
-#define GEN6_WM_DW4_URB_GRF_START2__SHIFT 0
-
-#define GEN6_WM_DW5_MAX_THREADS__MASK 0xfe000000
-#define GEN6_WM_DW5_MAX_THREADS__SHIFT 25
-#define GEN6_WM_DW5_LEGACY_LINE_RAST (0x1 << 23)
-#define GEN6_WM_DW5_PS_KILL_PIXEL (0x1 << 22)
-#define GEN6_WM_DW5_PS_COMPUTE_DEPTH (0x1 << 21)
-#define GEN6_WM_DW5_PS_USE_DEPTH (0x1 << 20)
-#define GEN6_WM_DW5_PS_DISPATCH_ENABLE (0x1 << 19)
-#define GEN6_WM_DW5_AA_LINE_CAP__MASK 0x00030000
-#define GEN6_WM_DW5_AA_LINE_CAP__SHIFT 16
-#define GEN6_WM_DW5_AA_LINE_CAP_0_5 (0x0 << 16)
-#define GEN6_WM_DW5_AA_LINE_CAP_1_0 (0x1 << 16)
-#define GEN6_WM_DW5_AA_LINE_CAP_2_0 (0x2 << 16)
-#define GEN6_WM_DW5_AA_LINE_CAP_4_0 (0x3 << 16)
-#define GEN6_WM_DW5_AA_LINE_WIDTH__MASK 0x0000c000
-#define GEN6_WM_DW5_AA_LINE_WIDTH__SHIFT 14
-#define GEN6_WM_DW5_AA_LINE_WIDTH_0_5 (0x0 << 14)
-#define GEN6_WM_DW5_AA_LINE_WIDTH_1_0 (0x1 << 14)
-#define GEN6_WM_DW5_AA_LINE_WIDTH_2_0 (0x2 << 14)
-#define GEN6_WM_DW5_AA_LINE_WIDTH_4_0 (0x3 << 14)
-#define GEN6_WM_DW5_POLY_STIPPLE_ENABLE (0x1 << 13)
-#define GEN6_WM_DW5_LINE_STIPPLE_ENABLE (0x1 << 11)
-#define GEN6_WM_DW5_PS_COMPUTE_OMASK (0x1 << 9)
-#define GEN6_WM_DW5_PS_USE_W (0x1 << 8)
-#define GEN6_WM_DW5_PS_DUAL_SOURCE_BLEND (0x1 << 7)
-#define GEN6_WM_DW5_PS_DISPATCH_MODE__MASK 0x00000007
-#define GEN6_WM_DW5_PS_DISPATCH_MODE__SHIFT 0
-
-#define GEN6_WM_DW6_SF_ATTR_COUNT__MASK 0x03f00000
-#define GEN6_WM_DW6_SF_ATTR_COUNT__SHIFT 20
-#define GEN6_WM_DW6_PS_POSOFFSET__MASK 0x000c0000
-#define GEN6_WM_DW6_PS_POSOFFSET__SHIFT 18
-#define GEN6_WM_DW6_ZW_INTERP__MASK 0x00030000
-#define GEN6_WM_DW6_ZW_INTERP__SHIFT 16
-#define GEN6_WM_DW6_BARYCENTRIC_INTERP__MASK 0x0000fc00
-#define GEN6_WM_DW6_BARYCENTRIC_INTERP__SHIFT 10
-#define GEN6_WM_DW6_POINT_RASTRULE__MASK 0x00000200
-#define GEN6_WM_DW6_POINT_RASTRULE__SHIFT 9
-#define GEN6_WM_DW6_POINT_RASTRULE_UPPER_LEFT (0x0 << 9)
-#define GEN6_WM_DW6_POINT_RASTRULE_UPPER_RIGHT (0x1 << 9)
-#define GEN6_WM_DW6_MSRASTMODE__MASK 0x00000006
-#define GEN6_WM_DW6_MSRASTMODE__SHIFT 1
-#define GEN6_WM_DW6_MSDISPMODE__MASK 0x00000001
-#define GEN6_WM_DW6_MSDISPMODE__SHIFT 0
-#define GEN6_WM_DW6_MSDISPMODE_PERSAMPLE 0x0
-#define GEN6_WM_DW6_MSDISPMODE_PERPIXEL 0x1
-
-#define GEN6_WM_DW7_KERNEL1_ADDR__MASK 0xffffffc0
-#define GEN6_WM_DW7_KERNEL1_ADDR__SHIFT 6
-#define GEN6_WM_DW7_KERNEL1_ADDR__SHR 6
-
-#define GEN6_WM_DW8_KERNEL2_ADDR__MASK 0xffffffc0
-#define GEN6_WM_DW8_KERNEL2_ADDR__SHIFT 6
-#define GEN6_WM_DW8_KERNEL2_ADDR__SHR 6
-
-
-#define GEN7_WM_DW1_STATISTICS (0x1 << 31)
-#define GEN7_WM_DW1_LEGACY_DEPTH_CLEAR (0x1 << 30)
-#define GEN7_WM_DW1_PS_DISPATCH_ENABLE (0x1 << 29)
-#define GEN7_WM_DW1_LEGACY_DEPTH_RESOLVE (0x1 << 28)
-#define GEN7_WM_DW1_LEGACY_HIZ_RESOLVE (0x1 << 27)
-#define GEN7_WM_DW1_LEGACY_LINE_RAST (0x1 << 26)
-#define GEN7_WM_DW1_PS_KILL_PIXEL (0x1 << 25)
-#define GEN7_WM_DW1_PSCDEPTH__MASK 0x01800000
-#define GEN7_WM_DW1_PSCDEPTH__SHIFT 23
-#define GEN7_WM_DW1_EDSC__MASK 0x00600000
-#define GEN7_WM_DW1_EDSC__SHIFT 21
-#define GEN7_WM_DW1_PS_USE_DEPTH (0x1 << 20)
-#define GEN7_WM_DW1_PS_USE_W (0x1 << 19)
-#define GEN8_WM_DW1_FORCE_DISPATCH_ENABLE__MASK 0x00180000
-#define GEN8_WM_DW1_FORCE_DISPATCH_ENABLE__SHIFT 19
-#define GEN8_WM_DW1_FORCE_DISPATCH_ENABLE_NORMAL (0x0 << 19)
-#define GEN8_WM_DW1_FORCE_DISPATCH_ENABLE_OFF (0x1 << 19)
-#define GEN8_WM_DW1_FORCE_DISPATCH_ENABLE_ON (0x2 << 19)
-#define GEN7_WM_DW1_ZW_INTERP__MASK 0x00060000
-#define GEN7_WM_DW1_ZW_INTERP__SHIFT 17
-#define GEN7_WM_DW1_BARYCENTRIC_INTERP__MASK 0x0001f800
-#define GEN7_WM_DW1_BARYCENTRIC_INTERP__SHIFT 11
-#define GEN7_WM_DW1_PS_USE_COVERAGE_MASK (0x1 << 10)
-#define GEN7_WM_DW1_AA_LINE_CAP__MASK 0x00000300
-#define GEN7_WM_DW1_AA_LINE_CAP__SHIFT 8
-#define GEN7_WM_DW1_AA_LINE_CAP_0_5 (0x0 << 8)
-#define GEN7_WM_DW1_AA_LINE_CAP_1_0 (0x1 << 8)
-#define GEN7_WM_DW1_AA_LINE_CAP_2_0 (0x2 << 8)
-#define GEN7_WM_DW1_AA_LINE_CAP_4_0 (0x3 << 8)
-#define GEN7_WM_DW1_AA_LINE_WIDTH__MASK 0x000000c0
-#define GEN7_WM_DW1_AA_LINE_WIDTH__SHIFT 6
-#define GEN7_WM_DW1_AA_LINE_WIDTH_0_5 (0x0 << 6)
-#define GEN7_WM_DW1_AA_LINE_WIDTH_1_0 (0x1 << 6)
-#define GEN7_WM_DW1_AA_LINE_WIDTH_2_0 (0x2 << 6)
-#define GEN7_WM_DW1_AA_LINE_WIDTH_4_0 (0x3 << 6)
-#define GEN75_WM_DW1_RT_INDEPENDENT_RAST (0x1 << 5)
-#define GEN7_WM_DW1_POLY_STIPPLE_ENABLE (0x1 << 4)
-#define GEN7_WM_DW1_LINE_STIPPLE_ENABLE (0x1 << 3)
-#define GEN7_WM_DW1_POINT_RASTRULE__MASK 0x00000004
-#define GEN7_WM_DW1_POINT_RASTRULE__SHIFT 2
-#define GEN7_WM_DW1_POINT_RASTRULE_UPPER_LEFT (0x0 << 2)
-#define GEN7_WM_DW1_POINT_RASTRULE_UPPER_RIGHT (0x1 << 2)
-#define GEN7_WM_DW1_MSRASTMODE__MASK 0x00000003
-#define GEN7_WM_DW1_MSRASTMODE__SHIFT 0
-#define GEN8_WM_DW1_FORCE_KILL_PIXEL__MASK 0x00000003
-#define GEN8_WM_DW1_FORCE_KILL_PIXEL__SHIFT 0
-#define GEN8_WM_DW1_FORCE_KILL_PIXEL_NORMAL 0x0
-#define GEN8_WM_DW1_FORCE_KILL_PIXEL_OFF 0x1
-#define GEN8_WM_DW1_FORCE_KILL_PIXEL_ON 0x2
-
-#define GEN7_WM_DW2_MSDISPMODE__MASK 0x80000000
-#define GEN7_WM_DW2_MSDISPMODE__SHIFT 31
-#define GEN7_WM_DW2_MSDISPMODE_PERSAMPLE (0x0 << 31)
-#define GEN7_WM_DW2_MSDISPMODE_PERPIXEL (0x1 << 31)
-#define GEN75_WM_DW2_PS_UAV_ONLY (0x1 << 30)
-
-#define GEN8_3DSTATE_WM_CHROMAKEY__SIZE 2
-
-
-#define GEN8_CHROMAKEY_DW1_KILL_ENABLE (0x1 << 31)
-
-#define GEN8_3DSTATE_WM_DEPTH_STENCIL__SIZE 4
-
-
-#define GEN8_ZS_DW1_STENCIL_FAIL_OP__MASK 0xe0000000
-#define GEN8_ZS_DW1_STENCIL_FAIL_OP__SHIFT 29
-#define GEN8_ZS_DW1_STENCIL_ZFAIL_OP__MASK 0x1c000000
-#define GEN8_ZS_DW1_STENCIL_ZFAIL_OP__SHIFT 26
-#define GEN8_ZS_DW1_STENCIL_ZPASS_OP__MASK 0x03800000
-#define GEN8_ZS_DW1_STENCIL_ZPASS_OP__SHIFT 23
-#define GEN8_ZS_DW1_STENCIL1_FUNC__MASK 0x00700000
-#define GEN8_ZS_DW1_STENCIL1_FUNC__SHIFT 20
-#define GEN8_ZS_DW1_STENCIL1_FAIL_OP__MASK 0x000e0000
-#define GEN8_ZS_DW1_STENCIL1_FAIL_OP__SHIFT 17
-#define GEN8_ZS_DW1_STENCIL1_ZFAIL_OP__MASK 0x0001c000
-#define GEN8_ZS_DW1_STENCIL1_ZFAIL_OP__SHIFT 14
-#define GEN8_ZS_DW1_STENCIL1_ZPASS_OP__MASK 0x00003800
-#define GEN8_ZS_DW1_STENCIL1_ZPASS_OP__SHIFT 11
-#define GEN8_ZS_DW1_STENCIL_FUNC__MASK 0x00000700
-#define GEN8_ZS_DW1_STENCIL_FUNC__SHIFT 8
-#define GEN8_ZS_DW1_DEPTH_FUNC__MASK 0x000000e0
-#define GEN8_ZS_DW1_DEPTH_FUNC__SHIFT 5
-#define GEN8_ZS_DW1_STENCIL1_ENABLE (0x1 << 4)
-#define GEN8_ZS_DW1_STENCIL_TEST_ENABLE (0x1 << 3)
-#define GEN8_ZS_DW1_STENCIL_WRITE_ENABLE (0x1 << 2)
-#define GEN8_ZS_DW1_DEPTH_TEST_ENABLE (0x1 << 1)
-#define GEN8_ZS_DW1_DEPTH_WRITE_ENABLE (0x1 << 0)
-
-#define GEN8_ZS_DW2_STENCIL_TEST_MASK__MASK 0xff000000
-#define GEN8_ZS_DW2_STENCIL_TEST_MASK__SHIFT 24
-#define GEN8_ZS_DW2_STENCIL_WRITE_MASK__MASK 0x00ff0000
-#define GEN8_ZS_DW2_STENCIL_WRITE_MASK__SHIFT 16
-#define GEN8_ZS_DW2_STENCIL1_TEST_MASK__MASK 0x0000ff00
-#define GEN8_ZS_DW2_STENCIL1_TEST_MASK__SHIFT 8
-#define GEN8_ZS_DW2_STENCIL1_WRITE_MASK__MASK 0x000000ff
-#define GEN8_ZS_DW2_STENCIL1_WRITE_MASK__SHIFT 0
-
-#define GEN9_ZS_DW3_STENCIL_REF__MASK 0x0000ff00
-#define GEN9_ZS_DW3_STENCIL_REF__SHIFT 8
-#define GEN9_ZS_DW3_STENCIL1_REF__MASK 0x000000ff
-#define GEN9_ZS_DW3_STENCIL1_REF__SHIFT 0
-
-#define GEN8_3DSTATE_WM_HZ_OP__SIZE 5
-
-
-#define GEN8_WM_HZ_DW1_STENCIL_CLEAR (0x1 << 31)
-#define GEN8_WM_HZ_DW1_DEPTH_CLEAR (0x1 << 30)
-#define GEN8_WM_HZ_DW1_SCISSOR_ENABLE (0x1 << 29)
-#define GEN8_WM_HZ_DW1_DEPTH_RESOLVE (0x1 << 28)
-#define GEN8_WM_HZ_DW1_HIZ_RESOLVE (0x1 << 27)
-#define GEN8_WM_HZ_DW1_PIXEL_OFFSET_ENABLE (0x1 << 26)
-#define GEN8_WM_HZ_DW1_FULL_SURFACE_DEPTH_CLEAR (0x1 << 25)
-#define GEN8_WM_HZ_DW1_STENCIL_CLEAR_VALUE__MASK 0x00ff0000
-#define GEN8_WM_HZ_DW1_STENCIL_CLEAR_VALUE__SHIFT 16
-#define GEN8_WM_HZ_DW1_NUM_SAMPLES__MASK 0x0000e000
-#define GEN8_WM_HZ_DW1_NUM_SAMPLES__SHIFT 13
-
-#define GEN8_WM_HZ_DW2_RECT_MIN_Y__MASK 0xffff0000
-#define GEN8_WM_HZ_DW2_RECT_MIN_Y__SHIFT 16
-#define GEN8_WM_HZ_DW2_RECT_MIN_X__MASK 0x0000ffff
-#define GEN8_WM_HZ_DW2_RECT_MIN_X__SHIFT 0
-
-#define GEN8_WM_HZ_DW3_RECT_MAX_Y__MASK 0xffff0000
-#define GEN8_WM_HZ_DW3_RECT_MAX_Y__SHIFT 16
-#define GEN8_WM_HZ_DW3_RECT_MAX_X__MASK 0x0000ffff
-#define GEN8_WM_HZ_DW3_RECT_MAX_X__SHIFT 0
-
-#define GEN8_WM_HZ_DW4_SAMPLE_MASK__MASK 0x0000ffff
-#define GEN8_WM_HZ_DW4_SAMPLE_MASK__SHIFT 0
-
-#define GEN7_3DSTATE_PS__SIZE 12
-
-
-#define GEN7_PS_DW1_KERNEL0_ADDR__MASK 0xffffffc0
-#define GEN7_PS_DW1_KERNEL0_ADDR__SHIFT 6
-#define GEN7_PS_DW1_KERNEL0_ADDR__SHR 6
-
-
-
-#define GEN7_PS_DW4_MAX_THREADS__MASK 0xff000000
-#define GEN7_PS_DW4_MAX_THREADS__SHIFT 24
-#define GEN75_PS_DW4_MAX_THREADS__MASK 0xff800000
-#define GEN75_PS_DW4_MAX_THREADS__SHIFT 23
-#define GEN75_PS_DW4_SAMPLE_MASK__MASK 0x000ff000
-#define GEN75_PS_DW4_SAMPLE_MASK__SHIFT 12
-#define GEN7_PS_DW4_PUSH_CONSTANT_ENABLE (0x1 << 11)
-#define GEN7_PS_DW4_ATTR_ENABLE (0x1 << 10)
-#define GEN7_PS_DW4_COMPUTE_OMASK (0x1 << 9)
-#define GEN7_PS_DW4_RT_FAST_CLEAR (0x1 << 8)
-#define GEN7_PS_DW4_DUAL_SOURCE_BLEND (0x1 << 7)
-#define GEN7_PS_DW4_RT_RESOLVE (0x1 << 6)
-#define GEN75_PS_DW4_ACCESS_UAV (0x1 << 5)
-#define GEN7_PS_DW4_POSOFFSET__MASK 0x00000018
-#define GEN7_PS_DW4_POSOFFSET__SHIFT 3
-#define GEN7_PS_DW4_DISPATCH_MODE__MASK 0x00000007
-#define GEN7_PS_DW4_DISPATCH_MODE__SHIFT 0
-
-#define GEN7_PS_DW5_URB_GRF_START0__MASK 0x007f0000
-#define GEN7_PS_DW5_URB_GRF_START0__SHIFT 16
-#define GEN7_PS_DW5_URB_GRF_START1__MASK 0x00007f00
-#define GEN7_PS_DW5_URB_GRF_START1__SHIFT 8
-#define GEN7_PS_DW5_URB_GRF_START2__MASK 0x0000007f
-#define GEN7_PS_DW5_URB_GRF_START2__SHIFT 0
-
-#define GEN7_PS_DW6_KERNEL1_ADDR__MASK 0xffffffc0
-#define GEN7_PS_DW6_KERNEL1_ADDR__SHIFT 6
-#define GEN7_PS_DW6_KERNEL1_ADDR__SHR 6
-
-#define GEN7_PS_DW7_KERNEL2_ADDR__MASK 0xffffffc0
-#define GEN7_PS_DW7_KERNEL2_ADDR__SHIFT 6
-#define GEN7_PS_DW7_KERNEL2_ADDR__SHR 6
-
-
-
-#define GEN8_PS_DW1_KERNEL0_ADDR__MASK 0xffffffc0
-#define GEN8_PS_DW1_KERNEL0_ADDR__SHIFT 6
-#define GEN8_PS_DW1_KERNEL0_ADDR__SHR 6
-
-
-
-
-
-#define GEN8_PS_DW6_MAX_THREADS__MASK 0xff800000
-#define GEN8_PS_DW6_MAX_THREADS__SHIFT 23
-#define GEN8_PS_DW6_PUSH_CONSTANT_ENABLE (0x1 << 11)
-#define GEN8_PS_DW6_RT_FAST_CLEAR (0x1 << 8)
-#define GEN8_PS_DW6_RT_RESOLVE (0x1 << 6)
-#define GEN8_PS_DW6_POSOFFSET__MASK 0x00000018
-#define GEN8_PS_DW6_POSOFFSET__SHIFT 3
-#define GEN8_PS_DW6_DISPATCH_MODE__MASK 0x00000007
-#define GEN8_PS_DW6_DISPATCH_MODE__SHIFT 0
-
-#define GEN8_PS_DW7_URB_GRF_START0__MASK 0x007f0000
-#define GEN8_PS_DW7_URB_GRF_START0__SHIFT 16
-#define GEN8_PS_DW7_URB_GRF_START1__MASK 0x00007f00
-#define GEN8_PS_DW7_URB_GRF_START1__SHIFT 8
-#define GEN8_PS_DW7_URB_GRF_START2__MASK 0x0000007f
-#define GEN8_PS_DW7_URB_GRF_START2__SHIFT 0
-
-#define GEN8_PS_DW8_KERNEL1_ADDR__MASK 0xffffffc0
-#define GEN8_PS_DW8_KERNEL1_ADDR__SHIFT 6
-#define GEN8_PS_DW8_KERNEL1_ADDR__SHR 6
-
-
-#define GEN8_PS_DW10_KERNEL2_ADDR__MASK 0xffffffc0
-#define GEN8_PS_DW10_KERNEL2_ADDR__SHIFT 6
-#define GEN8_PS_DW10_KERNEL2_ADDR__SHR 6
-
-
-#define GEN8_3DSTATE_PS_EXTRA__SIZE 2
-
-
-#define GEN8_PSX_DW1_VALID (0x1 << 31)
-#define GEN8_PSX_DW1_UAV_ONLY (0x1 << 30)
-#define GEN8_PSX_DW1_COMPUTE_OMASK (0x1 << 29)
-#define GEN8_PSX_DW1_KILL_PIXEL (0x1 << 28)
-#define GEN8_PSX_DW1_PSCDEPTH__MASK 0x0c000000
-#define GEN8_PSX_DW1_PSCDEPTH__SHIFT 26
-#define GEN8_PSX_DW1_FORCE_COMPUTE_DEPTH (0x1 << 25)
-#define GEN8_PSX_DW1_USE_DEPTH (0x1 << 24)
-#define GEN8_PSX_DW1_USE_W (0x1 << 23)
-#define GEN8_PSX_DW1_ATTR_ENABLE (0x1 << 8)
-#define GEN8_PSX_DW1_DISABLE_ALPHA_TO_COVERAGE (0x1 << 7)
-#define GEN8_PSX_DW1_PER_SAMPLE (0x1 << 6)
-#define GEN8_PSX_DW1_COMPUTE_STENCIL (0x1 << 5)
-#define GEN8_PSX_DW1_ACCESS_UAV (0x1 << 2)
-#define GEN8_PSX_DW1_USE_COVERAGE_MASK (0x1 << 1)
-
-#define GEN8_3DSTATE_PS_BLEND__SIZE 2
-
-
-#define GEN8_PS_BLEND_DW1_ALPHA_TO_COVERAGE (0x1 << 31)
-#define GEN8_PS_BLEND_DW1_WRITABLE_RT (0x1 << 30)
-#define GEN8_PS_BLEND_DW1_RT0_BLEND_ENABLE (0x1 << 29)
-#define GEN8_PS_BLEND_DW1_RT0_SRC_ALPHA_FACTOR__MASK 0x1f000000
-#define GEN8_PS_BLEND_DW1_RT0_SRC_ALPHA_FACTOR__SHIFT 24
-#define GEN8_PS_BLEND_DW1_RT0_DST_ALPHA_FACTOR__MASK 0x00f80000
-#define GEN8_PS_BLEND_DW1_RT0_DST_ALPHA_FACTOR__SHIFT 19
-#define GEN8_PS_BLEND_DW1_RT0_SRC_COLOR_FACTOR__MASK 0x0007c000
-#define GEN8_PS_BLEND_DW1_RT0_SRC_COLOR_FACTOR__SHIFT 14
-#define GEN8_PS_BLEND_DW1_RT0_DST_COLOR_FACTOR__MASK 0x00003e00
-#define GEN8_PS_BLEND_DW1_RT0_DST_COLOR_FACTOR__SHIFT 9
-#define GEN8_PS_BLEND_DW1_ALPHA_TEST_ENABLE (0x1 << 8)
-#define GEN8_PS_BLEND_DW1_RT0_INDEPENDENT_ALPHA_ENABLE (0x1 << 7)
-
-#define GEN6_3DSTATE_CONSTANT_ANY__SIZE 11
-
-#define GEN6_CONSTANT_DW0_BUFFER_ENABLES__MASK 0x0000f000
-#define GEN6_CONSTANT_DW0_BUFFER_ENABLES__SHIFT 12
-#define GEN6_CONSTANT_DW0_MOCS__MASK 0x00000f00
-#define GEN6_CONSTANT_DW0_MOCS__SHIFT 8
-
-#define GEN6_CONSTANT_DW_ADDR_READ_LEN__MASK 0x0000001f
-#define GEN6_CONSTANT_DW_ADDR_READ_LEN__SHIFT 0
-#define GEN6_CONSTANT_DW_ADDR_ADDR__MASK 0xffffffe0
-#define GEN6_CONSTANT_DW_ADDR_ADDR__SHIFT 5
-#define GEN6_CONSTANT_DW_ADDR_ADDR__SHR 5
-
-
-#define GEN8_CONSTANT_DW0_MOCS__MASK 0x00007f00
-#define GEN8_CONSTANT_DW0_MOCS__SHIFT 8
-
-#define GEN7_CONSTANT_DW1_BUFFER1_READ_LEN__MASK 0xffff0000
-#define GEN7_CONSTANT_DW1_BUFFER1_READ_LEN__SHIFT 16
-#define GEN7_CONSTANT_DW1_BUFFER0_READ_LEN__MASK 0x0000ffff
-#define GEN7_CONSTANT_DW1_BUFFER0_READ_LEN__SHIFT 0
-
-#define GEN7_CONSTANT_DW2_BUFFER3_READ_LEN__MASK 0xffff0000
-#define GEN7_CONSTANT_DW2_BUFFER3_READ_LEN__SHIFT 16
-#define GEN7_CONSTANT_DW2_BUFFER2_READ_LEN__MASK 0x0000ffff
-#define GEN7_CONSTANT_DW2_BUFFER2_READ_LEN__SHIFT 0
-
-#define GEN7_CONSTANT_DW_ADDR_MOCS__MASK 0x0000001f
-#define GEN7_CONSTANT_DW_ADDR_MOCS__SHIFT 0
-#define GEN7_CONSTANT_DW_ADDR_ADDR__MASK 0xffffffe0
-#define GEN7_CONSTANT_DW_ADDR_ADDR__SHIFT 5
-#define GEN7_CONSTANT_DW_ADDR_ADDR__SHR 5
-
-#define GEN8_CONSTANT_DW_ADDR_ADDR__MASK 0xffffffe0
-#define GEN8_CONSTANT_DW_ADDR_ADDR__SHIFT 5
-#define GEN8_CONSTANT_DW_ADDR_ADDR__SHR 5
-
-#define GEN6_3DSTATE_SAMPLE_MASK__SIZE 2
-
-
-#define GEN6_SAMPLE_MASK_DW1_VAL__MASK 0x0000000f
-#define GEN6_SAMPLE_MASK_DW1_VAL__SHIFT 0
-#define GEN7_SAMPLE_MASK_DW1_VAL__MASK 0x000000ff
-#define GEN7_SAMPLE_MASK_DW1_VAL__SHIFT 0
-#define GEN8_SAMPLE_MASK_DW1_VAL__MASK 0x0000ffff
-#define GEN8_SAMPLE_MASK_DW1_VAL__SHIFT 0
-
-#define GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE 4
-
-#define GEN8_DRAWING_RECTANGLE_DW0_CORE_MODE_SELECT__MASK 0x0000c000
-#define GEN8_DRAWING_RECTANGLE_DW0_CORE_MODE_SELECT__SHIFT 14
-
-#define GEN6_DRAWING_RECTANGLE_DW1_MIN_Y__MASK 0xffff0000
-#define GEN6_DRAWING_RECTANGLE_DW1_MIN_Y__SHIFT 16
-#define GEN6_DRAWING_RECTANGLE_DW1_MIN_X__MASK 0x0000ffff
-#define GEN6_DRAWING_RECTANGLE_DW1_MIN_X__SHIFT 0
-
-#define GEN6_DRAWING_RECTANGLE_DW2_MAX_Y__MASK 0xffff0000
-#define GEN6_DRAWING_RECTANGLE_DW2_MAX_Y__SHIFT 16
-#define GEN6_DRAWING_RECTANGLE_DW2_MAX_X__MASK 0x0000ffff
-#define GEN6_DRAWING_RECTANGLE_DW2_MAX_X__SHIFT 0
-
-#define GEN6_DRAWING_RECTANGLE_DW3_ORIGIN_Y__MASK 0xffff0000
-#define GEN6_DRAWING_RECTANGLE_DW3_ORIGIN_Y__SHIFT 16
-#define GEN6_DRAWING_RECTANGLE_DW3_ORIGIN_X__MASK 0x0000ffff
-#define GEN6_DRAWING_RECTANGLE_DW3_ORIGIN_X__SHIFT 0
-
-#define GEN6_3DSTATE_DEPTH_BUFFER__SIZE 8
-
-
-#define GEN6_DEPTH_DW1_TYPE__MASK 0xe0000000
-#define GEN6_DEPTH_DW1_TYPE__SHIFT 29
-#define GEN6_DEPTH_DW1_TILING__MASK 0x0c000000
-#define GEN6_DEPTH_DW1_TILING__SHIFT 26
-#define GEN6_DEPTH_DW1_STR_MODE__MASK 0x01800000
-#define GEN6_DEPTH_DW1_STR_MODE__SHIFT 23
-#define GEN6_DEPTH_DW1_HIZ_ENABLE (0x1 << 22)
-#define GEN6_DEPTH_DW1_SEPARATE_STENCIL (0x1 << 21)
-#define GEN6_DEPTH_DW1_FORMAT__MASK 0x001c0000
-#define GEN6_DEPTH_DW1_FORMAT__SHIFT 18
-#define GEN6_DEPTH_DW1_PITCH__MASK 0x0001ffff
-#define GEN6_DEPTH_DW1_PITCH__SHIFT 0
-
-
-#define GEN6_DEPTH_DW3_HEIGHT__MASK 0xfff80000
-#define GEN6_DEPTH_DW3_HEIGHT__SHIFT 19
-#define GEN6_DEPTH_DW3_WIDTH__MASK 0x0007ffc0
-#define GEN6_DEPTH_DW3_WIDTH__SHIFT 6
-#define GEN6_DEPTH_DW3_LOD__MASK 0x0000003c
-#define GEN6_DEPTH_DW3_LOD__SHIFT 2
-#define GEN6_DEPTH_DW3_MIPLAYOUT__MASK 0x00000002
-#define GEN6_DEPTH_DW3_MIPLAYOUT__SHIFT 1
-#define GEN6_DEPTH_DW3_MIPLAYOUT_BELOW (0x0 << 1)
-#define GEN6_DEPTH_DW3_MIPLAYOUT_RIGHT (0x1 << 1)
-
-#define GEN6_DEPTH_DW4_DEPTH__MASK 0xffe00000
-#define GEN6_DEPTH_DW4_DEPTH__SHIFT 21
-#define GEN6_DEPTH_DW4_MIN_ARRAY_ELEMENT__MASK 0x001ffc00
-#define GEN6_DEPTH_DW4_MIN_ARRAY_ELEMENT__SHIFT 10
-#define GEN6_DEPTH_DW4_RT_VIEW_EXTENT__MASK 0x000003fe
-#define GEN6_DEPTH_DW4_RT_VIEW_EXTENT__SHIFT 1
-
-#define GEN6_DEPTH_DW5_OFFSET_Y__MASK 0xffff0000
-#define GEN6_DEPTH_DW5_OFFSET_Y__SHIFT 16
-#define GEN6_DEPTH_DW5_OFFSET_X__MASK 0x0000ffff
-#define GEN6_DEPTH_DW5_OFFSET_X__SHIFT 0
-
-#define GEN6_DEPTH_DW6_MOCS__MASK 0xf8000000
-#define GEN6_DEPTH_DW6_MOCS__SHIFT 27
-
-
-
-#define GEN7_DEPTH_DW1_TYPE__MASK 0xe0000000
-#define GEN7_DEPTH_DW1_TYPE__SHIFT 29
-#define GEN7_DEPTH_DW1_DEPTH_WRITE_ENABLE (0x1 << 28)
-#define GEN7_DEPTH_DW1_STENCIL_WRITE_ENABLE (0x1 << 27)
-#define GEN7_DEPTH_DW1_HIZ_ENABLE (0x1 << 22)
-#define GEN7_DEPTH_DW1_FORMAT__MASK 0x001c0000
-#define GEN7_DEPTH_DW1_FORMAT__SHIFT 18
-#define GEN7_DEPTH_DW1_PITCH__MASK 0x0003ffff
-#define GEN7_DEPTH_DW1_PITCH__SHIFT 0
-
-
-#define GEN7_DEPTH_DW3_HEIGHT__MASK 0xfffc0000
-#define GEN7_DEPTH_DW3_HEIGHT__SHIFT 18
-#define GEN7_DEPTH_DW3_WIDTH__MASK 0x0003fff0
-#define GEN7_DEPTH_DW3_WIDTH__SHIFT 4
-#define GEN7_DEPTH_DW3_LOD__MASK 0x0000000f
-#define GEN7_DEPTH_DW3_LOD__SHIFT 0
-
-#define GEN7_DEPTH_DW4_DEPTH__MASK 0xffe00000
-#define GEN7_DEPTH_DW4_DEPTH__SHIFT 21
-#define GEN7_DEPTH_DW4_MIN_ARRAY_ELEMENT__MASK 0x001ffc00
-#define GEN7_DEPTH_DW4_MIN_ARRAY_ELEMENT__SHIFT 10
-#define GEN7_DEPTH_DW4_MOCS__MASK 0x0000000f
-#define GEN7_DEPTH_DW4_MOCS__SHIFT 0
-
-#define GEN7_DEPTH_DW5_OFFSET_Y__MASK 0xffff0000
-#define GEN7_DEPTH_DW5_OFFSET_Y__SHIFT 16
-#define GEN7_DEPTH_DW5_OFFSET_X__MASK 0x0000ffff
-#define GEN7_DEPTH_DW5_OFFSET_X__SHIFT 0
-
-#define GEN7_DEPTH_DW6_RT_VIEW_EXTENT__MASK 0xffe00000
-#define GEN7_DEPTH_DW6_RT_VIEW_EXTENT__SHIFT 21
-
-
-
-#define GEN8_DEPTH_DW1_TYPE__MASK 0xe0000000
-#define GEN8_DEPTH_DW1_TYPE__SHIFT 29
-#define GEN8_DEPTH_DW1_DEPTH_WRITE_ENABLE (0x1 << 28)
-#define GEN8_DEPTH_DW1_STENCIL_WRITE_ENABLE (0x1 << 27)
-#define GEN8_DEPTH_DW1_HIZ_ENABLE (0x1 << 22)
-#define GEN8_DEPTH_DW1_FORMAT__MASK 0x001c0000
-#define GEN8_DEPTH_DW1_FORMAT__SHIFT 18
-#define GEN8_DEPTH_DW1_PITCH__MASK 0x0003ffff
-#define GEN8_DEPTH_DW1_PITCH__SHIFT 0
-
-
-
-#define GEN8_DEPTH_DW4_HEIGHT__MASK 0xfffc0000
-#define GEN8_DEPTH_DW4_HEIGHT__SHIFT 18
-#define GEN8_DEPTH_DW4_WIDTH__MASK 0x0003fff0
-#define GEN8_DEPTH_DW4_WIDTH__SHIFT 4
-#define GEN8_DEPTH_DW4_LOD__MASK 0x0000000f
-#define GEN8_DEPTH_DW4_LOD__SHIFT 0
-
-#define GEN8_DEPTH_DW5_DEPTH__MASK 0xffe00000
-#define GEN8_DEPTH_DW5_DEPTH__SHIFT 21
-#define GEN8_DEPTH_DW5_MIN_ARRAY_ELEMENT__MASK 0x001ffc00
-#define GEN8_DEPTH_DW5_MIN_ARRAY_ELEMENT__SHIFT 10
-#define GEN8_DEPTH_DW5_MOCS__MASK 0x0000007f
-#define GEN8_DEPTH_DW5_MOCS__SHIFT 0
-
-
-#define GEN8_DEPTH_DW7_RT_VIEW_EXTENT__MASK 0xffe00000
-#define GEN8_DEPTH_DW7_RT_VIEW_EXTENT__SHIFT 21
-#define GEN8_DEPTH_DW7_QPITCH__MASK 0x00007fff
-#define GEN8_DEPTH_DW7_QPITCH__SHIFT 0
-#define GEN8_DEPTH_DW7_QPITCH__SHR 2
-
-#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE 2
-
-
-#define GEN6_POLY_STIPPLE_OFFSET_DW1_X__MASK 0x00001f00
-#define GEN6_POLY_STIPPLE_OFFSET_DW1_X__SHIFT 8
-#define GEN6_POLY_STIPPLE_OFFSET_DW1_Y__MASK 0x0000001f
-#define GEN6_POLY_STIPPLE_OFFSET_DW1_Y__SHIFT 0
-
-#define GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE 33
-
-
-
-#define GEN6_3DSTATE_LINE_STIPPLE__SIZE 3
-
-
-#define GEN6_LINE_STIPPLE_DW1_CURRENT_MODIFY_ENABLE (0x1 << 31)
-#define GEN6_LINE_STIPPLE_DW1_CURRENT_REPEAT_COUNTER__MASK 0x3fe00000
-#define GEN6_LINE_STIPPLE_DW1_CURRENT_REPEAT_COUNTER__SHIFT 21
-#define GEN6_LINE_STIPPLE_DW1_CURRENT_STIPPLE_INDEX__MASK 0x000f0000
-#define GEN6_LINE_STIPPLE_DW1_CURRENT_STIPPLE_INDEX__SHIFT 16
-#define GEN6_LINE_STIPPLE_DW1_PATTERN__MASK 0x0000ffff
-#define GEN6_LINE_STIPPLE_DW1_PATTERN__SHIFT 0
-
-#define GEN6_LINE_STIPPLE_DW2_INVERSE_REPEAT_COUNT__MASK 0xffff0000
-#define GEN6_LINE_STIPPLE_DW2_INVERSE_REPEAT_COUNT__SHIFT 16
-#define GEN6_LINE_STIPPLE_DW2_INVERSE_REPEAT_COUNT__RADIX 13
-#define GEN7_LINE_STIPPLE_DW2_INVERSE_REPEAT_COUNT__MASK 0xffff8000
-#define GEN7_LINE_STIPPLE_DW2_INVERSE_REPEAT_COUNT__SHIFT 15
-#define GEN7_LINE_STIPPLE_DW2_INVERSE_REPEAT_COUNT__RADIX 16
-#define GEN6_LINE_STIPPLE_DW2_REPEAT_COUNT__MASK 0x000001ff
-#define GEN6_LINE_STIPPLE_DW2_REPEAT_COUNT__SHIFT 0
-
-#define GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE 3
-
-
-#define GEN8_AA_LINE_DW1_POINT_BIAS__MASK 0xff000000
-#define GEN8_AA_LINE_DW1_POINT_BIAS__SHIFT 24
-#define GEN8_AA_LINE_DW1_POINT_BIAS__RADIX 8
-#define GEN6_AA_LINE_DW1_BIAS__MASK 0x00ff0000
-#define GEN6_AA_LINE_DW1_BIAS__SHIFT 16
-#define GEN6_AA_LINE_DW1_BIAS__RADIX 8
-#define GEN8_AA_LINE_DW1_POINT_SLOPE__MASK 0x0000ff00
-#define GEN8_AA_LINE_DW1_POINT_SLOPE__SHIFT 8
-#define GEN8_AA_LINE_DW1_POINT_SLOPE__RADIX 8
-#define GEN6_AA_LINE_DW1_SLOPE__MASK 0x000000ff
-#define GEN6_AA_LINE_DW1_SLOPE__SHIFT 0
-#define GEN6_AA_LINE_DW1_SLOPE__RADIX 8
-
-#define GEN8_AA_LINE_DW2_POINT_CAP_BIAS__MASK 0xff000000
-#define GEN8_AA_LINE_DW2_POINT_CAP_BIAS__SHIFT 24
-#define GEN8_AA_LINE_DW2_POINT_CAP_BIAS__RADIX 8
-#define GEN6_AA_LINE_DW2_CAP_BIAS__MASK 0x00ff0000
-#define GEN6_AA_LINE_DW2_CAP_BIAS__SHIFT 16
-#define GEN6_AA_LINE_DW2_CAP_BIAS__RADIX 8
-#define GEN8_AA_LINE_DW2_POINT_CAP_SLOPE__MASK 0x0000ff00
-#define GEN8_AA_LINE_DW2_POINT_CAP_SLOPE__SHIFT 8
-#define GEN8_AA_LINE_DW2_POINT_CAP_SLOPE__RADIX 8
-#define GEN6_AA_LINE_DW2_CAP_SLOPE__MASK 0x000000ff
-#define GEN6_AA_LINE_DW2_CAP_SLOPE__SHIFT 0
-#define GEN6_AA_LINE_DW2_CAP_SLOPE__RADIX 8
-
-#define GEN6_3DSTATE_GS_SVB_INDEX__SIZE 4
-
-
-#define GEN6_SVBI_DW1_INDEX__MASK 0x60000000
-#define GEN6_SVBI_DW1_INDEX__SHIFT 29
-#define GEN6_SVBI_DW1_LOAD_INTERNAL_VERTEX_COUNT (0x1 << 0)
-
-
-
-#define GEN6_3DSTATE_MULTISAMPLE__SIZE 4
-
-
-#define GEN75_MULTISAMPLE_DW1_PIXEL_OFFSET_ENABLE (0x1 << 5)
-#define GEN6_MULTISAMPLE_DW1_PIXEL_LOCATION__MASK 0x00000010
-#define GEN6_MULTISAMPLE_DW1_PIXEL_LOCATION__SHIFT 4
-#define GEN6_MULTISAMPLE_DW1_NUM_SAMPLES__MASK 0x0000000e
-#define GEN6_MULTISAMPLE_DW1_NUM_SAMPLES__SHIFT 1
-
-
-
-#define GEN8_3DSTATE_SAMPLE_PATTERN__SIZE 9
-
-
-
-
-
-#define GEN8_SAMPLE_PATTERN_DW8_1X__MASK 0x00ff0000
-#define GEN8_SAMPLE_PATTERN_DW8_1X__SHIFT 16
-#define GEN8_SAMPLE_PATTERN_DW8_2X__MASK 0x0000ffff
-#define GEN8_SAMPLE_PATTERN_DW8_2X__SHIFT 0
-
-#define GEN6_3DSTATE_STENCIL_BUFFER__SIZE 5
-
-
-#define GEN75_STENCIL_DW1_STENCIL_BUFFER_ENABLE (0x1 << 31)
-#define GEN6_STENCIL_DW1_MOCS__MASK 0x1e000000
-#define GEN6_STENCIL_DW1_MOCS__SHIFT 25
-#define GEN8_STENCIL_DW1_MOCS__MASK 0x1fc00000
-#define GEN8_STENCIL_DW1_MOCS__SHIFT 22
-#define GEN6_STENCIL_DW1_PITCH__MASK 0x0001ffff
-#define GEN6_STENCIL_DW1_PITCH__SHIFT 0
-
-
-
-#define GEN8_STENCIL_DW4_QPITCH__MASK 0x00007fff
-#define GEN8_STENCIL_DW4_QPITCH__SHIFT 0
-#define GEN8_STENCIL_DW4_QPITCH__SHR 2
-
-#define GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE 5
-
-
-#define GEN6_HIZ_DW1_MOCS__MASK 0x1e000000
-#define GEN6_HIZ_DW1_MOCS__SHIFT 25
-#define GEN8_HIZ_DW1_MOCS__MASK 0xfe000000
-#define GEN8_HIZ_DW1_MOCS__SHIFT 25
-#define GEN6_HIZ_DW1_PITCH__MASK 0x0001ffff
-#define GEN6_HIZ_DW1_PITCH__SHIFT 0
-
-
-
-#define GEN8_HIZ_DW4_QPITCH__MASK 0x00007fff
-#define GEN8_HIZ_DW4_QPITCH__SHIFT 0
-#define GEN8_HIZ_DW4_QPITCH__SHR 2
-
-#define GEN6_3DSTATE_CLEAR_PARAMS__SIZE 3
-
-#define GEN6_CLEAR_PARAMS_DW0_VALID (0x1 << 15)
-
-
-
-#define GEN7_CLEAR_PARAMS_DW2_VALID (0x1 << 0)
-
-#define GEN6_3DPRIMITIVE__SIZE 7
-
-#define GEN6_3DPRIM_DW0_ACCESS__MASK 0x00008000
-#define GEN6_3DPRIM_DW0_ACCESS__SHIFT 15
-#define GEN6_3DPRIM_DW0_ACCESS_SEQUENTIAL (0x0 << 15)
-#define GEN6_3DPRIM_DW0_ACCESS_RANDOM (0x1 << 15)
-#define GEN6_3DPRIM_DW0_TYPE__MASK 0x00007c00
-#define GEN6_3DPRIM_DW0_TYPE__SHIFT 10
-#define GEN6_3DPRIM_DW0_USE_INTERNAL_VERTEX_COUNT (0x1 << 9)
-
-
-
-
-
-
-
-#define GEN7_3DPRIM_DW0_INDIRECT_PARAM_ENABLE (0x1 << 10)
-#define GEN75_3DPRIM_DW0_UAV_COHERENCY_REQUIRED (0x1 << 9)
-#define GEN7_3DPRIM_DW0_PREDICATE_ENABLE (0x1 << 8)
-
-#define GEN7_3DPRIM_DW1_END_OFFSET_ENABLE (0x1 << 9)
-#define GEN7_3DPRIM_DW1_ACCESS__MASK 0x00000100
-#define GEN7_3DPRIM_DW1_ACCESS__SHIFT 8
-#define GEN7_3DPRIM_DW1_ACCESS_SEQUENTIAL (0x0 << 8)
-#define GEN7_3DPRIM_DW1_ACCESS_RANDOM (0x1 << 8)
-#define GEN7_3DPRIM_DW1_TYPE__MASK 0x0000003f
-#define GEN7_3DPRIM_DW1_TYPE__SHIFT 0
-
-
-
-
-
-
-
-#endif /* GEN_RENDER_3D_XML */
+++ /dev/null
-#ifndef GEN_RENDER_DYNAMIC_XML
-#define GEN_RENDER_DYNAMIC_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-https://github.com/olvaffe/envytools/
-git clone https://github.com/olvaffe/envytools.git
-
-Copyright (C) 2014-2015 by the following authors:
-- Chia-I Wu <olvaffe@gmail.com> (olv)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-enum gen_compare_function {
- GEN6_COMPAREFUNCTION_ALWAYS = 0x0,
- GEN6_COMPAREFUNCTION_NEVER = 0x1,
- GEN6_COMPAREFUNCTION_LESS = 0x2,
- GEN6_COMPAREFUNCTION_EQUAL = 0x3,
- GEN6_COMPAREFUNCTION_LEQUAL = 0x4,
- GEN6_COMPAREFUNCTION_GREATER = 0x5,
- GEN6_COMPAREFUNCTION_NOTEQUAL = 0x6,
- GEN6_COMPAREFUNCTION_GEQUAL = 0x7,
-};
-
-enum gen_stencil_op {
- GEN6_STENCILOP_KEEP = 0x0,
- GEN6_STENCILOP_ZERO = 0x1,
- GEN6_STENCILOP_REPLACE = 0x2,
- GEN6_STENCILOP_INCRSAT = 0x3,
- GEN6_STENCILOP_DECRSAT = 0x4,
- GEN6_STENCILOP_INCR = 0x5,
- GEN6_STENCILOP_DECR = 0x6,
- GEN6_STENCILOP_INVERT = 0x7,
-};
-
-enum gen_blend_factor {
- GEN6_BLENDFACTOR_ONE = 0x1,
- GEN6_BLENDFACTOR_SRC_COLOR = 0x2,
- GEN6_BLENDFACTOR_SRC_ALPHA = 0x3,
- GEN6_BLENDFACTOR_DST_ALPHA = 0x4,
- GEN6_BLENDFACTOR_DST_COLOR = 0x5,
- GEN6_BLENDFACTOR_SRC_ALPHA_SATURATE = 0x6,
- GEN6_BLENDFACTOR_CONST_COLOR = 0x7,
- GEN6_BLENDFACTOR_CONST_ALPHA = 0x8,
- GEN6_BLENDFACTOR_SRC1_COLOR = 0x9,
- GEN6_BLENDFACTOR_SRC1_ALPHA = 0xa,
- GEN6_BLENDFACTOR_ZERO = 0x11,
- GEN6_BLENDFACTOR_INV_SRC_COLOR = 0x12,
- GEN6_BLENDFACTOR_INV_SRC_ALPHA = 0x13,
- GEN6_BLENDFACTOR_INV_DST_ALPHA = 0x14,
- GEN6_BLENDFACTOR_INV_DST_COLOR = 0x15,
- GEN6_BLENDFACTOR_INV_CONST_COLOR = 0x17,
- GEN6_BLENDFACTOR_INV_CONST_ALPHA = 0x18,
- GEN6_BLENDFACTOR_INV_SRC1_COLOR = 0x19,
- GEN6_BLENDFACTOR_INV_SRC1_ALPHA = 0x1a,
-};
-
-enum gen_blend_function {
- GEN6_BLENDFUNCTION_ADD = 0x0,
- GEN6_BLENDFUNCTION_SUBTRACT = 0x1,
- GEN6_BLENDFUNCTION_REVERSE_SUBTRACT = 0x2,
- GEN6_BLENDFUNCTION_MIN = 0x3,
- GEN6_BLENDFUNCTION_MAX = 0x4,
-};
-
-enum gen_logic_op {
- GEN6_LOGICOP_CLEAR = 0x0,
- GEN6_LOGICOP_NOR = 0x1,
- GEN6_LOGICOP_AND_INVERTED = 0x2,
- GEN6_LOGICOP_COPY_INVERTED = 0x3,
- GEN6_LOGICOP_AND_REVERSE = 0x4,
- GEN6_LOGICOP_INVERT = 0x5,
- GEN6_LOGICOP_XOR = 0x6,
- GEN6_LOGICOP_NAND = 0x7,
- GEN6_LOGICOP_AND = 0x8,
- GEN6_LOGICOP_EQUIV = 0x9,
- GEN6_LOGICOP_NOOP = 0xa,
- GEN6_LOGICOP_OR_INVERTED = 0xb,
- GEN6_LOGICOP_COPY = 0xc,
- GEN6_LOGICOP_OR_REVERSE = 0xd,
- GEN6_LOGICOP_OR = 0xe,
- GEN6_LOGICOP_SET = 0xf,
-};
-
-enum gen_mip_filter {
- GEN6_MIPFILTER_NONE = 0x0,
- GEN6_MIPFILTER_NEAREST = 0x1,
- GEN6_MIPFILTER_LINEAR = 0x3,
-};
-
-enum gen_map_filter {
- GEN6_MAPFILTER_NEAREST = 0x0,
- GEN6_MAPFILTER_LINEAR = 0x1,
- GEN6_MAPFILTER_ANISOTROPIC = 0x2,
- GEN6_MAPFILTER_MONO = 0x6,
-};
-
-enum gen_prefilter_op {
- GEN6_PREFILTEROP_ALWAYS = 0x0,
- GEN6_PREFILTEROP_NEVER = 0x1,
- GEN6_PREFILTEROP_LESS = 0x2,
- GEN6_PREFILTEROP_EQUAL = 0x3,
- GEN6_PREFILTEROP_LEQUAL = 0x4,
- GEN6_PREFILTEROP_GREATER = 0x5,
- GEN6_PREFILTEROP_NOTEQUAL = 0x6,
- GEN6_PREFILTEROP_GEQUAL = 0x7,
-};
-
-enum gen_aniso_ratio {
- GEN6_ANISORATIO_2 = 0x0,
- GEN6_ANISORATIO_4 = 0x1,
- GEN6_ANISORATIO_6 = 0x2,
- GEN6_ANISORATIO_8 = 0x3,
- GEN6_ANISORATIO_10 = 0x4,
- GEN6_ANISORATIO_12 = 0x5,
- GEN6_ANISORATIO_14 = 0x6,
- GEN6_ANISORATIO_16 = 0x7,
-};
-
-enum gen_texcoord_mode {
- GEN6_TEXCOORDMODE_WRAP = 0x0,
- GEN6_TEXCOORDMODE_MIRROR = 0x1,
- GEN6_TEXCOORDMODE_CLAMP = 0x2,
- GEN6_TEXCOORDMODE_CUBE = 0x3,
- GEN6_TEXCOORDMODE_CLAMP_BORDER = 0x4,
- GEN6_TEXCOORDMODE_MIRROR_ONCE = 0x5,
- GEN8_TEXCOORDMODE_HALF_BORDER = 0x6,
-};
-
-enum gen_key_filter {
- GEN6_KEYFILTER_KILL_ON_ANY_MATCH = 0x0,
- GEN6_KEYFILTER_REPLACE_BLACK = 0x1,
-};
-
-#define GEN6_COLOR_CALC_STATE__SIZE 6
-
-#define GEN6_CC_DW0_STENCIL_REF__MASK 0xff000000
-#define GEN6_CC_DW0_STENCIL_REF__SHIFT 24
-#define GEN6_CC_DW0_STENCIL1_REF__MASK 0x00ff0000
-#define GEN6_CC_DW0_STENCIL1_REF__SHIFT 16
-#define GEN6_CC_DW0_ROUND_DISABLE_DISABLE (0x1 << 15)
-#define GEN6_CC_DW0_ALPHATEST__MASK 0x00000001
-#define GEN6_CC_DW0_ALPHATEST__SHIFT 0
-#define GEN6_CC_DW0_ALPHATEST_UNORM8 0x0
-#define GEN6_CC_DW0_ALPHATEST_FLOAT32 0x1
-
-
-
-
-
-
-#define GEN6_DEPTH_STENCIL_STATE__SIZE 3
-
-#define GEN6_ZS_DW0_STENCIL_TEST_ENABLE (0x1 << 31)
-#define GEN6_ZS_DW0_STENCIL_FUNC__MASK 0x70000000
-#define GEN6_ZS_DW0_STENCIL_FUNC__SHIFT 28
-#define GEN6_ZS_DW0_STENCIL_FAIL_OP__MASK 0x0e000000
-#define GEN6_ZS_DW0_STENCIL_FAIL_OP__SHIFT 25
-#define GEN6_ZS_DW0_STENCIL_ZFAIL_OP__MASK 0x01c00000
-#define GEN6_ZS_DW0_STENCIL_ZFAIL_OP__SHIFT 22
-#define GEN6_ZS_DW0_STENCIL_ZPASS_OP__MASK 0x00380000
-#define GEN6_ZS_DW0_STENCIL_ZPASS_OP__SHIFT 19
-#define GEN6_ZS_DW0_STENCIL_WRITE_ENABLE (0x1 << 18)
-#define GEN6_ZS_DW0_STENCIL1_ENABLE (0x1 << 15)
-#define GEN6_ZS_DW0_STENCIL1_FUNC__MASK 0x00007000
-#define GEN6_ZS_DW0_STENCIL1_FUNC__SHIFT 12
-#define GEN6_ZS_DW0_STENCIL1_FAIL_OP__MASK 0x00000e00
-#define GEN6_ZS_DW0_STENCIL1_FAIL_OP__SHIFT 9
-#define GEN6_ZS_DW0_STENCIL1_ZFAIL_OP__MASK 0x000001c0
-#define GEN6_ZS_DW0_STENCIL1_ZFAIL_OP__SHIFT 6
-#define GEN6_ZS_DW0_STENCIL1_ZPASS_OP__MASK 0x00000038
-#define GEN6_ZS_DW0_STENCIL1_ZPASS_OP__SHIFT 3
-
-#define GEN6_ZS_DW1_STENCIL_TEST_MASK__MASK 0xff000000
-#define GEN6_ZS_DW1_STENCIL_TEST_MASK__SHIFT 24
-#define GEN6_ZS_DW1_STENCIL_WRITE_MASK__MASK 0x00ff0000
-#define GEN6_ZS_DW1_STENCIL_WRITE_MASK__SHIFT 16
-#define GEN6_ZS_DW1_STENCIL1_TEST_MASK__MASK 0x0000ff00
-#define GEN6_ZS_DW1_STENCIL1_TEST_MASK__SHIFT 8
-#define GEN6_ZS_DW1_STENCIL1_WRITE_MASK__MASK 0x000000ff
-#define GEN6_ZS_DW1_STENCIL1_WRITE_MASK__SHIFT 0
-
-#define GEN6_ZS_DW2_DEPTH_TEST_ENABLE (0x1 << 31)
-#define GEN6_ZS_DW2_DEPTH_FUNC__MASK 0x38000000
-#define GEN6_ZS_DW2_DEPTH_FUNC__SHIFT 27
-#define GEN6_ZS_DW2_DEPTH_WRITE_ENABLE (0x1 << 26)
-
-#define GEN6_BLEND_STATE__SIZE 17
-
-
-#define GEN6_RT_DW0_BLEND_ENABLE (0x1 << 31)
-#define GEN6_RT_DW0_INDEPENDENT_ALPHA_ENABLE (0x1 << 30)
-#define GEN6_RT_DW0_ALPHA_FUNC__MASK 0x1c000000
-#define GEN6_RT_DW0_ALPHA_FUNC__SHIFT 26
-#define GEN6_RT_DW0_SRC_ALPHA_FACTOR__MASK 0x01f00000
-#define GEN6_RT_DW0_SRC_ALPHA_FACTOR__SHIFT 20
-#define GEN6_RT_DW0_DST_ALPHA_FACTOR__MASK 0x000f8000
-#define GEN6_RT_DW0_DST_ALPHA_FACTOR__SHIFT 15
-#define GEN6_RT_DW0_COLOR_FUNC__MASK 0x00003800
-#define GEN6_RT_DW0_COLOR_FUNC__SHIFT 11
-#define GEN6_RT_DW0_SRC_COLOR_FACTOR__MASK 0x000003e0
-#define GEN6_RT_DW0_SRC_COLOR_FACTOR__SHIFT 5
-#define GEN6_RT_DW0_DST_COLOR_FACTOR__MASK 0x0000001f
-#define GEN6_RT_DW0_DST_COLOR_FACTOR__SHIFT 0
-
-#define GEN6_RT_DW1_ALPHA_TO_COVERAGE (0x1 << 31)
-#define GEN6_RT_DW1_ALPHA_TO_ONE (0x1 << 30)
-#define GEN6_RT_DW1_ALPHA_TO_COVERAGE_DITHER (0x1 << 29)
-#define GEN6_RT_DW1_WRITE_DISABLES__MASK 0x0f000000
-#define GEN6_RT_DW1_WRITE_DISABLES__SHIFT 24
-#define GEN6_RT_DW1_WRITE_DISABLES_A (0x1 << 27)
-#define GEN6_RT_DW1_WRITE_DISABLES_R (0x1 << 26)
-#define GEN6_RT_DW1_WRITE_DISABLES_G (0x1 << 25)
-#define GEN6_RT_DW1_WRITE_DISABLES_B (0x1 << 24)
-#define GEN6_RT_DW1_LOGICOP_ENABLE (0x1 << 22)
-#define GEN6_RT_DW1_LOGICOP_FUNC__MASK 0x003c0000
-#define GEN6_RT_DW1_LOGICOP_FUNC__SHIFT 18
-#define GEN6_RT_DW1_ALPHA_TEST_ENABLE (0x1 << 16)
-#define GEN6_RT_DW1_ALPHA_TEST_FUNC__MASK 0x0000e000
-#define GEN6_RT_DW1_ALPHA_TEST_FUNC__SHIFT 13
-#define GEN6_RT_DW1_DITHER_ENABLE (0x1 << 12)
-#define GEN6_RT_DW1_X_DITHER_OFFSET__MASK 0x00000c00
-#define GEN6_RT_DW1_X_DITHER_OFFSET__SHIFT 10
-#define GEN6_RT_DW1_Y_DITHER_OFFSET__MASK 0x00000300
-#define GEN6_RT_DW1_Y_DITHER_OFFSET__SHIFT 8
-#define GEN6_RT_DW1_COLORCLAMP__MASK 0x0000000c
-#define GEN6_RT_DW1_COLORCLAMP__SHIFT 2
-#define GEN6_RT_DW1_COLORCLAMP_UNORM (0x0 << 2)
-#define GEN6_RT_DW1_COLORCLAMP_SNORM (0x1 << 2)
-#define GEN6_RT_DW1_COLORCLAMP_RTFORMAT (0x2 << 2)
-#define GEN6_RT_DW1_PRE_BLEND_CLAMP (0x1 << 1)
-#define GEN6_RT_DW1_POST_BLEND_CLAMP (0x1 << 0)
-
-
-#define GEN8_BLEND_DW0_ALPHA_TO_COVERAGE (0x1 << 31)
-#define GEN8_BLEND_DW0_INDEPENDENT_ALPHA_ENABLE (0x1 << 30)
-#define GEN8_BLEND_DW0_ALPHA_TO_ONE (0x1 << 29)
-#define GEN8_BLEND_DW0_ALPHA_TO_COVERAGE_DITHER (0x1 << 28)
-#define GEN8_BLEND_DW0_ALPHA_TEST_ENABLE (0x1 << 27)
-#define GEN8_BLEND_DW0_ALPHA_TEST_FUNC__MASK 0x07000000
-#define GEN8_BLEND_DW0_ALPHA_TEST_FUNC__SHIFT 24
-#define GEN8_BLEND_DW0_DITHER_ENABLE (0x1 << 23)
-#define GEN8_BLEND_DW0_X_DITHER_OFFSET__MASK 0x00600000
-#define GEN8_BLEND_DW0_X_DITHER_OFFSET__SHIFT 21
-#define GEN8_BLEND_DW0_Y_DITHER_OFFSET__MASK 0x00180000
-#define GEN8_BLEND_DW0_Y_DITHER_OFFSET__SHIFT 19
-
-
-#define GEN8_RT_DW0_BLEND_ENABLE (0x1 << 31)
-#define GEN8_RT_DW0_SRC_COLOR_FACTOR__MASK 0x7c000000
-#define GEN8_RT_DW0_SRC_COLOR_FACTOR__SHIFT 26
-#define GEN8_RT_DW0_DST_COLOR_FACTOR__MASK 0x03e00000
-#define GEN8_RT_DW0_DST_COLOR_FACTOR__SHIFT 21
-#define GEN8_RT_DW0_COLOR_FUNC__MASK 0x001c0000
-#define GEN8_RT_DW0_COLOR_FUNC__SHIFT 18
-#define GEN8_RT_DW0_SRC_ALPHA_FACTOR__MASK 0x0003e000
-#define GEN8_RT_DW0_SRC_ALPHA_FACTOR__SHIFT 13
-#define GEN8_RT_DW0_DST_ALPHA_FACTOR__MASK 0x00001f00
-#define GEN8_RT_DW0_DST_ALPHA_FACTOR__SHIFT 8
-#define GEN8_RT_DW0_ALPHA_FUNC__MASK 0x000000e0
-#define GEN8_RT_DW0_ALPHA_FUNC__SHIFT 5
-#define GEN8_RT_DW0_WRITE_DISABLES__MASK 0x0000000f
-#define GEN8_RT_DW0_WRITE_DISABLES__SHIFT 0
-#define GEN8_RT_DW0_WRITE_DISABLES_A (0x1 << 3)
-#define GEN8_RT_DW0_WRITE_DISABLES_R (0x1 << 2)
-#define GEN8_RT_DW0_WRITE_DISABLES_G (0x1 << 1)
-#define GEN8_RT_DW0_WRITE_DISABLES_B (0x1 << 0)
-
-#define GEN8_RT_DW1_LOGICOP_ENABLE (0x1 << 31)
-#define GEN8_RT_DW1_LOGICOP_FUNC__MASK 0x78000000
-#define GEN8_RT_DW1_LOGICOP_FUNC__SHIFT 27
-#define GEN8_RT_DW1_PRE_BLEND_CLAMP_SRC_ONLY (0x1 << 4)
-#define GEN8_RT_DW1_COLORCLAMP__MASK 0x0000000c
-#define GEN8_RT_DW1_COLORCLAMP__SHIFT 2
-#define GEN8_RT_DW1_COLORCLAMP_UNORM (0x0 << 2)
-#define GEN8_RT_DW1_COLORCLAMP_SNORM (0x1 << 2)
-#define GEN8_RT_DW1_COLORCLAMP_RTFORMAT (0x2 << 2)
-#define GEN8_RT_DW1_PRE_BLEND_CLAMP (0x1 << 1)
-#define GEN8_RT_DW1_POST_BLEND_CLAMP (0x1 << 0)
-
-#define GEN6_CLIP_VIEWPORT__SIZE 64
-
-
-
-
-
-
-#define GEN6_SF_VIEWPORT__SIZE 128
-
-
-
-
-
-
-
-
-
-
-#define GEN7_SF_CLIP_VIEWPORT__SIZE 256
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-#define GEN6_CC_VIEWPORT__SIZE 32
-
-
-
-
-#define GEN6_SCISSOR_RECT__SIZE 32
-
-
-#define GEN6_SCISSOR_DW0_MIN_Y__MASK 0xffff0000
-#define GEN6_SCISSOR_DW0_MIN_Y__SHIFT 16
-#define GEN6_SCISSOR_DW0_MIN_X__MASK 0x0000ffff
-#define GEN6_SCISSOR_DW0_MIN_X__SHIFT 0
-
-#define GEN6_SCISSOR_DW1_MAX_Y__MASK 0xffff0000
-#define GEN6_SCISSOR_DW1_MAX_Y__SHIFT 16
-#define GEN6_SCISSOR_DW1_MAX_X__MASK 0x0000ffff
-#define GEN6_SCISSOR_DW1_MAX_X__SHIFT 0
-
-#define GEN6_SAMPLER_BORDER_COLOR_STATE__SIZE 20
-
-#define GEN6_BORDER_COLOR_DW0_A__MASK 0xff000000
-#define GEN6_BORDER_COLOR_DW0_A__SHIFT 24
-#define GEN6_BORDER_COLOR_DW0_B__MASK 0x00ff0000
-#define GEN6_BORDER_COLOR_DW0_B__SHIFT 16
-#define GEN6_BORDER_COLOR_DW0_G__MASK 0x0000ff00
-#define GEN6_BORDER_COLOR_DW0_G__SHIFT 8
-#define GEN6_BORDER_COLOR_DW0_R__MASK 0x000000ff
-#define GEN6_BORDER_COLOR_DW0_R__SHIFT 0
-
-
-
-
-
-#define GEN6_BORDER_COLOR_DW5_G__MASK 0xffff0000
-#define GEN6_BORDER_COLOR_DW5_G__SHIFT 16
-#define GEN6_BORDER_COLOR_DW5_R__MASK 0x0000ffff
-#define GEN6_BORDER_COLOR_DW5_R__SHIFT 0
-
-#define GEN6_BORDER_COLOR_DW6_A__MASK 0xffff0000
-#define GEN6_BORDER_COLOR_DW6_A__SHIFT 16
-#define GEN6_BORDER_COLOR_DW6_B__MASK 0x0000ffff
-#define GEN6_BORDER_COLOR_DW6_B__SHIFT 0
-
-#define GEN6_BORDER_COLOR_DW7_G__MASK 0xffff0000
-#define GEN6_BORDER_COLOR_DW7_G__SHIFT 16
-#define GEN6_BORDER_COLOR_DW7_R__MASK 0x0000ffff
-#define GEN6_BORDER_COLOR_DW7_R__SHIFT 0
-
-#define GEN6_BORDER_COLOR_DW8_A__MASK 0xffff0000
-#define GEN6_BORDER_COLOR_DW8_A__SHIFT 16
-#define GEN6_BORDER_COLOR_DW8_B__MASK 0x0000ffff
-#define GEN6_BORDER_COLOR_DW8_B__SHIFT 0
-
-#define GEN6_BORDER_COLOR_DW9_G__MASK 0xffff0000
-#define GEN6_BORDER_COLOR_DW9_G__SHIFT 16
-#define GEN6_BORDER_COLOR_DW9_R__MASK 0x0000ffff
-#define GEN6_BORDER_COLOR_DW9_R__SHIFT 0
-
-#define GEN6_BORDER_COLOR_DW10_A__MASK 0xffff0000
-#define GEN6_BORDER_COLOR_DW10_A__SHIFT 16
-#define GEN6_BORDER_COLOR_DW10_B__MASK 0x0000ffff
-#define GEN6_BORDER_COLOR_DW10_B__SHIFT 0
-
-#define GEN6_BORDER_COLOR_DW11_A__MASK 0xff000000
-#define GEN6_BORDER_COLOR_DW11_A__SHIFT 24
-#define GEN6_BORDER_COLOR_DW11_B__MASK 0x00ff0000
-#define GEN6_BORDER_COLOR_DW11_B__SHIFT 16
-#define GEN6_BORDER_COLOR_DW11_G__MASK 0x0000ff00
-#define GEN6_BORDER_COLOR_DW11_G__SHIFT 8
-#define GEN6_BORDER_COLOR_DW11_R__MASK 0x000000ff
-#define GEN6_BORDER_COLOR_DW11_R__SHIFT 0
-
-
-
-
-
-
-
-
-#define GEN6_SAMPLER_STATE__SIZE 4
-
-#define GEN6_SAMPLER_DW0_DISABLE (0x1 << 31)
-#define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE__MASK 0x20000000
-#define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE__SHIFT 29
-#define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE_DX10_OGL (0x0 << 29)
-#define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE_DX9 (0x1 << 29)
-#define GEN6_SAMPLER_DW0_LOD_PRECLAMP_ENABLE (0x1 << 28)
-#define GEN6_SAMPLER_DW0_MIN_MAG_NOT_EQUAL (0x1 << 27)
-#define GEN8_SAMPLER_DW0_LOD_PRECLAMP_MODE__MASK 0x18000000
-#define GEN8_SAMPLER_DW0_LOD_PRECLAMP_MODE__SHIFT 27
-#define GEN8_SAMPLER_DW0_LOD_PRECLAMP_MODE_NONE (0x0 << 27)
-#define GEN8_SAMPLER_DW0_LOD_PRECLAMP_MODE_OGL (0x2 << 27)
-#define GEN6_SAMPLER_DW0_BASE_LOD__MASK 0x07c00000
-#define GEN6_SAMPLER_DW0_BASE_LOD__SHIFT 22
-#define GEN6_SAMPLER_DW0_BASE_LOD__RADIX 1
-#define GEN6_SAMPLER_DW0_MIP_FILTER__MASK 0x00300000
-#define GEN6_SAMPLER_DW0_MIP_FILTER__SHIFT 20
-#define GEN6_SAMPLER_DW0_MAG_FILTER__MASK 0x000e0000
-#define GEN6_SAMPLER_DW0_MAG_FILTER__SHIFT 17
-#define GEN6_SAMPLER_DW0_MIN_FILTER__MASK 0x0001c000
-#define GEN6_SAMPLER_DW0_MIN_FILTER__SHIFT 14
-#define GEN6_SAMPLER_DW0_LOD_BIAS__MASK 0x00003ff8
-#define GEN6_SAMPLER_DW0_LOD_BIAS__SHIFT 3
-#define GEN6_SAMPLER_DW0_LOD_BIAS__RADIX 6
-#define GEN6_SAMPLER_DW0_SHADOW_FUNC__MASK 0x00000007
-#define GEN6_SAMPLER_DW0_SHADOW_FUNC__SHIFT 0
-#define GEN7_SAMPLER_DW0_LOD_BIAS__MASK 0x00003ffe
-#define GEN7_SAMPLER_DW0_LOD_BIAS__SHIFT 1
-#define GEN7_SAMPLER_DW0_LOD_BIAS__RADIX 8
-#define GEN7_SAMPLER_DW0_ANISO_ALGO__MASK 0x00000001
-#define GEN7_SAMPLER_DW0_ANISO_ALGO__SHIFT 0
-#define GEN7_SAMPLER_DW0_ANISO_ALGO_LEGACY 0x0
-#define GEN7_SAMPLER_DW0_ANISO_ALGO_EWA 0x1
-
-#define GEN6_SAMPLER_DW1_MIN_LOD__MASK 0xffc00000
-#define GEN6_SAMPLER_DW1_MIN_LOD__SHIFT 22
-#define GEN6_SAMPLER_DW1_MIN_LOD__RADIX 6
-#define GEN6_SAMPLER_DW1_MAX_LOD__MASK 0x003ff000
-#define GEN6_SAMPLER_DW1_MAX_LOD__SHIFT 12
-#define GEN6_SAMPLER_DW1_MAX_LOD__RADIX 6
-#define GEN6_SAMPLER_DW1_CUBECTRLMODE__MASK 0x00000200
-#define GEN6_SAMPLER_DW1_CUBECTRLMODE__SHIFT 9
-#define GEN6_SAMPLER_DW1_CUBECTRLMODE_PROGRAMMED (0x0 << 9)
-#define GEN6_SAMPLER_DW1_CUBECTRLMODE_OVERRIDE (0x1 << 9)
-#define GEN6_SAMPLER_DW1_U_WRAP__MASK 0x000001c0
-#define GEN6_SAMPLER_DW1_U_WRAP__SHIFT 6
-#define GEN6_SAMPLER_DW1_V_WRAP__MASK 0x00000038
-#define GEN6_SAMPLER_DW1_V_WRAP__SHIFT 3
-#define GEN6_SAMPLER_DW1_R_WRAP__MASK 0x00000007
-#define GEN6_SAMPLER_DW1_R_WRAP__SHIFT 0
-
-#define GEN7_SAMPLER_DW1_MIN_LOD__MASK 0xfff00000
-#define GEN7_SAMPLER_DW1_MIN_LOD__SHIFT 20
-#define GEN7_SAMPLER_DW1_MIN_LOD__RADIX 8
-#define GEN7_SAMPLER_DW1_MAX_LOD__MASK 0x000fff00
-#define GEN7_SAMPLER_DW1_MAX_LOD__SHIFT 8
-#define GEN7_SAMPLER_DW1_MAX_LOD__RADIX 8
-#define GEN8_SAMPLER_DW1_CHROMAKEY_ENABLE (0x1 << 7)
-#define GEN8_SAMPLER_DW1_CHROMAKEY_INDEX__MASK 0x00000060
-#define GEN8_SAMPLER_DW1_CHROMAKEY_INDEX__SHIFT 5
-#define GEN8_SAMPLER_DW1_CHROMAKEY_MODE__MASK 0x00000010
-#define GEN8_SAMPLER_DW1_CHROMAKEY_MODE__SHIFT 4
-#define GEN7_SAMPLER_DW1_SHADOW_FUNC__MASK 0x0000000e
-#define GEN7_SAMPLER_DW1_SHADOW_FUNC__SHIFT 1
-#define GEN7_SAMPLER_DW1_CUBECTRLMODE__MASK 0x00000001
-#define GEN7_SAMPLER_DW1_CUBECTRLMODE__SHIFT 0
-#define GEN7_SAMPLER_DW1_CUBECTRLMODE_PROGRAMMED 0x0
-#define GEN7_SAMPLER_DW1_CUBECTRLMODE_OVERRIDE 0x1
-
-#define GEN6_SAMPLER_DW2_BORDER_COLOR_ADDR__MASK 0xffffffe0
-#define GEN6_SAMPLER_DW2_BORDER_COLOR_ADDR__SHIFT 5
-#define GEN6_SAMPLER_DW2_BORDER_COLOR_ADDR__SHR 5
-
-#define GEN8_SAMPLER_DW2_INDIRECT_STATE_ADDR__MASK 0x00ffffc0
-#define GEN8_SAMPLER_DW2_INDIRECT_STATE_ADDR__SHIFT 6
-#define GEN8_SAMPLER_DW2_INDIRECT_STATE_ADDR__SHR 6
-#define GEN8_SAMPLER_DW2_LOD_CLAMP_MAG_MODE (0x1 << 0)
-
-#define GEN6_SAMPLER_DW3_CHROMAKEY_ENABLE (0x1 << 25)
-#define GEN6_SAMPLER_DW3_CHROMAKEY_INDEX__MASK 0x01800000
-#define GEN6_SAMPLER_DW3_CHROMAKEY_INDEX__SHIFT 23
-#define GEN6_SAMPLER_DW3_CHROMAKEY_MODE__MASK 0x00400000
-#define GEN6_SAMPLER_DW3_CHROMAKEY_MODE__SHIFT 22
-#define GEN6_SAMPLER_DW3_MAX_ANISO__MASK 0x00380000
-#define GEN6_SAMPLER_DW3_MAX_ANISO__SHIFT 19
-#define GEN6_SAMPLER_DW3_U_MAG_ROUND (0x1 << 18)
-#define GEN6_SAMPLER_DW3_U_MIN_ROUND (0x1 << 17)
-#define GEN6_SAMPLER_DW3_V_MAG_ROUND (0x1 << 16)
-#define GEN6_SAMPLER_DW3_V_MIN_ROUND (0x1 << 15)
-#define GEN6_SAMPLER_DW3_R_MAG_ROUND (0x1 << 14)
-#define GEN6_SAMPLER_DW3_R_MIN_ROUND (0x1 << 13)
-#define GEN7_SAMPLER_DW3_TRIQUAL__MASK 0x00001800
-#define GEN7_SAMPLER_DW3_TRIQUAL__SHIFT 11
-#define GEN7_SAMPLER_DW3_TRIQUAL_FULL (0x0 << 11)
-#define GEN75_SAMPLER_DW3_TRIQUAL_HIGH (0x1 << 11)
-#define GEN7_SAMPLER_DW3_TRIQUAL_MED (0x2 << 11)
-#define GEN7_SAMPLER_DW3_TRIQUAL_LOW (0x3 << 11)
-#define GEN7_SAMPLER_DW3_NON_NORMALIZED_COORD (0x1 << 10)
-#define GEN7_SAMPLER_DW3_U_WRAP__MASK 0x000001c0
-#define GEN7_SAMPLER_DW3_U_WRAP__SHIFT 6
-#define GEN7_SAMPLER_DW3_V_WRAP__MASK 0x00000038
-#define GEN7_SAMPLER_DW3_V_WRAP__SHIFT 3
-#define GEN7_SAMPLER_DW3_R_WRAP__MASK 0x00000007
-#define GEN7_SAMPLER_DW3_R_WRAP__SHIFT 0
-#define GEN6_SAMPLER_DW3_NON_NORMALIZED_COORD (0x1 << 0)
-
-
-#endif /* GEN_RENDER_DYNAMIC_XML */
+++ /dev/null
-#ifndef GEN_RENDER_MEDIA_XML
-#define GEN_RENDER_MEDIA_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-https://github.com/olvaffe/envytools/
-git clone https://github.com/olvaffe/envytools.git
-
-Copyright (C) 2014-2015 by the following authors:
-- Chia-I Wu <olvaffe@gmail.com> (olv)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-#define GEN6_INTERFACE_DESCRIPTOR_DATA__SIZE 8
-
-#define GEN6_IDRT_DW0_KERNEL_ADDR__MASK 0xffffffc0
-#define GEN6_IDRT_DW0_KERNEL_ADDR__SHIFT 6
-#define GEN6_IDRT_DW0_KERNEL_ADDR__SHR 6
-
-#define GEN6_IDRT_DW1_SPF (0x1 << 18)
-#define GEN6_IDRT_DW1_PRIORITY_HIGH (0x1 << 17)
-#define GEN6_IDRT_DW1_FP_MODE_ALT (0x1 << 16)
-#define GEN6_IDRT_DW1_ILLEGAL_CODE_EXCEPTION (0x1 << 13)
-#define GEN6_IDRT_DW1_MASK_STACK_EXCEPTION (0x1 << 11)
-#define GEN6_IDRT_DW1_SOFTWARE_EXCEPTION (0x1 << 7)
-
-#define GEN6_IDRT_DW2_SAMPLER_COUNT__MASK 0x0000001c
-#define GEN6_IDRT_DW2_SAMPLER_COUNT__SHIFT 2
-#define GEN6_IDRT_DW2_SAMPLER_ADDR__MASK 0xffffffe0
-#define GEN6_IDRT_DW2_SAMPLER_ADDR__SHIFT 5
-#define GEN6_IDRT_DW2_SAMPLER_ADDR__SHR 5
-
-#define GEN6_IDRT_DW3_BINDING_TABLE_SIZE__MASK 0x0000001f
-#define GEN6_IDRT_DW3_BINDING_TABLE_SIZE__SHIFT 0
-
-#define GEN6_IDRT_DW4_CURBE_READ_LEN__MASK 0xffff0000
-#define GEN6_IDRT_DW4_CURBE_READ_LEN__SHIFT 16
-#define GEN6_IDRT_DW4_CURBE_READ_OFFSET__MASK 0x0000ffff
-#define GEN6_IDRT_DW4_CURBE_READ_OFFSET__SHIFT 0
-
-#define GEN6_IDRT_DW5_BARRIER_ID__MASK 0x0000000f
-#define GEN6_IDRT_DW5_BARRIER_ID__SHIFT 0
-
-#define GEN7_IDRT_DW5_BARRIER_RETURN_GRF__MASK 0xff000000
-#define GEN7_IDRT_DW5_BARRIER_RETURN_GRF__SHIFT 24
-#define GEN7_IDRT_DW5_ROUNDING_MODE__MASK 0x00c00000
-#define GEN7_IDRT_DW5_ROUNDING_MODE__SHIFT 22
-#define GEN7_IDRT_DW5_ROUNDING_MODE_RTNE (0x0 << 22)
-#define GEN7_IDRT_DW5_ROUNDING_MODE_RU (0x1 << 22)
-#define GEN7_IDRT_DW5_ROUNDING_MODE_RD (0x2 << 22)
-#define GEN7_IDRT_DW5_ROUNDING_MODE_RTZ (0x3 << 22)
-#define GEN7_IDRT_DW5_BARRIER_ENABLE (0x1 << 21)
-#define GEN7_IDRT_DW5_SLM_SIZE__MASK 0x001f0000
-#define GEN7_IDRT_DW5_SLM_SIZE__SHIFT 16
-#define GEN7_IDRT_DW5_BARRIER_RETURN_BYTE__MASK 0x0000ff00
-#define GEN7_IDRT_DW5_BARRIER_RETURN_BYTE__SHIFT 8
-#define GEN7_IDRT_DW5_THREAD_GROUP_SIZE__MASK 0x000000ff
-#define GEN7_IDRT_DW5_THREAD_GROUP_SIZE__SHIFT 0
-
-#define GEN75_IDRT_DW6_CROSS_THREAD_CURBE_READ_LEN__MASK 0x000000ff
-#define GEN75_IDRT_DW6_CROSS_THREAD_CURBE_READ_LEN__SHIFT 0
-
-
-
-#define GEN8_IDRT_DW0_KERNEL_ADDR__MASK 0xffffffc0
-#define GEN8_IDRT_DW0_KERNEL_ADDR__SHIFT 6
-#define GEN8_IDRT_DW0_KERNEL_ADDR__SHR 6
-
-
-#define GEN8_IDRT_DW2_THREAD_PREEMPTION_DISABLE (0x1 << 20)
-#define GEN8_IDRT_DW2_DENORM__MASK 0x00080000
-#define GEN8_IDRT_DW2_DENORM__SHIFT 19
-#define GEN8_IDRT_DW2_DENORM_FTZ (0x0 << 19)
-#define GEN8_IDRT_DW2_DENORM_RET (0x1 << 19)
-#define GEN8_IDRT_DW2_SPF (0x1 << 18)
-#define GEN8_IDRT_DW2_PRIORITY_HIGH (0x1 << 17)
-#define GEN8_IDRT_DW2_FP_MODE_ALT (0x1 << 16)
-#define GEN8_IDRT_DW2_ILLEGAL_CODE_EXCEPTION (0x1 << 13)
-#define GEN8_IDRT_DW2_MASK_STACK_EXCEPTION (0x1 << 11)
-#define GEN8_IDRT_DW2_SOFTWARE_EXCEPTION (0x1 << 7)
-
-#define GEN8_IDRT_DW3_SAMPLER_COUNT__MASK 0x0000001c
-#define GEN8_IDRT_DW3_SAMPLER_COUNT__SHIFT 2
-#define GEN8_IDRT_DW3_SAMPLER_ADDR__MASK 0xffffffe0
-#define GEN8_IDRT_DW3_SAMPLER_ADDR__SHIFT 5
-#define GEN8_IDRT_DW3_SAMPLER_ADDR__SHR 5
-
-#define GEN8_IDRT_DW4_BINDING_TABLE_SIZE__MASK 0x0000001f
-#define GEN8_IDRT_DW4_BINDING_TABLE_SIZE__SHIFT 0
-
-#define GEN8_IDRT_DW5_CURBE_READ_LEN__MASK 0xffff0000
-#define GEN8_IDRT_DW5_CURBE_READ_LEN__SHIFT 16
-#define GEN8_IDRT_DW5_CURBE_READ_OFFSET__MASK 0x0000ffff
-#define GEN8_IDRT_DW5_CURBE_READ_OFFSET__SHIFT 0
-
-#define GEN8_IDRT_DW6_ROUNDING_MODE__MASK 0x00c00000
-#define GEN8_IDRT_DW6_ROUNDING_MODE__SHIFT 22
-#define GEN8_IDRT_DW6_ROUNDING_MODE_RTNE (0x0 << 22)
-#define GEN8_IDRT_DW6_ROUNDING_MODE_RU (0x1 << 22)
-#define GEN8_IDRT_DW6_ROUNDING_MODE_RD (0x2 << 22)
-#define GEN8_IDRT_DW6_ROUNDING_MODE_RTZ (0x3 << 22)
-#define GEN8_IDRT_DW6_BARRIER_ENABLE (0x1 << 21)
-#define GEN8_IDRT_DW6_SLM_SIZE__MASK 0x001f0000
-#define GEN8_IDRT_DW6_SLM_SIZE__SHIFT 16
-#define GEN8_IDRT_DW6_THREAD_GROUP_SIZE__MASK 0x000003ff
-#define GEN8_IDRT_DW6_THREAD_GROUP_SIZE__SHIFT 0
-
-#define GEN8_IDRT_DW7_CROSS_THREAD_CURBE_READ_LEN__MASK 0x000000ff
-#define GEN8_IDRT_DW7_CROSS_THREAD_CURBE_READ_LEN__SHIFT 0
-
-#define GEN6_MEDIA_VFE_STATE__SIZE 9
-
-
-#define GEN6_VFE_DW1_SCRATCH_STACK_SIZE__MASK 0x000000f0
-#define GEN6_VFE_DW1_SCRATCH_STACK_SIZE__SHIFT 4
-#define GEN6_VFE_DW1_SCRATCH_SPACE_PER_THREAD__MASK 0x0000000f
-#define GEN6_VFE_DW1_SCRATCH_SPACE_PER_THREAD__SHIFT 0
-#define GEN6_VFE_DW1_SCRATCH_ADDR__MASK 0xfffffc00
-#define GEN6_VFE_DW1_SCRATCH_ADDR__SHIFT 10
-#define GEN6_VFE_DW1_SCRATCH_ADDR__SHR 10
-
-#define GEN6_VFE_DW2_MAX_THREADS__MASK 0xffff0000
-#define GEN6_VFE_DW2_MAX_THREADS__SHIFT 16
-#define GEN6_VFE_DW2_URB_ENTRY_COUNT__MASK 0x0000ff00
-#define GEN6_VFE_DW2_URB_ENTRY_COUNT__SHIFT 8
-#define GEN6_VFE_DW2_RESET_GATEWAY_TIMER (0x1 << 7)
-#define GEN6_VFE_DW2_BYPASS_GATEWAY_CONTROL (0x1 << 6)
-#define GEN6_VFE_DW2_FAST_PREEMPT (0x1 << 5)
-#define GEN7_VFE_DW2_GATEWAY_MMIO__MASK 0x00000018
-#define GEN7_VFE_DW2_GATEWAY_MMIO__SHIFT 3
-#define GEN7_VFE_DW2_GATEWAY_MMIO_NONE (0x0 << 3)
-#define GEN7_VFE_DW2_GATEWAY_MMIO_ANY (0x2 << 3)
-#define GEN7_VFE_DW2_GPGPU_MODE (0x1 << 2)
-
-#define GEN75_VFE_DW3_HALF_SLICE_DISABLE__MASK 0x00000003
-#define GEN75_VFE_DW3_HALF_SLICE_DISABLE__SHIFT 0
-#define GEN75_VFE_DW3_HALF_SLICE_DISABLE_NONE 0x0
-#define GEN75_VFE_DW3_HALF_SLICE_DISABLE_23 0x1
-#define GEN75_VFE_DW3_HALF_SLICE_DISABLE_123 0x3
-
-#define GEN6_VFE_DW4_URB_ENTRY_SIZE__MASK 0xffff0000
-#define GEN6_VFE_DW4_URB_ENTRY_SIZE__SHIFT 16
-#define GEN6_VFE_DW4_CURBE_SIZE__MASK 0x0000ffff
-#define GEN6_VFE_DW4_CURBE_SIZE__SHIFT 0
-
-#define GEN6_VFE_DW5_SCOREBOARD_ENABLE (0x1 << 31)
-#define GEN6_VFE_DW5_SCOREBOARD_TYPE__MASK 0x40000000
-#define GEN6_VFE_DW5_SCOREBOARD_TYPE__SHIFT 30
-#define GEN6_VFE_DW5_SCOREBOARD_TYPE_STALLING (0x0 << 30)
-#define GEN6_VFE_DW5_SCOREBOARD_TYPE_NON_STALLING (0x1 << 30)
-#define GEN6_VFE_DW5_SCOREBOARD_MASK__MASK 0x000000ff
-#define GEN6_VFE_DW5_SCOREBOARD_MASK__SHIFT 0
-
-
-
-
-#define GEN8_VFE_DW1_SCRATCH_STACK_SIZE__MASK 0x000000f0
-#define GEN8_VFE_DW1_SCRATCH_STACK_SIZE__SHIFT 4
-#define GEN8_VFE_DW1_SCRATCH_SPACE_PER_THREAD__MASK 0x0000000f
-#define GEN8_VFE_DW1_SCRATCH_SPACE_PER_THREAD__SHIFT 0
-#define GEN8_VFE_DW1_SCRATCH_ADDR__MASK 0xfffffc00
-#define GEN8_VFE_DW1_SCRATCH_ADDR__SHIFT 10
-#define GEN8_VFE_DW1_SCRATCH_ADDR__SHR 10
-
-
-#define GEN8_VFE_DW3_MAX_THREADS__MASK 0xffff0000
-#define GEN8_VFE_DW3_MAX_THREADS__SHIFT 16
-#define GEN8_VFE_DW3_URB_ENTRY_COUNT__MASK 0x0000ff00
-#define GEN8_VFE_DW3_URB_ENTRY_COUNT__SHIFT 8
-#define GEN8_VFE_DW3_RESET_GATEWAY_TIMER (0x1 << 7)
-#define GEN8_VFE_DW3_BYPASS_GATEWAY_CONTROL (0x1 << 6)
-
-#define GEN8_VFE_DW4_HALF_SLICE_DISABLE__MASK 0x00000003
-#define GEN8_VFE_DW4_HALF_SLICE_DISABLE__SHIFT 0
-#define GEN8_VFE_DW4_HALF_SLICE_DISABLE_NONE 0x0
-#define GEN8_VFE_DW4_HALF_SLICE_DISABLE_23 0x1
-#define GEN8_VFE_DW4_HALF_SLICE_DISABLE_123 0x3
-
-#define GEN8_VFE_DW5_URB_ENTRY_SIZE__MASK 0xffff0000
-#define GEN8_VFE_DW5_URB_ENTRY_SIZE__SHIFT 16
-#define GEN8_VFE_DW5_CURBE_SIZE__MASK 0x0000ffff
-#define GEN8_VFE_DW5_CURBE_SIZE__SHIFT 0
-
-#define GEN8_VFE_DW6_SCOREBOARD_ENABLE (0x1 << 31)
-#define GEN8_VFE_DW6_SCOREBOARD_TYPE__MASK 0x40000000
-#define GEN8_VFE_DW6_SCOREBOARD_TYPE__SHIFT 30
-#define GEN8_VFE_DW6_SCOREBOARD_TYPE_STALLING (0x0 << 30)
-#define GEN8_VFE_DW6_SCOREBOARD_TYPE_NON_STALLING (0x1 << 30)
-#define GEN8_VFE_DW6_SCOREBOARD_MASK__MASK 0x000000ff
-#define GEN8_VFE_DW6_SCOREBOARD_MASK__SHIFT 0
-
-
-#define GEN6_MEDIA_CURBE_LOAD__SIZE 4
-
-
-
-#define GEN6_CURBE_LOAD_DW2_LEN__MASK 0x0001ffff
-#define GEN6_CURBE_LOAD_DW2_LEN__SHIFT 0
-
-#define GEN6_CURBE_LOAD_DW3_ADDR__MASK 0xffffffe0
-#define GEN6_CURBE_LOAD_DW3_ADDR__SHIFT 5
-#define GEN6_CURBE_LOAD_DW3_ADDR__SHR 5
-
-#define GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD__SIZE 4
-
-
-
-#define GEN6_IDRT_LOAD_DW2_LEN__MASK 0x0001ffff
-#define GEN6_IDRT_LOAD_DW2_LEN__SHIFT 0
-
-#define GEN6_IDRT_LOAD_DW3_ADDR__MASK 0xffffffe0
-#define GEN6_IDRT_LOAD_DW3_ADDR__SHIFT 5
-#define GEN6_IDRT_LOAD_DW3_ADDR__SHR 5
-
-#define GEN6_MEDIA_STATE_FLUSH__SIZE 2
-
-
-#define GEN6_MEDIA_FLUSH_DW1_THREAD_COUNT_WATERMARK__MASK 0x00ff0000
-#define GEN6_MEDIA_FLUSH_DW1_THREAD_COUNT_WATERMARK__SHIFT 16
-#define GEN6_MEDIA_FLUSH_DW1_BARRIER_MASK__MASK 0x0000ffff
-#define GEN6_MEDIA_FLUSH_DW1_BARRIER_MASK__SHIFT 0
-
-#define GEN7_MEDIA_FLUSH_DW1_DISABLE_PREEMPTION (0x1 << 8)
-#define GEN75_MEDIA_FLUSH_DW1_FLUSH_TO_GO (0x1 << 7)
-#define GEN7_MEDIA_FLUSH_DW1_WATERMARK_REQUIRED (0x1 << 6)
-#define GEN7_MEDIA_FLUSH_DW1_IDRT_OFFSET__MASK 0x0000003f
-#define GEN7_MEDIA_FLUSH_DW1_IDRT_OFFSET__SHIFT 0
-
-#define GEN7_GPGPU_WALKER__SIZE 15
-
-#define GEN7_GPGPU_DW0_INDIRECT_PARAM_ENABLE (0x1 << 10)
-#define GEN7_GPGPU_DW0_PREDICATE_ENABLE (0x1 << 8)
-
-#define GEN7_GPGPU_DW1_IDRT_OFFSET__MASK 0x0000003f
-#define GEN7_GPGPU_DW1_IDRT_OFFSET__SHIFT 0
-
-#define GEN7_GPGPU_DW2_SIMD_SIZE__MASK 0xc0000000
-#define GEN7_GPGPU_DW2_SIMD_SIZE__SHIFT 30
-#define GEN7_GPGPU_DW2_SIMD_SIZE_SIMD8 (0x0 << 30)
-#define GEN7_GPGPU_DW2_SIMD_SIZE_SIMD16 (0x1 << 30)
-#define GEN7_GPGPU_DW2_SIMD_SIZE_SIMD32 (0x2 << 30)
-#define GEN7_GPGPU_DW2_THREAD_MAX_Z__MASK 0x003f0000
-#define GEN7_GPGPU_DW2_THREAD_MAX_Z__SHIFT 16
-#define GEN7_GPGPU_DW2_THREAD_MAX_Y__MASK 0x00003f00
-#define GEN7_GPGPU_DW2_THREAD_MAX_Y__SHIFT 8
-#define GEN7_GPGPU_DW2_THREAD_MAX_X__MASK 0x0000003f
-#define GEN7_GPGPU_DW2_THREAD_MAX_X__SHIFT 0
-
-
-
-
-
-
-
-
-
-
-#define GEN8_GPGPU_DW0_INDIRECT_PARAM_ENABLE (0x1 << 10)
-#define GEN8_GPGPU_DW0_PREDICATE_ENABLE (0x1 << 8)
-
-#define GEN8_GPGPU_DW1_IDRT_OFFSET__MASK 0x0000003f
-#define GEN8_GPGPU_DW1_IDRT_OFFSET__SHIFT 0
-
-#define GEN8_GPGPU_DW2_INDIRECT_LEN__MASK 0x0001ffff
-#define GEN8_GPGPU_DW2_INDIRECT_LEN__SHIFT 0
-
-#define GEN8_GPGPU_DW3_INDIRECT_ADDR__MASK 0xffffffe0
-#define GEN8_GPGPU_DW3_INDIRECT_ADDR__SHIFT 5
-#define GEN8_GPGPU_DW3_INDIRECT_ADDR__SHR 5
-
-#define GEN8_GPGPU_DW4_SIMD_SIZE__MASK 0xc0000000
-#define GEN8_GPGPU_DW4_SIMD_SIZE__SHIFT 30
-#define GEN8_GPGPU_DW4_SIMD_SIZE_SIMD8 (0x0 << 30)
-#define GEN8_GPGPU_DW4_SIMD_SIZE_SIMD16 (0x1 << 30)
-#define GEN8_GPGPU_DW4_SIMD_SIZE_SIMD32 (0x2 << 30)
-#define GEN8_GPGPU_DW4_THREAD_MAX_Z__MASK 0x003f0000
-#define GEN8_GPGPU_DW4_THREAD_MAX_Z__SHIFT 16
-#define GEN8_GPGPU_DW4_THREAD_MAX_Y__MASK 0x00003f00
-#define GEN8_GPGPU_DW4_THREAD_MAX_Y__SHIFT 8
-#define GEN8_GPGPU_DW4_THREAD_MAX_X__MASK 0x0000003f
-#define GEN8_GPGPU_DW4_THREAD_MAX_X__SHIFT 0
-
-
-
-
-
-
-
-
-
-
-
-
-#endif /* GEN_RENDER_MEDIA_XML */
+++ /dev/null
-#ifndef GEN_RENDER_SURFACE_XML
-#define GEN_RENDER_SURFACE_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-https://github.com/olvaffe/envytools/
-git clone https://github.com/olvaffe/envytools.git
-
-Copyright (C) 2014-2015 by the following authors:
-- Chia-I Wu <olvaffe@gmail.com> (olv)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-enum gen_surface_format {
- GEN6_FORMAT_R32G32B32A32_FLOAT = 0x0,
- GEN6_FORMAT_R32G32B32A32_SINT = 0x1,
- GEN6_FORMAT_R32G32B32A32_UINT = 0x2,
- GEN6_FORMAT_R32G32B32A32_UNORM = 0x3,
- GEN6_FORMAT_R32G32B32A32_SNORM = 0x4,
- GEN6_FORMAT_R64G64_FLOAT = 0x5,
- GEN6_FORMAT_R32G32B32X32_FLOAT = 0x6,
- GEN6_FORMAT_R32G32B32A32_SSCALED = 0x7,
- GEN6_FORMAT_R32G32B32A32_USCALED = 0x8,
- GEN6_FORMAT_R32G32B32A32_SFIXED = 0x20,
- GEN6_FORMAT_R64G64_PASSTHRU = 0x21,
- GEN6_FORMAT_R32G32B32_FLOAT = 0x40,
- GEN6_FORMAT_R32G32B32_SINT = 0x41,
- GEN6_FORMAT_R32G32B32_UINT = 0x42,
- GEN6_FORMAT_R32G32B32_UNORM = 0x43,
- GEN6_FORMAT_R32G32B32_SNORM = 0x44,
- GEN6_FORMAT_R32G32B32_SSCALED = 0x45,
- GEN6_FORMAT_R32G32B32_USCALED = 0x46,
- GEN6_FORMAT_R32G32B32_SFIXED = 0x50,
- GEN6_FORMAT_R16G16B16A16_UNORM = 0x80,
- GEN6_FORMAT_R16G16B16A16_SNORM = 0x81,
- GEN6_FORMAT_R16G16B16A16_SINT = 0x82,
- GEN6_FORMAT_R16G16B16A16_UINT = 0x83,
- GEN6_FORMAT_R16G16B16A16_FLOAT = 0x84,
- GEN6_FORMAT_R32G32_FLOAT = 0x85,
- GEN6_FORMAT_R32G32_SINT = 0x86,
- GEN6_FORMAT_R32G32_UINT = 0x87,
- GEN6_FORMAT_R32_FLOAT_X8X24_TYPELESS = 0x88,
- GEN6_FORMAT_X32_TYPELESS_G8X24_UINT = 0x89,
- GEN6_FORMAT_L32A32_FLOAT = 0x8a,
- GEN6_FORMAT_R32G32_UNORM = 0x8b,
- GEN6_FORMAT_R32G32_SNORM = 0x8c,
- GEN6_FORMAT_R64_FLOAT = 0x8d,
- GEN6_FORMAT_R16G16B16X16_UNORM = 0x8e,
- GEN6_FORMAT_R16G16B16X16_FLOAT = 0x8f,
- GEN6_FORMAT_A32X32_FLOAT = 0x90,
- GEN6_FORMAT_L32X32_FLOAT = 0x91,
- GEN6_FORMAT_I32X32_FLOAT = 0x92,
- GEN6_FORMAT_R16G16B16A16_SSCALED = 0x93,
- GEN6_FORMAT_R16G16B16A16_USCALED = 0x94,
- GEN6_FORMAT_R32G32_SSCALED = 0x95,
- GEN6_FORMAT_R32G32_USCALED = 0x96,
- GEN6_FORMAT_R32G32_SFIXED = 0xa0,
- GEN6_FORMAT_R64_PASSTHRU = 0xa1,
- GEN6_FORMAT_B8G8R8A8_UNORM = 0xc0,
- GEN6_FORMAT_B8G8R8A8_UNORM_SRGB = 0xc1,
- GEN6_FORMAT_R10G10B10A2_UNORM = 0xc2,
- GEN6_FORMAT_R10G10B10A2_UNORM_SRGB = 0xc3,
- GEN6_FORMAT_R10G10B10A2_UINT = 0xc4,
- GEN6_FORMAT_R10G10B10_SNORM_A2_UNORM = 0xc5,
- GEN6_FORMAT_R8G8B8A8_UNORM = 0xc7,
- GEN6_FORMAT_R8G8B8A8_UNORM_SRGB = 0xc8,
- GEN6_FORMAT_R8G8B8A8_SNORM = 0xc9,
- GEN6_FORMAT_R8G8B8A8_SINT = 0xca,
- GEN6_FORMAT_R8G8B8A8_UINT = 0xcb,
- GEN6_FORMAT_R16G16_UNORM = 0xcc,
- GEN6_FORMAT_R16G16_SNORM = 0xcd,
- GEN6_FORMAT_R16G16_SINT = 0xce,
- GEN6_FORMAT_R16G16_UINT = 0xcf,
- GEN6_FORMAT_R16G16_FLOAT = 0xd0,
- GEN6_FORMAT_B10G10R10A2_UNORM = 0xd1,
- GEN6_FORMAT_B10G10R10A2_UNORM_SRGB = 0xd2,
- GEN6_FORMAT_R11G11B10_FLOAT = 0xd3,
- GEN6_FORMAT_R32_SINT = 0xd6,
- GEN6_FORMAT_R32_UINT = 0xd7,
- GEN6_FORMAT_R32_FLOAT = 0xd8,
- GEN6_FORMAT_R24_UNORM_X8_TYPELESS = 0xd9,
- GEN6_FORMAT_X24_TYPELESS_G8_UINT = 0xda,
- GEN6_FORMAT_L32_UNORM = 0xdd,
- GEN6_FORMAT_A32_UNORM = 0xde,
- GEN6_FORMAT_L16A16_UNORM = 0xdf,
- GEN6_FORMAT_I24X8_UNORM = 0xe0,
- GEN6_FORMAT_L24X8_UNORM = 0xe1,
- GEN6_FORMAT_A24X8_UNORM = 0xe2,
- GEN6_FORMAT_I32_FLOAT = 0xe3,
- GEN6_FORMAT_L32_FLOAT = 0xe4,
- GEN6_FORMAT_A32_FLOAT = 0xe5,
- GEN6_FORMAT_X8B8_UNORM_G8R8_SNORM = 0xe6,
- GEN6_FORMAT_A8X8_UNORM_G8R8_SNORM = 0xe7,
- GEN6_FORMAT_B8X8_UNORM_G8R8_SNORM = 0xe8,
- GEN6_FORMAT_B8G8R8X8_UNORM = 0xe9,
- GEN6_FORMAT_B8G8R8X8_UNORM_SRGB = 0xea,
- GEN6_FORMAT_R8G8B8X8_UNORM = 0xeb,
- GEN6_FORMAT_R8G8B8X8_UNORM_SRGB = 0xec,
- GEN6_FORMAT_R9G9B9E5_SHAREDEXP = 0xed,
- GEN6_FORMAT_B10G10R10X2_UNORM = 0xee,
- GEN6_FORMAT_L16A16_FLOAT = 0xf0,
- GEN6_FORMAT_R32_UNORM = 0xf1,
- GEN6_FORMAT_R32_SNORM = 0xf2,
- GEN6_FORMAT_R10G10B10X2_USCALED = 0xf3,
- GEN6_FORMAT_R8G8B8A8_SSCALED = 0xf4,
- GEN6_FORMAT_R8G8B8A8_USCALED = 0xf5,
- GEN6_FORMAT_R16G16_SSCALED = 0xf6,
- GEN6_FORMAT_R16G16_USCALED = 0xf7,
- GEN6_FORMAT_R32_SSCALED = 0xf8,
- GEN6_FORMAT_R32_USCALED = 0xf9,
- GEN6_FORMAT_B5G6R5_UNORM = 0x100,
- GEN6_FORMAT_B5G6R5_UNORM_SRGB = 0x101,
- GEN6_FORMAT_B5G5R5A1_UNORM = 0x102,
- GEN6_FORMAT_B5G5R5A1_UNORM_SRGB = 0x103,
- GEN6_FORMAT_B4G4R4A4_UNORM = 0x104,
- GEN6_FORMAT_B4G4R4A4_UNORM_SRGB = 0x105,
- GEN6_FORMAT_R8G8_UNORM = 0x106,
- GEN6_FORMAT_R8G8_SNORM = 0x107,
- GEN6_FORMAT_R8G8_SINT = 0x108,
- GEN6_FORMAT_R8G8_UINT = 0x109,
- GEN6_FORMAT_R16_UNORM = 0x10a,
- GEN6_FORMAT_R16_SNORM = 0x10b,
- GEN6_FORMAT_R16_SINT = 0x10c,
- GEN6_FORMAT_R16_UINT = 0x10d,
- GEN6_FORMAT_R16_FLOAT = 0x10e,
- GEN6_FORMAT_A8P8_UNORM_PALETTE0 = 0x10f,
- GEN6_FORMAT_A8P8_UNORM_PALETTE1 = 0x110,
- GEN6_FORMAT_I16_UNORM = 0x111,
- GEN6_FORMAT_L16_UNORM = 0x112,
- GEN6_FORMAT_A16_UNORM = 0x113,
- GEN6_FORMAT_L8A8_UNORM = 0x114,
- GEN6_FORMAT_I16_FLOAT = 0x115,
- GEN6_FORMAT_L16_FLOAT = 0x116,
- GEN6_FORMAT_A16_FLOAT = 0x117,
- GEN6_FORMAT_L8A8_UNORM_SRGB = 0x118,
- GEN6_FORMAT_R5G5_SNORM_B6_UNORM = 0x119,
- GEN6_FORMAT_B5G5R5X1_UNORM = 0x11a,
- GEN6_FORMAT_B5G5R5X1_UNORM_SRGB = 0x11b,
- GEN6_FORMAT_R8G8_SSCALED = 0x11c,
- GEN6_FORMAT_R8G8_USCALED = 0x11d,
- GEN6_FORMAT_R16_SSCALED = 0x11e,
- GEN6_FORMAT_R16_USCALED = 0x11f,
- GEN6_FORMAT_P8A8_UNORM_PALETTE0 = 0x122,
- GEN6_FORMAT_P8A8_UNORM_PALETTE1 = 0x123,
- GEN6_FORMAT_A1B5G5R5_UNORM = 0x124,
- GEN6_FORMAT_A4B4G4R4_UNORM = 0x125,
- GEN6_FORMAT_L8A8_UINT = 0x126,
- GEN6_FORMAT_L8A8_SINT = 0x127,
- GEN6_FORMAT_R8_UNORM = 0x140,
- GEN6_FORMAT_R8_SNORM = 0x141,
- GEN6_FORMAT_R8_SINT = 0x142,
- GEN6_FORMAT_R8_UINT = 0x143,
- GEN6_FORMAT_A8_UNORM = 0x144,
- GEN6_FORMAT_I8_UNORM = 0x145,
- GEN6_FORMAT_L8_UNORM = 0x146,
- GEN6_FORMAT_P4A4_UNORM_PALETTE0 = 0x147,
- GEN6_FORMAT_A4P4_UNORM_PALETTE0 = 0x148,
- GEN6_FORMAT_R8_SSCALED = 0x149,
- GEN6_FORMAT_R8_USCALED = 0x14a,
- GEN6_FORMAT_P8_UNORM_PALETTE0 = 0x14b,
- GEN6_FORMAT_L8_UNORM_SRGB = 0x14c,
- GEN6_FORMAT_P8_UNORM_PALETTE1 = 0x14d,
- GEN6_FORMAT_P4A4_UNORM_PALETTE1 = 0x14e,
- GEN6_FORMAT_A4P4_UNORM_PALETTE1 = 0x14f,
- GEN6_FORMAT_Y8_UNORM = 0x150,
- GEN6_FORMAT_L8_UINT = 0x152,
- GEN6_FORMAT_L8_SINT = 0x153,
- GEN6_FORMAT_I8_UINT = 0x154,
- GEN6_FORMAT_I8_SINT = 0x155,
- GEN6_FORMAT_DXT1_RGB_SRGB = 0x180,
- GEN6_FORMAT_R1_UNORM = 0x181,
- GEN6_FORMAT_YCRCB_NORMAL = 0x182,
- GEN6_FORMAT_YCRCB_SWAPUVY = 0x183,
- GEN6_FORMAT_P2_UNORM_PALETTE0 = 0x184,
- GEN6_FORMAT_P2_UNORM_PALETTE1 = 0x185,
- GEN6_FORMAT_BC1_UNORM = 0x186,
- GEN6_FORMAT_BC2_UNORM = 0x187,
- GEN6_FORMAT_BC3_UNORM = 0x188,
- GEN6_FORMAT_BC4_UNORM = 0x189,
- GEN6_FORMAT_BC5_UNORM = 0x18a,
- GEN6_FORMAT_BC1_UNORM_SRGB = 0x18b,
- GEN6_FORMAT_BC2_UNORM_SRGB = 0x18c,
- GEN6_FORMAT_BC3_UNORM_SRGB = 0x18d,
- GEN6_FORMAT_MONO8 = 0x18e,
- GEN6_FORMAT_YCRCB_SWAPUV = 0x18f,
- GEN6_FORMAT_YCRCB_SWAPY = 0x190,
- GEN6_FORMAT_DXT1_RGB = 0x191,
- GEN6_FORMAT_FXT1 = 0x192,
- GEN6_FORMAT_R8G8B8_UNORM = 0x193,
- GEN6_FORMAT_R8G8B8_SNORM = 0x194,
- GEN6_FORMAT_R8G8B8_SSCALED = 0x195,
- GEN6_FORMAT_R8G8B8_USCALED = 0x196,
- GEN6_FORMAT_R64G64B64A64_FLOAT = 0x197,
- GEN6_FORMAT_R64G64B64_FLOAT = 0x198,
- GEN6_FORMAT_BC4_SNORM = 0x199,
- GEN6_FORMAT_BC5_SNORM = 0x19a,
- GEN6_FORMAT_R16G16B16_FLOAT = 0x19b,
- GEN6_FORMAT_R16G16B16_UNORM = 0x19c,
- GEN6_FORMAT_R16G16B16_SNORM = 0x19d,
- GEN6_FORMAT_R16G16B16_SSCALED = 0x19e,
- GEN6_FORMAT_R16G16B16_USCALED = 0x19f,
- GEN6_FORMAT_BC6H_SF16 = 0x1a1,
- GEN6_FORMAT_BC7_UNORM = 0x1a2,
- GEN6_FORMAT_BC7_UNORM_SRGB = 0x1a3,
- GEN6_FORMAT_BC6H_UF16 = 0x1a4,
- GEN6_FORMAT_PLANAR_420_8 = 0x1a5,
- GEN6_FORMAT_R8G8B8_UNORM_SRGB = 0x1a8,
- GEN6_FORMAT_ETC1_RGB8 = 0x1a9,
- GEN6_FORMAT_ETC2_RGB8 = 0x1aa,
- GEN6_FORMAT_EAC_R11 = 0x1ab,
- GEN6_FORMAT_EAC_RG11 = 0x1ac,
- GEN6_FORMAT_EAC_SIGNED_R11 = 0x1ad,
- GEN6_FORMAT_EAC_SIGNED_RG11 = 0x1ae,
- GEN6_FORMAT_ETC2_SRGB8 = 0x1af,
- GEN6_FORMAT_R16G16B16_UINT = 0x1b0,
- GEN6_FORMAT_R16G16B16_SINT = 0x1b1,
- GEN6_FORMAT_R32_SFIXED = 0x1b2,
- GEN6_FORMAT_R10G10B10A2_SNORM = 0x1b3,
- GEN6_FORMAT_R10G10B10A2_USCALED = 0x1b4,
- GEN6_FORMAT_R10G10B10A2_SSCALED = 0x1b5,
- GEN6_FORMAT_R10G10B10A2_SINT = 0x1b6,
- GEN6_FORMAT_B10G10R10A2_SNORM = 0x1b7,
- GEN6_FORMAT_B10G10R10A2_USCALED = 0x1b8,
- GEN6_FORMAT_B10G10R10A2_SSCALED = 0x1b9,
- GEN6_FORMAT_B10G10R10A2_UINT = 0x1ba,
- GEN6_FORMAT_B10G10R10A2_SINT = 0x1bb,
- GEN6_FORMAT_R64G64B64A64_PASSTHRU = 0x1bc,
- GEN6_FORMAT_R64G64B64_PASSTHRU = 0x1bd,
- GEN6_FORMAT_ETC2_RGB8_PTA = 0x1c0,
- GEN6_FORMAT_ETC2_SRGB8_PTA = 0x1c1,
- GEN6_FORMAT_ETC2_EAC_RGBA8 = 0x1c2,
- GEN6_FORMAT_ETC2_EAC_SRGB8_A8 = 0x1c3,
- GEN6_FORMAT_R8G8B8_UINT = 0x1c8,
- GEN6_FORMAT_R8G8B8_SINT = 0x1c9,
- GEN6_FORMAT_RAW = 0x1ff,
-};
-
-enum gen_surface_type {
- GEN6_SURFTYPE_1D = 0x0,
- GEN6_SURFTYPE_2D = 0x1,
- GEN6_SURFTYPE_3D = 0x2,
- GEN6_SURFTYPE_CUBE = 0x3,
- GEN6_SURFTYPE_BUFFER = 0x4,
- GEN7_SURFTYPE_STRBUF = 0x5,
- GEN6_SURFTYPE_NULL = 0x7,
-};
-
-enum gen_surface_tiling {
- GEN6_TILING_NONE = 0x0,
- GEN8_TILING_W = 0x1,
- GEN6_TILING_X = 0x2,
- GEN6_TILING_Y = 0x3,
-};
-
-enum gen_surface_clear_color {
- GEN7_CLEAR_COLOR_ZERO = 0x0,
- GEN7_CLEAR_COLOR_ONE = 0x1,
-};
-
-enum gen_surface_scs {
- GEN75_SCS_ZERO = 0x0,
- GEN75_SCS_ONE = 0x1,
- GEN75_SCS_RED = 0x4,
- GEN75_SCS_GREEN = 0x5,
- GEN75_SCS_BLUE = 0x6,
- GEN75_SCS_ALPHA = 0x7,
-};
-
-#define GEN6_SURFACE_STATE__SIZE 16
-
-#define GEN6_SURFACE_DW0_TYPE__MASK 0xe0000000
-#define GEN6_SURFACE_DW0_TYPE__SHIFT 29
-#define GEN6_SURFACE_DW0_FORMAT__MASK 0x07fc0000
-#define GEN6_SURFACE_DW0_FORMAT__SHIFT 18
-#define GEN6_SURFACE_DW0_VSTRIDE (0x1 << 12)
-#define GEN6_SURFACE_DW0_VSTRIDE_OFFSET (0x1 << 11)
-#define GEN6_SURFACE_DW0_MIPLAYOUT__MASK 0x00000400
-#define GEN6_SURFACE_DW0_MIPLAYOUT__SHIFT 10
-#define GEN6_SURFACE_DW0_MIPLAYOUT_BELOW (0x0 << 10)
-#define GEN6_SURFACE_DW0_MIPLAYOUT_RIGHT (0x1 << 10)
-#define GEN6_SURFACE_DW0_CUBE_MAP_CORNER_MODE__MASK 0x00000200
-#define GEN6_SURFACE_DW0_CUBE_MAP_CORNER_MODE__SHIFT 9
-#define GEN6_SURFACE_DW0_CUBE_MAP_CORNER_MODE_REPLICATE (0x0 << 9)
-#define GEN6_SURFACE_DW0_CUBE_MAP_CORNER_MODE_AVERAGE (0x1 << 9)
-#define GEN6_SURFACE_DW0_RENDER_CACHE_RW (0x1 << 8)
-#define GEN6_SURFACE_DW0_MEDIA_BOUNDARY_PIXEL_MODE__MASK 0x000000c0
-#define GEN6_SURFACE_DW0_MEDIA_BOUNDARY_PIXEL_MODE__SHIFT 6
-#define GEN6_SURFACE_DW0_CUBE_FACE_ENABLES__MASK 0x0000003f
-#define GEN6_SURFACE_DW0_CUBE_FACE_ENABLES__SHIFT 0
-
-
-#define GEN6_SURFACE_DW2_HEIGHT__MASK 0xfff80000
-#define GEN6_SURFACE_DW2_HEIGHT__SHIFT 19
-#define GEN6_SURFACE_DW2_WIDTH__MASK 0x0007ffc0
-#define GEN6_SURFACE_DW2_WIDTH__SHIFT 6
-#define GEN6_SURFACE_DW2_MIP_COUNT_LOD__MASK 0x0000003c
-#define GEN6_SURFACE_DW2_MIP_COUNT_LOD__SHIFT 2
-#define GEN6_SURFACE_DW2_RTROTATE__MASK 0x00000003
-#define GEN6_SURFACE_DW2_RTROTATE__SHIFT 0
-#define GEN6_SURFACE_DW2_RTROTATE_0DEG 0x0
-#define GEN6_SURFACE_DW2_RTROTATE_90DEG 0x1
-#define GEN6_SURFACE_DW2_RTROTATE_270DEG 0x3
-
-#define GEN6_SURFACE_DW3_DEPTH__MASK 0xffe00000
-#define GEN6_SURFACE_DW3_DEPTH__SHIFT 21
-#define GEN6_SURFACE_DW3_PITCH__MASK 0x000ffff8
-#define GEN6_SURFACE_DW3_PITCH__SHIFT 3
-#define GEN6_SURFACE_DW3_TILING__MASK 0x00000003
-#define GEN6_SURFACE_DW3_TILING__SHIFT 0
-
-#define GEN6_SURFACE_DW4_MIN_LOD__MASK 0xf0000000
-#define GEN6_SURFACE_DW4_MIN_LOD__SHIFT 28
-#define GEN6_SURFACE_DW4_MIN_ARRAY_ELEMENT__MASK 0x0ffe0000
-#define GEN6_SURFACE_DW4_MIN_ARRAY_ELEMENT__SHIFT 17
-#define GEN6_SURFACE_DW4_RT_VIEW_EXTENT__MASK 0x0001ff00
-#define GEN6_SURFACE_DW4_RT_VIEW_EXTENT__SHIFT 8
-#define GEN6_SURFACE_DW4_MULTISAMPLECOUNT__MASK 0x00000070
-#define GEN6_SURFACE_DW4_MULTISAMPLECOUNT__SHIFT 4
-#define GEN6_SURFACE_DW4_MULTISAMPLECOUNT_1 (0x0 << 4)
-#define GEN6_SURFACE_DW4_MULTISAMPLECOUNT_4 (0x2 << 4)
-#define GEN6_SURFACE_DW4_MSPOS_INDEX__MASK 0x00000007
-#define GEN6_SURFACE_DW4_MSPOS_INDEX__SHIFT 0
-
-#define GEN6_SURFACE_DW5_X_OFFSET__MASK 0xfe000000
-#define GEN6_SURFACE_DW5_X_OFFSET__SHIFT 25
-#define GEN6_SURFACE_DW5_X_OFFSET__SHR 2
-#define GEN6_SURFACE_DW5_VALIGN__MASK 0x01000000
-#define GEN6_SURFACE_DW5_VALIGN__SHIFT 24
-#define GEN6_SURFACE_DW5_VALIGN_2 (0x0 << 24)
-#define GEN6_SURFACE_DW5_VALIGN_4 (0x1 << 24)
-#define GEN6_SURFACE_DW5_Y_OFFSET__MASK 0x00f00000
-#define GEN6_SURFACE_DW5_Y_OFFSET__SHIFT 20
-#define GEN6_SURFACE_DW5_Y_OFFSET__SHR 1
-#define GEN6_SURFACE_DW5_MOCS__MASK 0x000f0000
-#define GEN6_SURFACE_DW5_MOCS__SHIFT 16
-
-
-#define GEN7_SURFACE_DW0_TYPE__MASK 0xe0000000
-#define GEN7_SURFACE_DW0_TYPE__SHIFT 29
-#define GEN7_SURFACE_DW0_IS_ARRAY (0x1 << 28)
-#define GEN7_SURFACE_DW0_FORMAT__MASK 0x07fc0000
-#define GEN7_SURFACE_DW0_FORMAT__SHIFT 18
-#define GEN7_SURFACE_DW0_VALIGN__MASK 0x00030000
-#define GEN7_SURFACE_DW0_VALIGN__SHIFT 16
-#define GEN7_SURFACE_DW0_VALIGN_2 (0x0 << 16)
-#define GEN7_SURFACE_DW0_VALIGN_4 (0x1 << 16)
-#define GEN8_SURFACE_DW0_VALIGN_8 (0x2 << 16)
-#define GEN8_SURFACE_DW0_VALIGN_16 (0x3 << 16)
-#define GEN7_SURFACE_DW0_HALIGN__MASK 0x00008000
-#define GEN7_SURFACE_DW0_HALIGN__SHIFT 15
-#define GEN7_SURFACE_DW0_HALIGN_4 (0x0 << 15)
-#define GEN7_SURFACE_DW0_HALIGN_8 (0x1 << 15)
-#define GEN7_SURFACE_DW0_TILING__MASK 0x00006000
-#define GEN7_SURFACE_DW0_TILING__SHIFT 13
-#define GEN7_SURFACE_DW0_VSTRIDE (0x1 << 12)
-#define GEN7_SURFACE_DW0_VSTRIDE_OFFSET (0x1 << 11)
-#define GEN7_SURFACE_DW0_ARYSPC__MASK 0x00000400
-#define GEN7_SURFACE_DW0_ARYSPC__SHIFT 10
-#define GEN7_SURFACE_DW0_ARYSPC_FULL (0x0 << 10)
-#define GEN7_SURFACE_DW0_ARYSPC_LOD0 (0x1 << 10)
-#define GEN8_SURFACE_DW0_HALIGN__MASK 0x0000c000
-#define GEN8_SURFACE_DW0_HALIGN__SHIFT 14
-#define GEN8_SURFACE_DW0_HALIGN_4 (0x1 << 14)
-#define GEN8_SURFACE_DW0_HALIGN_8 (0x2 << 14)
-#define GEN8_SURFACE_DW0_HALIGN_16 (0x3 << 14)
-#define GEN8_SURFACE_DW0_TILING__MASK 0x00003000
-#define GEN8_SURFACE_DW0_TILING__SHIFT 12
-#define GEN8_SURFACE_DW0_VSTRIDE (0x1 << 11)
-#define GEN8_SURFACE_DW0_VSTRIDE_OFFSET (0x1 << 10)
-#define GEN8_SURFACE_DW0_SAMPLER_L2_BYPASS_DISABLE (0x1 << 9)
-#define GEN7_SURFACE_DW0_RENDER_CACHE_RW (0x1 << 8)
-#define GEN7_SURFACE_DW0_MEDIA_BOUNDARY_PIXEL_MODE__MASK 0x000000c0
-#define GEN7_SURFACE_DW0_MEDIA_BOUNDARY_PIXEL_MODE__SHIFT 6
-#define GEN7_SURFACE_DW0_CUBE_FACE_ENABLES__MASK 0x0000003f
-#define GEN7_SURFACE_DW0_CUBE_FACE_ENABLES__SHIFT 0
-
-
-#define GEN8_SURFACE_DW1_MOCS__MASK 0x7f000000
-#define GEN8_SURFACE_DW1_MOCS__SHIFT 24
-#define GEN8_SURFACE_DW1_BASE_LOD__MASK 0x00f80000
-#define GEN8_SURFACE_DW1_BASE_LOD__SHIFT 19
-#define GEN8_SURFACE_DW1_QPITCH__MASK 0x00007fff
-#define GEN8_SURFACE_DW1_QPITCH__SHIFT 0
-#define GEN8_SURFACE_DW1_QPITCH__SHR 2
-
-#define GEN7_SURFACE_DW2_HEIGHT__MASK 0x3fff0000
-#define GEN7_SURFACE_DW2_HEIGHT__SHIFT 16
-#define GEN7_SURFACE_DW2_WIDTH__MASK 0x00003fff
-#define GEN7_SURFACE_DW2_WIDTH__SHIFT 0
-
-#define GEN7_SURFACE_DW3_DEPTH__MASK 0xffe00000
-#define GEN7_SURFACE_DW3_DEPTH__SHIFT 21
-#define GEN75_SURFACE_DW3_INTEGER_SURFACE_FORMAT__MASK 0x001c0000
-#define GEN75_SURFACE_DW3_INTEGER_SURFACE_FORMAT__SHIFT 18
-#define GEN7_SURFACE_DW3_PITCH__MASK 0x0003ffff
-#define GEN7_SURFACE_DW3_PITCH__SHIFT 0
-
-#define GEN7_SURFACE_DW4_RTROTATE__MASK 0x60000000
-#define GEN7_SURFACE_DW4_RTROTATE__SHIFT 29
-#define GEN7_SURFACE_DW4_RTROTATE_0DEG (0x0 << 29)
-#define GEN7_SURFACE_DW4_RTROTATE_90DEG (0x1 << 29)
-#define GEN7_SURFACE_DW4_RTROTATE_270DEG (0x3 << 29)
-#define GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT__MASK 0x1ffc0000
-#define GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT__SHIFT 18
-#define GEN7_SURFACE_DW4_RT_VIEW_EXTENT__MASK 0x0003ff80
-#define GEN7_SURFACE_DW4_RT_VIEW_EXTENT__SHIFT 7
-#define GEN7_SURFACE_DW4_MSFMT__MASK 0x00000040
-#define GEN7_SURFACE_DW4_MSFMT__SHIFT 6
-#define GEN7_SURFACE_DW4_MSFMT_MSS (0x0 << 6)
-#define GEN7_SURFACE_DW4_MSFMT_DEPTH_STENCIL (0x1 << 6)
-#define GEN7_SURFACE_DW4_MULTISAMPLECOUNT__MASK 0x00000038
-#define GEN7_SURFACE_DW4_MULTISAMPLECOUNT__SHIFT 3
-#define GEN7_SURFACE_DW4_MULTISAMPLECOUNT_1 (0x0 << 3)
-#define GEN8_SURFACE_DW4_MULTISAMPLECOUNT_2 (0x1 << 3)
-#define GEN7_SURFACE_DW4_MULTISAMPLECOUNT_4 (0x2 << 3)
-#define GEN7_SURFACE_DW4_MULTISAMPLECOUNT_8 (0x3 << 3)
-#define GEN7_SURFACE_DW4_MSPOS_INDEX__MASK 0x00000007
-#define GEN7_SURFACE_DW4_MSPOS_INDEX__SHIFT 0
-#define GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT_STRBUF__MASK 0x07ffffff
-#define GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT_STRBUF__SHIFT 0
-
-#define GEN7_SURFACE_DW5_X_OFFSET__MASK 0xfe000000
-#define GEN7_SURFACE_DW5_X_OFFSET__SHIFT 25
-#define GEN7_SURFACE_DW5_X_OFFSET__SHR 2
-#define GEN7_SURFACE_DW5_Y_OFFSET__MASK 0x00f00000
-#define GEN7_SURFACE_DW5_Y_OFFSET__SHIFT 20
-#define GEN7_SURFACE_DW5_Y_OFFSET__SHR 1
-#define GEN7_SURFACE_DW5_MOCS__MASK 0x000f0000
-#define GEN7_SURFACE_DW5_MOCS__SHIFT 16
-#define GEN8_SURFACE_DW5_Y_OFFSET__MASK 0x00e00000
-#define GEN8_SURFACE_DW5_Y_OFFSET__SHIFT 21
-#define GEN8_SURFACE_DW5_Y_OFFSET__SHR 1
-#define GEN8_SURFACE_DW5_CUBE_EWA_DISABLE (0x1 << 20)
-#define GEN8_SURFACE_DW5_COHERENCY_TYPE__MASK 0x00004000
-#define GEN8_SURFACE_DW5_COHERENCY_TYPE__SHIFT 14
-#define GEN8_SURFACE_DW5_COHERENCY_TYPE_GPU (0x0 << 14)
-#define GEN8_SURFACE_DW5_COHERENCY_TYPE_IA (0x1 << 14)
-#define GEN7_SURFACE_DW5_MIN_LOD__MASK 0x000000f0
-#define GEN7_SURFACE_DW5_MIN_LOD__SHIFT 4
-#define GEN7_SURFACE_DW5_MIP_COUNT_LOD__MASK 0x0000000f
-#define GEN7_SURFACE_DW5_MIP_COUNT_LOD__SHIFT 0
-
-#define GEN8_SURFACE_DW6_SEPARATE_UV_ENABLE (0x1 << 31)
-#define GEN7_SURFACE_DW6_UV_X_OFFSET__MASK 0x3fff0000
-#define GEN7_SURFACE_DW6_UV_X_OFFSET__SHIFT 16
-#define GEN7_SURFACE_DW6_UV_Y_OFFSET__MASK 0x00003fff
-#define GEN7_SURFACE_DW6_UV_Y_OFFSET__SHIFT 0
-#define GEN7_SURFACE_DW6_APPEND_COUNTER_ADDR__MASK 0xffffffc0
-#define GEN7_SURFACE_DW6_APPEND_COUNTER_ADDR__SHIFT 6
-#define GEN7_SURFACE_DW6_APPEND_COUNTER_ADDR__SHR 6
-#define GEN7_SURFACE_DW6_MCS_ADDR__MASK 0xfffff000
-#define GEN7_SURFACE_DW6_MCS_ADDR__SHIFT 12
-#define GEN7_SURFACE_DW6_MCS_ADDR__SHR 12
-#define GEN8_SURFACE_DW6_AUX_QPITCH__MASK 0x7fff0000
-#define GEN8_SURFACE_DW6_AUX_QPITCH__SHIFT 16
-#define GEN8_SURFACE_DW6_AUX_QPITCH__SHR 2
-#define GEN7_SURFACE_DW6_AUX_PITCH__MASK 0x00000ff8
-#define GEN7_SURFACE_DW6_AUX_PITCH__SHIFT 3
-#define GEN7_SURFACE_DW6_AUX__MASK 0x00000007
-#define GEN7_SURFACE_DW6_AUX__SHIFT 0
-#define GEN7_SURFACE_DW6_AUX_NONE 0x0
-#define GEN7_SURFACE_DW6_AUX_MCS 0x1
-#define GEN7_SURFACE_DW6_AUX_APPEND 0x2
-#define GEN8_SURFACE_DW6_AUX_HIZ 0x3
-
-#define GEN7_SURFACE_DW7_CC_R__MASK 0x80000000
-#define GEN7_SURFACE_DW7_CC_R__SHIFT 31
-#define GEN7_SURFACE_DW7_CC_G__MASK 0x40000000
-#define GEN7_SURFACE_DW7_CC_G__SHIFT 30
-#define GEN7_SURFACE_DW7_CC_B__MASK 0x20000000
-#define GEN7_SURFACE_DW7_CC_B__SHIFT 29
-#define GEN7_SURFACE_DW7_CC_A__MASK 0x10000000
-#define GEN7_SURFACE_DW7_CC_A__SHIFT 28
-#define GEN75_SURFACE_DW7_SCS__MASK 0x0fff0000
-#define GEN75_SURFACE_DW7_SCS__SHIFT 16
-#define GEN75_SURFACE_DW7_SCS_R__MASK 0x0e000000
-#define GEN75_SURFACE_DW7_SCS_R__SHIFT 25
-#define GEN75_SURFACE_DW7_SCS_G__MASK 0x01c00000
-#define GEN75_SURFACE_DW7_SCS_G__SHIFT 22
-#define GEN75_SURFACE_DW7_SCS_B__MASK 0x00380000
-#define GEN75_SURFACE_DW7_SCS_B__SHIFT 19
-#define GEN75_SURFACE_DW7_SCS_A__MASK 0x00070000
-#define GEN75_SURFACE_DW7_SCS_A__SHIFT 16
-#define GEN7_SURFACE_DW7_RES_MIN_LOD__MASK 0x00000fff
-#define GEN7_SURFACE_DW7_RES_MIN_LOD__SHIFT 0
-
-
-
-
-#define GEN8_SURFACE_DW11_V_X_OFFSET__MASK 0x3fff0000
-#define GEN8_SURFACE_DW11_V_X_OFFSET__SHIFT 16
-#define GEN8_SURFACE_DW11_V_Y_OFFSET__MASK 0x00003fff
-#define GEN8_SURFACE_DW11_V_Y_OFFSET__SHIFT 0
-#define GEN8_SURFACE_DW11_AUX_ADDR_HI__MASK 0xffffffff
-#define GEN8_SURFACE_DW11_AUX_ADDR_HI__SHIFT 0
-
-
-
-
-
-#define GEN6_BINDING_TABLE_STATE__SIZE 256
-
-#define GEN6_BINDING_TABLE_DW_ADDR__MASK 0xffffffe0
-#define GEN6_BINDING_TABLE_DW_ADDR__SHIFT 5
-#define GEN6_BINDING_TABLE_DW_ADDR__SHR 5
-
-#define GEN8_BINDING_TABLE_DW_ADDR__MASK 0xffffffc0
-#define GEN8_BINDING_TABLE_DW_ADDR__SHIFT 6
-#define GEN8_BINDING_TABLE_DW_ADDR__SHR 6
-
-
-#endif /* GEN_RENDER_SURFACE_XML */
+++ /dev/null
-/*
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef GENHW_H
-#define GENHW_H
-
-#include <stdbool.h>
-#include <stdint.h>
-#include <assert.h>
-
-#include "gen_regs.xml.h"
-#include "gen_mi.xml.h"
-#include "gen_blitter.xml.h"
-#include "gen_render.xml.h"
-#include "gen_render_surface.xml.h"
-#include "gen_render_dynamic.xml.h"
-#include "gen_render_3d.xml.h"
-#include "gen_render_media.xml.h"
-#include "gen_eu_isa.xml.h"
-#include "gen_eu_message.xml.h"
-
-#define GEN_MI_CMD(gen, op) (GEN6_MI_TYPE_MI | gen ## _MI_OPCODE_ ## op)
-#define GEN6_MI_CMD(op) GEN_MI_CMD(GEN6, op)
-#define GEN7_MI_CMD(op) GEN_MI_CMD(GEN7, op)
-
-#define GEN_BLITTER_CMD(gen, op) \
- (GEN6_BLITTER_TYPE_BLITTER | gen ## _BLITTER_OPCODE_ ## op)
-#define GEN6_BLITTER_CMD(op) GEN_BLITTER_CMD(GEN6, op)
-
-#define GEN_RENDER_CMD(subtype, gen, op) \
- (GEN6_RENDER_TYPE_RENDER | \
- GEN6_RENDER_SUBTYPE_ ## subtype | \
- gen ## _RENDER_OPCODE_ ## op)
-#define GEN6_RENDER_CMD(subtype, op) GEN_RENDER_CMD(subtype, GEN6, op)
-#define GEN7_RENDER_CMD(subtype, op) GEN_RENDER_CMD(subtype, GEN7, op)
-#define GEN75_RENDER_CMD(subtype, op) GEN_RENDER_CMD(subtype, GEN75, op)
-#define GEN8_RENDER_CMD(subtype, op) GEN_RENDER_CMD(subtype, GEN8, op)
-
-#define GEN_EXTRACT(bits, field) (((bits) & field ## __MASK) >> field ## __SHIFT)
-#define GEN_SHIFT32(bits, field) gen_shift32(bits, field ## __MASK, field ## __SHIFT)
-
-static inline uint32_t
-gen_shift32(uint32_t bits, uint32_t mask, int shift)
-{
- bits <<= shift;
-
- assert((bits & mask) == bits);
- return bits & mask;
-}
-
-static inline bool
-gen_is_snb(int devid)
-{
- return (devid == 0x0102 || /* GT1 desktop */
- devid == 0x0112 || /* GT2 desktop */
- devid == 0x0122 || /* GT2_PLUS desktop */
- devid == 0x0106 || /* GT1 mobile */
- devid == 0x0116 || /* GT2 mobile */
- devid == 0x0126 || /* GT2_PLUS mobile */
- devid == 0x010a); /* GT1 server */
-}
-
-static inline int
-gen_get_snb_gt(int devid)
-{
- assert(gen_is_snb(devid));
- return (devid & 0x30) ? 2 : 1;
-}
-
-static inline bool
-gen_is_ivb(int devid)
-{
- return (devid == 0x0152 || /* GT1 desktop */
- devid == 0x0162 || /* GT2 desktop */
- devid == 0x0156 || /* GT1 mobile */
- devid == 0x0166 || /* GT2 mobile */
- devid == 0x015a || /* GT1 server */
- devid == 0x016a); /* GT2 server */
-}
-
-static inline int
-gen_get_ivb_gt(int devid)
-{
- assert(gen_is_ivb(devid));
- return (devid & 0x30) >> 4;
-}
-
-static inline bool
-gen_is_hsw(int devid)
-{
- return (devid == 0x0402 || /* GT1 desktop */
- devid == 0x0412 || /* GT2 desktop */
- devid == 0x0422 || /* GT3 desktop */
- devid == 0x0406 || /* GT1 mobile */
- devid == 0x0416 || /* GT2 mobile */
- devid == 0x0426 || /* GT2 mobile */
- devid == 0x040a || /* GT1 server */
- devid == 0x041a || /* GT2 server */
- devid == 0x042a || /* GT3 server */
- devid == 0x040b || /* GT1 reserved */
- devid == 0x041b || /* GT2 reserved */
- devid == 0x042b || /* GT3 reserved */
- devid == 0x040e || /* GT1 reserved */
- devid == 0x041e || /* GT2 reserved */
- devid == 0x042e || /* GT3 reserved */
- devid == 0x0c02 || /* SDV */
- devid == 0x0c12 ||
- devid == 0x0c22 ||
- devid == 0x0c06 ||
- devid == 0x0c16 ||
- devid == 0x0c26 ||
- devid == 0x0c0a ||
- devid == 0x0c1a ||
- devid == 0x0c2a ||
- devid == 0x0c0b ||
- devid == 0x0c1b ||
- devid == 0x0c2b ||
- devid == 0x0c0e ||
- devid == 0x0c1e ||
- devid == 0x0c2e ||
- devid == 0x0a02 || /* ULT */
- devid == 0x0a12 ||
- devid == 0x0a22 ||
- devid == 0x0a06 ||
- devid == 0x0a16 ||
- devid == 0x0a26 ||
- devid == 0x0a0a ||
- devid == 0x0a1a ||
- devid == 0x0a2a ||
- devid == 0x0a0b ||
- devid == 0x0a1b ||
- devid == 0x0a2b ||
- devid == 0x0a0e ||
- devid == 0x0a1e ||
- devid == 0x0a2e ||
- devid == 0x0d02 || /* CRW */
- devid == 0x0d12 ||
- devid == 0x0d22 ||
- devid == 0x0d06 ||
- devid == 0x0d16 ||
- devid == 0x0d26 ||
- devid == 0x0d0a ||
- devid == 0x0d1a ||
- devid == 0x0d2a ||
- devid == 0x0d0b ||
- devid == 0x0d1b ||
- devid == 0x0d2b ||
- devid == 0x0d0e ||
- devid == 0x0d1e ||
- devid == 0x0d2e);
-}
-
-static inline int
-gen_get_hsw_gt(int devid)
-{
- assert(gen_is_hsw(devid));
- return ((devid & 0x30) >> 4) + 1;
-}
-
-static inline bool
-gen_is_bdw(int devid)
-{
- return (devid == 0x1602 || /* GT1 ULT */
- devid == 0x1606 || /* GT1 ULT */
- devid == 0x160a || /* GT1 server */
- devid == 0x160b || /* GT1 Iris */
- devid == 0x160d || /* GT1 workstation */
- devid == 0x160e || /* GT1 ULX */
- devid == 0x1612 || /* GT2 */
- devid == 0x1616 ||
- devid == 0x161a ||
- devid == 0x161b ||
- devid == 0x161d ||
- devid == 0x161e ||
- devid == 0x1622 || /* GT3 */
- devid == 0x1626 ||
- devid == 0x162a ||
- devid == 0x162b ||
- devid == 0x162d ||
- devid == 0x162e);
-}
-
-static inline int
-gen_get_bdw_gt(int devid)
-{
- assert(gen_is_bdw(devid));
- return ((devid & 0x30) >> 4) + 1;
-}
-
-static inline bool
-gen_is_vlv(int devid)
-{
- return (devid == 0x0f30 ||
- devid == 0x0f31 ||
- devid == 0x0f32 ||
- devid == 0x0f33 ||
- devid == 0x0157 ||
- devid == 0x0155);
-}
-
-static inline bool
-gen_is_chv(int devid)
-{
- return (devid == 0x22b0 ||
- devid == 0x22b1 ||
- devid == 0x22b2 ||
- devid == 0x22b3);
-}
-
-static inline bool
-gen_is_atom(int devid)
-{
- return (gen_is_vlv(devid) ||
- gen_is_chv(devid));
-}
-
-static inline bool
-gen_is_desktop(int devid)
-{
- assert(!gen_is_atom(devid));
- return ((devid & 0xf) == 0x2);
-}
-
-static inline bool
-gen_is_mobile(int devid)
-{
- assert(!gen_is_atom(devid));
- return ((devid & 0xf) == 0x6);
-}
-
-static inline bool
-gen_is_server(int devid)
-{
- assert(!gen_is_atom(devid));
- return ((devid & 0xf) == 0xa);
-}
-
-#endif /* GENHW_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "util/u_surface.h"
-
-#include "ilo_blitter.h"
-#include "ilo_context.h"
-#include "ilo_blit.h"
-
-static void
-ilo_resource_copy_region(struct pipe_context *pipe,
- struct pipe_resource *dst,
- unsigned dst_level,
- unsigned dstx, unsigned dsty, unsigned dstz,
- struct pipe_resource *src,
- unsigned src_level,
- const struct pipe_box *src_box)
-{
- struct ilo_context *ilo = ilo_context(pipe);
-
- if (ilo_blitter_blt_copy_resource(ilo->blitter,
- dst, dst_level, dstx, dsty, dstz,
- src, src_level, src_box))
- return;
-
- if (ilo_blitter_pipe_copy_resource(ilo->blitter,
- dst, dst_level, dstx, dsty, dstz,
- src, src_level, src_box))
- return;
-
- util_resource_copy_region(&ilo->base, dst, dst_level,
- dstx, dsty, dstz, src, src_level, src_box);
-}
-
-static void
-ilo_clear(struct pipe_context *pipe,
- unsigned buffers,
- const union pipe_color_union *color,
- double depth,
- unsigned stencil)
-{
- struct ilo_context *ilo = ilo_context(pipe);
- struct ilo_state_vector *vec = &ilo->state_vector;
-
- if ((buffers & PIPE_CLEAR_DEPTHSTENCIL) && vec->fb.state.zsbuf) {
- if (ilo_blitter_rectlist_clear_zs(ilo->blitter, vec->fb.state.zsbuf,
- buffers & PIPE_CLEAR_DEPTHSTENCIL, depth, stencil))
- buffers &= ~PIPE_CLEAR_DEPTHSTENCIL;
-
- if (!buffers)
- return;
- }
-
- ilo_blitter_pipe_clear_fb(ilo->blitter, buffers, color, depth, stencil);
-}
-
-static void
-ilo_clear_render_target(struct pipe_context *pipe,
- struct pipe_surface *dst,
- const union pipe_color_union *color,
- unsigned dstx, unsigned dsty,
- unsigned width, unsigned height,
- bool render_condition_enabled)
-{
- struct ilo_context *ilo = ilo_context(pipe);
-
- if (!width || !height || dstx >= dst->width || dsty >= dst->height)
- return;
-
- if (dstx + width > dst->width)
- width = dst->width - dstx;
- if (dsty + height > dst->height)
- height = dst->height - dsty;
-
- if (ilo_blitter_blt_clear_rt(ilo->blitter,
- dst, color, dstx, dsty, width, height))
- return;
-
- ilo_blitter_pipe_clear_rt(ilo->blitter,
- dst, color, dstx, dsty, width, height);
-}
-
-static void
-ilo_clear_depth_stencil(struct pipe_context *pipe,
- struct pipe_surface *dst,
- unsigned clear_flags,
- double depth,
- unsigned stencil,
- unsigned dstx, unsigned dsty,
- unsigned width, unsigned height,
- bool render_condition_enabled)
-{
- struct ilo_context *ilo = ilo_context(pipe);
-
- if (!width || !height || dstx >= dst->width || dsty >= dst->height)
- return;
-
- if (dstx + width > dst->width)
- width = dst->width - dstx;
- if (dsty + height > dst->height)
- height = dst->height - dsty;
-
- if (ilo_blitter_blt_clear_zs(ilo->blitter,
- dst, clear_flags, depth, stencil, dstx, dsty, width, height))
- return;
-
- ilo_blitter_pipe_clear_zs(ilo->blitter,
- dst, clear_flags, depth, stencil, dstx, dsty, width, height);
-}
-
-static void
-ilo_blit(struct pipe_context *pipe, const struct pipe_blit_info *info)
-{
- struct ilo_context *ilo = ilo_context(pipe);
-
- ilo_blitter_pipe_blit(ilo->blitter, info);
-}
-
-static void
-ilo_flush_resource(struct pipe_context *pipe, struct pipe_resource *res)
-{
- struct ilo_context *ilo = ilo_context(pipe);
- const unsigned flags = ILO_TEXTURE_CPU_READ |
- ILO_TEXTURE_BLT_READ |
- ILO_TEXTURE_RENDER_READ;
-
- ilo_blit_resolve_resource(ilo, res, flags);
-}
-
-void
-ilo_blit_resolve_slices_for_hiz(struct ilo_context *ilo,
- struct pipe_resource *res, unsigned level,
- unsigned first_slice, unsigned num_slices,
- unsigned resolve_flags)
-{
- struct ilo_texture *tex = ilo_texture(res);
- const unsigned any_reader =
- ILO_TEXTURE_RENDER_READ |
- ILO_TEXTURE_BLT_READ |
- ILO_TEXTURE_CPU_READ;
- const unsigned other_writers =
- ILO_TEXTURE_BLT_WRITE |
- ILO_TEXTURE_CPU_WRITE;
- unsigned i;
-
- assert(tex->base.target != PIPE_BUFFER &&
- ilo_image_can_enable_aux(&tex->image, level));
-
- if (resolve_flags & ILO_TEXTURE_RENDER_WRITE) {
- /*
- * When ILO_TEXTURE_RENDER_WRITE is set, there can be no reader. We
- * need to perform a HiZ Buffer Resolve in case the resource was
- * previously written by another writer, unless this is a clear.
- *
- * When slices have different clear values, we perform a Depth Buffer
- * Resolve on all slices not sharing the clear value of the first slice.
- * After resolving, those slices do not use 3DSTATE_CLEAR_PARAMS and can
- * be made to have the same clear value as the first slice does. This
- * way,
- *
- * - 3DSTATE_CLEAR_PARAMS can be set to the clear value of any slice
- * - we will not resolve unnecessarily next time this function is
- * called
- *
- * Since slice clear value is the value the slice is cleared to when
- * ILO_TEXTURE_CLEAR is set, the bit needs to be unset.
- */
- assert(!(resolve_flags & (other_writers | any_reader)));
-
- if (!(resolve_flags & ILO_TEXTURE_CLEAR)) {
- const uint32_t first_clear_value = ilo_texture_get_slice(tex,
- level, first_slice)->clear_value;
- bool set_clear_value = false;
-
- for (i = 0; i < num_slices; i++) {
- const struct ilo_texture_slice *slice =
- ilo_texture_get_slice(tex, level, first_slice + i);
-
- if (slice->flags & other_writers) {
- ilo_blitter_rectlist_resolve_hiz(ilo->blitter,
- res, level, first_slice + i);
- } else if (slice->clear_value != first_clear_value &&
- (slice->flags & ILO_TEXTURE_RENDER_WRITE)) {
- ilo_blitter_rectlist_resolve_z(ilo->blitter,
- res, level, first_slice + i);
- set_clear_value = true;
- }
- }
-
- if (set_clear_value) {
- /* ILO_TEXTURE_CLEAR will be cleared later */
- ilo_texture_set_slice_clear_value(tex, level,
- first_slice, num_slices, first_clear_value);
- }
- }
- }
- else if ((resolve_flags & any_reader) ||
- ((resolve_flags & other_writers) &&
- !(resolve_flags & ILO_TEXTURE_CLEAR))) {
- /*
- * When there is at least a reader or writer, we need to perform a
- * Depth Buffer Resolve in case the resource was previously written
- * by ILO_TEXTURE_RENDER_WRITE.
- */
- for (i = 0; i < num_slices; i++) {
- const struct ilo_texture_slice *slice =
- ilo_texture_get_slice(tex, level, first_slice + i);
-
- if (slice->flags & ILO_TEXTURE_RENDER_WRITE) {
- ilo_blitter_rectlist_resolve_z(ilo->blitter,
- &tex->base, level, first_slice + i);
- }
- }
- }
-}
-
-/**
- * Initialize blit-related functions.
- */
-void
-ilo_init_blit_functions(struct ilo_context *ilo)
-{
- ilo->base.resource_copy_region = ilo_resource_copy_region;
- ilo->base.blit = ilo_blit;
- ilo->base.flush_resource = ilo_flush_resource;
-
- ilo->base.clear = ilo_clear;
- ilo->base.clear_render_target = ilo_clear_render_target;
- ilo->base.clear_depth_stencil = ilo_clear_depth_stencil;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_BLIT_H
-#define ILO_BLIT_H
-
-#include "ilo_common.h"
-#include "ilo_context.h"
-#include "ilo_state.h"
-#include "ilo_resource.h"
-
-void
-ilo_blit_resolve_slices_for_hiz(struct ilo_context *ilo,
- struct pipe_resource *res, unsigned level,
- unsigned first_slice, unsigned num_slices,
- unsigned resolve_flags);
-
-static inline void
-ilo_blit_resolve_slices(struct ilo_context *ilo,
- struct pipe_resource *res, unsigned level,
- unsigned first_slice, unsigned num_slices,
- unsigned resolve_flags)
-{
- struct ilo_texture *tex;
- unsigned slice_mask;
-
- if (res->target == PIPE_BUFFER)
- return;
-
- tex = ilo_texture(res);
-
- /*
- * This function is called frequently and we need to make it run faster.
- * As it is only used to resolve HiZ right now, return early when there is
- * no HiZ.
- */
- if (tex->image.aux.type != ILO_IMAGE_AUX_HIZ ||
- !ilo_image_can_enable_aux(&tex->image, level))
- return;
-
- if (tex->image.aux.type == ILO_IMAGE_AUX_HIZ &&
- ilo_image_can_enable_aux(&tex->image, level)) {
- ilo_blit_resolve_slices_for_hiz(ilo, res, level,
- first_slice, num_slices, resolve_flags);
- }
-
- slice_mask =
- ILO_TEXTURE_CPU_WRITE |
- ILO_TEXTURE_BLT_WRITE |
- ILO_TEXTURE_RENDER_WRITE;
- /* when there is a new writer, we may need to clear ILO_TEXTURE_CLEAR */
- if (resolve_flags & slice_mask)
- slice_mask |= ILO_TEXTURE_CLEAR;
-
- ilo_texture_set_slice_flags(tex, level,
- first_slice, num_slices, slice_mask, resolve_flags);
-}
-
-static inline void
-ilo_blit_resolve_resource(struct ilo_context *ilo,
- struct pipe_resource *res,
- unsigned resolve_flags)
-{
- unsigned lv;
-
- for (lv = 0; lv <= res->last_level; lv++) {
- const unsigned num_slices = (res->target == PIPE_TEXTURE_3D) ?
- u_minify(res->depth0, lv) : res->array_size;
-
- ilo_blit_resolve_slices(ilo, res, lv, 0, num_slices, resolve_flags);
- }
-}
-
-static inline void
-ilo_blit_resolve_surface(struct ilo_context *ilo,
- struct pipe_surface *surf,
- unsigned resolve_flags)
-{
- if (surf->texture->target == PIPE_BUFFER)
- return;
-
- ilo_blit_resolve_slices(ilo, surf->texture,
- surf->u.tex.level, surf->u.tex.first_layer,
- surf->u.tex.last_layer - surf->u.tex.first_layer + 1,
- resolve_flags);
-}
-
-static inline void
-ilo_blit_resolve_transfer(struct ilo_context *ilo,
- const struct pipe_transfer *xfer)
-{
- unsigned resolve_flags = 0;
-
- if (xfer->resource->target == PIPE_BUFFER)
- return;
-
- if (xfer->usage & PIPE_TRANSFER_READ)
- resolve_flags |= ILO_TEXTURE_CPU_READ;
- if (xfer->usage & PIPE_TRANSFER_WRITE)
- resolve_flags |= ILO_TEXTURE_CPU_WRITE;
-
- ilo_blit_resolve_slices(ilo, xfer->resource, xfer->level,
- xfer->box.z, xfer->box.depth, resolve_flags);
-}
-
-static inline void
-ilo_blit_resolve_view(struct ilo_context *ilo,
- const struct pipe_sampler_view *view)
-{
- const unsigned resolve_flags = ILO_TEXTURE_RENDER_READ;
- unsigned lv;
-
- if (view->texture->target == PIPE_BUFFER)
- return;
-
- for (lv = view->u.tex.first_level; lv <= view->u.tex.last_level; lv++) {
- unsigned first_slice, num_slices;
-
- if (view->texture->target == PIPE_TEXTURE_3D) {
- first_slice = 0;
- num_slices = u_minify(view->texture->depth0, lv);
- }
- else {
- first_slice = view->u.tex.first_layer;
- num_slices = view->u.tex.last_layer - view->u.tex.first_layer + 1;
- }
-
- ilo_blit_resolve_slices(ilo, view->texture,
- lv, first_slice, num_slices, resolve_flags);
- }
-}
-
-static inline void
-ilo_blit_resolve_framebuffer(struct ilo_context *ilo)
-{
- struct ilo_state_vector *vec = &ilo->state_vector;
- const struct pipe_framebuffer_state *fb = &vec->fb.state;
- unsigned sh, i;
-
- /* Not all bound views are sampled by the shaders. How do we tell? */
- for (sh = 0; sh < ARRAY_SIZE(vec->view); sh++) {
- for (i = 0; i < vec->view[sh].count; i++) {
- if (vec->view[sh].states[i])
- ilo_blit_resolve_view(ilo, vec->view[sh].states[i]);
- }
- }
-
- for (i = 0; i < fb->nr_cbufs; i++) {
- struct pipe_surface *surf = fb->cbufs[i];
- if (surf)
- ilo_blit_resolve_surface(ilo, surf, ILO_TEXTURE_RENDER_WRITE);
- }
-
- if (fb->zsbuf)
- ilo_blit_resolve_surface(ilo, fb->zsbuf, ILO_TEXTURE_RENDER_WRITE);
-}
-
-void
-ilo_init_blit_functions(struct ilo_context *ilo);
-
-#endif /* ILO_BLIT_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "util/u_blitter.h"
-
-#include "ilo_context.h"
-#include "ilo_blitter.h"
-
-static bool
-ilo_blitter_pipe_create(struct ilo_blitter *blitter)
-{
- if (blitter->pipe_blitter)
- return true;
-
- blitter->pipe_blitter = util_blitter_create(&blitter->ilo->base);
-
- return (blitter->pipe_blitter != NULL);
-}
-
-/**
- * Create a blitter. Because the use of util_blitter, this must be called
- * after the context is initialized.
- */
-struct ilo_blitter *
-ilo_blitter_create(struct ilo_context *ilo)
-{
- struct ilo_blitter *blitter;
-
- blitter = CALLOC_STRUCT(ilo_blitter);
- if (!blitter)
- return NULL;
-
- blitter->ilo = ilo;
-
- if (!ilo_blitter_pipe_create(blitter)) {
- FREE(blitter);
- return NULL;
- }
-
- return blitter;
-}
-
-void
-ilo_blitter_destroy(struct ilo_blitter *blitter)
-{
- if (blitter->pipe_blitter)
- util_blitter_destroy(blitter->pipe_blitter);
-
- FREE(blitter);
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_BLITTER_H
-#define ILO_BLITTER_H
-
-#include "ilo_common.h"
-#include "ilo_state.h"
-
-enum ilo_blitter_uses {
- ILO_BLITTER_USE_DSA = 1 << 0,
- ILO_BLITTER_USE_CC = 1 << 1,
- ILO_BLITTER_USE_VIEWPORT = 1 << 2,
- ILO_BLITTER_USE_FB_DEPTH = 1 << 3,
- ILO_BLITTER_USE_FB_STENCIL = 1 << 4,
-};
-
-struct blitter_context;
-struct pipe_resource;
-struct pipe_surface;
-struct ilo_context;
-
-struct ilo_blitter {
- struct ilo_context *ilo;
- struct blitter_context *pipe_blitter;
-
- /*
- * A minimal context with the goal to send RECTLISTs down the pipeline.
- */
- enum ilo_state_raster_earlyz_op earlyz_op;
- bool earlyz_stencil_clear;
- uint32_t uses;
-
- bool initialized;
-
- float vertices[3][2];
- struct gen6_3dprimitive_info draw_info;
-
- uint32_t vf_data[4];
- struct ilo_state_vf vf;
-
- struct ilo_state_vs vs;
- struct ilo_state_hs hs;
- struct ilo_state_ds ds;
- struct ilo_state_gs gs;
-
- struct ilo_state_sol sol;
-
- struct ilo_state_viewport vp;
- uint32_t vp_data[20];
-
- struct ilo_state_sbe sbe;
- struct ilo_state_ps ps;
- struct ilo_state_cc cc;
-
- uint32_t depth_clear_value;
-
- struct ilo_state_urb urb;
-
- struct {
- struct ilo_surface_cso dst;
- unsigned width, height;
- unsigned num_samples;
-
- struct ilo_state_raster rs;
- } fb;
-};
-
-struct ilo_blitter *
-ilo_blitter_create(struct ilo_context *ilo);
-
-void
-ilo_blitter_destroy(struct ilo_blitter *blitter);
-
-bool
-ilo_blitter_pipe_blit(struct ilo_blitter *blitter,
- const struct pipe_blit_info *info);
-
-bool
-ilo_blitter_pipe_copy_resource(struct ilo_blitter *blitter,
- struct pipe_resource *dst, unsigned dst_level,
- unsigned dst_x, unsigned dst_y, unsigned dst_z,
- struct pipe_resource *src, unsigned src_level,
- const struct pipe_box *src_box);
-
-bool
-ilo_blitter_pipe_clear_rt(struct ilo_blitter *blitter,
- struct pipe_surface *rt,
- const union pipe_color_union *color,
- unsigned x, unsigned y,
- unsigned width, unsigned height);
-
-bool
-ilo_blitter_pipe_clear_zs(struct ilo_blitter *blitter,
- struct pipe_surface *zs,
- unsigned clear_flags,
- double depth, unsigned stencil,
- unsigned x, unsigned y,
- unsigned width, unsigned height);
-
-bool
-ilo_blitter_pipe_clear_fb(struct ilo_blitter *blitter,
- unsigned buffers,
- const union pipe_color_union *color,
- double depth, unsigned stencil);
-
-bool
-ilo_blitter_blt_copy_resource(struct ilo_blitter *blitter,
- struct pipe_resource *dst, unsigned dst_level,
- unsigned dst_x, unsigned dst_y, unsigned dst_z,
- struct pipe_resource *src, unsigned src_level,
- const struct pipe_box *src_box);
-
-bool
-ilo_blitter_blt_clear_rt(struct ilo_blitter *blitter,
- struct pipe_surface *rt,
- const union pipe_color_union *color,
- unsigned x, unsigned y,
- unsigned width, unsigned height);
-
-bool
-ilo_blitter_blt_clear_zs(struct ilo_blitter *blitter,
- struct pipe_surface *zs,
- unsigned clear_flags,
- double depth, unsigned stencil,
- unsigned x, unsigned y,
- unsigned width, unsigned height);
-
-bool
-ilo_blitter_rectlist_clear_zs(struct ilo_blitter *blitter,
- struct pipe_surface *zs,
- unsigned clear_flags,
- double depth, unsigned stencil);
-
-void
-ilo_blitter_rectlist_resolve_z(struct ilo_blitter *blitter,
- struct pipe_resource *res,
- unsigned level, unsigned slice);
-
-void
-ilo_blitter_rectlist_resolve_hiz(struct ilo_blitter *blitter,
- struct pipe_resource *res,
- unsigned level, unsigned slice);
-
-#endif /* ILO_BLITTER_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "genhw/genhw.h"
-#include "core/ilo_builder_mi.h"
-#include "core/ilo_builder_blt.h"
-#include "util/u_pack_color.h"
-
-#include "ilo_context.h"
-#include "ilo_cp.h"
-#include "ilo_blit.h"
-#include "ilo_resource.h"
-#include "ilo_blitter.h"
-
-static uint32_t
-ilo_blitter_blt_begin(struct ilo_blitter *blitter, int max_cmd_size,
- struct intel_bo *dst,
- enum gen_surface_tiling dst_tiling,
- struct intel_bo *src,
- enum gen_surface_tiling src_tiling)
-{
- struct ilo_cp *cp = blitter->ilo->cp;
- struct intel_bo *aper_check[2];
- int count;
- uint32_t swctrl;
-
- /* change owner */
- ilo_cp_set_owner(cp, INTEL_RING_BLT, NULL);
-
- /* check aperture space */
- aper_check[0] = dst;
- count = 1;
-
- if (src) {
- aper_check[1] = src;
- count++;
- }
-
- if (!ilo_builder_validate(&cp->builder, count, aper_check))
- ilo_cp_submit(cp, "out of aperture");
-
- /* set BCS_SWCTRL */
- swctrl = 0x0;
-
- assert(dst_tiling == GEN6_TILING_NONE ||
- dst_tiling == GEN6_TILING_X ||
- dst_tiling == GEN6_TILING_Y);
- assert(src_tiling == GEN6_TILING_NONE ||
- src_tiling == GEN6_TILING_X ||
- src_tiling == GEN6_TILING_Y);
-
- if (dst_tiling == GEN6_TILING_Y) {
- swctrl |= GEN6_REG_BCS_SWCTRL_DST_TILING_Y << 16 |
- GEN6_REG_BCS_SWCTRL_DST_TILING_Y;
- }
-
- if (src && src_tiling == GEN6_TILING_Y) {
- swctrl |= GEN6_REG_BCS_SWCTRL_SRC_TILING_Y << 16 |
- GEN6_REG_BCS_SWCTRL_SRC_TILING_Y;
- }
-
- /*
- * Most clients expect BLT engine to be stateless. If we have to set
- * BCS_SWCTRL to a non-default value, we have to set it back in the same
- * batch buffer.
- */
- if (swctrl)
- max_cmd_size += (4 + 3) * 2;
-
- if (ilo_cp_space(cp) < max_cmd_size) {
- ilo_cp_submit(cp, "out of space");
- assert(ilo_cp_space(cp) >= max_cmd_size);
- }
-
- if (swctrl) {
- /*
- * From the Ivy Bridge PRM, volume 1 part 4, page 133:
- *
- * "SW is required to flush the HW before changing the polarity of
- * this bit (Tile Y Destination/Source)."
- */
- gen6_MI_FLUSH_DW(&cp->builder);
- gen6_MI_LOAD_REGISTER_IMM(&cp->builder, GEN6_REG_BCS_SWCTRL, swctrl);
-
- swctrl &= ~(GEN6_REG_BCS_SWCTRL_DST_TILING_Y |
- GEN6_REG_BCS_SWCTRL_SRC_TILING_Y);
- }
-
- return swctrl;
-}
-
-static void
-ilo_blitter_blt_end(struct ilo_blitter *blitter, uint32_t swctrl)
-{
- struct ilo_builder *builder = &blitter->ilo->cp->builder;
-
- /* set BCS_SWCTRL back */
- if (swctrl) {
- gen6_MI_FLUSH_DW(builder);
- gen6_MI_LOAD_REGISTER_IMM(builder, GEN6_REG_BCS_SWCTRL, swctrl);
- }
-}
-
-static bool
-buf_clear_region(struct ilo_blitter *blitter,
- struct ilo_buffer_resource *buf, unsigned offset,
- uint32_t val, unsigned size,
- enum gen6_blt_mask value_mask,
- enum gen6_blt_mask write_mask)
-{
- const uint8_t rop = 0xf0; /* PATCOPY */
- const int cpp = gen6_blt_translate_value_cpp(value_mask);
- struct ilo_builder *builder = &blitter->ilo->cp->builder;
- struct gen6_blt_bo dst;
-
- if (offset % cpp || size % cpp)
- return false;
-
- dst.bo = buf->vma.bo;
- dst.offset = buf->vma.bo_offset + offset;
-
- ilo_blitter_blt_begin(blitter, GEN6_COLOR_BLT__SIZE *
- (1 + size / 32764 / gen6_blt_max_scanlines),
- dst.bo, GEN6_TILING_NONE, NULL, GEN6_TILING_NONE);
-
- while (size) {
- unsigned width, height;
-
- width = size;
- height = 1;
-
- if (width > gen6_blt_max_bytes_per_scanline) {
- /* less than INT16_MAX and dword-aligned */
- width = 32764;
- height = size / width;
- if (height > gen6_blt_max_scanlines)
- height = gen6_blt_max_scanlines;
-
- dst.pitch = width;
- } else {
- dst.pitch = 0;
- }
-
- gen6_COLOR_BLT(builder, &dst, val,
- width, height, rop, value_mask, write_mask);
-
- dst.offset += dst.pitch * height;
- size -= width * height;
- }
-
- ilo_blitter_blt_end(blitter, 0);
-
- return true;
-}
-
-static bool
-buf_copy_region(struct ilo_blitter *blitter,
- struct ilo_buffer_resource *dst_buf, unsigned dst_offset,
- struct ilo_buffer_resource *src_buf, unsigned src_offset,
- unsigned size)
-{
- const uint8_t rop = 0xcc; /* SRCCOPY */
- struct ilo_builder *builder = &blitter->ilo->cp->builder;
- struct gen6_blt_bo dst, src;
-
- dst.bo = dst_buf->vma.bo;
- dst.offset = dst_buf->vma.bo_offset + dst_offset;
- dst.pitch = 0;
-
- src.bo = src_buf->vma.bo;
- src.offset = src_buf->vma.bo_offset + src_offset;
- src.pitch = 0;
-
- ilo_blitter_blt_begin(blitter, GEN6_SRC_COPY_BLT__SIZE *
- (1 + size / 32764 / gen6_blt_max_scanlines),
- dst_buf->vma.bo, GEN6_TILING_NONE,
- src_buf->vma.bo, GEN6_TILING_NONE);
-
- while (size) {
- unsigned width, height;
-
- width = size;
- height = 1;
-
- if (width > gen6_blt_max_bytes_per_scanline) {
- /* less than INT16_MAX and dword-aligned */
- width = 32764;
- height = size / width;
- if (height > gen6_blt_max_scanlines)
- height = gen6_blt_max_scanlines;
-
- dst.pitch = width;
- src.pitch = width;
- } else {
- dst.pitch = 0;
- src.pitch = 0;
- }
-
- gen6_SRC_COPY_BLT(builder, &dst, &src,
- width, height, rop, GEN6_BLT_MASK_8, GEN6_BLT_MASK_8);
-
- dst.offset += dst.pitch * height;
- src.offset += src.pitch * height;
- size -= width * height;
- }
-
- ilo_blitter_blt_end(blitter, 0);
-
- return true;
-}
-
-static bool
-tex_clear_region(struct ilo_blitter *blitter,
- struct ilo_texture *dst_tex, unsigned dst_level,
- const struct pipe_box *dst_box,
- uint32_t val,
- enum gen6_blt_mask value_mask,
- enum gen6_blt_mask write_mask)
-{
- const int cpp = gen6_blt_translate_value_cpp(value_mask);
- const unsigned max_extent = 32767; /* INT16_MAX */
- const uint8_t rop = 0xf0; /* PATCOPY */
- struct ilo_builder *builder = &blitter->ilo->cp->builder;
- struct gen6_blt_xy_bo dst;
- uint32_t swctrl;
- int slice;
-
- /* no W-tiling nor separate stencil support */
- if (dst_tex->image.tiling == GEN8_TILING_W || dst_tex->separate_s8)
- return false;
-
- if (dst_tex->image.bo_stride > max_extent)
- return false;
-
- if (dst_box->width * cpp > gen6_blt_max_bytes_per_scanline)
- return false;
-
- dst.bo = dst_tex->vma.bo;
- dst.offset = dst_tex->vma.bo_offset;
- dst.pitch = dst_tex->image.bo_stride;
- dst.tiling = dst_tex->image.tiling;
-
- swctrl = ilo_blitter_blt_begin(blitter,
- GEN6_XY_COLOR_BLT__SIZE * dst_box->depth,
- dst_tex->vma.bo, dst_tex->image.tiling, NULL, GEN6_TILING_NONE);
-
- for (slice = 0; slice < dst_box->depth; slice++) {
- unsigned x, y;
-
- ilo_image_get_slice_pos(&dst_tex->image,
- dst_level, dst_box->z + slice, &x, &y);
-
- dst.x = x + dst_box->x;
- dst.y = y + dst_box->y;
-
- if (dst.x + dst_box->width > max_extent ||
- dst.y + dst_box->height > max_extent)
- break;
-
- gen6_XY_COLOR_BLT(builder, &dst, val,
- dst_box->width, dst_box->height, rop, value_mask, write_mask);
- }
-
- ilo_blitter_blt_end(blitter, swctrl);
-
- return (slice == dst_box->depth);
-}
-
-static bool
-tex_copy_region(struct ilo_blitter *blitter,
- struct ilo_texture *dst_tex,
- unsigned dst_level,
- unsigned dst_x, unsigned dst_y, unsigned dst_z,
- struct ilo_texture *src_tex,
- unsigned src_level,
- const struct pipe_box *src_box)
-{
- const struct util_format_description *desc =
- util_format_description(dst_tex->image_format);
- const unsigned max_extent = 32767; /* INT16_MAX */
- const uint8_t rop = 0xcc; /* SRCCOPY */
- struct ilo_builder *builder = &blitter->ilo->cp->builder;
- enum gen6_blt_mask mask;
- struct gen6_blt_xy_bo dst, src;
- uint32_t swctrl;
- int cpp, xscale, slice;
-
- /* no W-tiling nor separate stencil support */
- if (dst_tex->image.tiling == GEN8_TILING_W || dst_tex->separate_s8 ||
- src_tex->image.tiling == GEN8_TILING_W || src_tex->separate_s8)
- return false;
-
- if (dst_tex->image.bo_stride > max_extent ||
- src_tex->image.bo_stride > max_extent)
- return false;
-
- cpp = desc->block.bits / 8;
- xscale = 1;
-
- /* accommodate for larger cpp */
- if (cpp > 4) {
- if (cpp % 2 == 1)
- return false;
-
- cpp = (cpp % 4 == 0) ? 4 : 2;
- xscale = (desc->block.bits / 8) / cpp;
- }
-
- if (src_box->width * cpp * xscale > gen6_blt_max_bytes_per_scanline)
- return false;
-
- switch (cpp) {
- case 1:
- mask = GEN6_BLT_MASK_8;
- break;
- case 2:
- mask = GEN6_BLT_MASK_16;
- break;
- case 4:
- mask = GEN6_BLT_MASK_32;
- break;
- default:
- return false;
- break;
- }
-
- dst.bo = dst_tex->vma.bo;
- dst.offset = dst_tex->vma.bo_offset;
- dst.pitch = dst_tex->image.bo_stride;
- dst.tiling = dst_tex->image.tiling;
-
- src.bo = src_tex->vma.bo;
- src.offset = src_tex->vma.bo_offset;
- src.pitch = src_tex->image.bo_stride;
- src.tiling = src_tex->image.tiling;
-
- swctrl = ilo_blitter_blt_begin(blitter,
- GEN6_XY_SRC_COPY_BLT__SIZE * src_box->depth,
- dst.bo, dst.tiling, src.bo, src.tiling);
-
- for (slice = 0; slice < src_box->depth; slice++) {
- unsigned dx, dy, sx, sy, width, height;
-
- ilo_image_get_slice_pos(&dst_tex->image,
- dst_level, dst_z + slice, &dx, &dy);
- ilo_image_get_slice_pos(&src_tex->image,
- src_level, src_box->z + slice, &sx, &sy);
-
- dst.x = (dx + dst_x) * xscale;
- dst.y = dy + dst_y;
- src.x = (sx + src_box->x) * xscale;
- src.y = sy + src_box->y;
- width = src_box->width * xscale;
- height = src_box->height;
-
- /* in blocks */
- dst.x /= desc->block.width;
- dst.y /= desc->block.height;
- src.x /= desc->block.width;
- src.y /= desc->block.height;
- width /= desc->block.width;
- height /= desc->block.height;
-
- if (src.x + width > max_extent || src.y + height > max_extent ||
- dst.x + width > max_extent || dst.y + height > max_extent)
- break;
-
- gen6_XY_SRC_COPY_BLT(builder, &dst, &src,
- width, height, rop, mask, mask);
- }
-
- ilo_blitter_blt_end(blitter, swctrl);
-
- return (slice == src_box->depth);
-}
-
-bool
-ilo_blitter_blt_copy_resource(struct ilo_blitter *blitter,
- struct pipe_resource *dst, unsigned dst_level,
- unsigned dst_x, unsigned dst_y, unsigned dst_z,
- struct pipe_resource *src, unsigned src_level,
- const struct pipe_box *src_box)
-{
- bool success;
-
- ilo_blit_resolve_slices(blitter->ilo, src, src_level,
- src_box->z, src_box->depth, ILO_TEXTURE_BLT_READ);
- ilo_blit_resolve_slices(blitter->ilo, dst, dst_level,
- dst_z, src_box->depth, ILO_TEXTURE_BLT_WRITE);
-
- if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
- const unsigned dst_offset = dst_x;
- const unsigned src_offset = src_box->x;
- const unsigned size = src_box->width;
-
- assert(dst_level == 0 && dst_y == 0 && dst_z == 0);
- assert(src_level == 0 &&
- src_box->y == 0 &&
- src_box->z == 0 &&
- src_box->height == 1 &&
- src_box->depth == 1);
-
- success = buf_copy_region(blitter, ilo_buffer_resource(dst), dst_offset,
- ilo_buffer_resource(src), src_offset, size);
- }
- else if (dst->target != PIPE_BUFFER && src->target != PIPE_BUFFER) {
- success = tex_copy_region(blitter,
- ilo_texture(dst), dst_level, dst_x, dst_y, dst_z,
- ilo_texture(src), src_level, src_box);
- }
- else {
- success = false;
- }
-
- return success;
-}
-
-bool
-ilo_blitter_blt_clear_rt(struct ilo_blitter *blitter,
- struct pipe_surface *rt,
- const union pipe_color_union *color,
- unsigned x, unsigned y,
- unsigned width, unsigned height)
-{
- const int cpp = util_format_get_blocksize(rt->format);
- enum gen6_blt_mask mask;
- union util_color packed;
- bool success;
-
- if (ilo_skip_rendering(blitter->ilo))
- return true;
-
- switch (cpp) {
- case 1:
- mask = GEN6_BLT_MASK_8;
- break;
- case 2:
- mask = GEN6_BLT_MASK_16;
- break;
- case 4:
- mask = GEN6_BLT_MASK_32;
- break;
- default:
- return false;
- break;
- }
-
- if (util_format_is_pure_integer(rt->format) ||
- util_format_is_compressed(rt->format))
- return false;
-
- ilo_blit_resolve_surface(blitter->ilo, rt, ILO_TEXTURE_BLT_WRITE);
-
- util_pack_color(color->f, rt->format, &packed);
-
- if (rt->texture->target == PIPE_BUFFER) {
- unsigned offset, end, size;
-
- assert(y == 0 && height == 1);
-
- offset = (rt->u.buf.first_element + x) * cpp;
- end = (rt->u.buf.last_element + 1) * cpp;
-
- size = width * cpp;
- if (offset + size > end)
- size = end - offset;
-
- success = buf_clear_region(blitter, ilo_buffer_resource(rt->texture),
- offset, packed.ui[0], size, mask, mask);
- }
- else {
- struct pipe_box box;
-
- u_box_3d(x, y, rt->u.tex.first_layer, width, height,
- rt->u.tex.last_layer - rt->u.tex.first_layer + 1, &box);
-
- success = tex_clear_region(blitter, ilo_texture(rt->texture),
- rt->u.tex.level, &box, packed.ui[0], mask, mask);
- }
-
- return success;
-}
-
-bool
-ilo_blitter_blt_clear_zs(struct ilo_blitter *blitter,
- struct pipe_surface *zs,
- unsigned clear_flags,
- double depth, unsigned stencil,
- unsigned x, unsigned y,
- unsigned width, unsigned height)
-{
- enum gen6_blt_mask value_mask, write_mask;
- struct pipe_box box;
- uint32_t val;
-
- if (ilo_skip_rendering(blitter->ilo))
- return true;
-
- switch (zs->format) {
- case PIPE_FORMAT_Z16_UNORM:
- if (!(clear_flags & PIPE_CLEAR_DEPTH))
- return true;
-
- value_mask = GEN6_BLT_MASK_16;
- write_mask = GEN6_BLT_MASK_16;
- break;
- case PIPE_FORMAT_Z32_FLOAT:
- if (!(clear_flags & PIPE_CLEAR_DEPTH))
- return true;
-
- value_mask = GEN6_BLT_MASK_32;
- write_mask = GEN6_BLT_MASK_32;
- break;
- case PIPE_FORMAT_Z24X8_UNORM:
- if (!(clear_flags & PIPE_CLEAR_DEPTH))
- return true;
-
- value_mask = GEN6_BLT_MASK_32;
- write_mask = GEN6_BLT_MASK_32_LO;
- break;
- case PIPE_FORMAT_Z24_UNORM_S8_UINT:
- if (!(clear_flags & PIPE_CLEAR_DEPTHSTENCIL))
- return true;
-
- value_mask = GEN6_BLT_MASK_32;
-
- if ((clear_flags & PIPE_CLEAR_DEPTHSTENCIL) == PIPE_CLEAR_DEPTHSTENCIL)
- write_mask = GEN6_BLT_MASK_32;
- else if (clear_flags & PIPE_CLEAR_DEPTH)
- write_mask = GEN6_BLT_MASK_32_LO;
- else
- write_mask = GEN6_BLT_MASK_32_HI;
- break;
- default:
- return false;
- break;
- }
-
- ilo_blit_resolve_surface(blitter->ilo, zs, ILO_TEXTURE_BLT_WRITE);
-
- val = util_pack_z_stencil(zs->format, depth, stencil);
-
- u_box_3d(x, y, zs->u.tex.first_layer, width, height,
- zs->u.tex.last_layer - zs->u.tex.first_layer + 1, &box);
-
- assert(zs->texture->target != PIPE_BUFFER);
-
- return tex_clear_region(blitter, ilo_texture(zs->texture),
- zs->u.tex.level, &box, val, value_mask, write_mask);
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "util/u_blitter.h"
-#include "util/u_surface.h"
-
-#include "ilo_context.h"
-#include "ilo_blitter.h"
-
-enum ilo_blitter_pipe_op {
- ILO_BLITTER_PIPE_BLIT,
- ILO_BLITTER_PIPE_COPY,
- ILO_BLITTER_PIPE_CLEAR,
- ILO_BLITTER_PIPE_CLEAR_FB,
-};
-
-static void
-ilo_blitter_pipe_begin(struct ilo_blitter *blitter,
- enum ilo_blitter_pipe_op op,
- bool scissor_enable)
-{
- struct blitter_context *b = blitter->pipe_blitter;
- struct ilo_state_vector *vec = &blitter->ilo->state_vector;
-
- /* vertex states */
- util_blitter_save_vertex_buffer_slot(b, vec->vb.states);
- util_blitter_save_vertex_elements(b, (void *) vec->ve);
- util_blitter_save_vertex_shader(b, vec->vs);
- util_blitter_save_geometry_shader(b, vec->gs);
- util_blitter_save_so_targets(b, vec->so.count, vec->so.states);
- util_blitter_save_rasterizer(b, (void *) vec->rasterizer);
-
- /* fragment states */
- util_blitter_save_fragment_shader(b, vec->fs);
- util_blitter_save_depth_stencil_alpha(b, (void *) vec->dsa);
- util_blitter_save_blend(b, (void *) vec->blend);
- util_blitter_save_sample_mask(b, vec->sample_mask);
- util_blitter_save_stencil_ref(b, &vec->stencil_ref);
- util_blitter_save_viewport(b, &vec->viewport.viewport0);
-
- if (scissor_enable)
- util_blitter_save_scissor(b, &vec->viewport.scissor0);
-
- switch (op) {
- case ILO_BLITTER_PIPE_BLIT:
- case ILO_BLITTER_PIPE_COPY:
- /*
- * We are about to call util_blitter_blit() or
- * util_blitter_copy_texture(). Note that util_blitter uses at most two
- * textures.
- */
- util_blitter_save_fragment_sampler_states(b,
- 2, (void **) vec->sampler[PIPE_SHADER_FRAGMENT].cso);
-
- util_blitter_save_fragment_sampler_views(b,
- vec->view[PIPE_SHADER_FRAGMENT].count,
- vec->view[PIPE_SHADER_FRAGMENT].states);
-
- util_blitter_save_framebuffer(b, &vec->fb.state);
-
- /* resource_copy_region() or blit() does not honor render condition */
- util_blitter_save_render_condition(b,
- blitter->ilo->render_condition.query,
- blitter->ilo->render_condition.condition,
- blitter->ilo->render_condition.mode);
- break;
- case ILO_BLITTER_PIPE_CLEAR:
- /*
- * we are about to call util_blitter_clear_render_target() or
- * util_blitter_clear_depth_stencil()
- */
- util_blitter_save_framebuffer(b, &vec->fb.state);
- break;
- case ILO_BLITTER_PIPE_CLEAR_FB:
- /* we are about to call util_blitter_clear() */
- break;
- default:
- break;
- }
-}
-
-static void
-ilo_blitter_pipe_end(struct ilo_blitter *blitter)
-{
-}
-
-bool
-ilo_blitter_pipe_blit(struct ilo_blitter *blitter,
- const struct pipe_blit_info *info)
-{
- struct blitter_context *b = blitter->pipe_blitter;
- struct pipe_blit_info skip_stencil;
-
- if (util_try_blit_via_copy_region(&blitter->ilo->base, info))
- return true;
-
- if (!util_blitter_is_blit_supported(b, info)) {
- /* try without stencil */
- if (info->mask & PIPE_MASK_S) {
- skip_stencil = *info;
- skip_stencil.mask = info->mask & ~PIPE_MASK_S;
-
- if (util_blitter_is_blit_supported(blitter->pipe_blitter,
- &skip_stencil)) {
- ilo_warn("ignore stencil buffer blitting\n");
- info = &skip_stencil;
- }
- }
-
- if (info != &skip_stencil) {
- ilo_warn("failed to blit with pipe blitter\n");
- return false;
- }
- }
-
- ilo_blitter_pipe_begin(blitter, ILO_BLITTER_PIPE_BLIT,
- info->scissor_enable);
- util_blitter_blit(b, info);
- ilo_blitter_pipe_end(blitter);
-
- return true;
-}
-
-bool
-ilo_blitter_pipe_copy_resource(struct ilo_blitter *blitter,
- struct pipe_resource *dst, unsigned dst_level,
- unsigned dst_x, unsigned dst_y, unsigned dst_z,
- struct pipe_resource *src, unsigned src_level,
- const struct pipe_box *src_box)
-{
- /* not until we allow rendertargets to be buffers */
- if (dst->target == PIPE_BUFFER || src->target == PIPE_BUFFER)
- return false;
-
- if (!util_blitter_is_copy_supported(blitter->pipe_blitter, dst, src))
- return false;
-
- ilo_blitter_pipe_begin(blitter, ILO_BLITTER_PIPE_COPY, false);
-
- util_blitter_copy_texture(blitter->pipe_blitter,
- dst, dst_level, dst_x, dst_y, dst_z,
- src, src_level, src_box);
-
- ilo_blitter_pipe_end(blitter);
-
- return true;
-}
-
-bool
-ilo_blitter_pipe_clear_rt(struct ilo_blitter *blitter,
- struct pipe_surface *rt,
- const union pipe_color_union *color,
- unsigned x, unsigned y,
- unsigned width, unsigned height)
-{
- ilo_blitter_pipe_begin(blitter, ILO_BLITTER_PIPE_CLEAR, false);
-
- util_blitter_clear_render_target(blitter->pipe_blitter,
- rt, color, x, y, width, height);
-
- ilo_blitter_pipe_end(blitter);
-
- return true;
-}
-
-bool
-ilo_blitter_pipe_clear_zs(struct ilo_blitter *blitter,
- struct pipe_surface *zs,
- unsigned clear_flags,
- double depth, unsigned stencil,
- unsigned x, unsigned y,
- unsigned width, unsigned height)
-{
- ilo_blitter_pipe_begin(blitter, ILO_BLITTER_PIPE_CLEAR, false);
-
- util_blitter_clear_depth_stencil(blitter->pipe_blitter,
- zs, clear_flags, depth, stencil, x, y, width, height);
-
- ilo_blitter_pipe_end(blitter);
-
- return true;
-}
-
-bool
-ilo_blitter_pipe_clear_fb(struct ilo_blitter *blitter,
- unsigned buffers,
- const union pipe_color_union *color,
- double depth, unsigned stencil)
-{
- struct ilo_state_vector *vec = &blitter->ilo->state_vector;
-
- /* TODO we should pause/resume some queries */
- ilo_blitter_pipe_begin(blitter, ILO_BLITTER_PIPE_CLEAR_FB, false);
-
- util_blitter_clear(blitter->pipe_blitter,
- vec->fb.state.width, vec->fb.state.height, 1,
- buffers, color, depth, stencil);
-
- ilo_blitter_pipe_end(blitter);
-
- return true;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "util/u_draw.h"
-#include "util/u_pack_color.h"
-
-#include "ilo_draw.h"
-#include "ilo_state.h"
-#include "ilo_blit.h"
-#include "ilo_blitter.h"
-
-/**
- * Set the states that are invariant between all ops.
- */
-static bool
-ilo_blitter_set_invariants(struct ilo_blitter *blitter)
-{
- struct ilo_state_vf_element_info elem;
-
- if (blitter->initialized)
- return true;
-
- /* a rectangle has 3 vertices in a RECTLIST */
- blitter->draw_info.topology = GEN6_3DPRIM_RECTLIST;
- blitter->draw_info.vertex_count = 3;
- blitter->draw_info.instance_count = 1;
-
- memset(&elem, 0, sizeof(elem));
- /* only vertex X and Y */
- elem.format = GEN6_FORMAT_R32G32_FLOAT;
- elem.format_size = 8;
- elem.component_count = 2;
-
- ilo_state_vf_init_for_rectlist(&blitter->vf, blitter->ilo->dev,
- blitter->vf_data, sizeof(blitter->vf_data), &elem, 1);
-
- ilo_state_vs_init_disabled(&blitter->vs, blitter->ilo->dev);
- ilo_state_hs_init_disabled(&blitter->hs, blitter->ilo->dev);
- ilo_state_ds_init_disabled(&blitter->ds, blitter->ilo->dev);
- ilo_state_gs_init_disabled(&blitter->gs, blitter->ilo->dev);
- ilo_state_sol_init_disabled(&blitter->sol, blitter->ilo->dev, false);
-
- /**
- * From the Haswell PRM, volume 7, page 615:
- *
- * "The clear value must be between the min and max depth values
- * (inclusive) defined in the CC_VIEWPORT."
- *
- * Even though clipping and viewport transformation will be disabled, we
- * still need to set up the viewport states.
- */
- ilo_state_viewport_init_for_rectlist(&blitter->vp, blitter->ilo->dev,
- blitter->vp_data, sizeof(blitter->vp_data));
-
- ilo_state_sbe_init_for_rectlist(&blitter->sbe, blitter->ilo->dev, 0, 0);
- ilo_state_ps_init_disabled(&blitter->ps, blitter->ilo->dev);
-
- ilo_state_urb_init_for_rectlist(&blitter->urb, blitter->ilo->dev,
- ilo_state_vf_get_attr_count(&blitter->vf));
-
- blitter->initialized = true;
-
- return true;
-}
-
-static void
-ilo_blitter_set_earlyz_op(struct ilo_blitter *blitter,
- enum ilo_state_raster_earlyz_op op,
- bool earlyz_stencil_clear)
-{
- blitter->earlyz_op = op;
- blitter->earlyz_stencil_clear = earlyz_stencil_clear;
-}
-
-/**
- * Set the rectangle primitive.
- */
-static void
-ilo_blitter_set_rectlist(struct ilo_blitter *blitter,
- unsigned x, unsigned y,
- unsigned width, unsigned height)
-{
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 11:
- *
- * "(RECTLIST) A list of independent rectangles, where only 3 vertices
- * are provided per rectangle object, with the fourth vertex implied
- * by the definition of a rectangle. V0=LowerRight, V1=LowerLeft,
- * V2=UpperLeft. Implied V3 = V0- V1+V2."
- */
- blitter->vertices[0][0] = (float) (x + width);
- blitter->vertices[0][1] = (float) (y + height);
- blitter->vertices[1][0] = (float) x;
- blitter->vertices[1][1] = (float) (y + height);
- blitter->vertices[2][0] = (float) x;
- blitter->vertices[2][1] = (float) y;
-}
-
-static void
-ilo_blitter_set_depth_clear_value(struct ilo_blitter *blitter,
- uint32_t depth)
-{
- blitter->depth_clear_value = depth;
-}
-
-static void
-ilo_blitter_set_cc(struct ilo_blitter *blitter,
- const struct ilo_state_cc_info *info)
-{
- memset(&blitter->cc, 0, sizeof(blitter->cc));
- ilo_state_cc_init(&blitter->cc, blitter->ilo->dev, info);
-}
-
-static void
-ilo_blitter_set_fb_rs(struct ilo_blitter *blitter)
-{
- memset(&blitter->fb.rs, 0, sizeof(blitter->fb.rs));
- ilo_state_raster_init_for_rectlist(&blitter->fb.rs, blitter->ilo->dev,
- blitter->fb.num_samples, blitter->earlyz_op,
- blitter->earlyz_stencil_clear);
-}
-
-static void
-ilo_blitter_set_fb(struct ilo_blitter *blitter,
- struct pipe_resource *res, unsigned level,
- const struct ilo_surface_cso *cso)
-{
- struct ilo_texture *tex = ilo_texture(res);
-
- blitter->fb.width = u_minify(tex->image.width0, level);
- blitter->fb.height = u_minify(tex->image.height0, level);
-
- blitter->fb.num_samples = res->nr_samples;
- if (!blitter->fb.num_samples)
- blitter->fb.num_samples = 1;
-
- memcpy(&blitter->fb.dst, cso, sizeof(*cso));
-
- ilo_blitter_set_fb_rs(blitter);
-}
-
-static void
-ilo_blitter_set_fb_from_surface(struct ilo_blitter *blitter,
- struct pipe_surface *surf)
-{
- ilo_blitter_set_fb(blitter, surf->texture, surf->u.tex.level,
- (const struct ilo_surface_cso *) surf);
-}
-
-static void
-ilo_blitter_set_fb_from_resource(struct ilo_blitter *blitter,
- struct pipe_resource *res,
- enum pipe_format format,
- unsigned level, unsigned slice)
-{
- struct pipe_surface templ, *surf;
-
- memset(&templ, 0, sizeof(templ));
- templ.format = format;
- templ.u.tex.level = level;
- templ.u.tex.first_layer = slice;
- templ.u.tex.last_layer = slice;
-
- /* if we did not call create_surface(), it would never fail */
- surf = blitter->ilo->base.create_surface(&blitter->ilo->base, res, &templ);
- assert(surf);
-
- ilo_blitter_set_fb(blitter, res, level,
- (const struct ilo_surface_cso *) surf);
-
- pipe_surface_reference(&surf, NULL);
-}
-
-static void
-ilo_blitter_set_uses(struct ilo_blitter *blitter, uint32_t uses)
-{
- blitter->uses = uses;
-}
-
-static void
-hiz_align_fb(struct ilo_blitter *blitter)
-{
- unsigned align_w, align_h;
-
- switch (blitter->earlyz_op) {
- case ILO_STATE_RASTER_EARLYZ_DEPTH_CLEAR:
- case ILO_STATE_RASTER_EARLYZ_DEPTH_RESOLVE:
- break;
- default:
- return;
- break;
- }
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 313-314:
- *
- * "A rectangle primitive representing the clear area is delivered. The
- * primitive must adhere to the following restrictions on size:
- *
- * - If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
- * aligned to an 8x4 pixel block relative to the upper left corner
- * of the depth buffer, and contain an integer number of these pixel
- * blocks, and all 8x4 pixels must be lit.
- *
- * - If Number of Multisamples is NUMSAMPLES_4, the rectangle must be
- * aligned to a 4x2 pixel block (8x4 sample block) relative to the
- * upper left corner of the depth buffer, and contain an integer
- * number of these pixel blocks, and all samples of the 4x2 pixels
- * must be lit
- *
- * - If Number of Multisamples is NUMSAMPLES_8, the rectangle must be
- * aligned to a 2x2 pixel block (8x4 sample block) relative to the
- * upper left corner of the depth buffer, and contain an integer
- * number of these pixel blocks, and all samples of the 2x2 pixels
- * must be list."
- *
- * "The following is required when performing a depth buffer resolve:
- *
- * - A rectangle primitive of the same size as the previous depth
- * buffer clear operation must be delivered, and depth buffer state
- * cannot have changed since the previous depth buffer clear
- * operation."
- */
- switch (blitter->fb.num_samples) {
- case 1:
- align_w = 8;
- align_h = 4;
- break;
- case 2:
- align_w = 4;
- align_h = 4;
- break;
- case 4:
- align_w = 4;
- align_h = 2;
- break;
- case 8:
- default:
- align_w = 2;
- align_h = 2;
- break;
- }
-
- if (blitter->fb.width % align_w || blitter->fb.height % align_h) {
- blitter->fb.width = align(blitter->fb.width, align_w);
- blitter->fb.height = align(blitter->fb.height, align_h);
- }
-}
-
-static void
-hiz_emit_rectlist(struct ilo_blitter *blitter)
-{
- hiz_align_fb(blitter);
-
- ilo_blitter_set_rectlist(blitter, 0, 0,
- blitter->fb.width, blitter->fb.height);
-
- ilo_draw_rectlist(blitter->ilo);
-}
-
-static bool
-hiz_can_clear_zs(const struct ilo_blitter *blitter,
- const struct ilo_texture *tex)
-{
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 314:
- *
- * "Several cases exist where Depth Buffer Clear cannot be enabled (the
- * legacy method of clearing must be performed):
- *
- * - If the depth buffer format is D32_FLOAT_S8X24_UINT or
- * D24_UNORM_S8_UINT.
- *
- * - If stencil test is enabled but the separate stencil buffer is
- * disabled.
- *
- * - [DevSNB-A{W/A}]: ...
- *
- * - [DevSNB{W/A}]: When depth buffer format is D16_UNORM and the
- * width of the map (LOD0) is not multiple of 16, fast clear
- * optimization must be disabled."
- *
- * From the Ivy Bridge PRM, volume 2 part 1, page 313:
- *
- * "Several cases exist where Depth Buffer Clear cannot be enabled (the
- * legacy method of clearing must be performed):
- *
- * - If the depth buffer format is D32_FLOAT_S8X24_UINT or
- * D24_UNORM_S8_UINT.
- *
- * - If stencil test is enabled but the separate stencil buffer is
- * disabled."
- *
- * The truth is when HiZ is enabled, separate stencil is also enabled on
- * all GENs. The depth buffer format cannot be combined depth/stencil.
- */
- switch (tex->image_format) {
- case PIPE_FORMAT_Z16_UNORM:
- if (ilo_dev_gen(blitter->ilo->dev) == ILO_GEN(6) &&
- tex->base.width0 % 16)
- return false;
- break;
- case PIPE_FORMAT_Z24_UNORM_S8_UINT:
- case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
- assert(!"HiZ with combined depth/stencil");
- return false;
- break;
- default:
- break;
- }
-
- return true;
-}
-
-bool
-ilo_blitter_rectlist_clear_zs(struct ilo_blitter *blitter,
- struct pipe_surface *zs,
- unsigned clear_flags,
- double depth, unsigned stencil)
-{
- struct ilo_texture *tex = ilo_texture(zs->texture);
- struct ilo_state_cc_info info;
- uint32_t uses, clear_value;
-
- if (!ilo_image_can_enable_aux(&tex->image, zs->u.tex.level))
- return false;
-
- if (!hiz_can_clear_zs(blitter, tex))
- return false;
-
- if (ilo_dev_gen(blitter->ilo->dev) >= ILO_GEN(8))
- clear_value = fui(depth);
- else
- clear_value = util_pack_z(tex->image_format, depth);
-
- ilo_blit_resolve_surface(blitter->ilo, zs,
- ILO_TEXTURE_RENDER_WRITE | ILO_TEXTURE_CLEAR);
- ilo_texture_set_slice_clear_value(tex, zs->u.tex.level,
- zs->u.tex.first_layer,
- zs->u.tex.last_layer - zs->u.tex.first_layer + 1,
- clear_value);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 313-314:
- *
- * "- Depth Test Enable must be disabled and Depth Buffer Write Enable
- * must be enabled (if depth is being cleared).
- *
- * - Stencil buffer clear can be performed at the same time by
- * enabling Stencil Buffer Write Enable. Stencil Test Enable must
- * be enabled and Stencil Pass Depth Pass Op set to REPLACE, and the
- * clear value that is placed in the stencil buffer is the Stencil
- * Reference Value from COLOR_CALC_STATE.
- *
- * - Note also that stencil buffer clear can be performed without
- * depth buffer clear. For stencil only clear, Depth Test Enable and
- * Depth Buffer Write Enable must be disabled.
- *
- * - [DevSNB] errata: For stencil buffer only clear, the previous
- * depth clear value must be delivered during the clear."
- */
- memset(&info, 0, sizeof(info));
-
- if (clear_flags & PIPE_CLEAR_DEPTH) {
- info.depth.cv_has_buffer = true;
- info.depth.write_enable = true;
- }
-
- if (clear_flags & PIPE_CLEAR_STENCIL) {
- info.stencil.cv_has_buffer = true;
- info.stencil.test_enable = true;
- info.stencil.front.test_func = GEN6_COMPAREFUNCTION_ALWAYS;
- info.stencil.front.fail_op = GEN6_STENCILOP_KEEP;
- info.stencil.front.zfail_op = GEN6_STENCILOP_KEEP;
- info.stencil.front.zpass_op = GEN6_STENCILOP_REPLACE;
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 277:
- *
- * "Additionally the following must be set to the correct values.
- *
- * - DEPTH_STENCIL_STATE::Stencil Write Mask must be 0xFF
- * - DEPTH_STENCIL_STATE::Stencil Test Mask must be 0xFF
- * - DEPTH_STENCIL_STATE::Back Face Stencil Write Mask must be 0xFF
- * - DEPTH_STENCIL_STATE::Back Face Stencil Test Mask must be 0xFF"
- *
- * Back frace masks will be copied from front face masks.
- */
- info.params.stencil_front.test_ref = (uint8_t) stencil;
- info.params.stencil_front.test_mask = 0xff;
- info.params.stencil_front.write_mask = 0xff;
- }
-
- ilo_blitter_set_invariants(blitter);
- ilo_blitter_set_earlyz_op(blitter,
- ILO_STATE_RASTER_EARLYZ_DEPTH_CLEAR,
- clear_flags & PIPE_CLEAR_STENCIL);
-
- ilo_blitter_set_cc(blitter, &info);
- ilo_blitter_set_depth_clear_value(blitter, clear_value);
- ilo_blitter_set_fb_from_surface(blitter, zs);
-
- uses = ILO_BLITTER_USE_DSA;
- if (clear_flags & PIPE_CLEAR_DEPTH)
- uses |= ILO_BLITTER_USE_VIEWPORT | ILO_BLITTER_USE_FB_DEPTH;
- if (clear_flags & PIPE_CLEAR_STENCIL)
- uses |= ILO_BLITTER_USE_CC | ILO_BLITTER_USE_FB_STENCIL;
- ilo_blitter_set_uses(blitter, uses);
-
- hiz_emit_rectlist(blitter);
-
- return true;
-}
-
-void
-ilo_blitter_rectlist_resolve_z(struct ilo_blitter *blitter,
- struct pipe_resource *res,
- unsigned level, unsigned slice)
-{
- struct ilo_texture *tex = ilo_texture(res);
- struct ilo_state_cc_info info;
- const struct ilo_texture_slice *s =
- ilo_texture_get_slice(tex, level, slice);
-
- if (!ilo_image_can_enable_aux(&tex->image, level))
- return;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 314:
- *
- * "Depth Test Enable must be enabled with the Depth Test Function set
- * to NEVER. Depth Buffer Write Enable must be enabled. Stencil Test
- * Enable and Stencil Buffer Write Enable must be disabled."
- */
- memset(&info, 0, sizeof(info));
- info.depth.cv_has_buffer = true;
- info.depth.test_enable = true;
- info.depth.write_enable = true;
- info.depth.test_func = GEN6_COMPAREFUNCTION_NEVER;
-
- ilo_blitter_set_invariants(blitter);
- ilo_blitter_set_earlyz_op(blitter,
- ILO_STATE_RASTER_EARLYZ_DEPTH_RESOLVE, false);
-
- ilo_blitter_set_cc(blitter, &info);
- ilo_blitter_set_depth_clear_value(blitter, s->clear_value);
- ilo_blitter_set_fb_from_resource(blitter, res, res->format, level, slice);
- ilo_blitter_set_uses(blitter,
- ILO_BLITTER_USE_DSA | ILO_BLITTER_USE_FB_DEPTH);
-
- hiz_emit_rectlist(blitter);
-}
-
-void
-ilo_blitter_rectlist_resolve_hiz(struct ilo_blitter *blitter,
- struct pipe_resource *res,
- unsigned level, unsigned slice)
-{
- struct ilo_texture *tex = ilo_texture(res);
- struct ilo_state_cc_info info;
-
- if (!ilo_image_can_enable_aux(&tex->image, level))
- return;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 315:
- *
- * "(Hierarchical Depth Buffer Resolve) Depth Test Enable must be
- * disabled. Depth Buffer Write Enable must be enabled. Stencil Test
- * Enable and Stencil Buffer Write Enable must be disabled."
- */
- memset(&info, 0, sizeof(info));
- info.depth.cv_has_buffer = true;
- info.depth.write_enable = true;
-
- ilo_blitter_set_invariants(blitter);
- ilo_blitter_set_earlyz_op(blitter,
- ILO_STATE_RASTER_EARLYZ_HIZ_RESOLVE, false);
-
- ilo_blitter_set_cc(blitter, &info);
- ilo_blitter_set_fb_from_resource(blitter, res, res->format, level, slice);
- ilo_blitter_set_uses(blitter,
- ILO_BLITTER_USE_DSA | ILO_BLITTER_USE_FB_DEPTH);
-
- hiz_emit_rectlist(blitter);
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_COMMON_H
-#define ILO_COMMON_H
-
-#include "pipe/p_format.h"
-#include "pipe/p_defines.h"
-
-#include "util/list.h"
-#include "util/u_format.h"
-#include "util/u_inlines.h"
-#include "util/u_memory.h"
-#include "util/u_pointer.h"
-
-#include "core/ilo_core.h"
-#include "core/ilo_debug.h"
-#include "core/ilo_dev.h"
-
-#endif /* ILO_COMMON_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "util/u_upload_mgr.h"
-
-#include "ilo_blit.h"
-#include "ilo_blitter.h"
-#include "ilo_cp.h"
-#include "ilo_draw.h"
-#include "ilo_gpgpu.h"
-#include "ilo_query.h"
-#include "ilo_render.h"
-#include "ilo_resource.h"
-#include "ilo_screen.h"
-#include "ilo_shader.h"
-#include "ilo_state.h"
-#include "ilo_transfer.h"
-#include "ilo_video.h"
-#include "ilo_context.h"
-
-static void
-ilo_context_cp_submitted(struct ilo_cp *cp, void *data)
-{
- struct ilo_context *ilo = ilo_context(data);
-
- /* builder buffers are reallocated */
- ilo_render_invalidate_builder(ilo->render);
-}
-
-static void
-ilo_flush(struct pipe_context *pipe,
- struct pipe_fence_handle **f,
- unsigned flags)
-{
- struct ilo_context *ilo = ilo_context(pipe);
-
- ilo_cp_submit(ilo->cp,
- (flags & PIPE_FLUSH_END_OF_FRAME) ? "frame end" : "user request");
-
- if (f) {
- struct pipe_screen *screen = pipe->screen;
- screen->fence_reference(screen, f, NULL);
- *f = ilo_screen_fence_create(pipe->screen, ilo->cp->last_submitted_bo);
- }
-}
-
-static void
-ilo_render_condition(struct pipe_context *pipe,
- struct pipe_query *query,
- boolean condition,
- uint mode)
-{
- struct ilo_context *ilo = ilo_context(pipe);
-
- /* reference count? */
- ilo->render_condition.query = query;
- ilo->render_condition.condition = condition;
- ilo->render_condition.mode = mode;
-}
-
-bool
-ilo_skip_rendering(struct ilo_context *ilo)
-{
- uint64_t result;
- bool wait;
-
- if (!ilo->render_condition.query)
- return false;
-
- switch (ilo->render_condition.mode) {
- case PIPE_RENDER_COND_WAIT:
- case PIPE_RENDER_COND_BY_REGION_WAIT:
- wait = true;
- break;
- case PIPE_RENDER_COND_NO_WAIT:
- case PIPE_RENDER_COND_BY_REGION_NO_WAIT:
- default:
- wait = false;
- break;
- }
-
- if (ilo->base.get_query_result(&ilo->base, ilo->render_condition.query,
- wait, (union pipe_query_result *) &result))
- return ((bool) result == ilo->render_condition.condition);
- else
- return false;
-}
-
-static void
-ilo_context_destroy(struct pipe_context *pipe)
-{
- struct ilo_context *ilo = ilo_context(pipe);
-
- ilo_state_vector_cleanup(&ilo->state_vector);
-
- if (ilo->uploader)
- u_upload_destroy(ilo->uploader);
-
- if (ilo->blitter)
- ilo_blitter_destroy(ilo->blitter);
- if (ilo->render)
- ilo_render_destroy(ilo->render);
- if (ilo->shader_cache)
- ilo_shader_cache_destroy(ilo->shader_cache);
- if (ilo->cp)
- ilo_cp_destroy(ilo->cp);
-
- slab_destroy(&ilo->transfer_mempool);
-
- FREE(ilo);
-}
-
-static struct pipe_context *
-ilo_context_create(struct pipe_screen *screen, void *priv, unsigned flags)
-{
- struct ilo_screen *is = ilo_screen(screen);
- struct ilo_context *ilo;
-
- ilo = CALLOC_STRUCT(ilo_context);
- if (!ilo)
- return NULL;
-
- ilo->winsys = is->dev.winsys;
- ilo->dev = &is->dev;
-
- /*
- * initialize first, otherwise it may not be safe to call
- * ilo_context_destroy() on errors
- */
- slab_create(&ilo->transfer_mempool,
- sizeof(struct ilo_transfer), 64);
-
- ilo->shader_cache = ilo_shader_cache_create();
- ilo->cp = ilo_cp_create(ilo->dev, ilo->winsys, ilo->shader_cache);
- if (ilo->cp)
- ilo->render = ilo_render_create(&ilo->cp->builder);
-
- if (!ilo->cp || !ilo->shader_cache || !ilo->render) {
- ilo_context_destroy(&ilo->base);
- return NULL;
- }
-
- ilo_cp_set_submit_callback(ilo->cp,
- ilo_context_cp_submitted, (void *) ilo);
-
- ilo->base.screen = screen;
- ilo->base.priv = priv;
-
- ilo->base.destroy = ilo_context_destroy;
- ilo->base.flush = ilo_flush;
- ilo->base.render_condition = ilo_render_condition;
-
- ilo_init_draw_functions(ilo);
- ilo_init_query_functions(ilo);
- ilo_init_state_functions(ilo);
- ilo_init_blit_functions(ilo);
- ilo_init_transfer_functions(ilo);
- ilo_init_video_functions(ilo);
- ilo_init_gpgpu_functions(ilo);
-
- ilo_init_draw(ilo);
- ilo_state_vector_init(ilo->dev, &ilo->state_vector);
-
- /*
- * These must be called last as u_upload/u_blitter are clients of the pipe
- * context.
- */
- ilo->uploader = u_upload_create(&ilo->base, 1024 * 1024,
- PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_INDEX_BUFFER,
- PIPE_USAGE_STREAM);
- if (!ilo->uploader) {
- ilo_context_destroy(&ilo->base);
- return NULL;
- }
-
- ilo->blitter = ilo_blitter_create(ilo);
- if (!ilo->blitter) {
- ilo_context_destroy(&ilo->base);
- return NULL;
- }
-
- return &ilo->base;
-}
-
-/**
- * Initialize context-related functions.
- */
-void
-ilo_init_context_functions(struct ilo_screen *is)
-{
- is->base.context_create = ilo_context_create;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_CONTEXT_H
-#define ILO_CONTEXT_H
-
-#include "pipe/p_context.h"
-#include "util/slab.h"
-
-#include "ilo_common.h"
-#include "ilo_cp.h"
-#include "ilo_draw.h"
-#include "ilo_state.h"
-
-struct u_upload_mgr;
-struct intel_winsys;
-
-struct ilo_blitter;
-struct ilo_render;
-struct ilo_screen;
-struct ilo_shader_cache;
-
-struct ilo_context {
- struct pipe_context base;
-
- struct intel_winsys *winsys;
- struct ilo_dev *dev;
-
- struct slab_mempool transfer_mempool;
-
- struct ilo_cp *cp;
-
- struct ilo_shader_cache *shader_cache;
- struct ilo_blitter *blitter;
- struct ilo_render *render;
-
- struct u_upload_mgr *uploader;
-
- struct ilo_state_vector state_vector;
-
- struct {
- struct pipe_query *query;
- bool condition;
- unsigned mode;
- } render_condition;
-
- struct {
- struct ilo_cp_owner cp_owner;
- struct list_head queries;
- } draw;
-};
-
-static inline struct ilo_context *
-ilo_context(struct pipe_context *pipe)
-{
- return (struct ilo_context *) pipe;
-}
-
-void
-ilo_init_context_functions(struct ilo_screen *is);
-
-bool
-ilo_skip_rendering(struct ilo_context *ilo);
-
-#endif /* ILO_CONTEXT_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "core/ilo_builder_mi.h"
-#include "core/intel_winsys.h"
-
-#include "ilo_shader.h"
-#include "ilo_cp.h"
-
-static const struct ilo_cp_owner ilo_cp_default_owner;
-
-static void
-ilo_cp_release_owner(struct ilo_cp *cp)
-{
- if (cp->owner != &ilo_cp_default_owner) {
- const struct ilo_cp_owner *owner = cp->owner;
-
- cp->owner = &ilo_cp_default_owner;
-
- assert(ilo_cp_space(cp) >= owner->reserve);
- owner->release(cp, owner->data);
- }
-}
-
-/**
- * Set the parser owner. If this is a new owner or a new ring, the old owner
- * is released and the new owner's own() is called. The parser may implicitly
- * submit if there is a ring change.
- *
- * own() is called before \p owner owns the parser. It must make sure there
- * is more space than \p owner->reserve when it returns. Calling
- * ilo_cp_submit() is allowed.
- *
- * release() will be called after \p owner loses the parser. That may happen
- * just before the parser submits and ilo_cp_submit() is not allowed.
- */
-void
-ilo_cp_set_owner(struct ilo_cp *cp, enum intel_ring_type ring,
- const struct ilo_cp_owner *owner)
-{
- if (!owner)
- owner = &ilo_cp_default_owner;
-
- if (cp->ring != ring) {
- ilo_cp_submit(cp, "ring change");
- cp->ring = ring;
- }
-
- if (cp->owner != owner) {
- ilo_cp_release_owner(cp);
-
- owner->own(cp, owner->data);
-
- assert(ilo_cp_space(cp) >= owner->reserve);
- cp->owner = owner;
- }
-}
-
-static struct intel_bo *
-ilo_cp_end_batch(struct ilo_cp *cp, unsigned *used)
-{
- struct intel_bo *bo;
-
- ilo_cp_release_owner(cp);
-
- if (!ilo_builder_batch_used(&cp->builder)) {
- ilo_builder_batch_discard(&cp->builder);
- return NULL;
- }
-
- /* see ilo_cp_space() */
- assert(ilo_builder_batch_space(&cp->builder) >= 2);
- gen6_mi_batch_buffer_end(&cp->builder);
-
- bo = ilo_builder_end(&cp->builder, used);
-
- /* we have to assume that kernel uploads also failed */
- if (!bo)
- ilo_shader_cache_invalidate(cp->shader_cache);
-
- return bo;
-}
-
-static bool
-ilo_cp_detect_hang(struct ilo_cp *cp)
-{
- uint32_t active_lost, pending_lost;
- bool guilty = false;
-
- if (likely(!(ilo_debug & ILO_DEBUG_HANG)))
- return false;
-
- /* wait and get reset stats */
- if (intel_bo_wait(cp->last_submitted_bo, -1) ||
- intel_winsys_get_reset_stats(cp->winsys, cp->render_ctx,
- &active_lost, &pending_lost))
- return false;
-
- if (cp->active_lost != active_lost) {
- ilo_err("GPU hang caused by bo %p\n", cp->last_submitted_bo);
- cp->active_lost = active_lost;
- guilty = true;
- }
-
- if (cp->pending_lost != pending_lost) {
- ilo_err("GPU hang detected\n");
- cp->pending_lost = pending_lost;
- }
-
- return guilty;
-}
-
-/**
- * Flush the command parser and execute the commands. When the parser buffer
- * is empty, the callback is not invoked.
- */
-void
-ilo_cp_submit_internal(struct ilo_cp *cp)
-{
- const bool do_exec = !(ilo_debug & ILO_DEBUG_NOHW);
- struct intel_bo *bo;
- unsigned used;
- int err;
-
- bo = ilo_cp_end_batch(cp, &used);
- if (!bo)
- return;
-
- if (likely(do_exec)) {
- err = intel_winsys_submit_bo(cp->winsys, cp->ring,
- bo, used, cp->render_ctx, cp->one_off_flags);
- }
- else {
- err = 0;
- }
-
- cp->one_off_flags = 0;
-
- if (!err) {
- bool guilty;
-
- intel_bo_unref(cp->last_submitted_bo);
- cp->last_submitted_bo = intel_bo_ref(bo);
-
- guilty = ilo_cp_detect_hang(cp);
-
- if (unlikely((ilo_debug & ILO_DEBUG_BATCH) || guilty)) {
- ilo_builder_decode(&cp->builder);
- if (guilty)
- abort();
- }
-
- if (cp->submit_callback)
- cp->submit_callback(cp, cp->submit_callback_data);
- }
-
- ilo_builder_begin(&cp->builder);
-}
-
-/**
- * Destroy the command parser.
- */
-void
-ilo_cp_destroy(struct ilo_cp *cp)
-{
- ilo_builder_reset(&cp->builder);
-
- intel_winsys_destroy_context(cp->winsys, cp->render_ctx);
- FREE(cp);
-}
-
-/**
- * Create a command parser.
- */
-struct ilo_cp *
-ilo_cp_create(const struct ilo_dev *dev,
- struct intel_winsys *winsys,
- struct ilo_shader_cache *shc)
-{
- struct ilo_cp *cp;
-
- cp = CALLOC_STRUCT(ilo_cp);
- if (!cp)
- return NULL;
-
- cp->winsys = winsys;
- cp->shader_cache = shc;
- cp->render_ctx = intel_winsys_create_context(winsys);
- if (!cp->render_ctx) {
- FREE(cp);
- return NULL;
- }
-
- cp->ring = INTEL_RING_RENDER;
- cp->owner = &ilo_cp_default_owner;
-
- ilo_builder_init(&cp->builder, dev, winsys);
-
- if (!ilo_builder_begin(&cp->builder)) {
- ilo_cp_destroy(cp);
- return NULL;
- }
-
- return cp;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_CP_H
-#define ILO_CP_H
-
-#include "core/ilo_builder.h"
-#include "core/intel_winsys.h"
-
-#include "ilo_common.h"
-
-struct ilo_cp;
-struct ilo_shader_cache;
-
-typedef void (*ilo_cp_callback)(struct ilo_cp *cp, void *data);
-
-/**
- * Parser owners are notified when they gain or lose the ownership of the
- * parser. This gives owners a chance to emit prolog or epilog.
- */
-struct ilo_cp_owner {
- ilo_cp_callback own;
- ilo_cp_callback release;
- void *data;
-
- /*
- * Space reserved for release(). This can be modified at any time, as long
- * as it is never increased by more than ilo_cp_space().
- */
- int reserve;
-};
-
-/**
- * Command parser.
- */
-struct ilo_cp {
- struct intel_winsys *winsys;
- struct ilo_shader_cache *shader_cache;
- struct intel_context *render_ctx;
-
- ilo_cp_callback submit_callback;
- void *submit_callback_data;
-
- enum intel_ring_type ring;
- const struct ilo_cp_owner *owner;
-
- unsigned one_off_flags;
-
- struct ilo_builder builder;
- struct intel_bo *last_submitted_bo;
-
- uint32_t active_lost;
- uint32_t pending_lost;
-};
-
-struct ilo_cp *
-ilo_cp_create(const struct ilo_dev *dev,
- struct intel_winsys *winsys,
- struct ilo_shader_cache *shc);
-
-void
-ilo_cp_destroy(struct ilo_cp *cp);
-
-void
-ilo_cp_submit_internal(struct ilo_cp *cp);
-
-static inline void
-ilo_cp_submit(struct ilo_cp *cp, const char *reason)
-{
- if (ilo_debug & ILO_DEBUG_SUBMIT) {
- ilo_printf("submit batch buffer to %s ring because of %s: ",
- (cp->ring == INTEL_RING_RENDER) ? "render" : "unknown", reason);
- ilo_builder_batch_print_stats(&cp->builder);
- }
-
- ilo_cp_submit_internal(cp);
-}
-
-void
-ilo_cp_set_owner(struct ilo_cp *cp, enum intel_ring_type ring,
- const struct ilo_cp_owner *owner);
-
-/**
- * Return the remaining space (in dwords) in the parser buffer.
- */
-static inline int
-ilo_cp_space(struct ilo_cp *cp)
-{
- const int space = ilo_builder_batch_space(&cp->builder);
- const int mi_batch_buffer_end_space = 2;
-
- assert(space >= cp->owner->reserve + mi_batch_buffer_end_space);
-
- return space - cp->owner->reserve - mi_batch_buffer_end_space;
-}
-
-/**
- * Set one-off flags. They will be cleared after submission.
- */
-static inline void
-ilo_cp_set_one_off_flags(struct ilo_cp *cp, unsigned flags)
-{
- cp->one_off_flags |= flags;
-}
-
-/**
- * Set submit callback. The callback is invoked after the bo has been
- * successfully submitted, and before the bo is reallocated.
- */
-static inline void
-ilo_cp_set_submit_callback(struct ilo_cp *cp, ilo_cp_callback callback,
- void *data)
-{
- cp->submit_callback = callback;
- cp->submit_callback_data = data;
-}
-
-#endif /* ILO_CP_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "util/u_prim.h"
-#include "core/intel_winsys.h"
-
-#include "ilo_render.h"
-#include "ilo_blit.h"
-#include "ilo_context.h"
-#include "ilo_cp.h"
-#include "ilo_query.h"
-#include "ilo_shader.h"
-#include "ilo_state.h"
-#include "ilo_draw.h"
-
-static void
-ilo_draw_set_owner(struct ilo_context *ilo)
-{
- ilo_cp_set_owner(ilo->cp, INTEL_RING_RENDER, &ilo->draw.cp_owner);
-}
-
-static uint64_t
-query_timestamp_to_ns(const struct ilo_context *ilo, uint64_t timestamp)
-{
- /* see ilo_get_timestamp() */
- return (timestamp & 0xffffffff) * 80;
-}
-
-/**
- * Process the bo and accumulate the result. The bo is emptied.
- */
-static void
-query_process_bo(const struct ilo_context *ilo, struct ilo_query *q)
-{
- const uint64_t *vals;
- uint64_t tmp;
- int i;
-
- if (!q->used)
- return;
-
- vals = intel_bo_map(q->bo, false);
- if (!vals) {
- q->used = 0;
- return;
- }
-
- switch (q->type) {
- case PIPE_QUERY_OCCLUSION_COUNTER:
- case PIPE_QUERY_OCCLUSION_PREDICATE:
- case PIPE_QUERY_TIME_ELAPSED:
- case PIPE_QUERY_PRIMITIVES_GENERATED:
- case PIPE_QUERY_PRIMITIVES_EMITTED:
- assert(q->stride == sizeof(*vals) * 2);
-
- tmp = 0;
- for (i = 0; i < q->used; i++)
- tmp += vals[2 * i + 1] - vals[2 * i];
-
- if (q->type == PIPE_QUERY_TIME_ELAPSED)
- tmp = query_timestamp_to_ns(ilo, tmp);
-
- q->result.u64 += tmp;
- break;
- case PIPE_QUERY_TIMESTAMP:
- assert(q->stride == sizeof(*vals));
-
- q->result.u64 = query_timestamp_to_ns(ilo, vals[q->used - 1]);
- break;
- case PIPE_QUERY_PIPELINE_STATISTICS:
- assert(q->stride == sizeof(*vals) * 22);
-
- for (i = 0; i < q->used; i++) {
- struct pipe_query_data_pipeline_statistics *stats =
- &q->result.pipeline_statistics;
- const uint64_t *begin = vals + 22 * i;
- const uint64_t *end = begin + 11;
-
- stats->ia_vertices += end[0] - begin[0];
- stats->ia_primitives += end[1] - begin[1];
- stats->vs_invocations += end[2] - begin[2];
- stats->gs_invocations += end[3] - begin[3];
- stats->gs_primitives += end[4] - begin[4];
- stats->c_invocations += end[5] - begin[5];
- stats->c_primitives += end[6] - begin[6];
- stats->ps_invocations += end[7] - begin[7];
- stats->hs_invocations += end[8] - begin[8];
- stats->ds_invocations += end[9] - begin[9];
- stats->cs_invocations += end[10] - begin[10];
- }
- break;
- default:
- break;
- }
-
- intel_bo_unmap(q->bo);
-
- q->used = 0;
-}
-
-static void
-query_begin_bo(struct ilo_context *ilo, struct ilo_query *q)
-{
- /* bo is full */
- if (q->used >= q->count)
- query_process_bo(ilo, q);
-
- /* write the beginning value to the bo */
- if (q->in_pairs)
- ilo_render_emit_query(ilo->render, q, q->stride * q->used);
-}
-
-static void
-query_end_bo(struct ilo_context *ilo, struct ilo_query *q)
-{
- uint32_t offset;
-
- assert(q->used < q->count);
-
- offset = q->stride * q->used;
- if (q->in_pairs)
- offset += q->stride >> 1;
-
- q->used++;
-
- /* write the ending value to the bo */
- ilo_render_emit_query(ilo->render, q, offset);
-}
-
-bool
-ilo_init_draw_query(struct ilo_context *ilo, struct ilo_query *q)
-{
- unsigned bo_size;
-
- switch (q->type) {
- case PIPE_QUERY_OCCLUSION_COUNTER:
- case PIPE_QUERY_OCCLUSION_PREDICATE:
- case PIPE_QUERY_TIME_ELAPSED:
- case PIPE_QUERY_PRIMITIVES_GENERATED:
- case PIPE_QUERY_PRIMITIVES_EMITTED:
- q->stride = sizeof(uint64_t);
- q->in_pairs = true;
- break;
- case PIPE_QUERY_TIMESTAMP:
- q->stride = sizeof(uint64_t);
- q->in_pairs = false;
- break;
- case PIPE_QUERY_PIPELINE_STATISTICS:
- q->stride = sizeof(uint64_t) * 11;
- q->in_pairs = true;
- break;
- default:
- return false;
- break;
- }
-
- q->cmd_len = ilo_render_get_query_len(ilo->render, q->type);
-
- /* double cmd_len and stride if in pairs */
- q->cmd_len <<= q->in_pairs;
- q->stride <<= q->in_pairs;
-
- bo_size = (q->stride > 4096) ? q->stride : 4096;
- q->bo = intel_winsys_alloc_bo(ilo->winsys, "query", bo_size, false);
- if (!q->bo)
- return false;
-
- q->count = bo_size / q->stride;
-
- return true;
-}
-
-void
-ilo_begin_draw_query(struct ilo_context *ilo, struct ilo_query *q)
-{
- ilo_draw_set_owner(ilo);
-
- /* need to submit first */
- if (!ilo_builder_validate(&ilo->cp->builder, 1, &q->bo) ||
- ilo_cp_space(ilo->cp) < q->cmd_len) {
- ilo_cp_submit(ilo->cp, "out of aperture or space");
-
- assert(ilo_builder_validate(&ilo->cp->builder, 1, &q->bo));
- assert(ilo_cp_space(ilo->cp) >= q->cmd_len);
-
- ilo_draw_set_owner(ilo);
- }
-
- /* reserve the space for ending/pausing the query */
- ilo->draw.cp_owner.reserve += q->cmd_len >> q->in_pairs;
-
- query_begin_bo(ilo, q);
-
- if (q->in_pairs)
- list_add(&q->list, &ilo->draw.queries);
-}
-
-void
-ilo_end_draw_query(struct ilo_context *ilo, struct ilo_query *q)
-{
- ilo_draw_set_owner(ilo);
-
- /* reclaim the reserved space */
- ilo->draw.cp_owner.reserve -= q->cmd_len >> q->in_pairs;
- assert(ilo->draw.cp_owner.reserve >= 0);
-
- query_end_bo(ilo, q);
-
- list_delinit(&q->list);
-}
-
-/**
- * Process the raw query data.
- */
-void
-ilo_process_draw_query(struct ilo_context *ilo, struct ilo_query *q)
-{
- query_process_bo(ilo, q);
-}
-
-static void
-ilo_draw_own_cp(struct ilo_cp *cp, void *data)
-{
- struct ilo_context *ilo = data;
-
- /* multiply by 2 for both resuming and pausing */
- if (ilo_cp_space(ilo->cp) < ilo->draw.cp_owner.reserve * 2) {
- ilo_cp_submit(ilo->cp, "out of space");
- assert(ilo_cp_space(ilo->cp) >= ilo->draw.cp_owner.reserve * 2);
- }
-
- while (true) {
- struct ilo_builder_snapshot snapshot;
- struct ilo_query *q;
-
- ilo_builder_batch_snapshot(&ilo->cp->builder, &snapshot);
-
- /* resume queries */
- LIST_FOR_EACH_ENTRY(q, &ilo->draw.queries, list)
- query_begin_bo(ilo, q);
-
- if (!ilo_builder_validate(&ilo->cp->builder, 0, NULL)) {
- ilo_builder_batch_restore(&ilo->cp->builder, &snapshot);
-
- if (ilo_builder_batch_used(&ilo->cp->builder)) {
- ilo_cp_submit(ilo->cp, "out of aperture");
- continue;
- }
- }
-
- break;
- }
-
- assert(ilo_cp_space(ilo->cp) >= ilo->draw.cp_owner.reserve);
-}
-
-static void
-ilo_draw_release_cp(struct ilo_cp *cp, void *data)
-{
- struct ilo_context *ilo = data;
- struct ilo_query *q;
-
- assert(ilo_cp_space(ilo->cp) >= ilo->draw.cp_owner.reserve);
-
- /* pause queries */
- LIST_FOR_EACH_ENTRY(q, &ilo->draw.queries, list)
- query_end_bo(ilo, q);
-}
-
-static bool
-draw_vbo(struct ilo_context *ilo, const struct ilo_state_vector *vec)
-{
- bool need_flush = false;
- bool success = true;
- int max_len, before_space;
-
- /* on Gen7 and Gen7.5, we need SOL_RESET to reset the SO write offsets */
- if (ilo_dev_gen(ilo->dev) >= ILO_GEN(7) &&
- ilo_dev_gen(ilo->dev) <= ILO_GEN(7.5) &&
- (vec->dirty & ILO_DIRTY_SO) && vec->so.enabled &&
- !vec->so.append_bitmask) {
- ilo_cp_submit(ilo->cp, "SOL_RESET");
- ilo_cp_set_one_off_flags(ilo->cp, INTEL_EXEC_GEN7_SOL_RESET);
- }
-
- if (ilo_builder_batch_used(&ilo->cp->builder)) {
- /*
- * Without a better tracking mechanism, when the framebuffer changes, we
- * have to assume that the old framebuffer may be sampled from. If that
- * happens in the middle of a batch buffer, we need to insert manual
- * flushes.
- */
- need_flush = (vec->dirty & ILO_DIRTY_FB);
-
- /* same to SO target changes */
- need_flush |= (vec->dirty & ILO_DIRTY_SO);
- }
-
- ilo_draw_set_owner(ilo);
-
- /* make sure there is enough room first */
- max_len = ilo_render_get_draw_len(ilo->render, vec);
- if (need_flush)
- max_len += ilo_render_get_flush_len(ilo->render);
-
- if (max_len > ilo_cp_space(ilo->cp)) {
- ilo_cp_submit(ilo->cp, "out of space");
- need_flush = false;
- assert(max_len <= ilo_cp_space(ilo->cp));
- }
-
- /* space available before emission */
- before_space = ilo_cp_space(ilo->cp);
-
- if (need_flush)
- ilo_render_emit_flush(ilo->render);
-
- while (true) {
- struct ilo_builder_snapshot snapshot;
-
- ilo_builder_batch_snapshot(&ilo->cp->builder, &snapshot);
-
- ilo_render_emit_draw(ilo->render, vec);
-
- if (!ilo_builder_validate(&ilo->cp->builder, 0, NULL)) {
- ilo_builder_batch_restore(&ilo->cp->builder, &snapshot);
-
- /* flush and try again */
- if (ilo_builder_batch_used(&ilo->cp->builder)) {
- ilo_cp_submit(ilo->cp, "out of aperture");
- continue;
- }
-
- success = false;
- }
-
- break;
- }
-
- /* sanity check size estimation */
- assert(before_space - ilo_cp_space(ilo->cp) <= max_len);
-
- return success;
-}
-
-void
-ilo_draw_rectlist(struct ilo_context *ilo)
-{
- int max_len, before_space;
- bool need_flush;
-
- need_flush = ilo_builder_batch_used(&ilo->cp->builder);
-
- ilo_draw_set_owner(ilo);
-
- max_len = ilo_render_get_rectlist_len(ilo->render, ilo->blitter);
- max_len += ilo_render_get_flush_len(ilo->render) * 2;
-
- if (max_len > ilo_cp_space(ilo->cp)) {
- ilo_cp_submit(ilo->cp, "out of space");
- need_flush = false;
- assert(max_len <= ilo_cp_space(ilo->cp));
- }
-
- before_space = ilo_cp_space(ilo->cp);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 313:
- *
- * "If other rendering operations have preceded this clear, a
- * PIPE_CONTROL with write cache flush enabled and Z-inhibit
- * disabled must be issued before the rectangle primitive used for
- * the depth buffer clear operation."
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 314:
- *
- * "Depth buffer clear pass must be followed by a PIPE_CONTROL
- * command with DEPTH_STALL bit set and Then followed by Depth
- * FLUSH"
- *
- * But the pipeline has to be flushed both before and after not only
- * because of these workarounds. We need them for reasons such as
- *
- * - we may sample from a texture that was rendered to
- * - we may sample from the fb shortly after
- *
- * Skip checking blitter->op and do the flushes.
- */
- if (need_flush)
- ilo_render_emit_flush(ilo->render);
-
- while (true) {
- struct ilo_builder_snapshot snapshot;
-
- ilo_builder_batch_snapshot(&ilo->cp->builder, &snapshot);
-
- ilo_render_emit_rectlist(ilo->render, ilo->blitter);
-
- if (!ilo_builder_validate(&ilo->cp->builder, 0, NULL)) {
- ilo_builder_batch_restore(&ilo->cp->builder, &snapshot);
-
- /* flush and try again */
- if (ilo_builder_batch_used(&ilo->cp->builder)) {
- ilo_cp_submit(ilo->cp, "out of aperture");
- continue;
- }
- }
-
- break;
- }
-
- ilo_render_invalidate_hw(ilo->render);
-
- ilo_render_emit_flush(ilo->render);
-
- /* sanity check size estimation */
- assert(before_space - ilo_cp_space(ilo->cp) <= max_len);
-}
-
-static void
-draw_vbo_with_sw_restart(struct ilo_context *ilo,
- const struct pipe_draw_info *info)
-{
- const struct ilo_ib_state *ib = &ilo->state_vector.ib;
- const struct ilo_vma *vma;
- union {
- const void *ptr;
- const uint8_t *u8;
- const uint16_t *u16;
- const uint32_t *u32;
- } u;
-
- /* we will draw with IB mapped */
- if (ib->state.buffer) {
- vma = ilo_resource_get_vma(ib->state.buffer);
- u.ptr = intel_bo_map(vma->bo, false);
- if (u.ptr)
- u.u8 += vma->bo_offset + ib->state.offset;
- } else {
- vma = NULL;
- u.ptr = ib->state.user_buffer;
- }
-
- if (!u.ptr)
- return;
-
-#define DRAW_VBO_WITH_SW_RESTART(pipe, info, ptr) do { \
- const unsigned end = (info)->start + (info)->count; \
- struct pipe_draw_info subinfo; \
- unsigned i; \
- \
- subinfo = *(info); \
- subinfo.primitive_restart = false; \
- for (i = (info)->start; i < end; i++) { \
- if ((ptr)[i] == (info)->restart_index) { \
- subinfo.count = i - subinfo.start; \
- if (subinfo.count) \
- (pipe)->draw_vbo(pipe, &subinfo); \
- subinfo.start = i + 1; \
- } \
- } \
- subinfo.count = i - subinfo.start; \
- if (subinfo.count) \
- (pipe)->draw_vbo(pipe, &subinfo); \
-} while (0)
-
- switch (ib->state.index_size) {
- case 1:
- DRAW_VBO_WITH_SW_RESTART(&ilo->base, info, u.u8);
- break;
- case 2:
- DRAW_VBO_WITH_SW_RESTART(&ilo->base, info, u.u16);
- break;
- case 4:
- DRAW_VBO_WITH_SW_RESTART(&ilo->base, info, u.u32);
- break;
- default:
- assert(!"unsupported index size");
- break;
- }
-
-#undef DRAW_VBO_WITH_SW_RESTART
-
- if (vma)
- intel_bo_unmap(vma->bo);
-}
-
-static bool
-draw_vbo_need_sw_restart(const struct ilo_context *ilo,
- const struct pipe_draw_info *info)
-{
- /* the restart index is fixed prior to GEN7.5 */
- if (ilo_dev_gen(ilo->dev) < ILO_GEN(7.5)) {
- const unsigned cut_index =
- (ilo->state_vector.ib.state.index_size == 1) ? 0xff :
- (ilo->state_vector.ib.state.index_size == 2) ? 0xffff :
- (ilo->state_vector.ib.state.index_size == 4) ? 0xffffffff : 0;
-
- if (info->restart_index < cut_index)
- return true;
- }
-
- switch (info->mode) {
- case PIPE_PRIM_POINTS:
- case PIPE_PRIM_LINES:
- case PIPE_PRIM_LINE_STRIP:
- case PIPE_PRIM_TRIANGLES:
- case PIPE_PRIM_TRIANGLE_STRIP:
- /* these never need software fallback */
- return false;
- case PIPE_PRIM_LINE_LOOP:
- case PIPE_PRIM_POLYGON:
- case PIPE_PRIM_QUAD_STRIP:
- case PIPE_PRIM_QUADS:
- case PIPE_PRIM_TRIANGLE_FAN:
- /* these need software fallback prior to GEN7.5 */
- return (ilo_dev_gen(ilo->dev) < ILO_GEN(7.5));
- default:
- /* the rest always needs software fallback */
- return true;
- }
-}
-
-static void
-ilo_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
-{
- struct ilo_context *ilo = ilo_context(pipe);
- int vs_scratch_size, gs_scratch_size, fs_scratch_size;
-
- if (ilo_debug & ILO_DEBUG_DRAW) {
- if (info->indexed) {
- ilo_printf("indexed draw %s: "
- "index start %d, count %d, vertex range [%d, %d]\n",
- u_prim_name(info->mode), info->start, info->count,
- info->min_index, info->max_index);
- }
- else {
- ilo_printf("draw %s: vertex start %d, count %d\n",
- u_prim_name(info->mode), info->start, info->count);
- }
-
- ilo_state_vector_dump_dirty(&ilo->state_vector);
- }
-
- if (ilo_skip_rendering(ilo))
- return;
-
- if (info->primitive_restart && info->indexed &&
- draw_vbo_need_sw_restart(ilo, info)) {
- draw_vbo_with_sw_restart(ilo, info);
- return;
- }
-
- ilo_finalize_3d_states(ilo, info);
-
- /* upload kernels */
- ilo_shader_cache_upload(ilo->shader_cache, &ilo->cp->builder);
-
- /* prepare scratch spaces */
- ilo_shader_cache_get_max_scratch_sizes(ilo->shader_cache,
- &vs_scratch_size, &gs_scratch_size, &fs_scratch_size);
- ilo_render_prepare_scratch_spaces(ilo->render,
- vs_scratch_size, gs_scratch_size, fs_scratch_size);
-
- ilo_blit_resolve_framebuffer(ilo);
-
- /* If draw_vbo ever fails, return immediately. */
- if (!draw_vbo(ilo, &ilo->state_vector))
- return;
-
- /* clear dirty status */
- ilo->state_vector.dirty = 0x0;
-
- /* avoid dangling pointer reference */
- ilo->state_vector.draw = NULL;
-
- if (ilo_debug & ILO_DEBUG_NOCACHE)
- ilo_render_emit_flush(ilo->render);
-}
-
-static void
-ilo_texture_barrier(struct pipe_context *pipe, unsigned flags)
-{
- struct ilo_context *ilo = ilo_context(pipe);
-
- if (ilo->cp->ring != INTEL_RING_RENDER)
- return;
-
- ilo_render_emit_flush(ilo->render);
-
- /* don't know why */
- if (ilo_dev_gen(ilo->dev) >= ILO_GEN(7))
- ilo_cp_submit(ilo->cp, "texture barrier");
-}
-
-static void
-ilo_get_sample_position(struct pipe_context *pipe,
- unsigned sample_count,
- unsigned sample_index,
- float *out_value)
-{
- struct ilo_context *ilo = ilo_context(pipe);
-
- ilo_render_get_sample_position(ilo->render,
- sample_count, sample_index,
- &out_value[0], &out_value[1]);
-}
-
-void
-ilo_init_draw(struct ilo_context *ilo)
-{
- ilo->draw.cp_owner.own = ilo_draw_own_cp;
- ilo->draw.cp_owner.release = ilo_draw_release_cp;
- ilo->draw.cp_owner.data = (void *) ilo;
- ilo->draw.cp_owner.reserve = 0;
-
- list_inithead(&ilo->draw.queries);
-}
-
-/**
- * Initialize 3D-related functions.
- */
-void
-ilo_init_draw_functions(struct ilo_context *ilo)
-{
- ilo->base.draw_vbo = ilo_draw_vbo;
- ilo->base.texture_barrier = ilo_texture_barrier;
- ilo->base.get_sample_position = ilo_get_sample_position;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_DRAW_H
-#define ILO_DRAW_H
-
-#include "ilo_common.h"
-
-struct ilo_context;
-struct ilo_query;
-
-void
-ilo_init_draw_functions(struct ilo_context *ilo);
-
-void
-ilo_init_draw(struct ilo_context *ilo);
-
-bool
-ilo_init_draw_query(struct ilo_context *ilo, struct ilo_query *q);
-
-void
-ilo_begin_draw_query(struct ilo_context *ilo, struct ilo_query *q);
-
-void
-ilo_end_draw_query(struct ilo_context *ilo, struct ilo_query *q);
-
-void
-ilo_process_draw_query(struct ilo_context *ilo, struct ilo_query *q);
-
-void
-ilo_draw_rectlist(struct ilo_context *ilo);
-
-#endif /* ILO_DRAW_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "genhw/genhw.h"
-#include "core/ilo_state_surface.h"
-#include "core/ilo_state_vf.h"
-#include "ilo_format.h"
-
-bool
-ilo_format_support_vb(const struct ilo_dev *dev,
- enum pipe_format format)
-{
- const int idx = ilo_format_translate(dev, format, PIPE_BIND_VERTEX_BUFFER);
-
- return (idx >= 0 && ilo_state_vf_valid_element_format(dev, idx));
-}
-
-bool
-ilo_format_support_sol(const struct ilo_dev *dev,
- enum pipe_format format)
-{
- const int idx = ilo_format_translate(dev, format, PIPE_BIND_STREAM_OUTPUT);
-
- return (idx >= 0 && ilo_state_surface_valid_format(dev,
- ILO_STATE_SURFACE_ACCESS_DP_SVB, idx));
-}
-
-bool
-ilo_format_support_sampler(const struct ilo_dev *dev,
- enum pipe_format format)
-{
- const int idx = ilo_format_translate(dev, format, PIPE_BIND_SAMPLER_VIEW);
-
- return (idx >= 0 && ilo_state_surface_valid_format(dev,
- ILO_STATE_SURFACE_ACCESS_SAMPLER, idx));
-}
-
-bool
-ilo_format_support_rt(const struct ilo_dev *dev,
- enum pipe_format format)
-{
- const int idx = ilo_format_translate(dev, format, PIPE_BIND_RENDER_TARGET);
-
- return (idx >= 0 && ilo_state_surface_valid_format(dev,
- ILO_STATE_SURFACE_ACCESS_DP_RENDER, idx));
-}
-
-bool
-ilo_format_support_zs(const struct ilo_dev *dev,
- enum pipe_format format)
-{
- switch (format) {
- case PIPE_FORMAT_Z16_UNORM:
- case PIPE_FORMAT_Z24X8_UNORM:
- case PIPE_FORMAT_Z32_FLOAT:
- case PIPE_FORMAT_Z24_UNORM_S8_UINT:
- case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
- return true;
- case PIPE_FORMAT_S8_UINT:
- /* TODO separate stencil */
- default:
- return false;
- }
-}
-
-/**
- * Translate a color (non-depth/stencil) pipe format to the matching hardware
- * format. Return -1 on errors.
- */
-int
-ilo_format_translate_color(const struct ilo_dev *dev,
- enum pipe_format format)
-{
- static const int format_mapping[PIPE_FORMAT_COUNT] = {
- [PIPE_FORMAT_NONE] = 0,
- [PIPE_FORMAT_B8G8R8A8_UNORM] = GEN6_FORMAT_B8G8R8A8_UNORM,
- [PIPE_FORMAT_B8G8R8X8_UNORM] = GEN6_FORMAT_B8G8R8X8_UNORM,
- [PIPE_FORMAT_A8R8G8B8_UNORM] = 0,
- [PIPE_FORMAT_X8R8G8B8_UNORM] = 0,
- [PIPE_FORMAT_B5G5R5A1_UNORM] = GEN6_FORMAT_B5G5R5A1_UNORM,
- [PIPE_FORMAT_B4G4R4A4_UNORM] = GEN6_FORMAT_B4G4R4A4_UNORM,
- [PIPE_FORMAT_B5G6R5_UNORM] = GEN6_FORMAT_B5G6R5_UNORM,
- [PIPE_FORMAT_R10G10B10A2_UNORM] = GEN6_FORMAT_R10G10B10A2_UNORM,
- [PIPE_FORMAT_L8_UNORM] = GEN6_FORMAT_L8_UNORM,
- [PIPE_FORMAT_A8_UNORM] = GEN6_FORMAT_A8_UNORM,
- [PIPE_FORMAT_I8_UNORM] = GEN6_FORMAT_I8_UNORM,
- [PIPE_FORMAT_L8A8_UNORM] = GEN6_FORMAT_L8A8_UNORM,
- [PIPE_FORMAT_L16_UNORM] = GEN6_FORMAT_L16_UNORM,
- [PIPE_FORMAT_UYVY] = GEN6_FORMAT_YCRCB_SWAPUVY,
- [PIPE_FORMAT_YUYV] = GEN6_FORMAT_YCRCB_NORMAL,
- [PIPE_FORMAT_Z16_UNORM] = 0,
- [PIPE_FORMAT_Z32_UNORM] = 0,
- [PIPE_FORMAT_Z32_FLOAT] = 0,
- [PIPE_FORMAT_Z24_UNORM_S8_UINT] = 0,
- [PIPE_FORMAT_S8_UINT_Z24_UNORM] = 0,
- [PIPE_FORMAT_Z24X8_UNORM] = 0,
- [PIPE_FORMAT_X8Z24_UNORM] = 0,
- [PIPE_FORMAT_S8_UINT] = 0,
- [PIPE_FORMAT_R64_FLOAT] = GEN6_FORMAT_R64_FLOAT,
- [PIPE_FORMAT_R64G64_FLOAT] = GEN6_FORMAT_R64G64_FLOAT,
- [PIPE_FORMAT_R64G64B64_FLOAT] = GEN6_FORMAT_R64G64B64_FLOAT,
- [PIPE_FORMAT_R64G64B64A64_FLOAT] = GEN6_FORMAT_R64G64B64A64_FLOAT,
- [PIPE_FORMAT_R32_FLOAT] = GEN6_FORMAT_R32_FLOAT,
- [PIPE_FORMAT_R32G32_FLOAT] = GEN6_FORMAT_R32G32_FLOAT,
- [PIPE_FORMAT_R32G32B32_FLOAT] = GEN6_FORMAT_R32G32B32_FLOAT,
- [PIPE_FORMAT_R32G32B32A32_FLOAT] = GEN6_FORMAT_R32G32B32A32_FLOAT,
- [PIPE_FORMAT_R32_UNORM] = GEN6_FORMAT_R32_UNORM,
- [PIPE_FORMAT_R32G32_UNORM] = GEN6_FORMAT_R32G32_UNORM,
- [PIPE_FORMAT_R32G32B32_UNORM] = GEN6_FORMAT_R32G32B32_UNORM,
- [PIPE_FORMAT_R32G32B32A32_UNORM] = GEN6_FORMAT_R32G32B32A32_UNORM,
- [PIPE_FORMAT_R32_USCALED] = GEN6_FORMAT_R32_USCALED,
- [PIPE_FORMAT_R32G32_USCALED] = GEN6_FORMAT_R32G32_USCALED,
- [PIPE_FORMAT_R32G32B32_USCALED] = GEN6_FORMAT_R32G32B32_USCALED,
- [PIPE_FORMAT_R32G32B32A32_USCALED] = GEN6_FORMAT_R32G32B32A32_USCALED,
- [PIPE_FORMAT_R32_SNORM] = GEN6_FORMAT_R32_SNORM,
- [PIPE_FORMAT_R32G32_SNORM] = GEN6_FORMAT_R32G32_SNORM,
- [PIPE_FORMAT_R32G32B32_SNORM] = GEN6_FORMAT_R32G32B32_SNORM,
- [PIPE_FORMAT_R32G32B32A32_SNORM] = GEN6_FORMAT_R32G32B32A32_SNORM,
- [PIPE_FORMAT_R32_SSCALED] = GEN6_FORMAT_R32_SSCALED,
- [PIPE_FORMAT_R32G32_SSCALED] = GEN6_FORMAT_R32G32_SSCALED,
- [PIPE_FORMAT_R32G32B32_SSCALED] = GEN6_FORMAT_R32G32B32_SSCALED,
- [PIPE_FORMAT_R32G32B32A32_SSCALED] = GEN6_FORMAT_R32G32B32A32_SSCALED,
- [PIPE_FORMAT_R16_UNORM] = GEN6_FORMAT_R16_UNORM,
- [PIPE_FORMAT_R16G16_UNORM] = GEN6_FORMAT_R16G16_UNORM,
- [PIPE_FORMAT_R16G16B16_UNORM] = GEN6_FORMAT_R16G16B16_UNORM,
- [PIPE_FORMAT_R16G16B16A16_UNORM] = GEN6_FORMAT_R16G16B16A16_UNORM,
- [PIPE_FORMAT_R16_USCALED] = GEN6_FORMAT_R16_USCALED,
- [PIPE_FORMAT_R16G16_USCALED] = GEN6_FORMAT_R16G16_USCALED,
- [PIPE_FORMAT_R16G16B16_USCALED] = GEN6_FORMAT_R16G16B16_USCALED,
- [PIPE_FORMAT_R16G16B16A16_USCALED] = GEN6_FORMAT_R16G16B16A16_USCALED,
- [PIPE_FORMAT_R16_SNORM] = GEN6_FORMAT_R16_SNORM,
- [PIPE_FORMAT_R16G16_SNORM] = GEN6_FORMAT_R16G16_SNORM,
- [PIPE_FORMAT_R16G16B16_SNORM] = GEN6_FORMAT_R16G16B16_SNORM,
- [PIPE_FORMAT_R16G16B16A16_SNORM] = GEN6_FORMAT_R16G16B16A16_SNORM,
- [PIPE_FORMAT_R16_SSCALED] = GEN6_FORMAT_R16_SSCALED,
- [PIPE_FORMAT_R16G16_SSCALED] = GEN6_FORMAT_R16G16_SSCALED,
- [PIPE_FORMAT_R16G16B16_SSCALED] = GEN6_FORMAT_R16G16B16_SSCALED,
- [PIPE_FORMAT_R16G16B16A16_SSCALED] = GEN6_FORMAT_R16G16B16A16_SSCALED,
- [PIPE_FORMAT_R8_UNORM] = GEN6_FORMAT_R8_UNORM,
- [PIPE_FORMAT_R8G8_UNORM] = GEN6_FORMAT_R8G8_UNORM,
- [PIPE_FORMAT_R8G8B8_UNORM] = GEN6_FORMAT_R8G8B8_UNORM,
- [PIPE_FORMAT_R8G8B8A8_UNORM] = GEN6_FORMAT_R8G8B8A8_UNORM,
- [PIPE_FORMAT_X8B8G8R8_UNORM] = 0,
- [PIPE_FORMAT_R8_USCALED] = GEN6_FORMAT_R8_USCALED,
- [PIPE_FORMAT_R8G8_USCALED] = GEN6_FORMAT_R8G8_USCALED,
- [PIPE_FORMAT_R8G8B8_USCALED] = GEN6_FORMAT_R8G8B8_USCALED,
- [PIPE_FORMAT_R8G8B8A8_USCALED] = GEN6_FORMAT_R8G8B8A8_USCALED,
- [PIPE_FORMAT_R8_SNORM] = GEN6_FORMAT_R8_SNORM,
- [PIPE_FORMAT_R8G8_SNORM] = GEN6_FORMAT_R8G8_SNORM,
- [PIPE_FORMAT_R8G8B8_SNORM] = GEN6_FORMAT_R8G8B8_SNORM,
- [PIPE_FORMAT_R8G8B8A8_SNORM] = GEN6_FORMAT_R8G8B8A8_SNORM,
- [PIPE_FORMAT_R8_SSCALED] = GEN6_FORMAT_R8_SSCALED,
- [PIPE_FORMAT_R8G8_SSCALED] = GEN6_FORMAT_R8G8_SSCALED,
- [PIPE_FORMAT_R8G8B8_SSCALED] = GEN6_FORMAT_R8G8B8_SSCALED,
- [PIPE_FORMAT_R8G8B8A8_SSCALED] = GEN6_FORMAT_R8G8B8A8_SSCALED,
- [PIPE_FORMAT_R32_FIXED] = GEN6_FORMAT_R32_SFIXED,
- [PIPE_FORMAT_R32G32_FIXED] = GEN6_FORMAT_R32G32_SFIXED,
- [PIPE_FORMAT_R32G32B32_FIXED] = GEN6_FORMAT_R32G32B32_SFIXED,
- [PIPE_FORMAT_R32G32B32A32_FIXED] = GEN6_FORMAT_R32G32B32A32_SFIXED,
- [PIPE_FORMAT_R16_FLOAT] = GEN6_FORMAT_R16_FLOAT,
- [PIPE_FORMAT_R16G16_FLOAT] = GEN6_FORMAT_R16G16_FLOAT,
- [PIPE_FORMAT_R16G16B16_FLOAT] = GEN6_FORMAT_R16G16B16_FLOAT,
- [PIPE_FORMAT_R16G16B16A16_FLOAT] = GEN6_FORMAT_R16G16B16A16_FLOAT,
- [PIPE_FORMAT_L8_SRGB] = GEN6_FORMAT_L8_UNORM_SRGB,
- [PIPE_FORMAT_L8A8_SRGB] = GEN6_FORMAT_L8A8_UNORM_SRGB,
- [PIPE_FORMAT_R8G8B8_SRGB] = GEN6_FORMAT_R8G8B8_UNORM_SRGB,
- [PIPE_FORMAT_A8B8G8R8_SRGB] = 0,
- [PIPE_FORMAT_X8B8G8R8_SRGB] = 0,
- [PIPE_FORMAT_B8G8R8A8_SRGB] = GEN6_FORMAT_B8G8R8A8_UNORM_SRGB,
- [PIPE_FORMAT_B8G8R8X8_SRGB] = GEN6_FORMAT_B8G8R8X8_UNORM_SRGB,
- [PIPE_FORMAT_A8R8G8B8_SRGB] = 0,
- [PIPE_FORMAT_X8R8G8B8_SRGB] = 0,
- [PIPE_FORMAT_R8G8B8A8_SRGB] = GEN6_FORMAT_R8G8B8A8_UNORM_SRGB,
- [PIPE_FORMAT_DXT1_RGB] = GEN6_FORMAT_DXT1_RGB,
- [PIPE_FORMAT_DXT1_RGBA] = GEN6_FORMAT_BC1_UNORM,
- [PIPE_FORMAT_DXT3_RGBA] = GEN6_FORMAT_BC2_UNORM,
- [PIPE_FORMAT_DXT5_RGBA] = GEN6_FORMAT_BC3_UNORM,
- [PIPE_FORMAT_DXT1_SRGB] = GEN6_FORMAT_DXT1_RGB_SRGB,
- [PIPE_FORMAT_DXT1_SRGBA] = GEN6_FORMAT_BC1_UNORM_SRGB,
- [PIPE_FORMAT_DXT3_SRGBA] = GEN6_FORMAT_BC2_UNORM_SRGB,
- [PIPE_FORMAT_DXT5_SRGBA] = GEN6_FORMAT_BC3_UNORM_SRGB,
- [PIPE_FORMAT_RGTC1_UNORM] = GEN6_FORMAT_BC4_UNORM,
- [PIPE_FORMAT_RGTC1_SNORM] = GEN6_FORMAT_BC4_SNORM,
- [PIPE_FORMAT_RGTC2_UNORM] = GEN6_FORMAT_BC5_UNORM,
- [PIPE_FORMAT_RGTC2_SNORM] = GEN6_FORMAT_BC5_SNORM,
- [PIPE_FORMAT_R8G8_B8G8_UNORM] = 0,
- [PIPE_FORMAT_G8R8_G8B8_UNORM] = 0,
- [PIPE_FORMAT_R8SG8SB8UX8U_NORM] = 0,
- [PIPE_FORMAT_R5SG5SB6U_NORM] = 0,
- [PIPE_FORMAT_A8B8G8R8_UNORM] = 0,
- [PIPE_FORMAT_B5G5R5X1_UNORM] = GEN6_FORMAT_B5G5R5X1_UNORM,
- [PIPE_FORMAT_R10G10B10A2_USCALED] = GEN6_FORMAT_R10G10B10A2_USCALED,
- [PIPE_FORMAT_R11G11B10_FLOAT] = GEN6_FORMAT_R11G11B10_FLOAT,
- [PIPE_FORMAT_R9G9B9E5_FLOAT] = GEN6_FORMAT_R9G9B9E5_SHAREDEXP,
- [PIPE_FORMAT_Z32_FLOAT_S8X24_UINT] = 0,
- [PIPE_FORMAT_R1_UNORM] = GEN6_FORMAT_R1_UNORM,
- [PIPE_FORMAT_R10G10B10X2_USCALED] = GEN6_FORMAT_R10G10B10X2_USCALED,
- [PIPE_FORMAT_R10G10B10X2_SNORM] = 0,
- [PIPE_FORMAT_L4A4_UNORM] = 0,
- [PIPE_FORMAT_B10G10R10A2_UNORM] = GEN6_FORMAT_B10G10R10A2_UNORM,
- [PIPE_FORMAT_R10SG10SB10SA2U_NORM] = 0,
- [PIPE_FORMAT_R8G8Bx_SNORM] = 0,
- [PIPE_FORMAT_R8G8B8X8_UNORM] = GEN6_FORMAT_R8G8B8X8_UNORM,
- [PIPE_FORMAT_B4G4R4X4_UNORM] = 0,
- [PIPE_FORMAT_X24S8_UINT] = 0,
- [PIPE_FORMAT_S8X24_UINT] = 0,
- [PIPE_FORMAT_X32_S8X24_UINT] = 0,
- [PIPE_FORMAT_B2G3R3_UNORM] = 0,
- [PIPE_FORMAT_L16A16_UNORM] = GEN6_FORMAT_L16A16_UNORM,
- [PIPE_FORMAT_A16_UNORM] = GEN6_FORMAT_A16_UNORM,
- [PIPE_FORMAT_I16_UNORM] = GEN6_FORMAT_I16_UNORM,
- [PIPE_FORMAT_LATC1_UNORM] = 0,
- [PIPE_FORMAT_LATC1_SNORM] = 0,
- [PIPE_FORMAT_LATC2_UNORM] = 0,
- [PIPE_FORMAT_LATC2_SNORM] = 0,
- [PIPE_FORMAT_A8_SNORM] = 0,
- [PIPE_FORMAT_L8_SNORM] = 0,
- [PIPE_FORMAT_L8A8_SNORM] = 0,
- [PIPE_FORMAT_I8_SNORM] = 0,
- [PIPE_FORMAT_A16_SNORM] = 0,
- [PIPE_FORMAT_L16_SNORM] = 0,
- [PIPE_FORMAT_L16A16_SNORM] = 0,
- [PIPE_FORMAT_I16_SNORM] = 0,
- [PIPE_FORMAT_A16_FLOAT] = GEN6_FORMAT_A16_FLOAT,
- [PIPE_FORMAT_L16_FLOAT] = GEN6_FORMAT_L16_FLOAT,
- [PIPE_FORMAT_L16A16_FLOAT] = GEN6_FORMAT_L16A16_FLOAT,
- [PIPE_FORMAT_I16_FLOAT] = GEN6_FORMAT_I16_FLOAT,
- [PIPE_FORMAT_A32_FLOAT] = GEN6_FORMAT_A32_FLOAT,
- [PIPE_FORMAT_L32_FLOAT] = GEN6_FORMAT_L32_FLOAT,
- [PIPE_FORMAT_L32A32_FLOAT] = GEN6_FORMAT_L32A32_FLOAT,
- [PIPE_FORMAT_I32_FLOAT] = GEN6_FORMAT_I32_FLOAT,
- [PIPE_FORMAT_YV12] = 0,
- [PIPE_FORMAT_YV16] = 0,
- [PIPE_FORMAT_IYUV] = 0,
- [PIPE_FORMAT_NV12] = 0,
- [PIPE_FORMAT_NV21] = 0,
- [PIPE_FORMAT_A4R4_UNORM] = 0,
- [PIPE_FORMAT_R4A4_UNORM] = 0,
- [PIPE_FORMAT_R8A8_UNORM] = 0,
- [PIPE_FORMAT_A8R8_UNORM] = 0,
- [PIPE_FORMAT_R10G10B10A2_SSCALED] = GEN6_FORMAT_R10G10B10A2_SSCALED,
- [PIPE_FORMAT_R10G10B10A2_SNORM] = GEN6_FORMAT_R10G10B10A2_SNORM,
- [PIPE_FORMAT_B10G10R10A2_USCALED] = GEN6_FORMAT_B10G10R10A2_USCALED,
- [PIPE_FORMAT_B10G10R10A2_SSCALED] = GEN6_FORMAT_B10G10R10A2_SSCALED,
- [PIPE_FORMAT_B10G10R10A2_SNORM] = GEN6_FORMAT_B10G10R10A2_SNORM,
- [PIPE_FORMAT_R8_UINT] = GEN6_FORMAT_R8_UINT,
- [PIPE_FORMAT_R8G8_UINT] = GEN6_FORMAT_R8G8_UINT,
- [PIPE_FORMAT_R8G8B8_UINT] = GEN6_FORMAT_R8G8B8_UINT,
- [PIPE_FORMAT_R8G8B8A8_UINT] = GEN6_FORMAT_R8G8B8A8_UINT,
- [PIPE_FORMAT_R8_SINT] = GEN6_FORMAT_R8_SINT,
- [PIPE_FORMAT_R8G8_SINT] = GEN6_FORMAT_R8G8_SINT,
- [PIPE_FORMAT_R8G8B8_SINT] = GEN6_FORMAT_R8G8B8_SINT,
- [PIPE_FORMAT_R8G8B8A8_SINT] = GEN6_FORMAT_R8G8B8A8_SINT,
- [PIPE_FORMAT_R16_UINT] = GEN6_FORMAT_R16_UINT,
- [PIPE_FORMAT_R16G16_UINT] = GEN6_FORMAT_R16G16_UINT,
- [PIPE_FORMAT_R16G16B16_UINT] = GEN6_FORMAT_R16G16B16_UINT,
- [PIPE_FORMAT_R16G16B16A16_UINT] = GEN6_FORMAT_R16G16B16A16_UINT,
- [PIPE_FORMAT_R16_SINT] = GEN6_FORMAT_R16_SINT,
- [PIPE_FORMAT_R16G16_SINT] = GEN6_FORMAT_R16G16_SINT,
- [PIPE_FORMAT_R16G16B16_SINT] = GEN6_FORMAT_R16G16B16_SINT,
- [PIPE_FORMAT_R16G16B16A16_SINT] = GEN6_FORMAT_R16G16B16A16_SINT,
- [PIPE_FORMAT_R32_UINT] = GEN6_FORMAT_R32_UINT,
- [PIPE_FORMAT_R32G32_UINT] = GEN6_FORMAT_R32G32_UINT,
- [PIPE_FORMAT_R32G32B32_UINT] = GEN6_FORMAT_R32G32B32_UINT,
- [PIPE_FORMAT_R32G32B32A32_UINT] = GEN6_FORMAT_R32G32B32A32_UINT,
- [PIPE_FORMAT_R32_SINT] = GEN6_FORMAT_R32_SINT,
- [PIPE_FORMAT_R32G32_SINT] = GEN6_FORMAT_R32G32_SINT,
- [PIPE_FORMAT_R32G32B32_SINT] = GEN6_FORMAT_R32G32B32_SINT,
- [PIPE_FORMAT_R32G32B32A32_SINT] = GEN6_FORMAT_R32G32B32A32_SINT,
- [PIPE_FORMAT_A8_UINT] = 0,
- [PIPE_FORMAT_I8_UINT] = GEN6_FORMAT_I8_UINT,
- [PIPE_FORMAT_L8_UINT] = GEN6_FORMAT_L8_UINT,
- [PIPE_FORMAT_L8A8_UINT] = GEN6_FORMAT_L8A8_UINT,
- [PIPE_FORMAT_A8_SINT] = 0,
- [PIPE_FORMAT_I8_SINT] = GEN6_FORMAT_I8_SINT,
- [PIPE_FORMAT_L8_SINT] = GEN6_FORMAT_L8_SINT,
- [PIPE_FORMAT_L8A8_SINT] = GEN6_FORMAT_L8A8_SINT,
- [PIPE_FORMAT_A16_UINT] = 0,
- [PIPE_FORMAT_I16_UINT] = 0,
- [PIPE_FORMAT_L16_UINT] = 0,
- [PIPE_FORMAT_L16A16_UINT] = 0,
- [PIPE_FORMAT_A16_SINT] = 0,
- [PIPE_FORMAT_I16_SINT] = 0,
- [PIPE_FORMAT_L16_SINT] = 0,
- [PIPE_FORMAT_L16A16_SINT] = 0,
- [PIPE_FORMAT_A32_UINT] = 0,
- [PIPE_FORMAT_I32_UINT] = 0,
- [PIPE_FORMAT_L32_UINT] = 0,
- [PIPE_FORMAT_L32A32_UINT] = 0,
- [PIPE_FORMAT_A32_SINT] = 0,
- [PIPE_FORMAT_I32_SINT] = 0,
- [PIPE_FORMAT_L32_SINT] = 0,
- [PIPE_FORMAT_L32A32_SINT] = 0,
- [PIPE_FORMAT_B10G10R10A2_UINT] = GEN6_FORMAT_B10G10R10A2_UINT,
- [PIPE_FORMAT_ETC1_RGB8] = GEN6_FORMAT_ETC1_RGB8,
- [PIPE_FORMAT_R8G8_R8B8_UNORM] = 0,
- [PIPE_FORMAT_G8R8_B8R8_UNORM] = 0,
- [PIPE_FORMAT_R8G8B8X8_SNORM] = 0,
- [PIPE_FORMAT_R8G8B8X8_SRGB] = 0,
- [PIPE_FORMAT_R8G8B8X8_UINT] = 0,
- [PIPE_FORMAT_R8G8B8X8_SINT] = 0,
- [PIPE_FORMAT_B10G10R10X2_UNORM] = GEN6_FORMAT_B10G10R10X2_UNORM,
- [PIPE_FORMAT_R16G16B16X16_UNORM] = GEN6_FORMAT_R16G16B16X16_UNORM,
- [PIPE_FORMAT_R16G16B16X16_SNORM] = 0,
- [PIPE_FORMAT_R16G16B16X16_FLOAT] = GEN6_FORMAT_R16G16B16X16_FLOAT,
- [PIPE_FORMAT_R16G16B16X16_UINT] = 0,
- [PIPE_FORMAT_R16G16B16X16_SINT] = 0,
- [PIPE_FORMAT_R32G32B32X32_FLOAT] = GEN6_FORMAT_R32G32B32X32_FLOAT,
- [PIPE_FORMAT_R32G32B32X32_UINT] = 0,
- [PIPE_FORMAT_R32G32B32X32_SINT] = 0,
- [PIPE_FORMAT_R8A8_SNORM] = 0,
- [PIPE_FORMAT_R16A16_UNORM] = 0,
- [PIPE_FORMAT_R16A16_SNORM] = 0,
- [PIPE_FORMAT_R16A16_FLOAT] = 0,
- [PIPE_FORMAT_R32A32_FLOAT] = 0,
- [PIPE_FORMAT_R8A8_UINT] = 0,
- [PIPE_FORMAT_R8A8_SINT] = 0,
- [PIPE_FORMAT_R16A16_UINT] = 0,
- [PIPE_FORMAT_R16A16_SINT] = 0,
- [PIPE_FORMAT_R32A32_UINT] = 0,
- [PIPE_FORMAT_R32A32_SINT] = 0,
- [PIPE_FORMAT_R10G10B10A2_UINT] = GEN6_FORMAT_R10G10B10A2_UINT,
- [PIPE_FORMAT_B5G6R5_SRGB] = GEN6_FORMAT_B5G6R5_UNORM_SRGB,
- };
- int sfmt = format_mapping[format];
-
- /* GEN6_FORMAT_R32G32B32A32_FLOAT happens to be 0 */
- if (!sfmt && format != PIPE_FORMAT_R32G32B32A32_FLOAT)
- sfmt = -1;
-
- return sfmt;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_FORMAT_H
-#define ILO_FORMAT_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_common.h"
-
-bool
-ilo_format_support_vb(const struct ilo_dev *dev,
- enum pipe_format format);
-
-bool
-ilo_format_support_sol(const struct ilo_dev *dev,
- enum pipe_format format);
-
-bool
-ilo_format_support_sampler(const struct ilo_dev *dev,
- enum pipe_format format);
-
-bool
-ilo_format_support_rt(const struct ilo_dev *dev,
- enum pipe_format format);
-
-bool
-ilo_format_support_zs(const struct ilo_dev *dev,
- enum pipe_format format);
-
-int
-ilo_format_translate_color(const struct ilo_dev *dev,
- enum pipe_format format);
-
-/**
- * Translate a pipe format to a hardware surface format suitable for
- * the given purpose. Return -1 on errors.
- *
- * This is an inline function not only for performance reasons. There are
- * caveats that the callers should be aware of before calling this function.
- */
-static inline int
-ilo_format_translate(const struct ilo_dev *dev,
- enum pipe_format format, unsigned bind)
-{
- switch (bind) {
- case PIPE_BIND_RENDER_TARGET:
- /*
- * Some RGBX formats are not supported as render target formats. But we
- * can use their RGBA counterparts and force the destination alpha to be
- * one when blending is enabled.
- */
- switch (format) {
- case PIPE_FORMAT_B8G8R8X8_UNORM:
- return GEN6_FORMAT_B8G8R8A8_UNORM;
- default:
- return ilo_format_translate_color(dev, format);
- }
- break;
- case PIPE_BIND_SAMPLER_VIEW:
- /*
- * For depth formats, we want the depth values to be returned as R
- * values. But we assume in many places that the depth values are
- * returned as I values (util_make_fragment_tex_shader_writedepth() is
- * one such example). We have to live with that at least for now.
- *
- * For ETC1 format, the texture data will be decompressed before being
- * written to the bo. See tex_staging_sys_convert_write().
- */
- switch (format) {
- case PIPE_FORMAT_Z16_UNORM:
- return GEN6_FORMAT_I16_UNORM;
- case PIPE_FORMAT_Z32_FLOAT:
- return GEN6_FORMAT_I32_FLOAT;
- case PIPE_FORMAT_Z24X8_UNORM:
- case PIPE_FORMAT_Z24_UNORM_S8_UINT:
- return GEN6_FORMAT_I24X8_UNORM;
- case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
- return GEN6_FORMAT_I32X32_FLOAT;
- case PIPE_FORMAT_ETC1_RGB8:
- return GEN6_FORMAT_R8G8B8X8_UNORM;
- default:
- return ilo_format_translate_color(dev, format);
- }
- break;
- case PIPE_BIND_VERTEX_BUFFER:
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5))
- return ilo_format_translate_color(dev, format);
-
- /*
- * Some 3-component formats are not supported as vertex element formats.
- * But since we move between vertices using vb->stride, we should be
- * good to use their 4-component counterparts if we force the W
- * component to be one. The only exception is that the vb boundary
- * check for the last vertex may fail.
- */
- switch (format) {
- case PIPE_FORMAT_R16G16B16_FLOAT:
- return GEN6_FORMAT_R16G16B16A16_FLOAT;
- case PIPE_FORMAT_R16G16B16_UINT:
- return GEN6_FORMAT_R16G16B16A16_UINT;
- case PIPE_FORMAT_R16G16B16_SINT:
- return GEN6_FORMAT_R16G16B16A16_SINT;
- case PIPE_FORMAT_R8G8B8_UINT:
- return GEN6_FORMAT_R8G8B8A8_UINT;
- case PIPE_FORMAT_R8G8B8_SINT:
- return GEN6_FORMAT_R8G8B8A8_SINT;
- default:
- return ilo_format_translate_color(dev, format);
- }
- break;
- case PIPE_BIND_STREAM_OUTPUT:
- return ilo_format_translate_color(dev, format);
- break;
- default:
- assert(!"cannot translate format");
- break;
- }
-
- return -1;
-}
-
-static inline int
-ilo_format_translate_render(const struct ilo_dev *dev,
- enum pipe_format format)
-{
- return ilo_format_translate(dev, format, PIPE_BIND_RENDER_TARGET);
-}
-
-static inline int
-ilo_format_translate_texture(const struct ilo_dev *dev,
- enum pipe_format format)
-{
- return ilo_format_translate(dev, format, PIPE_BIND_SAMPLER_VIEW);
-}
-
-static inline int
-ilo_format_translate_vertex(const struct ilo_dev *dev,
- enum pipe_format format)
-{
- return ilo_format_translate(dev, format, PIPE_BIND_VERTEX_BUFFER);
-}
-
-static inline enum gen_depth_format
-ilo_format_translate_depth(const struct ilo_dev *dev,
- enum pipe_format format)
-{
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- switch (format) {
- case PIPE_FORMAT_Z32_FLOAT:
- return GEN6_ZFORMAT_D32_FLOAT;
- case PIPE_FORMAT_Z24X8_UNORM:
- return GEN6_ZFORMAT_D24_UNORM_X8_UINT;
- case PIPE_FORMAT_Z16_UNORM:
- return GEN6_ZFORMAT_D16_UNORM;
- default:
- assert(!"unknown depth format");
- return GEN6_ZFORMAT_D32_FLOAT;
- }
- } else {
- switch (format) {
- case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
- return GEN6_ZFORMAT_D32_FLOAT_S8X24_UINT;
- case PIPE_FORMAT_Z32_FLOAT:
- return GEN6_ZFORMAT_D32_FLOAT;
- case PIPE_FORMAT_Z24_UNORM_S8_UINT:
- return GEN6_ZFORMAT_D24_UNORM_S8_UINT;
- case PIPE_FORMAT_Z24X8_UNORM:
- return GEN6_ZFORMAT_D24_UNORM_X8_UINT;
- case PIPE_FORMAT_Z16_UNORM:
- return GEN6_ZFORMAT_D16_UNORM;
- default:
- assert(!"unknown depth format");
- return GEN6_ZFORMAT_D32_FLOAT;
- }
- }
-}
-
-#endif /* ILO_FORMAT_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "util/u_upload_mgr.h"
-#include "ilo_context.h"
-#include "ilo_render.h"
-#include "ilo_shader.h"
-#include "ilo_gpgpu.h"
-
-static void
-launch_grid(struct ilo_context *ilo,
- const uint *block_layout, const uint *grid_layout,
- const struct pipe_constant_buffer *input, uint32_t pc)
-{
- const unsigned grid_offset[3] = { 0, 0, 0 };
- const unsigned thread_group_size =
- block_layout[0] * block_layout[1] * block_layout[2];
- int max_len, before_space;
-
- ilo_cp_set_owner(ilo->cp, INTEL_RING_RENDER, NULL);
-
- max_len = ilo_render_get_launch_grid_len(ilo->render, &ilo->state_vector);
- max_len += ilo_render_get_flush_len(ilo->render) * 2;
-
- if (max_len > ilo_cp_space(ilo->cp)) {
- ilo_cp_submit(ilo->cp, "out of space");
- assert(max_len <= ilo_cp_space(ilo->cp));
- }
-
- before_space = ilo_cp_space(ilo->cp);
-
- while (true) {
- struct ilo_builder_snapshot snapshot;
-
- ilo_builder_batch_snapshot(&ilo->cp->builder, &snapshot);
-
- ilo_render_emit_launch_grid(ilo->render, &ilo->state_vector,
- grid_offset, grid_layout, thread_group_size, input, pc);
-
- if (!ilo_builder_validate(&ilo->cp->builder, 0, NULL)) {
- ilo_builder_batch_restore(&ilo->cp->builder, &snapshot);
-
- /* flush and try again */
- if (ilo_builder_batch_used(&ilo->cp->builder)) {
- ilo_cp_submit(ilo->cp, "out of aperture");
- continue;
- }
- }
-
- break;
- }
-
- /* sanity check size estimation */
- assert(before_space - ilo_cp_space(ilo->cp) <= max_len);
-}
-
-static void
-ilo_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
-{
- struct ilo_context *ilo = ilo_context(pipe);
- struct ilo_shader_state *cs = ilo->state_vector.cs;
- struct pipe_constant_buffer input_buf;
-
- memset(&input_buf, 0, sizeof(input_buf));
-
- input_buf.buffer_size =
- ilo_shader_get_kernel_param(cs, ILO_KERNEL_CS_INPUT_SIZE);
- if (input_buf.buffer_size) {
- u_upload_data(ilo->uploader, 0, input_buf.buffer_size, 16, info->input,
- &input_buf.buffer_offset, &input_buf.buffer);
- }
-
- ilo_shader_cache_upload(ilo->shader_cache, &ilo->cp->builder);
-
- launch_grid(ilo, info->block, info->grid, &input_buf, info->pc);
-
- ilo_render_invalidate_hw(ilo->render);
-
- if (ilo_debug & ILO_DEBUG_NOCACHE)
- ilo_render_emit_flush(ilo->render);
-
- if (input_buf.buffer_size)
- pipe_resource_reference(&input_buf.buffer, NULL);
-}
-
-/**
- * Initialize GPGPU-related functions.
- */
-void
-ilo_init_gpgpu_functions(struct ilo_context *ilo)
-{
- ilo->base.launch_grid = ilo_launch_grid;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_GPGPU_H
-#define ILO_GPGPU_H
-
-#include "ilo_common.h"
-
-struct ilo_context;
-
-void
-ilo_init_gpgpu_functions(struct ilo_context *ilo);
-
-#endif /* ILO_GPGPU_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_PUBLIC_H
-#define ILO_PUBLIC_H
-
-struct intel_winsys;
-struct pipe_screen;
-
-struct pipe_screen *
-ilo_screen_create(struct intel_winsys *ws);
-
-#endif /* ILO_PUBLIC_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "core/intel_winsys.h"
-
-#include "ilo_context.h"
-#include "ilo_cp.h"
-#include "ilo_draw.h"
-#include "ilo_query.h"
-
-static const struct {
- bool (*init)(struct ilo_context *ilo, struct ilo_query *q);
- void (*begin)(struct ilo_context *ilo, struct ilo_query *q);
- void (*end)(struct ilo_context *ilo, struct ilo_query *q);
- void (*process)(struct ilo_context *ilo, struct ilo_query *q);
-} ilo_query_table[PIPE_QUERY_TYPES] = {
-#define INFO(mod) { \
- .init = ilo_init_ ## mod ## _query, \
- .begin = ilo_begin_ ## mod ## _query, \
- .end = ilo_end_ ## mod ## _query, \
- .process = ilo_process_ ## mod ## _query, \
-}
-#define INFOX(prefix) { NULL, NULL, NULL, NULL, }
-
- [PIPE_QUERY_OCCLUSION_COUNTER] = INFO(draw),
- [PIPE_QUERY_OCCLUSION_PREDICATE] = INFO(draw),
- [PIPE_QUERY_TIMESTAMP] = INFO(draw),
- [PIPE_QUERY_TIMESTAMP_DISJOINT] = INFOX(draw),
- [PIPE_QUERY_TIME_ELAPSED] = INFO(draw),
- [PIPE_QUERY_PRIMITIVES_GENERATED] = INFO(draw),
- [PIPE_QUERY_PRIMITIVES_EMITTED] = INFO(draw),
- [PIPE_QUERY_SO_STATISTICS] = INFOX(draw),
- [PIPE_QUERY_SO_OVERFLOW_PREDICATE] = INFOX(draw),
- [PIPE_QUERY_GPU_FINISHED] = INFOX(draw),
- [PIPE_QUERY_PIPELINE_STATISTICS] = INFO(draw),
-
-#undef INFO
-#undef INFOX
-};
-
-static inline struct ilo_query *
-ilo_query(struct pipe_query *query)
-{
- return (struct ilo_query *) query;
-}
-
-static struct pipe_query *
-ilo_create_query(struct pipe_context *pipe, unsigned query_type, unsigned index)
-{
- struct ilo_query *q;
-
- switch (query_type) {
- case PIPE_QUERY_OCCLUSION_COUNTER:
- case PIPE_QUERY_OCCLUSION_PREDICATE:
- case PIPE_QUERY_TIMESTAMP:
- case PIPE_QUERY_TIME_ELAPSED:
- case PIPE_QUERY_PRIMITIVES_GENERATED:
- case PIPE_QUERY_PRIMITIVES_EMITTED:
- case PIPE_QUERY_PIPELINE_STATISTICS:
- break;
- default:
- return NULL;
- }
-
- q = CALLOC_STRUCT(ilo_query);
- if (!q)
- return NULL;
-
- q->type = query_type;
- q->index = index;
-
- list_inithead(&q->list);
-
- if (!ilo_query_table[q->type].init(ilo_context(pipe), q)) {
- FREE(q);
- return NULL;
- }
-
- return (struct pipe_query *) q;
-}
-
-static void
-ilo_destroy_query(struct pipe_context *pipe, struct pipe_query *query)
-{
- struct ilo_query *q = ilo_query(query);
-
- intel_bo_unref(q->bo);
- FREE(q);
-}
-
-static boolean
-ilo_begin_query(struct pipe_context *pipe, struct pipe_query *query)
-{
- struct ilo_query *q = ilo_query(query);
-
- if (q->active)
- return false;
-
- util_query_clear_result(&q->result, q->type);
- q->used = 0;
- q->active = true;
-
- ilo_query_table[q->type].begin(ilo_context(pipe), q);
- return true;
-}
-
-static bool
-ilo_end_query(struct pipe_context *pipe, struct pipe_query *query)
-{
- struct ilo_query *q = ilo_query(query);
-
- if (!q->active) {
- /* require ilo_begin_query() first */
- if (q->in_pairs)
- return false;
-
- ilo_begin_query(pipe, query);
- }
-
- q->active = false;
-
- ilo_query_table[q->type].end(ilo_context(pipe), q);
-
- return true;
-}
-
-/**
- * Serialize the result. The size of \p buf is
- * sizeof(union pipe_query_result).
- */
-static void
-query_serialize(const struct ilo_query *q, void *buf)
-{
- switch (q->type) {
- case PIPE_QUERY_OCCLUSION_COUNTER:
- case PIPE_QUERY_TIMESTAMP:
- case PIPE_QUERY_TIME_ELAPSED:
- case PIPE_QUERY_PRIMITIVES_GENERATED:
- case PIPE_QUERY_PRIMITIVES_EMITTED:
- {
- uint64_t *dst = buf;
- dst[0] = q->result.u64;
- }
- break;
- case PIPE_QUERY_OCCLUSION_PREDICATE:
- {
- uint64_t *dst = buf;
- dst[0] = !!q->result.u64;
- }
- break;
- case PIPE_QUERY_PIPELINE_STATISTICS:
- {
- const struct pipe_query_data_pipeline_statistics *stats =
- &q->result.pipeline_statistics;
- uint64_t *dst = buf;
-
- dst[0] = stats->ia_vertices;
- dst[1] = stats->ia_primitives;
- dst[2] = stats->vs_invocations;
- dst[3] = stats->gs_invocations;
- dst[4] = stats->gs_primitives;
- dst[5] = stats->c_invocations;
- dst[6] = stats->c_primitives;
- dst[7] = stats->ps_invocations;
- dst[8] = stats->hs_invocations;
- dst[9] = stats->ds_invocations;
- dst[10] = stats->cs_invocations;
- }
- break;
- default:
- memset(buf, 0, sizeof(union pipe_query_result));
- break;
- }
-}
-
-static boolean
-ilo_get_query_result(struct pipe_context *pipe, struct pipe_query *query,
- boolean wait, union pipe_query_result *result)
-{
- struct ilo_query *q = ilo_query(query);
-
- if (q->active)
- return false;
-
- if (q->bo) {
- struct ilo_cp *cp = ilo_context(pipe)->cp;
-
- if (ilo_builder_has_reloc(&cp->builder, q->bo))
- ilo_cp_submit(cp, "syncing for queries");
-
- if (!wait && intel_bo_is_busy(q->bo))
- return false;
- }
-
- ilo_query_table[q->type].process(ilo_context(pipe), q);
-
- if (result)
- query_serialize(q, (void *) result);
-
- return true;
-}
-
-static void
-ilo_set_active_query_state(struct pipe_context *pipe, boolean enable)
-{
-}
-
-/**
- * Initialize query-related functions.
- */
-void
-ilo_init_query_functions(struct ilo_context *ilo)
-{
- ilo->base.create_query = ilo_create_query;
- ilo->base.destroy_query = ilo_destroy_query;
- ilo->base.begin_query = ilo_begin_query;
- ilo->base.end_query = ilo_end_query;
- ilo->base.get_query_result = ilo_get_query_result;
- ilo->base.set_active_query_state = ilo_set_active_query_state;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_QUERY_H
-#define ILO_QUERY_H
-
-#include "ilo_common.h"
-
-struct intel_bo;
-struct ilo_context;
-
-/**
- * Queries can be bound to various places in the driver. While bound, it tells
- * the driver to collect the data indicated by the type of the query.
- */
-struct ilo_query {
- unsigned type;
- unsigned index;
-
- struct list_head list;
-
- bool active;
-
- /* for queries that need to read hardware statistics */
- int cmd_len; /* in dwords, as expected by ilo_cp */
- bool in_pairs;
- struct intel_bo *bo;
- int stride, count;
- int used;
-
- /* storage for the collected data */
- union pipe_query_result result;
-};
-
-void
-ilo_init_query_functions(struct ilo_context *ilo);
-
-#endif /* ILO_QUERY_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "genhw/genhw.h"
-#include "core/ilo_builder.h"
-#include "core/ilo_builder_mi.h"
-#include "core/ilo_builder_render.h"
-#include "core/intel_winsys.h"
-#include "util/u_prim.h"
-
-#include "ilo_query.h"
-#include "ilo_render_gen.h"
-
-struct ilo_render *
-ilo_render_create(struct ilo_builder *builder)
-{
- struct ilo_render *render;
-
- render = CALLOC_STRUCT(ilo_render);
- if (!render)
- return NULL;
-
- render->dev = builder->dev;
- render->builder = builder;
-
- render->workaround_bo = intel_winsys_alloc_bo(builder->winsys,
- "PIPE_CONTROL workaround", 4096, false);
- if (!render->workaround_bo) {
- ilo_warn("failed to allocate PIPE_CONTROL workaround bo\n");
- FREE(render);
- return NULL;
- }
-
- ilo_state_sample_pattern_init_default(&render->sample_pattern,
- render->dev);
-
- ilo_render_invalidate_hw(render);
- ilo_render_invalidate_builder(render);
-
- return render;
-}
-
-void
-ilo_render_destroy(struct ilo_render *render)
-{
- intel_bo_unref(render->vs_scratch.bo);
- intel_bo_unref(render->gs_scratch.bo);
- intel_bo_unref(render->fs_scratch.bo);
-
- intel_bo_unref(render->workaround_bo);
- FREE(render);
-}
-
-static bool
-resize_scratch_space(struct ilo_render *render,
- struct ilo_render_scratch_space *scratch,
- const char *name, int new_size)
-{
- struct intel_bo *bo;
-
- if (scratch->size >= new_size)
- return true;
-
- bo = intel_winsys_alloc_bo(render->builder->winsys, name, new_size, false);
- if (!bo)
- return false;
-
- intel_bo_unref(scratch->bo);
- scratch->bo = bo;
- scratch->size = new_size;
-
- return true;
-}
-
-bool
-ilo_render_prepare_scratch_spaces(struct ilo_render *render,
- int vs_scratch_size,
- int gs_scratch_size,
- int fs_scratch_size)
-{
- return (resize_scratch_space(render, &render->vs_scratch,
- "vs scratch", vs_scratch_size) &&
- resize_scratch_space(render, &render->gs_scratch,
- "gs scratch", gs_scratch_size) &&
- resize_scratch_space(render, &render->fs_scratch,
- "fs scratch", fs_scratch_size));
-}
-
-void
-ilo_render_get_sample_position(const struct ilo_render *render,
- unsigned sample_count,
- unsigned sample_index,
- float *x, float *y)
-{
- uint8_t off_x, off_y;
-
- ilo_state_sample_pattern_get_offset(&render->sample_pattern, render->dev,
- sample_count, sample_index, &off_x, &off_y);
-
- *x = (float) off_x / 16.0f;
- *y = (float) off_y / 16.0f;
-}
-
-void
-ilo_render_invalidate_hw(struct ilo_render *render)
-{
- render->hw_ctx_changed = true;
-}
-
-void
-ilo_render_invalidate_builder(struct ilo_render *render)
-{
- render->batch_bo_changed = true;
- render->state_bo_changed = true;
- render->instruction_bo_changed = true;
-
- /* Kernel flushes everything. Shouldn't we set all bits here? */
- render->state.current_pipe_control_dw1 = 0;
-}
-
-/**
- * Return the command length of ilo_render_emit_flush().
- */
-int
-ilo_render_get_flush_len(const struct ilo_render *render)
-{
- int len;
-
- ILO_DEV_ASSERT(render->dev, 6, 8);
-
- len = GEN6_PIPE_CONTROL__SIZE;
-
- /* plus gen6_wa_pre_pipe_control() */
- if (ilo_dev_gen(render->dev) == ILO_GEN(6))
- len *= 3;
-
- return len;
-}
-
-/**
- * Emit PIPE_CONTROLs to flush all caches.
- */
-void
-ilo_render_emit_flush(struct ilo_render *render)
-{
- const uint32_t dw1 = GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE |
- GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH |
- GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- GEN6_PIPE_CONTROL_VF_CACHE_INVALIDATE |
- GEN6_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
- GEN6_PIPE_CONTROL_CS_STALL;
- const unsigned batch_used = ilo_builder_batch_used(render->builder);
-
- ILO_DEV_ASSERT(render->dev, 6, 8);
-
- if (ilo_dev_gen(render->dev) == ILO_GEN(6))
- gen6_wa_pre_pipe_control(render, dw1);
-
- ilo_render_pipe_control(render, dw1);
-
- assert(ilo_builder_batch_used(render->builder) <= batch_used +
- ilo_render_get_flush_len(render));
-}
-
-/**
- * Return the command length of ilo_render_emit_query().
- */
-int
-ilo_render_get_query_len(const struct ilo_render *render,
- unsigned query_type)
-{
- int len;
-
- ILO_DEV_ASSERT(render->dev, 6, 8);
-
- /* always a flush or a variant of flush */
- len = ilo_render_get_flush_len(render);
-
- switch (query_type) {
- case PIPE_QUERY_OCCLUSION_COUNTER:
- case PIPE_QUERY_OCCLUSION_PREDICATE:
- case PIPE_QUERY_TIMESTAMP:
- case PIPE_QUERY_TIME_ELAPSED:
- /* no reg */
- break;
- case PIPE_QUERY_PRIMITIVES_GENERATED:
- case PIPE_QUERY_PRIMITIVES_EMITTED:
- len += GEN6_MI_STORE_REGISTER_MEM__SIZE * 2;
- break;
- case PIPE_QUERY_PIPELINE_STATISTICS:
- {
- const int num_regs =
- (ilo_dev_gen(render->dev) >= ILO_GEN(7)) ? 10 : 8;
- const int num_pads =
- (ilo_dev_gen(render->dev) >= ILO_GEN(7)) ? 1 : 3;
-
- len += GEN6_MI_STORE_REGISTER_MEM__SIZE * 2 * num_regs +
- GEN6_MI_STORE_DATA_IMM__SIZE * num_pads;
- }
- break;
- default:
- len = 0;
- break;
- }
-
- return len;
-}
-
-/**
- * Emit PIPE_CONTROLs or MI_STORE_REGISTER_MEMs to store register values.
- */
-void
-ilo_render_emit_query(struct ilo_render *render,
- struct ilo_query *q, uint32_t offset)
-{
- const uint32_t pipeline_statistics_regs[11] = {
- GEN6_REG_IA_VERTICES_COUNT,
- GEN6_REG_IA_PRIMITIVES_COUNT,
- GEN6_REG_VS_INVOCATION_COUNT,
- GEN6_REG_GS_INVOCATION_COUNT,
- GEN6_REG_GS_PRIMITIVES_COUNT,
- GEN6_REG_CL_INVOCATION_COUNT,
- GEN6_REG_CL_PRIMITIVES_COUNT,
- GEN6_REG_PS_INVOCATION_COUNT,
- (ilo_dev_gen(render->dev) >= ILO_GEN(7)) ?
- GEN7_REG_HS_INVOCATION_COUNT : 0,
- (ilo_dev_gen(render->dev) >= ILO_GEN(7)) ?
- GEN7_REG_DS_INVOCATION_COUNT : 0,
- 0,
- };
- const uint32_t primitives_generated_reg =
- (ilo_dev_gen(render->dev) >= ILO_GEN(7) && q->index > 0) ?
- GEN7_REG_SO_PRIM_STORAGE_NEEDED(q->index) :
- GEN6_REG_CL_INVOCATION_COUNT;
- const uint32_t primitives_emitted_reg =
- (ilo_dev_gen(render->dev) >= ILO_GEN(7)) ?
- GEN7_REG_SO_NUM_PRIMS_WRITTEN(q->index) :
- GEN6_REG_SO_NUM_PRIMS_WRITTEN;
- const unsigned batch_used = ilo_builder_batch_used(render->builder);
- const uint32_t *regs;
- int reg_count = 0, i;
- uint32_t pipe_control_dw1 = 0;
-
- ILO_DEV_ASSERT(render->dev, 6, 8);
-
- switch (q->type) {
- case PIPE_QUERY_OCCLUSION_COUNTER:
- case PIPE_QUERY_OCCLUSION_PREDICATE:
- pipe_control_dw1 = GEN6_PIPE_CONTROL_DEPTH_STALL |
- GEN6_PIPE_CONTROL_WRITE_PS_DEPTH_COUNT;
- break;
- case PIPE_QUERY_TIMESTAMP:
- case PIPE_QUERY_TIME_ELAPSED:
- pipe_control_dw1 = GEN6_PIPE_CONTROL_WRITE_TIMESTAMP;
- break;
- case PIPE_QUERY_PRIMITIVES_GENERATED:
- regs = &primitives_generated_reg;
- reg_count = 1;
- break;
- case PIPE_QUERY_PRIMITIVES_EMITTED:
- regs = &primitives_emitted_reg;
- reg_count = 1;
- break;
- case PIPE_QUERY_PIPELINE_STATISTICS:
- regs = pipeline_statistics_regs;
- reg_count = ARRAY_SIZE(pipeline_statistics_regs);
- break;
- default:
- break;
- }
-
- if (pipe_control_dw1) {
- assert(!reg_count);
-
- if (ilo_dev_gen(render->dev) == ILO_GEN(6))
- gen6_wa_pre_pipe_control(render, pipe_control_dw1);
-
- gen6_PIPE_CONTROL(render->builder, pipe_control_dw1, q->bo, offset, 0);
-
- render->state.current_pipe_control_dw1 |= pipe_control_dw1;
- render->state.deferred_pipe_control_dw1 &= ~pipe_control_dw1;
- } else if (reg_count) {
- ilo_render_emit_flush(render);
- }
-
- for (i = 0; i < reg_count; i++) {
- if (regs[i]) {
- /* store lower 32 bits */
- gen6_MI_STORE_REGISTER_MEM(render->builder, regs[i], q->bo, offset);
- /* store higher 32 bits */
- gen6_MI_STORE_REGISTER_MEM(render->builder, regs[i] + 4,
- q->bo, offset + 4);
- } else {
- gen6_MI_STORE_DATA_IMM(render->builder, q->bo, offset, 0);
- }
-
- offset += 8;
- }
-
- assert(ilo_builder_batch_used(render->builder) <= batch_used +
- ilo_render_get_query_len(render, q->type));
-}
-
-int
-ilo_render_get_rectlist_len(const struct ilo_render *render,
- const struct ilo_blitter *blitter)
-{
- ILO_DEV_ASSERT(render->dev, 6, 8);
-
- return ilo_render_get_rectlist_dynamic_states_len(render, blitter) +
- ilo_render_get_rectlist_commands_len(render, blitter);
-}
-
-void
-ilo_render_emit_rectlist(struct ilo_render *render,
- const struct ilo_blitter *blitter)
-{
- struct ilo_render_rectlist_session session;
-
- ILO_DEV_ASSERT(render->dev, 6, 8);
-
- memset(&session, 0, sizeof(session));
- ilo_render_emit_rectlist_dynamic_states(render, blitter, &session);
- ilo_render_emit_rectlist_commands(render, blitter, &session);
-}
-
-int
-ilo_render_get_draw_len(const struct ilo_render *render,
- const struct ilo_state_vector *vec)
-{
- ILO_DEV_ASSERT(render->dev, 6, 8);
-
- return ilo_render_get_draw_dynamic_states_len(render, vec) +
- ilo_render_get_draw_surface_states_len(render, vec) +
- ilo_render_get_draw_commands_len(render, vec);
-}
-
-static void
-draw_session_prepare(struct ilo_render *render,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- memset(session, 0, sizeof(*session));
- session->pipe_dirty = vec->dirty;
- session->reduced_prim = u_reduced_prim(vec->draw->mode);
-
- if (render->hw_ctx_changed) {
- /* these should be enough to make everything uploaded */
- render->batch_bo_changed = true;
- render->state_bo_changed = true;
- render->instruction_bo_changed = true;
-
- session->prim_changed = true;
-
- ilo_state_urb_full_delta(&vec->urb, render->dev, &session->urb_delta);
- ilo_state_vf_full_delta(&vec->ve->vf, render->dev, &session->vf_delta);
-
- ilo_state_raster_full_delta(&vec->rasterizer->rs, render->dev,
- &session->rs_delta);
-
- ilo_state_viewport_full_delta(&vec->viewport.vp, render->dev,
- &session->vp_delta);
-
- ilo_state_cc_full_delta(&vec->blend->cc, render->dev,
- &session->cc_delta);
- } else {
- session->prim_changed =
- (render->state.reduced_prim != session->reduced_prim);
-
- ilo_state_urb_get_delta(&vec->urb, render->dev,
- &render->state.urb, &session->urb_delta);
-
- if (vec->dirty & ILO_DIRTY_VE) {
- ilo_state_vf_full_delta(&vec->ve->vf, render->dev,
- &session->vf_delta);
- }
-
- if (vec->dirty & ILO_DIRTY_RASTERIZER) {
- ilo_state_raster_get_delta(&vec->rasterizer->rs, render->dev,
- &render->state.rs, &session->rs_delta);
- }
-
- if (vec->dirty & ILO_DIRTY_VIEWPORT) {
- ilo_state_viewport_full_delta(&vec->viewport.vp, render->dev,
- &session->vp_delta);
- }
-
- if (vec->dirty & ILO_DIRTY_BLEND) {
- ilo_state_cc_get_delta(&vec->blend->cc, render->dev,
- &render->state.cc, &session->cc_delta);
- }
- }
-}
-
-static void
-draw_session_end(struct ilo_render *render,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- render->hw_ctx_changed = false;
-
- render->batch_bo_changed = false;
- render->state_bo_changed = false;
- render->instruction_bo_changed = false;
-
- render->state.reduced_prim = session->reduced_prim;
-
- render->state.urb = vec->urb;
- render->state.rs = vec->rasterizer->rs;
- render->state.cc = vec->blend->cc;
-}
-
-void
-ilo_render_emit_draw(struct ilo_render *render,
- const struct ilo_state_vector *vec)
-{
- struct ilo_render_draw_session session;
-
- ILO_DEV_ASSERT(render->dev, 6, 8);
-
- draw_session_prepare(render, vec, &session);
-
- /* force all states to be uploaded if the state bo changed */
- if (render->state_bo_changed)
- session.pipe_dirty = ILO_DIRTY_ALL;
- else
- session.pipe_dirty = vec->dirty;
-
- ilo_render_emit_draw_dynamic_states(render, vec, &session);
- ilo_render_emit_draw_surface_states(render, vec, &session);
-
- /* force all commands to be uploaded if the HW context changed */
- if (render->hw_ctx_changed)
- session.pipe_dirty = ILO_DIRTY_ALL;
- else
- session.pipe_dirty = vec->dirty;
-
- ilo_render_emit_draw_commands(render, vec, &session);
-
- draw_session_end(render, vec, &session);
-}
-
-int
-ilo_render_get_launch_grid_len(const struct ilo_render *render,
- const struct ilo_state_vector *vec)
-{
- ILO_DEV_ASSERT(render->dev, 7, 7.5);
-
- return ilo_render_get_launch_grid_surface_states_len(render, vec) +
- ilo_render_get_launch_grid_dynamic_states_len(render, vec) +
- ilo_render_get_launch_grid_commands_len(render, vec);
-}
-
-void
-ilo_render_emit_launch_grid(struct ilo_render *render,
- const struct ilo_state_vector *vec,
- const unsigned thread_group_offset[3],
- const unsigned thread_group_dim[3],
- unsigned thread_group_size,
- const struct pipe_constant_buffer *input,
- uint32_t pc)
-{
- struct ilo_render_launch_grid_session session;
-
- ILO_DEV_ASSERT(render->dev, 7, 7.5);
-
- assert(input->buffer);
-
- memset(&session, 0, sizeof(session));
-
- session.thread_group_offset = thread_group_offset;
- session.thread_group_dim = thread_group_dim;
- session.thread_group_size = thread_group_size;
- session.input = input;
- session.pc = pc;
-
- ilo_render_emit_launch_grid_surface_states(render, vec, &session);
- ilo_render_emit_launch_grid_dynamic_states(render, vec, &session);
- ilo_render_emit_launch_grid_commands(render, vec, &session);
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_RENDER_H
-#define ILO_RENDER_H
-
-#include "ilo_common.h"
-
-struct pipe_constant_buffer;
-struct ilo_blitter;
-struct ilo_builder;
-struct ilo_query;
-struct ilo_render;
-struct ilo_state_vector;
-
-struct ilo_render *
-ilo_render_create(struct ilo_builder *builder);
-
-void
-ilo_render_destroy(struct ilo_render *render);
-
-bool
-ilo_render_prepare_scratch_spaces(struct ilo_render *render,
- int vs_scratch_size,
- int gs_scratch_size,
- int fs_scratch_size);
-
-void
-ilo_render_get_sample_position(const struct ilo_render *render,
- unsigned sample_count,
- unsigned sample_index,
- float *x, float *y);
-
-void
-ilo_render_invalidate_hw(struct ilo_render *render);
-
-void
-ilo_render_invalidate_builder(struct ilo_render *render);
-
-int
-ilo_render_get_flush_len(const struct ilo_render *render);
-
-void
-ilo_render_emit_flush(struct ilo_render *render);
-
-int
-ilo_render_get_query_len(const struct ilo_render *render,
- unsigned query_type);
-
-void
-ilo_render_emit_query(struct ilo_render *render,
- struct ilo_query *q, uint32_t offset);
-
-int
-ilo_render_get_rectlist_len(const struct ilo_render *render,
- const struct ilo_blitter *blitter);
-
-void
-ilo_render_emit_rectlist(struct ilo_render *render,
- const struct ilo_blitter *blitter);
-
-int
-ilo_render_get_draw_len(const struct ilo_render *render,
- const struct ilo_state_vector *vec);
-
-void
-ilo_render_emit_draw(struct ilo_render *render,
- const struct ilo_state_vector *vec);
-
-int
-ilo_render_get_launch_grid_len(const struct ilo_render *render,
- const struct ilo_state_vector *vec);
-
-void
-ilo_render_emit_launch_grid(struct ilo_render *render,
- const struct ilo_state_vector *vec,
- const unsigned thread_group_offset[3],
- const unsigned thread_group_dim[3],
- unsigned thread_group_size,
- const struct pipe_constant_buffer *input,
- uint32_t pc);
-
-#endif /* ILO_RENDER_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "core/ilo_builder_3d.h"
-#include "core/ilo_builder_media.h"
-
-#include "ilo_common.h"
-#include "ilo_blitter.h"
-#include "ilo_shader.h"
-#include "ilo_state.h"
-#include "ilo_render_gen.h"
-
-#define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
-
-static void
-gen6_emit_draw_dynamic_viewports(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- ILO_DEV_ASSERT(r->dev, 6, 6);
-
- /* CLIP_VIEWPORT, SF_VIEWPORT, and CC_VIEWPORT */
- if ((session->vp_delta.dirty & (ILO_STATE_VIEWPORT_SF_CLIP_VIEWPORT |
- ILO_STATE_VIEWPORT_CC_VIEWPORT)) ||
- r->state_bo_changed) {
- r->state.CLIP_VIEWPORT = gen6_CLIP_VIEWPORT(r->builder,
- &vec->viewport.vp);
- r->state.SF_VIEWPORT = gen6_SF_VIEWPORT(r->builder, &vec->viewport.vp);
- r->state.CC_VIEWPORT = gen6_CC_VIEWPORT(r->builder, &vec->viewport.vp);
-
- session->viewport_changed = true;
- }
-}
-
-static void
-gen7_emit_draw_dynamic_viewports(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- ILO_DEV_ASSERT(r->dev, 7, 8);
-
- /* SF_CLIP_VIEWPORT and CC_VIEWPORT */
- if ((session->vp_delta.dirty & (ILO_STATE_VIEWPORT_SF_CLIP_VIEWPORT |
- ILO_STATE_VIEWPORT_CC_VIEWPORT)) ||
- r->state_bo_changed) {
- r->state.SF_CLIP_VIEWPORT = gen7_SF_CLIP_VIEWPORT(r->builder,
- &vec->viewport.vp);
- r->state.CC_VIEWPORT = gen6_CC_VIEWPORT(r->builder, &vec->viewport.vp);
-
- session->viewport_changed = true;
- }
-}
-
-static void
-gen6_emit_draw_dynamic_scissors(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- ILO_DEV_ASSERT(r->dev, 6, 8);
-
- /* SCISSOR_RECT */
- if ((session->vp_delta.dirty & ILO_STATE_VIEWPORT_SCISSOR_RECT) ||
- r->state_bo_changed) {
- r->state.SCISSOR_RECT = gen6_SCISSOR_RECT(r->builder,
- &vec->viewport.vp);
-
- session->scissor_changed = true;
- }
-}
-
-static void
-gen6_emit_draw_dynamic_cc(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- ILO_DEV_ASSERT(r->dev, 6, 8);
-
- /* BLEND_STATE */
- if ((session->cc_delta.dirty & ILO_STATE_CC_BLEND_STATE) ||
- r->state_bo_changed) {
- if (ilo_dev_gen(r->dev) >= ILO_GEN(8))
- r->state.BLEND_STATE = gen8_BLEND_STATE(r->builder, &vec->blend->cc);
- else
- r->state.BLEND_STATE = gen6_BLEND_STATE(r->builder, &vec->blend->cc);
-
- session->blend_changed = true;
- }
-
- /* COLOR_CALC_STATE */
- if ((session->cc_delta.dirty & ILO_STATE_CC_COLOR_CALC_STATE) ||
- r->state_bo_changed) {
- r->state.COLOR_CALC_STATE =
- gen6_COLOR_CALC_STATE(r->builder, &vec->blend->cc);
- session->cc_changed = true;
- }
-
- /* DEPTH_STENCIL_STATE */
- if (ilo_dev_gen(r->dev) < ILO_GEN(8) &&
- ((session->cc_delta.dirty & ILO_STATE_CC_DEPTH_STENCIL_STATE) ||
- r->state_bo_changed)) {
- r->state.DEPTH_STENCIL_STATE =
- gen6_DEPTH_STENCIL_STATE(r->builder, &vec->blend->cc);
- session->dsa_changed = true;
- }
-}
-
-static void
-gen6_emit_draw_dynamic_samplers(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- int shader_type,
- struct ilo_render_draw_session *session)
-{
- const struct ilo_view_cso * const *views =
- (const struct ilo_view_cso **) vec->view[shader_type].states;
- struct ilo_state_sampler samplers[ILO_MAX_SAMPLERS];
- uint32_t *sampler_state, *border_color_state;
- int sampler_count, i;
- bool emit_border_color = false;
- bool skip = false;
-
- ILO_DEV_ASSERT(r->dev, 6, 8);
-
- /* SAMPLER_BORDER_COLOR_STATE and SAMPLER_STATE */
- switch (shader_type) {
- case PIPE_SHADER_VERTEX:
- if (DIRTY(VS) || DIRTY(SAMPLER_VS) || DIRTY(VIEW_VS)) {
- sampler_state = &r->state.vs.SAMPLER_STATE;
- border_color_state = r->state.vs.SAMPLER_BORDER_COLOR_STATE;
-
- if (DIRTY(VS) || DIRTY(SAMPLER_VS))
- emit_border_color = true;
-
- sampler_count = (vec->vs) ? ilo_shader_get_kernel_param(vec->vs,
- ILO_KERNEL_SAMPLER_COUNT) : 0;
-
- session->sampler_vs_changed = true;
- } else {
- skip = true;
- }
- break;
- case PIPE_SHADER_FRAGMENT:
- if (DIRTY(FS) || DIRTY(SAMPLER_FS) || DIRTY(VIEW_FS)) {
- sampler_state = &r->state.wm.SAMPLER_STATE;
- border_color_state = r->state.wm.SAMPLER_BORDER_COLOR_STATE;
-
- if (DIRTY(VS) || DIRTY(SAMPLER_FS))
- emit_border_color = true;
-
- sampler_count = (vec->fs) ? ilo_shader_get_kernel_param(vec->fs,
- ILO_KERNEL_SAMPLER_COUNT) : 0;
-
- session->sampler_fs_changed = true;
- } else {
- skip = true;
- }
- break;
- default:
- skip = true;
- break;
- }
-
- if (skip)
- return;
-
- assert(sampler_count <= ARRAY_SIZE(vec->view[shader_type].states) &&
- sampler_count <= ARRAY_SIZE(vec->sampler[shader_type].cso));
-
- if (emit_border_color) {
- for (i = 0; i < sampler_count; i++) {
- const struct ilo_sampler_cso *cso = vec->sampler[shader_type].cso[i];
-
- border_color_state[i] = (cso) ?
- gen6_SAMPLER_BORDER_COLOR_STATE(r->builder, &cso->border) : 0;
- }
- }
-
- for (i = 0; i < sampler_count; i++) {
- const struct ilo_sampler_cso *cso = vec->sampler[shader_type].cso[i];
-
- if (cso && views[i]) {
- samplers[i] = cso->sampler;
- ilo_state_sampler_set_surface(&samplers[i],
- r->dev, &views[i]->surface);
- } else {
- samplers[i] = vec->disabled_sampler;
- }
- }
-
- *sampler_state = gen6_SAMPLER_STATE(r->builder, samplers,
- border_color_state, sampler_count);
-}
-
-static void
-gen6_emit_draw_dynamic_pcb(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- ILO_DEV_ASSERT(r->dev, 6, 8);
-
- /* push constant buffer for VS */
- if (DIRTY(VS) || DIRTY(CBUF) || DIRTY(CLIP)) {
- const int cbuf0_size = (vec->vs) ?
- ilo_shader_get_kernel_param(vec->vs,
- ILO_KERNEL_PCB_CBUF0_SIZE) : 0;
- const int clip_state_size = (vec->vs) ?
- ilo_shader_get_kernel_param(vec->vs,
- ILO_KERNEL_VS_PCB_UCP_SIZE) : 0;
- const int total_size = cbuf0_size + clip_state_size;
-
- if (total_size) {
- void *pcb;
-
- r->state.vs.PUSH_CONSTANT_BUFFER =
- gen6_push_constant_buffer(r->builder, total_size, &pcb);
- r->state.vs.PUSH_CONSTANT_BUFFER_size = total_size;
-
- if (cbuf0_size) {
- const struct ilo_cbuf_state *cbuf =
- &vec->cbuf[PIPE_SHADER_VERTEX];
-
- if (cbuf0_size <= cbuf->cso[0].info.size) {
- memcpy(pcb, cbuf->cso[0].user_buffer, cbuf0_size);
- } else {
- memcpy(pcb, cbuf->cso[0].user_buffer,
- cbuf->cso[0].info.size);
- memset(pcb + cbuf->cso[0].info.size, 0,
- cbuf0_size - cbuf->cso[0].info.size);
- }
-
- pcb += cbuf0_size;
- }
-
- if (clip_state_size)
- memcpy(pcb, &vec->clip, clip_state_size);
-
- session->pcb_vs_changed = true;
- } else if (r->state.vs.PUSH_CONSTANT_BUFFER_size) {
- r->state.vs.PUSH_CONSTANT_BUFFER = 0;
- r->state.vs.PUSH_CONSTANT_BUFFER_size = 0;
-
- session->pcb_vs_changed = true;
- }
- }
-
- /* push constant buffer for FS */
- if (DIRTY(FS) || DIRTY(CBUF)) {
- const int cbuf0_size = (vec->fs) ?
- ilo_shader_get_kernel_param(vec->fs, ILO_KERNEL_PCB_CBUF0_SIZE) : 0;
-
- if (cbuf0_size) {
- const struct ilo_cbuf_state *cbuf = &vec->cbuf[PIPE_SHADER_FRAGMENT];
- void *pcb;
-
- r->state.wm.PUSH_CONSTANT_BUFFER =
- gen6_push_constant_buffer(r->builder, cbuf0_size, &pcb);
- r->state.wm.PUSH_CONSTANT_BUFFER_size = cbuf0_size;
-
- if (cbuf0_size <= cbuf->cso[0].info.size) {
- memcpy(pcb, cbuf->cso[0].user_buffer, cbuf0_size);
- } else {
- memcpy(pcb, cbuf->cso[0].user_buffer,
- cbuf->cso[0].info.size);
- memset(pcb + cbuf->cso[0].info.size, 0,
- cbuf0_size - cbuf->cso[0].info.size);
- }
-
- session->pcb_fs_changed = true;
- } else if (r->state.wm.PUSH_CONSTANT_BUFFER_size) {
- r->state.wm.PUSH_CONSTANT_BUFFER = 0;
- r->state.wm.PUSH_CONSTANT_BUFFER_size = 0;
-
- session->pcb_fs_changed = true;
- }
- }
-}
-
-#undef DIRTY
-
-int
-ilo_render_get_draw_dynamic_states_len(const struct ilo_render *render,
- const struct ilo_state_vector *vec)
-{
- static int static_len;
- int sh_type, len;
-
- ILO_DEV_ASSERT(render->dev, 6, 8);
-
- if (!static_len) {
- /* 64 bytes, or 16 dwords */
- const int alignment = 64 / 4;
-
- /* pad first */
- len = alignment - 1;
-
- /* CC states */
- len += align(GEN6_BLEND_STATE__SIZE, alignment);
- len += align(GEN6_COLOR_CALC_STATE__SIZE, alignment);
- if (ilo_dev_gen(render->dev) < ILO_GEN(8))
- len += align(GEN6_DEPTH_STENCIL_STATE__SIZE, alignment);
-
- /* viewport arrays */
- if (ilo_dev_gen(render->dev) >= ILO_GEN(7)) {
- len += 15 + /* pad first */
- align(GEN7_SF_CLIP_VIEWPORT__SIZE, 16) +
- align(GEN6_CC_VIEWPORT__SIZE, 8) +
- align(GEN6_SCISSOR_RECT__SIZE, 8);
- } else {
- len += 7 + /* pad first */
- align(GEN6_SF_VIEWPORT__SIZE, 8) +
- align(GEN6_CLIP_VIEWPORT__SIZE, 8) +
- align(GEN6_CC_VIEWPORT__SIZE, 8) +
- align(GEN6_SCISSOR_RECT__SIZE, 8);
- }
-
- static_len = len;
- }
-
- len = static_len;
-
- for (sh_type = 0; sh_type < PIPE_SHADER_TYPES; sh_type++) {
- const int alignment = 32 / 4;
- int num_samplers = 0, pcb_len = 0;
-
- switch (sh_type) {
- case PIPE_SHADER_VERTEX:
- if (vec->vs) {
- num_samplers = ilo_shader_get_kernel_param(vec->vs,
- ILO_KERNEL_SAMPLER_COUNT);
- pcb_len = ilo_shader_get_kernel_param(vec->vs,
- ILO_KERNEL_PCB_CBUF0_SIZE);
- pcb_len += ilo_shader_get_kernel_param(vec->vs,
- ILO_KERNEL_VS_PCB_UCP_SIZE);
- }
- break;
- case PIPE_SHADER_GEOMETRY:
- break;
- case PIPE_SHADER_FRAGMENT:
- if (vec->fs) {
- num_samplers = ilo_shader_get_kernel_param(vec->fs,
- ILO_KERNEL_SAMPLER_COUNT);
- pcb_len = ilo_shader_get_kernel_param(vec->fs,
- ILO_KERNEL_PCB_CBUF0_SIZE);
- }
- break;
- default:
- break;
- }
-
- /* SAMPLER_STATE array and SAMPLER_BORDER_COLORs */
- if (num_samplers) {
- /* prefetches are done in multiples of 4 */
- num_samplers = align(num_samplers, 4);
-
- len += align(GEN6_SAMPLER_STATE__SIZE * num_samplers, alignment);
-
- if (ilo_dev_gen(render->dev) >= ILO_GEN(8)) {
- len += align(GEN6_SAMPLER_BORDER_COLOR_STATE__SIZE, 64 / 4) *
- num_samplers;
- } else {
- len += align(GEN6_SAMPLER_BORDER_COLOR_STATE__SIZE, alignment) *
- num_samplers;
- }
- }
-
- /* PCB */
- if (pcb_len)
- len += align(pcb_len, alignment);
- }
-
- return len;
-}
-
-void
-ilo_render_emit_draw_dynamic_states(struct ilo_render *render,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- const unsigned dynamic_used = ilo_builder_dynamic_used(render->builder);
-
- ILO_DEV_ASSERT(render->dev, 6, 8);
-
- if (ilo_dev_gen(render->dev) >= ILO_GEN(7))
- gen7_emit_draw_dynamic_viewports(render, vec, session);
- else
- gen6_emit_draw_dynamic_viewports(render, vec, session);
-
- gen6_emit_draw_dynamic_cc(render, vec, session);
- gen6_emit_draw_dynamic_scissors(render, vec, session);
- gen6_emit_draw_dynamic_pcb(render, vec, session);
-
- gen6_emit_draw_dynamic_samplers(render, vec,
- PIPE_SHADER_VERTEX, session);
- gen6_emit_draw_dynamic_samplers(render, vec,
- PIPE_SHADER_FRAGMENT, session);
-
- assert(ilo_builder_dynamic_used(render->builder) <= dynamic_used +
- ilo_render_get_draw_dynamic_states_len(render, vec));
-}
-
-int
-ilo_render_get_rectlist_dynamic_states_len(const struct ilo_render *render,
- const struct ilo_blitter *blitter)
-{
- ILO_DEV_ASSERT(render->dev, 6, 8);
-
- return (ilo_dev_gen(render->dev) >= ILO_GEN(8)) ? 0 : 96;
-}
-
-void
-ilo_render_emit_rectlist_dynamic_states(struct ilo_render *render,
- const struct ilo_blitter *blitter,
- struct ilo_render_rectlist_session *session)
-{
- const unsigned dynamic_used = ilo_builder_dynamic_used(render->builder);
-
- ILO_DEV_ASSERT(render->dev, 6, 8);
-
- if (ilo_dev_gen(render->dev) >= ILO_GEN(8))
- return;
-
- /* both are inclusive */
- session->vb_start = gen6_user_vertex_buffer(render->builder,
- sizeof(blitter->vertices), (const void *) blitter->vertices);
- session->vb_end = session->vb_start + sizeof(blitter->vertices) - 1;
-
- if (blitter->uses & ILO_BLITTER_USE_DSA) {
- render->state.DEPTH_STENCIL_STATE =
- gen6_DEPTH_STENCIL_STATE(render->builder, &blitter->cc);
- }
-
- if (blitter->uses & ILO_BLITTER_USE_CC) {
- render->state.COLOR_CALC_STATE =
- gen6_COLOR_CALC_STATE(render->builder, &blitter->cc);
- }
-
- if (blitter->uses & ILO_BLITTER_USE_VIEWPORT) {
- render->state.CC_VIEWPORT =
- gen6_CC_VIEWPORT(render->builder, &blitter->vp);
- }
-
- assert(ilo_builder_dynamic_used(render->builder) <= dynamic_used +
- ilo_render_get_rectlist_dynamic_states_len(render, blitter));
-}
-
-static void
-gen6_emit_launch_grid_dynamic_samplers(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_launch_grid_session *session)
-{
- const unsigned shader_type = PIPE_SHADER_COMPUTE;
- const struct ilo_shader_state *cs = vec->cs;
- const struct ilo_view_cso * const *views =
- (const struct ilo_view_cso **) vec->view[shader_type].states;
- struct ilo_state_sampler samplers[ILO_MAX_SAMPLERS];
- int sampler_count, i;
-
- ILO_DEV_ASSERT(r->dev, 7, 7.5);
-
- sampler_count = ilo_shader_get_kernel_param(cs, ILO_KERNEL_SAMPLER_COUNT);
-
- assert(sampler_count <= ARRAY_SIZE(vec->view[shader_type].states) &&
- sampler_count <= ARRAY_SIZE(vec->sampler[shader_type].cso));
-
- for (i = 0; i < sampler_count; i++) {
- const struct ilo_sampler_cso *cso = vec->sampler[shader_type].cso[i];
-
- r->state.cs.SAMPLER_BORDER_COLOR_STATE[i] = (cso) ?
- gen6_SAMPLER_BORDER_COLOR_STATE(r->builder, &cso->border) : 0;
- }
-
- for (i = 0; i < sampler_count; i++) {
- const struct ilo_sampler_cso *cso = vec->sampler[shader_type].cso[i];
-
- if (cso && views[i]) {
- samplers[i] = cso->sampler;
- ilo_state_sampler_set_surface(&samplers[i],
- r->dev, &views[i]->surface);
- } else {
- samplers[i] = vec->disabled_sampler;
- }
- }
-
- r->state.cs.SAMPLER_STATE = gen6_SAMPLER_STATE(r->builder, samplers,
- r->state.cs.SAMPLER_BORDER_COLOR_STATE, sampler_count);
-}
-
-static void
-gen6_emit_launch_grid_dynamic_pcb(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_launch_grid_session *session)
-{
- r->state.cs.PUSH_CONSTANT_BUFFER = 0;
- r->state.cs.PUSH_CONSTANT_BUFFER_size = 0;
-}
-
-static void
-gen6_emit_launch_grid_dynamic_idrt(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_launch_grid_session *session)
-{
- const struct ilo_shader_state *cs = vec->cs;
- struct ilo_state_compute_interface_info interface;
- struct ilo_state_compute_info info;
- uint32_t kernel_offset;
-
- ILO_DEV_ASSERT(r->dev, 7, 7.5);
-
- memset(&interface, 0, sizeof(interface));
-
- interface.sampler_count =
- ilo_shader_get_kernel_param(cs, ILO_KERNEL_SAMPLER_COUNT);
- interface.surface_count =
- ilo_shader_get_kernel_param(cs, ILO_KERNEL_SURFACE_TOTAL_COUNT);
- interface.thread_group_size = session->thread_group_size;
- interface.slm_size =
- ilo_shader_get_kernel_param(cs, ILO_KERNEL_CS_LOCAL_SIZE);
- interface.curbe_read_length = r->state.cs.PUSH_CONSTANT_BUFFER_size;
-
- memset(&info, 0, sizeof(info));
- info.data = session->compute_data;
- info.data_size = sizeof(session->compute_data);
- info.interfaces = &interface;
- info.interface_count = 1;
- info.cv_urb_alloc_size = r->dev->urb_size;
- info.curbe_alloc_size = r->state.cs.PUSH_CONSTANT_BUFFER_size;
-
- ilo_state_compute_init(&session->compute, r->dev, &info);
-
- kernel_offset = ilo_shader_get_kernel_offset(cs);
-
- session->idrt = gen6_INTERFACE_DESCRIPTOR_DATA(r->builder,
- &session->compute, &kernel_offset,
- &r->state.cs.SAMPLER_STATE, &r->state.cs.BINDING_TABLE_STATE);
-
- session->idrt_size = 32;
-}
-
-int
-ilo_render_get_launch_grid_dynamic_states_len(const struct ilo_render *render,
- const struct ilo_state_vector *vec)
-{
- const int alignment = 32 / 4;
- int num_samplers;
- int len = 0;
-
- ILO_DEV_ASSERT(render->dev, 7, 7.5);
-
- num_samplers = ilo_shader_get_kernel_param(vec->cs,
- ILO_KERNEL_SAMPLER_COUNT);
-
- /* SAMPLER_STATE array and SAMPLER_BORDER_COLORs */
- if (num_samplers) {
- /* prefetches are done in multiples of 4 */
- num_samplers = align(num_samplers, 4);
-
- len += align(GEN6_SAMPLER_STATE__SIZE * num_samplers, alignment) +
- align(GEN6_SAMPLER_BORDER_COLOR_STATE__SIZE, alignment) *
- num_samplers;
- }
-
- len += GEN6_INTERFACE_DESCRIPTOR_DATA__SIZE;
-
- return len;
-}
-
-void
-ilo_render_emit_launch_grid_dynamic_states(struct ilo_render *render,
- const struct ilo_state_vector *vec,
- struct ilo_render_launch_grid_session *session)
-{
- const unsigned dynamic_used = ilo_builder_dynamic_used(render->builder);
-
- ILO_DEV_ASSERT(render->dev, 7, 7.5);
-
- gen6_emit_launch_grid_dynamic_samplers(render, vec, session);
- gen6_emit_launch_grid_dynamic_pcb(render, vec, session);
- gen6_emit_launch_grid_dynamic_idrt(render, vec, session);
-
- assert(ilo_builder_dynamic_used(render->builder) <= dynamic_used +
- ilo_render_get_launch_grid_dynamic_states_len(render, vec));
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_RENDER_GEN_H
-#define ILO_RENDER_GEN_H
-
-#include "core/ilo_builder.h"
-#include "core/ilo_builder_3d.h"
-#include "core/ilo_builder_render.h"
-#include "core/ilo_state_raster.h"
-
-#include "ilo_common.h"
-#include "ilo_state.h"
-#include "ilo_render.h"
-
-struct ilo_bo;
-struct ilo_blitter;
-struct ilo_render;
-struct ilo_state_vector;
-
-/**
- * Render Engine.
- */
-struct ilo_render {
- const struct ilo_dev *dev;
- struct ilo_builder *builder;
-
- struct intel_bo *workaround_bo;
-
- struct ilo_render_scratch_space {
- struct intel_bo *bo;
- int size;
- } vs_scratch, gs_scratch, fs_scratch;
-
- struct ilo_state_sample_pattern sample_pattern;
-
- bool hw_ctx_changed;
-
- /*
- * Any state that involves resources needs to be re-emitted when the
- * batch bo changed. This is because we do not pin the resources and
- * their offsets (or existence) may change between batch buffers.
- */
- bool batch_bo_changed;
- bool state_bo_changed;
- bool instruction_bo_changed;
-
- /**
- * HW states.
- */
- struct ilo_render_state {
- /*
- * When a WA is needed before some command, we always emit the WA right
- * before the command. Knowing what have already been done since last
- * 3DPRIMITIVE allows us to skip some WAs.
- */
- uint32_t current_pipe_control_dw1;
-
- /*
- * When a WA is needed after some command, we may have the WA follow the
- * command immediately or defer it. If this is non-zero, a PIPE_CONTROL
- * will be emitted before 3DPRIMITIVE.
- */
- uint32_t deferred_pipe_control_dw1;
-
- int reduced_prim;
- int so_max_vertices;
-
- struct ilo_state_urb urb;
- struct ilo_state_raster rs;
- struct ilo_state_cc cc;
-
- uint32_t SF_VIEWPORT;
- uint32_t CLIP_VIEWPORT;
- uint32_t SF_CLIP_VIEWPORT; /* GEN7+ */
- uint32_t CC_VIEWPORT;
-
- uint32_t COLOR_CALC_STATE;
- uint32_t BLEND_STATE;
- uint32_t DEPTH_STENCIL_STATE;
-
- uint32_t SCISSOR_RECT;
-
- struct {
- uint32_t BINDING_TABLE_STATE;
- uint32_t SURFACE_STATE[ILO_MAX_SURFACES];
- uint32_t SAMPLER_STATE;
- uint32_t SAMPLER_BORDER_COLOR_STATE[ILO_MAX_SAMPLERS];
- uint32_t PUSH_CONSTANT_BUFFER;
- int PUSH_CONSTANT_BUFFER_size;
- } vs;
-
- struct {
- uint32_t BINDING_TABLE_STATE;
- uint32_t SURFACE_STATE[ILO_MAX_SURFACES];
- bool active;
- } gs;
-
- struct {
- uint32_t BINDING_TABLE_STATE;
- uint32_t SURFACE_STATE[ILO_MAX_SURFACES];
- uint32_t SAMPLER_STATE;
- uint32_t SAMPLER_BORDER_COLOR_STATE[ILO_MAX_SAMPLERS];
- uint32_t PUSH_CONSTANT_BUFFER;
- int PUSH_CONSTANT_BUFFER_size;
- } wm;
-
- struct {
- uint32_t BINDING_TABLE_STATE;
- uint32_t SURFACE_STATE[ILO_MAX_SURFACES];
- uint32_t SAMPLER_STATE;
- uint32_t SAMPLER_BORDER_COLOR_STATE[ILO_MAX_SAMPLERS];
- uint32_t PUSH_CONSTANT_BUFFER;
- int PUSH_CONSTANT_BUFFER_size;
- } cs;
- } state;
-};
-
-struct ilo_render_draw_session {
- uint32_t pipe_dirty;
-
- /* commands */
- int reduced_prim;
-
- bool prim_changed;
-
- struct ilo_state_urb_delta urb_delta;
- struct ilo_state_vf_delta vf_delta;
- struct ilo_state_raster_delta rs_delta;
- struct ilo_state_viewport_delta vp_delta;
- struct ilo_state_cc_delta cc_delta;
-
- /* dynamic states */
- bool viewport_changed;
- bool scissor_changed;
-
- bool cc_changed;
- bool dsa_changed;
- bool blend_changed;
-
- bool sampler_vs_changed;
- bool sampler_gs_changed;
- bool sampler_fs_changed;
-
- bool pcb_vs_changed;
- bool pcb_gs_changed;
- bool pcb_fs_changed;
-
- /* surface states */
- bool binding_table_vs_changed;
- bool binding_table_gs_changed;
- bool binding_table_fs_changed;
-};
-
-struct ilo_render_rectlist_session {
- uint32_t vb_start;
- uint32_t vb_end;
-};
-
-struct ilo_render_launch_grid_session {
- const unsigned *thread_group_offset;
- const unsigned *thread_group_dim;
- unsigned thread_group_size;
- const struct pipe_constant_buffer *input;
- uint32_t pc;
-
- uint32_t idrt;
- int idrt_size;
-
- uint32_t compute_data[6];
- struct ilo_state_compute compute;
-};
-
-int
-ilo_render_get_draw_commands_len_gen6(const struct ilo_render *render,
- const struct ilo_state_vector *vec);
-
-int
-ilo_render_get_draw_commands_len_gen7(const struct ilo_render *render,
- const struct ilo_state_vector *vec);
-
-int
-ilo_render_get_draw_commands_len_gen8(const struct ilo_render *render,
- const struct ilo_state_vector *vec);
-
-static inline int
-ilo_render_get_draw_commands_len(const struct ilo_render *render,
- const struct ilo_state_vector *vec)
-{
- if (ilo_dev_gen(render->dev) >= ILO_GEN(8))
- return ilo_render_get_draw_commands_len_gen8(render, vec);
- else if (ilo_dev_gen(render->dev) >= ILO_GEN(7))
- return ilo_render_get_draw_commands_len_gen7(render, vec);
- else
- return ilo_render_get_draw_commands_len_gen6(render, vec);
-}
-
-void
-ilo_render_emit_draw_commands_gen6(struct ilo_render *render,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session);
-
-void
-ilo_render_emit_draw_commands_gen7(struct ilo_render *render,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session);
-
-void
-ilo_render_emit_draw_commands_gen8(struct ilo_render *render,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session);
-
-static inline void
-ilo_render_emit_draw_commands(struct ilo_render *render,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- const unsigned batch_used = ilo_builder_batch_used(render->builder);
-
- if (ilo_dev_gen(render->dev) >= ILO_GEN(8))
- ilo_render_emit_draw_commands_gen8(render, vec, session);
- else if (ilo_dev_gen(render->dev) >= ILO_GEN(7))
- ilo_render_emit_draw_commands_gen7(render, vec, session);
- else
- ilo_render_emit_draw_commands_gen6(render, vec, session);
-
- assert(ilo_builder_batch_used(render->builder) <= batch_used +
- ilo_render_get_draw_commands_len(render, vec));
-}
-
-int
-ilo_render_get_rectlist_commands_len_gen6(const struct ilo_render *render,
- const struct ilo_blitter *blitter);
-
-int
-ilo_render_get_rectlist_commands_len_gen8(const struct ilo_render *render,
- const struct ilo_blitter *blitter);
-
-static inline int
-ilo_render_get_rectlist_commands_len(const struct ilo_render *render,
- const struct ilo_blitter *blitter)
-{
- if (ilo_dev_gen(render->dev) >= ILO_GEN(8))
- return ilo_render_get_rectlist_commands_len_gen8(render, blitter);
- else
- return ilo_render_get_rectlist_commands_len_gen6(render, blitter);
-}
-
-void
-ilo_render_emit_rectlist_commands_gen6(struct ilo_render *r,
- const struct ilo_blitter *blitter,
- const struct ilo_render_rectlist_session *session);
-
-void
-ilo_render_emit_rectlist_commands_gen7(struct ilo_render *r,
- const struct ilo_blitter *blitter,
- const struct ilo_render_rectlist_session *session);
-
-void
-ilo_render_emit_rectlist_commands_gen8(struct ilo_render *r,
- const struct ilo_blitter *blitter,
- const struct ilo_render_rectlist_session *session);
-
-static inline void
-ilo_render_emit_rectlist_commands(struct ilo_render *render,
- const struct ilo_blitter *blitter,
- const struct ilo_render_rectlist_session *session)
-{
- const unsigned batch_used = ilo_builder_batch_used(render->builder);
-
- if (ilo_dev_gen(render->dev) >= ILO_GEN(8))
- ilo_render_emit_rectlist_commands_gen8(render, blitter, session);
- else if (ilo_dev_gen(render->dev) >= ILO_GEN(7))
- ilo_render_emit_rectlist_commands_gen7(render, blitter, session);
- else
- ilo_render_emit_rectlist_commands_gen6(render, blitter, session);
-
- assert(ilo_builder_batch_used(render->builder) <= batch_used +
- ilo_render_get_rectlist_commands_len(render, blitter));
-}
-
-int
-ilo_render_get_launch_grid_commands_len(const struct ilo_render *render,
- const struct ilo_state_vector *vec);
-
-void
-ilo_render_emit_launch_grid_commands(struct ilo_render *render,
- const struct ilo_state_vector *vec,
- const struct ilo_render_launch_grid_session *session);
-
-int
-ilo_render_get_draw_dynamic_states_len(const struct ilo_render *render,
- const struct ilo_state_vector *vec);
-
-void
-ilo_render_emit_draw_dynamic_states(struct ilo_render *render,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session);
-
-int
-ilo_render_get_rectlist_dynamic_states_len(const struct ilo_render *render,
- const struct ilo_blitter *blitter);
-
-void
-ilo_render_emit_rectlist_dynamic_states(struct ilo_render *render,
- const struct ilo_blitter *blitter,
- struct ilo_render_rectlist_session *session);
-
-int
-ilo_render_get_launch_grid_dynamic_states_len(const struct ilo_render *render,
- const struct ilo_state_vector *vec);
-
-void
-ilo_render_emit_launch_grid_dynamic_states(struct ilo_render *render,
- const struct ilo_state_vector *vec,
- struct ilo_render_launch_grid_session *session);
-
-int
-ilo_render_get_draw_surface_states_len(const struct ilo_render *render,
- const struct ilo_state_vector *vec);
-
-void
-ilo_render_emit_draw_surface_states(struct ilo_render *render,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session);
-
-int
-ilo_render_get_launch_grid_surface_states_len(const struct ilo_render *render,
- const struct ilo_state_vector *vec);
-
-void
-ilo_render_emit_launch_grid_surface_states(struct ilo_render *render,
- const struct ilo_state_vector *vec,
- struct ilo_render_launch_grid_session *session);
-
-/**
- * A convenient wrapper for gen6_PIPE_CONTROL(). This should be enough for
- * our needs everywhere except for queries.
- */
-static inline void
-ilo_render_pipe_control(struct ilo_render *r, uint32_t dw1)
-{
- const uint32_t write_mask = (dw1 & GEN6_PIPE_CONTROL_WRITE__MASK);
- struct intel_bo *bo = (write_mask) ? r->workaround_bo : NULL;
-
- ILO_DEV_ASSERT(r->dev, 6, 8);
-
- if (write_mask)
- assert(write_mask == GEN6_PIPE_CONTROL_WRITE_IMM);
-
- if (dw1 & GEN6_PIPE_CONTROL_CS_STALL) {
- /* CS stall cannot be set alone */
- const uint32_t mask = GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH |
- GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL |
- GEN6_PIPE_CONTROL_DEPTH_STALL |
- GEN6_PIPE_CONTROL_WRITE__MASK;
- if (!(dw1 & mask))
- dw1 |= GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL;
- }
-
- gen6_PIPE_CONTROL(r->builder, dw1, bo, 0, 0);
-
- r->state.current_pipe_control_dw1 |= dw1;
- r->state.deferred_pipe_control_dw1 &= ~dw1;
-}
-
-/**
- * A convenient wrapper for gen{6,7}_3DPRIMITIVE().
- */
-static inline void
-ilo_render_3dprimitive(struct ilo_render *r,
- const struct gen6_3dprimitive_info *info)
-{
- ILO_DEV_ASSERT(r->dev, 6, 8);
-
- if (r->state.deferred_pipe_control_dw1)
- ilo_render_pipe_control(r, r->state.deferred_pipe_control_dw1);
-
- /* 3DPRIMITIVE */
- if (ilo_dev_gen(r->dev) >= ILO_GEN(7))
- gen7_3DPRIMITIVE(r->builder, info);
- else
- gen6_3DPRIMITIVE(r->builder, info);
-
- r->state.current_pipe_control_dw1 = 0;
- assert(!r->state.deferred_pipe_control_dw1);
-}
-
-void
-gen6_wa_pre_pipe_control(struct ilo_render *r, uint32_t dw1);
-
-void
-gen6_draw_common_select(struct ilo_render *r,
- const struct ilo_state_vector *ilo,
- struct ilo_render_draw_session *session);
-
-void
-gen6_draw_common_sip(struct ilo_render *r,
- const struct ilo_state_vector *ilo,
- struct ilo_render_draw_session *session);
-
-void
-gen6_draw_common_base_address(struct ilo_render *r,
- const struct ilo_state_vector *ilo,
- struct ilo_render_draw_session *session);
-
-void
-gen6_draw_vf(struct ilo_render *r,
- const struct ilo_state_vector *ilo,
- struct ilo_render_draw_session *session);
-
-void
-gen6_draw_vf_statistics(struct ilo_render *r,
- const struct ilo_state_vector *ilo,
- struct ilo_render_draw_session *session);
-
-void
-gen6_draw_vs(struct ilo_render *r,
- const struct ilo_state_vector *ilo,
- struct ilo_render_draw_session *session);
-
-void
-gen6_draw_clip(struct ilo_render *r,
- const struct ilo_state_vector *ilo,
- struct ilo_render_draw_session *session);
-
-void
-gen6_draw_sf_rect(struct ilo_render *r,
- const struct ilo_state_vector *ilo,
- struct ilo_render_draw_session *session);
-
-void
-gen6_draw_wm_raster(struct ilo_render *r,
- const struct ilo_state_vector *ilo,
- struct ilo_render_draw_session *session);
-
-void
-gen7_draw_common_pcb_alloc(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session);
-
-void
-gen7_draw_common_pointers_1(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session);
-
-void
-gen7_draw_common_urb(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session);
-
-void
-gen7_draw_common_pointers_2(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session);
-
-void
-gen7_draw_vs(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session);
-
-void
-gen7_draw_ds(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session);
-
-void
-gen7_draw_te(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session);
-
-void
-gen7_draw_hs(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session);
-
-void
-gen7_draw_gs(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session);
-
-void
-gen7_draw_sol(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session);
-
-#endif /* ILO_RENDER_GEN_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "genhw/genhw.h"
-#include "core/ilo_builder_3d.h"
-#include "core/ilo_builder_mi.h"
-#include "core/ilo_builder_render.h"
-#include "util/u_prim.h"
-
-#include "ilo_blitter.h"
-#include "ilo_query.h"
-#include "ilo_resource.h"
-#include "ilo_shader.h"
-#include "ilo_state.h"
-#include "ilo_render_gen.h"
-
-/**
- * This should be called before PIPE_CONTROL.
- */
-void
-gen6_wa_pre_pipe_control(struct ilo_render *r, uint32_t dw1)
-{
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 60:
- *
- * "Pipe-control with CS-stall bit set must be sent BEFORE the
- * pipe-control with a post-sync op and no write-cache flushes."
- *
- * This WA may also be triggered indirectly by the other two WAs on the
- * same page:
- *
- * "Before any depth stall flush (including those produced by
- * non-pipelined state commands), software needs to first send a
- * PIPE_CONTROL with no bits set except Post-Sync Operation != 0."
- *
- * "Before a PIPE_CONTROL with Write Cache Flush Enable =1, a
- * PIPE_CONTROL with any non-zero post-sync-op is required."
- */
- const bool direct_wa_cond = (dw1 & GEN6_PIPE_CONTROL_WRITE__MASK) &&
- !(dw1 & GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH);
- const bool indirect_wa_cond = (dw1 & GEN6_PIPE_CONTROL_DEPTH_STALL) |
- (dw1 & GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH);
-
- ILO_DEV_ASSERT(r->dev, 6, 6);
-
- if (!direct_wa_cond && !indirect_wa_cond)
- return;
-
- if (!(r->state.current_pipe_control_dw1 & GEN6_PIPE_CONTROL_CS_STALL)) {
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 73:
- *
- * "1 of the following must also be set (when CS stall is set):
- *
- * - Depth Cache Flush Enable ([0] of DW1)
- * - Stall at Pixel Scoreboard ([1] of DW1)
- * - Depth Stall ([13] of DW1)
- * - Post-Sync Operation ([13] of DW1)
- * - Render Target Cache Flush Enable ([12] of DW1)
- * - Notify Enable ([8] of DW1)"
- *
- * Because of the WAs above, we have to pick Stall at Pixel Scoreboard.
- */
- const uint32_t direct_wa = GEN6_PIPE_CONTROL_CS_STALL |
- GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL;
-
- ilo_render_pipe_control(r, direct_wa);
- }
-
- if (indirect_wa_cond &&
- !(r->state.current_pipe_control_dw1 & GEN6_PIPE_CONTROL_WRITE__MASK)) {
- const uint32_t indirect_wa = GEN6_PIPE_CONTROL_WRITE_IMM;
-
- ilo_render_pipe_control(r, indirect_wa);
- }
-}
-
-/**
- * This should be called before any non-pipelined state command.
- */
-static void
-gen6_wa_pre_non_pipelined(struct ilo_render *r)
-{
- ILO_DEV_ASSERT(r->dev, 6, 6);
-
- /* non-pipelined state commands produce depth stall */
- gen6_wa_pre_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
-}
-
-static void
-gen6_wa_post_3dstate_urb_no_gs(struct ilo_render *r)
-{
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 27:
- *
- * "Because of a urb corruption caused by allocating a previous
- * gsunit's urb entry to vsunit software is required to send a
- * "GS NULL Fence" (Send URB fence with VS URB size == 1 and GS URB
- * size == 0) plus a dummy DRAW call before any case where VS will
- * be taking over GS URB space."
- */
- const uint32_t dw1 = GEN6_PIPE_CONTROL_CS_STALL;
-
- if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
- gen6_wa_pre_pipe_control(r, dw1);
- if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
- ilo_render_pipe_control(r, dw1);
-}
-
-static void
-gen6_wa_post_3dstate_constant_vs(struct ilo_render *r)
-{
- /*
- * According to upload_vs_state() of the classic driver, we need to emit a
- * PIPE_CONTROL after 3DSTATE_CONSTANT_VS, otherwise the command is kept
- * being buffered by VS FF, to the point that the FF dies.
- */
- const uint32_t dw1 = GEN6_PIPE_CONTROL_DEPTH_STALL |
- GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE |
- GEN6_PIPE_CONTROL_STATE_CACHE_INVALIDATE;
-
- if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
- gen6_wa_pre_pipe_control(r, dw1);
- if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
- ilo_render_pipe_control(r, dw1);
-}
-
-static void
-gen6_wa_pre_3dstate_vs_toggle(struct ilo_render *r)
-{
- /*
- * The classic driver has this undocumented WA:
- *
- * From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
- * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
- *
- * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
- * command that causes the VS Function Enable to toggle. Pipeline
- * flush can be executed by sending a PIPE_CONTROL command with CS
- * stall bit set and a post sync operation.
- */
- const uint32_t dw1 = GEN6_PIPE_CONTROL_WRITE_IMM |
- GEN6_PIPE_CONTROL_CS_STALL;
-
- if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
- gen6_wa_pre_pipe_control(r, dw1);
- if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
- ilo_render_pipe_control(r, dw1);
-}
-
-static void
-gen6_wa_pre_3dstate_wm_max_threads(struct ilo_render *r)
-{
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 274:
- *
- * "A PIPE_CONTROL command, with only the Stall At Pixel Scoreboard
- * field set (DW1 Bit 1), must be issued prior to any change to the
- * value in this field (Maximum Number of Threads in 3DSTATE_WM)"
- */
- const uint32_t dw1 = GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL;
-
- ILO_DEV_ASSERT(r->dev, 6, 6);
-
- if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
- gen6_wa_pre_pipe_control(r, dw1);
- if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
- ilo_render_pipe_control(r, dw1);
-}
-
-static void
-gen6_wa_pre_3dstate_multisample(struct ilo_render *r)
-{
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 305:
- *
- * "Driver must guarentee that all the caches in the depth pipe are
- * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
- * requires driver to send a PIPE_CONTROL with a CS stall along with a
- * Depth Flush prior to this command."
- */
- const uint32_t dw1 = GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- GEN6_PIPE_CONTROL_CS_STALL;
-
- ILO_DEV_ASSERT(r->dev, 6, 6);
-
- if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
- gen6_wa_pre_pipe_control(r, dw1);
- if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
- ilo_render_pipe_control(r, dw1);
-}
-
-static void
-gen6_wa_pre_depth(struct ilo_render *r)
-{
- ILO_DEV_ASSERT(r->dev, 6, 6);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 315:
- *
- * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
- * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
- * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
- * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
- * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
- * Depth Flush Bit set, followed by another pipelined depth stall
- * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
- * guarantee that the pipeline from WM onwards is already flushed
- * (e.g., via a preceding MI_FLUSH)."
- *
- * According to the classic driver, it also applies for GEN6.
- */
- gen6_wa_pre_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL |
- GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH);
-
- ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
- ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH);
- ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
-}
-
-#define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
-
-void
-gen6_draw_common_select(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* PIPELINE_SELECT */
- if (r->hw_ctx_changed) {
- if (ilo_dev_gen(r->dev) == ILO_GEN(6))
- gen6_wa_pre_non_pipelined(r);
-
- gen6_PIPELINE_SELECT(r->builder, 0x0);
- }
-}
-
-void
-gen6_draw_common_sip(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* STATE_SIP */
- if (r->hw_ctx_changed) {
- if (ilo_dev_gen(r->dev) == ILO_GEN(6))
- gen6_wa_pre_non_pipelined(r);
-
- gen6_STATE_SIP(r->builder, 0);
- }
-}
-
-void
-gen6_draw_common_base_address(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* STATE_BASE_ADDRESS */
- if (r->state_bo_changed || r->instruction_bo_changed ||
- r->batch_bo_changed) {
- if (ilo_dev_gen(r->dev) == ILO_GEN(6))
- gen6_wa_pre_non_pipelined(r);
-
- if (ilo_dev_gen(r->dev) >= ILO_GEN(8))
- gen8_state_base_address(r->builder, r->hw_ctx_changed);
- else
- gen6_state_base_address(r->builder, r->hw_ctx_changed);
-
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 28:
- *
- * "The following commands must be reissued following any change to
- * the base addresses:
- *
- * * 3DSTATE_BINDING_TABLE_POINTERS
- * * 3DSTATE_SAMPLER_STATE_POINTERS
- * * 3DSTATE_VIEWPORT_STATE_POINTERS
- * * 3DSTATE_CC_POINTERS
- * * MEDIA_STATE_POINTERS"
- *
- * 3DSTATE_SCISSOR_STATE_POINTERS is not on the list, but it is
- * reasonable to also reissue the command. Same to PCB.
- */
- session->viewport_changed = true;
-
- session->scissor_changed = true;
-
- session->blend_changed = true;
- session->dsa_changed = true;
- session->cc_changed = true;
-
- session->sampler_vs_changed = true;
- session->sampler_gs_changed = true;
- session->sampler_fs_changed = true;
-
- session->pcb_vs_changed = true;
- session->pcb_gs_changed = true;
- session->pcb_fs_changed = true;
-
- session->binding_table_vs_changed = true;
- session->binding_table_gs_changed = true;
- session->binding_table_fs_changed = true;
- }
-}
-
-static void
-gen6_draw_common_urb(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- const bool gs_active = (vec->gs || (vec->vs &&
- ilo_shader_get_kernel_param(vec->vs, ILO_KERNEL_VS_GEN6_SO)));
-
- /* 3DSTATE_URB */
- if (session->urb_delta.dirty & (ILO_STATE_URB_3DSTATE_URB_VS |
- ILO_STATE_URB_3DSTATE_URB_GS)) {
- gen6_3DSTATE_URB(r->builder, &vec->urb);
-
- if (r->state.gs.active && !gs_active)
- gen6_wa_post_3dstate_urb_no_gs(r);
- }
-
- r->state.gs.active = gs_active;
-}
-
-static void
-gen6_draw_common_pointers_1(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_VIEWPORT_STATE_POINTERS */
- if (session->viewport_changed) {
- gen6_3DSTATE_VIEWPORT_STATE_POINTERS(r->builder,
- r->state.CLIP_VIEWPORT,
- r->state.SF_VIEWPORT,
- r->state.CC_VIEWPORT);
- }
-}
-
-static void
-gen6_draw_common_pointers_2(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_CC_STATE_POINTERS */
- if (session->blend_changed ||
- session->dsa_changed ||
- session->cc_changed) {
- gen6_3DSTATE_CC_STATE_POINTERS(r->builder,
- r->state.BLEND_STATE,
- r->state.DEPTH_STENCIL_STATE,
- r->state.COLOR_CALC_STATE);
- }
-
- /* 3DSTATE_SAMPLER_STATE_POINTERS */
- if (session->sampler_vs_changed ||
- session->sampler_gs_changed ||
- session->sampler_fs_changed) {
- gen6_3DSTATE_SAMPLER_STATE_POINTERS(r->builder,
- r->state.vs.SAMPLER_STATE,
- 0,
- r->state.wm.SAMPLER_STATE);
- }
-}
-
-static void
-gen6_draw_common_pointers_3(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_SCISSOR_STATE_POINTERS */
- if (session->scissor_changed) {
- gen6_3DSTATE_SCISSOR_STATE_POINTERS(r->builder,
- r->state.SCISSOR_RECT);
- }
-
- /* 3DSTATE_BINDING_TABLE_POINTERS */
- if (session->binding_table_vs_changed ||
- session->binding_table_gs_changed ||
- session->binding_table_fs_changed) {
- gen6_3DSTATE_BINDING_TABLE_POINTERS(r->builder,
- r->state.vs.BINDING_TABLE_STATE,
- r->state.gs.BINDING_TABLE_STATE,
- r->state.wm.BINDING_TABLE_STATE);
- }
-}
-
-void
-gen6_draw_vf(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- if (ilo_dev_gen(r->dev) >= ILO_GEN(7.5)) {
- /* 3DSTATE_INDEX_BUFFER */
- if ((session->vf_delta.dirty & ILO_STATE_VF_3DSTATE_INDEX_BUFFER) ||
- DIRTY(IB) || r->batch_bo_changed)
- gen6_3DSTATE_INDEX_BUFFER(r->builder, &vec->ve->vf, &vec->ib.ib);
-
- /* 3DSTATE_VF */
- if (session->vf_delta.dirty & ILO_STATE_VF_3DSTATE_VF)
- gen75_3DSTATE_VF(r->builder, &vec->ve->vf);
- } else {
- /* 3DSTATE_INDEX_BUFFER */
- if ((session->vf_delta.dirty & ILO_STATE_VF_3DSTATE_INDEX_BUFFER) ||
- DIRTY(IB) || r->batch_bo_changed)
- gen6_3DSTATE_INDEX_BUFFER(r->builder, &vec->ve->vf, &vec->ib.ib);
- }
-
- /* 3DSTATE_VERTEX_BUFFERS */
- if ((session->vf_delta.dirty & ILO_STATE_VF_3DSTATE_VERTEX_BUFFERS) ||
- DIRTY(VB) || DIRTY(VE) || r->batch_bo_changed) {
- gen6_3DSTATE_VERTEX_BUFFERS(r->builder, &vec->ve->vf,
- vec->vb.vb, vec->ve->vb_count);
- }
-
- /* 3DSTATE_VERTEX_ELEMENTS */
- if (session->vf_delta.dirty & ILO_STATE_VF_3DSTATE_VERTEX_ELEMENTS)
- gen6_3DSTATE_VERTEX_ELEMENTS(r->builder, &vec->ve->vf);
-}
-
-void
-gen6_draw_vf_statistics(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_VF_STATISTICS */
- if (r->hw_ctx_changed)
- gen6_3DSTATE_VF_STATISTICS(r->builder, false);
-}
-
-void
-gen6_draw_vs(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_CONSTANT_VS */
- if (session->pcb_vs_changed) {
- gen6_3DSTATE_CONSTANT_VS(r->builder,
- &r->state.vs.PUSH_CONSTANT_BUFFER,
- &r->state.vs.PUSH_CONSTANT_BUFFER_size,
- 1);
-
- if (ilo_dev_gen(r->dev) == ILO_GEN(6))
- gen6_wa_post_3dstate_constant_vs(r);
- }
-
- /* 3DSTATE_VS */
- if (DIRTY(VS) || r->instruction_bo_changed) {
- const union ilo_shader_cso *cso = ilo_shader_get_kernel_cso(vec->vs);
- const uint32_t kernel_offset = ilo_shader_get_kernel_offset(vec->vs);
-
- if (ilo_dev_gen(r->dev) == ILO_GEN(6))
- gen6_wa_pre_3dstate_vs_toggle(r);
-
- if (ilo_dev_gen(r->dev) == ILO_GEN(6) &&
- ilo_shader_get_kernel_param(vec->vs, ILO_KERNEL_VS_GEN6_SO)) {
- gen6_3DSTATE_VS(r->builder, &cso->vs_sol.vs,
- kernel_offset, r->vs_scratch.bo);
- } else {
- gen6_3DSTATE_VS(r->builder, &cso->vs,
- kernel_offset, r->vs_scratch.bo);
- }
- }
-}
-
-static void
-gen6_draw_gs(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_CONSTANT_GS */
- if (session->pcb_gs_changed)
- gen6_3DSTATE_CONSTANT_GS(r->builder, NULL, NULL, 0);
-
- /* 3DSTATE_GS */
- if (DIRTY(GS) || DIRTY(VS) ||
- session->prim_changed || r->instruction_bo_changed) {
- const union ilo_shader_cso *cso;
- uint32_t kernel_offset;
-
- if (vec->gs) {
- cso = ilo_shader_get_kernel_cso(vec->gs);
- kernel_offset = ilo_shader_get_kernel_offset(vec->gs);
-
- gen6_3DSTATE_GS(r->builder, &cso->gs,
- kernel_offset, r->gs_scratch.bo);
- } else if (ilo_dev_gen(r->dev) == ILO_GEN(6) &&
- ilo_shader_get_kernel_param(vec->vs, ILO_KERNEL_VS_GEN6_SO)) {
- const int verts_per_prim =
- u_vertices_per_prim(session->reduced_prim);
- enum ilo_kernel_param param;
-
- switch (verts_per_prim) {
- case 1:
- param = ILO_KERNEL_VS_GEN6_SO_POINT_OFFSET;
- break;
- case 2:
- param = ILO_KERNEL_VS_GEN6_SO_LINE_OFFSET;
- break;
- default:
- param = ILO_KERNEL_VS_GEN6_SO_TRI_OFFSET;
- break;
- }
-
- cso = ilo_shader_get_kernel_cso(vec->vs);
- kernel_offset = ilo_shader_get_kernel_offset(vec->vs) +
- ilo_shader_get_kernel_param(vec->vs, param);
-
- gen6_3DSTATE_GS(r->builder, &cso->vs_sol.sol,
- kernel_offset, r->gs_scratch.bo);
- } else {
- gen6_3DSTATE_GS(r->builder, &vec->disabled_gs, 0, NULL);
- }
- }
-}
-
-static bool
-gen6_draw_update_max_svbi(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- if (DIRTY(VS) || DIRTY(GS) || DIRTY(SO)) {
- const struct pipe_stream_output_info *so_info =
- (vec->gs) ? ilo_shader_get_kernel_so_info(vec->gs) :
- (vec->vs) ? ilo_shader_get_kernel_so_info(vec->vs) : NULL;
- unsigned max_svbi = 0xffffffff;
- int i;
-
- for (i = 0; i < so_info->num_outputs; i++) {
- const int output_buffer = so_info->output[i].output_buffer;
- const struct pipe_stream_output_target *so =
- vec->so.states[output_buffer];
- const int struct_size = so_info->stride[output_buffer] * 4;
- const int elem_size = so_info->output[i].num_components * 4;
- int buf_size, count;
-
- if (!so) {
- max_svbi = 0;
- break;
- }
-
- buf_size = so->buffer_size - so_info->output[i].dst_offset * 4;
-
- count = buf_size / struct_size;
- if (buf_size % struct_size >= elem_size)
- count++;
-
- if (count < max_svbi)
- max_svbi = count;
- }
-
- if (r->state.so_max_vertices != max_svbi) {
- r->state.so_max_vertices = max_svbi;
- return true;
- }
- }
-
- return false;
-}
-
-static void
-gen6_draw_gs_svbi(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- const bool emit = gen6_draw_update_max_svbi(r, vec, session);
-
- /* 3DSTATE_GS_SVB_INDEX */
- if (emit) {
- if (ilo_dev_gen(r->dev) == ILO_GEN(6))
- gen6_wa_pre_non_pipelined(r);
-
- gen6_3DSTATE_GS_SVB_INDEX(r->builder,
- 0, 0, r->state.so_max_vertices,
- false);
-
- if (r->hw_ctx_changed) {
- int i;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 148:
- *
- * "If a buffer is not enabled then the SVBI must be set to 0x0
- * in order to not cause overflow in that SVBI."
- *
- * "If a buffer is not enabled then the MaxSVBI must be set to
- * 0xFFFFFFFF in order to not cause overflow in that SVBI."
- */
- for (i = 1; i < 4; i++) {
- gen6_3DSTATE_GS_SVB_INDEX(r->builder,
- i, 0, 0xffffffff, false);
- }
- }
- }
-}
-
-void
-gen6_draw_clip(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_CLIP */
- if (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_CLIP)
- gen6_3DSTATE_CLIP(r->builder, &vec->rasterizer->rs);
-}
-
-static void
-gen6_draw_sf(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_SF */
- if ((session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_SF) || DIRTY(FS)) {
- const struct ilo_state_sbe *sbe = ilo_shader_get_kernel_sbe(vec->fs);
- gen6_3DSTATE_SF(r->builder, &vec->rasterizer->rs, sbe);
- }
-}
-
-void
-gen6_draw_sf_rect(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_DRAWING_RECTANGLE */
- if (DIRTY(FB)) {
- if (ilo_dev_gen(r->dev) == ILO_GEN(6))
- gen6_wa_pre_non_pipelined(r);
-
- gen6_3DSTATE_DRAWING_RECTANGLE(r->builder, 0, 0,
- vec->fb.state.width, vec->fb.state.height);
- }
-}
-
-static void
-gen6_draw_wm(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_CONSTANT_PS */
- if (session->pcb_fs_changed) {
- gen6_3DSTATE_CONSTANT_PS(r->builder,
- &r->state.wm.PUSH_CONSTANT_BUFFER,
- &r->state.wm.PUSH_CONSTANT_BUFFER_size,
- 1);
- }
-
- /* 3DSTATE_WM */
- if (DIRTY(FS) ||
- (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_WM) ||
- r->instruction_bo_changed) {
- const union ilo_shader_cso *cso = ilo_shader_get_kernel_cso(vec->fs);
- const uint32_t kernel_offset = ilo_shader_get_kernel_offset(vec->fs);
-
- if (ilo_dev_gen(r->dev) == ILO_GEN(6) && r->hw_ctx_changed)
- gen6_wa_pre_3dstate_wm_max_threads(r);
-
- gen6_3DSTATE_WM(r->builder, &vec->rasterizer->rs,
- &cso->ps, kernel_offset, r->fs_scratch.bo);
- }
-}
-
-static void
-gen6_draw_wm_multisample(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_MULTISAMPLE */
- if (DIRTY(FB) || (session->rs_delta.dirty &
- ILO_STATE_RASTER_3DSTATE_MULTISAMPLE)) {
- const uint8_t sample_count = (vec->fb.num_samples > 1) ? 4 : 1;
-
- if (ilo_dev_gen(r->dev) == ILO_GEN(6)) {
- gen6_wa_pre_non_pipelined(r);
- gen6_wa_pre_3dstate_multisample(r);
- }
-
- gen6_3DSTATE_MULTISAMPLE(r->builder, &vec->rasterizer->rs,
- &r->sample_pattern, sample_count);
- }
-
- /* 3DSTATE_SAMPLE_MASK */
- if (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_SAMPLE_MASK)
- gen6_3DSTATE_SAMPLE_MASK(r->builder, &vec->rasterizer->rs);
-}
-
-static void
-gen6_draw_wm_depth(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
- if (DIRTY(FB) || r->batch_bo_changed) {
- const struct ilo_state_zs *zs;
- uint32_t clear_params;
-
- if (vec->fb.state.zsbuf) {
- const struct ilo_surface_cso *surface =
- (const struct ilo_surface_cso *) vec->fb.state.zsbuf;
- const struct ilo_texture_slice *slice =
- ilo_texture_get_slice(ilo_texture(surface->base.texture),
- surface->base.u.tex.level, surface->base.u.tex.first_layer);
-
- assert(!surface->is_rt);
-
- zs = &surface->u.zs;
- clear_params = slice->clear_value;
- }
- else {
- zs = &vec->fb.null_zs;
- clear_params = 0;
- }
-
- if (ilo_dev_gen(r->dev) == ILO_GEN(6)) {
- gen6_wa_pre_non_pipelined(r);
- gen6_wa_pre_depth(r);
- }
-
- gen6_3DSTATE_DEPTH_BUFFER(r->builder, zs);
- gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder, zs);
- gen6_3DSTATE_STENCIL_BUFFER(r->builder, zs);
- gen6_3DSTATE_CLEAR_PARAMS(r->builder, clear_params);
- }
-}
-
-void
-gen6_draw_wm_raster(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_POLY_STIPPLE_PATTERN and 3DSTATE_POLY_STIPPLE_OFFSET */
- if ((DIRTY(RASTERIZER) || DIRTY(POLY_STIPPLE)) &&
- vec->rasterizer->state.poly_stipple_enable) {
- if (ilo_dev_gen(r->dev) == ILO_GEN(6))
- gen6_wa_pre_non_pipelined(r);
-
- gen6_3DSTATE_POLY_STIPPLE_PATTERN(r->builder, &vec->poly_stipple);
- gen6_3DSTATE_POLY_STIPPLE_OFFSET(r->builder, &vec->poly_stipple);
- }
-
- /* 3DSTATE_LINE_STIPPLE */
- if (DIRTY(RASTERIZER) && vec->rasterizer->state.line_stipple_enable) {
- if (ilo_dev_gen(r->dev) == ILO_GEN(6))
- gen6_wa_pre_non_pipelined(r);
-
- gen6_3DSTATE_LINE_STIPPLE(r->builder, &vec->line_stipple);
- }
-
- /* 3DSTATE_AA_LINE_PARAMETERS */
- if (session->rs_delta.dirty &
- ILO_STATE_RASTER_3DSTATE_AA_LINE_PARAMETERS) {
- if (ilo_dev_gen(r->dev) == ILO_GEN(6))
- gen6_wa_pre_non_pipelined(r);
-
- gen6_3DSTATE_AA_LINE_PARAMETERS(r->builder, &vec->rasterizer->rs);
- }
-}
-
-#undef DIRTY
-
-void
-ilo_render_emit_draw_commands_gen6(struct ilo_render *render,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- ILO_DEV_ASSERT(render->dev, 6, 6);
-
- /*
- * We try to keep the order of the commands match, as closely as possible,
- * that of the classic i965 driver. It allows us to compare the command
- * streams easily.
- */
- gen6_draw_common_select(render, vec, session);
- gen6_draw_gs_svbi(render, vec, session);
- gen6_draw_common_sip(render, vec, session);
- gen6_draw_vf_statistics(render, vec, session);
- gen6_draw_common_base_address(render, vec, session);
- gen6_draw_common_pointers_1(render, vec, session);
- gen6_draw_common_urb(render, vec, session);
- gen6_draw_common_pointers_2(render, vec, session);
- gen6_draw_wm_multisample(render, vec, session);
- gen6_draw_vs(render, vec, session);
- gen6_draw_gs(render, vec, session);
- gen6_draw_clip(render, vec, session);
- gen6_draw_sf(render, vec, session);
- gen6_draw_wm(render, vec, session);
- gen6_draw_common_pointers_3(render, vec, session);
- gen6_draw_wm_depth(render, vec, session);
- gen6_draw_wm_raster(render, vec, session);
- gen6_draw_sf_rect(render, vec, session);
- gen6_draw_vf(render, vec, session);
-
- ilo_render_3dprimitive(render, &vec->draw_info);
-}
-
-static void
-gen6_rectlist_vs_to_sf(struct ilo_render *r,
- const struct ilo_blitter *blitter)
-{
- gen6_3DSTATE_CONSTANT_VS(r->builder, NULL, NULL, 0);
- gen6_wa_post_3dstate_constant_vs(r);
-
- gen6_wa_pre_3dstate_vs_toggle(r);
- gen6_3DSTATE_VS(r->builder, &blitter->vs, 0, NULL);
-
- gen6_3DSTATE_CONSTANT_GS(r->builder, NULL, NULL, 0);
- gen6_3DSTATE_GS(r->builder, &blitter->gs, 0, NULL);
-
- gen6_3DSTATE_CLIP(r->builder, &blitter->fb.rs);
- gen6_3DSTATE_SF(r->builder, &blitter->fb.rs, &blitter->sbe);
-}
-
-static void
-gen6_rectlist_wm(struct ilo_render *r,
- const struct ilo_blitter *blitter)
-{
- gen6_3DSTATE_CONSTANT_PS(r->builder, NULL, NULL, 0);
-
- gen6_wa_pre_3dstate_wm_max_threads(r);
- gen6_3DSTATE_WM(r->builder, &blitter->fb.rs, &blitter->ps, 0, NULL);
-}
-
-static void
-gen6_rectlist_wm_depth(struct ilo_render *r,
- const struct ilo_blitter *blitter)
-{
- gen6_wa_pre_depth(r);
-
- if (blitter->uses & (ILO_BLITTER_USE_FB_DEPTH |
- ILO_BLITTER_USE_FB_STENCIL))
- gen6_3DSTATE_DEPTH_BUFFER(r->builder, &blitter->fb.dst.u.zs);
-
- if (blitter->uses & ILO_BLITTER_USE_FB_DEPTH) {
- gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder,
- &blitter->fb.dst.u.zs);
- }
-
- if (blitter->uses & ILO_BLITTER_USE_FB_STENCIL) {
- gen6_3DSTATE_STENCIL_BUFFER(r->builder,
- &blitter->fb.dst.u.zs);
- }
-
- gen6_3DSTATE_CLEAR_PARAMS(r->builder,
- blitter->depth_clear_value);
-}
-
-static void
-gen6_rectlist_wm_multisample(struct ilo_render *r,
- const struct ilo_blitter *blitter)
-{
- const uint8_t sample_count = (blitter->fb.num_samples > 1) ? 4 : 1;
-
- gen6_wa_pre_3dstate_multisample(r);
-
- gen6_3DSTATE_MULTISAMPLE(r->builder, &blitter->fb.rs, &r->sample_pattern, sample_count);
- gen6_3DSTATE_SAMPLE_MASK(r->builder, &blitter->fb.rs);
-}
-
-int
-ilo_render_get_rectlist_commands_len_gen6(const struct ilo_render *render,
- const struct ilo_blitter *blitter)
-{
- ILO_DEV_ASSERT(render->dev, 6, 7.5);
-
- return 256;
-}
-
-void
-ilo_render_emit_rectlist_commands_gen6(struct ilo_render *r,
- const struct ilo_blitter *blitter,
- const struct ilo_render_rectlist_session *session)
-{
- ILO_DEV_ASSERT(r->dev, 6, 6);
-
- gen6_wa_pre_non_pipelined(r);
-
- gen6_rectlist_wm_multisample(r, blitter);
-
- gen6_state_base_address(r->builder, true);
-
- gen6_user_3DSTATE_VERTEX_BUFFERS(r->builder,
- session->vb_start, session->vb_end,
- sizeof(blitter->vertices[0]));
-
- gen6_3DSTATE_VERTEX_ELEMENTS(r->builder, &blitter->vf);
-
- gen6_3DSTATE_URB(r->builder, &blitter->urb);
-
- if (r->state.gs.active) {
- gen6_wa_post_3dstate_urb_no_gs(r);
- r->state.gs.active = false;
- }
-
- if (blitter->uses &
- (ILO_BLITTER_USE_DSA | ILO_BLITTER_USE_CC)) {
- gen6_3DSTATE_CC_STATE_POINTERS(r->builder, 0,
- r->state.DEPTH_STENCIL_STATE, r->state.COLOR_CALC_STATE);
- }
-
- gen6_rectlist_vs_to_sf(r, blitter);
- gen6_rectlist_wm(r, blitter);
-
- if (blitter->uses & ILO_BLITTER_USE_VIEWPORT) {
- gen6_3DSTATE_VIEWPORT_STATE_POINTERS(r->builder,
- 0, 0, r->state.CC_VIEWPORT);
- }
-
- gen6_rectlist_wm_depth(r, blitter);
-
- gen6_3DSTATE_DRAWING_RECTANGLE(r->builder, 0, 0,
- blitter->fb.width, blitter->fb.height);
-
- ilo_render_3dprimitive(r, &blitter->draw_info);
-}
-
-int
-ilo_render_get_draw_commands_len_gen6(const struct ilo_render *render,
- const struct ilo_state_vector *vec)
-{
- static int len;
-
- ILO_DEV_ASSERT(render->dev, 6, 6);
-
- if (!len) {
- len += GEN6_3DSTATE_CONSTANT_ANY__SIZE * 3;
- len += GEN6_3DSTATE_GS_SVB_INDEX__SIZE * 4;
- len += GEN6_PIPE_CONTROL__SIZE * 5;
-
- len +=
- GEN6_STATE_BASE_ADDRESS__SIZE +
- GEN6_STATE_SIP__SIZE +
- GEN6_3DSTATE_VF_STATISTICS__SIZE +
- GEN6_PIPELINE_SELECT__SIZE +
- GEN6_3DSTATE_BINDING_TABLE_POINTERS__SIZE +
- GEN6_3DSTATE_SAMPLER_STATE_POINTERS__SIZE +
- GEN6_3DSTATE_URB__SIZE +
- GEN6_3DSTATE_VERTEX_BUFFERS__SIZE +
- GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE +
- GEN6_3DSTATE_INDEX_BUFFER__SIZE +
- GEN6_3DSTATE_VIEWPORT_STATE_POINTERS__SIZE +
- GEN6_3DSTATE_CC_STATE_POINTERS__SIZE +
- GEN6_3DSTATE_SCISSOR_STATE_POINTERS__SIZE +
- GEN6_3DSTATE_VS__SIZE +
- GEN6_3DSTATE_GS__SIZE +
- GEN6_3DSTATE_CLIP__SIZE +
- GEN6_3DSTATE_SF__SIZE +
- GEN6_3DSTATE_WM__SIZE +
- GEN6_3DSTATE_SAMPLE_MASK__SIZE +
- GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE +
- GEN6_3DSTATE_DEPTH_BUFFER__SIZE +
- GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE +
- GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE +
- GEN6_3DSTATE_LINE_STIPPLE__SIZE +
- GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE +
- GEN6_3DSTATE_MULTISAMPLE__SIZE +
- GEN6_3DSTATE_STENCIL_BUFFER__SIZE +
- GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE +
- GEN6_3DSTATE_CLEAR_PARAMS__SIZE +
- GEN6_3DPRIMITIVE__SIZE;
- }
-
- return len;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "genhw/genhw.h"
-#include "core/ilo_builder_3d.h"
-#include "core/ilo_builder_render.h"
-
-#include "ilo_blitter.h"
-#include "ilo_resource.h"
-#include "ilo_shader.h"
-#include "ilo_state.h"
-#include "ilo_render_gen.h"
-
-static void
-gen7_wa_post_3dstate_push_constant_alloc_ps(struct ilo_render *r)
-{
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 292:
- *
- * "A PIPE_CONTOL command with the CS Stall bit set must be programmed
- * in the ring after this instruction
- * (3DSTATE_PUSH_CONSTANT_ALLOC_PS)."
- */
- const uint32_t dw1 = GEN6_PIPE_CONTROL_CS_STALL;
-
- ILO_DEV_ASSERT(r->dev, 7, 7);
-
- r->state.deferred_pipe_control_dw1 |= dw1;
-}
-
-static void
-gen7_wa_pre_vs(struct ilo_render *r)
-{
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 106:
- *
- * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
- * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
- * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
- * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
- * needs to be sent before any combination of VS associated 3DSTATE."
- */
- const uint32_t dw1 = GEN6_PIPE_CONTROL_DEPTH_STALL |
- GEN6_PIPE_CONTROL_WRITE_IMM;
-
- ILO_DEV_ASSERT(r->dev, 7, 7);
-
- if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
- ilo_render_pipe_control(r, dw1);
-}
-
-static void
-gen7_wa_pre_3dstate_sf_depth_bias(struct ilo_render *r)
-{
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 258:
- *
- * "Due to an HW issue driver needs to send a pipe control with stall
- * when ever there is state change in depth bias related state (in
- * 3DSTATE_SF)"
- */
- const uint32_t dw1 = GEN6_PIPE_CONTROL_CS_STALL;
-
- ILO_DEV_ASSERT(r->dev, 7, 7);
-
- if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
- ilo_render_pipe_control(r, dw1);
-}
-
-static void
-gen7_wa_pre_3dstate_multisample(struct ilo_render *r)
-{
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 304:
- *
- * "Driver must ierarchi that all the caches in the depth pipe are
- * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
- * requires driver to send a PIPE_CONTROL with a CS stall along with a
- * Depth Flush prior to this command.
- */
- const uint32_t dw1 = GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- GEN6_PIPE_CONTROL_CS_STALL;
-
- ILO_DEV_ASSERT(r->dev, 7, 7.5);
-
- if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
- ilo_render_pipe_control(r, dw1);
-}
-
-static void
-gen7_wa_pre_depth(struct ilo_render *r)
-{
- ILO_DEV_ASSERT(r->dev, 7, 7.5);
-
- if (ilo_dev_gen(r->dev) == ILO_GEN(7)) {
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 315:
- *
- * "Driver must send a least one PIPE_CONTROL command with CS Stall
- * and a post sync operation prior to the group of depth
- * commands(3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
- * 3DSTATE_STENCIL_BUFFER, and 3DSTATE_HIER_DEPTH_BUFFER)."
- */
- const uint32_t dw1 = GEN6_PIPE_CONTROL_CS_STALL |
- GEN6_PIPE_CONTROL_WRITE_IMM;
-
- if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
- ilo_render_pipe_control(r, dw1);
- }
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 315:
- *
- * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
- * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
- * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
- * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
- * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
- * Depth Flush Bit set, followed by another pipelined depth stall
- * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
- * guarantee that the pipeline from WM onwards is already flushed
- * (e.g., via a preceding MI_FLUSH)."
- */
- ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
- ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH);
- ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
-}
-
-static void
-gen7_wa_pre_3dstate_ps_max_threads(struct ilo_render *r)
-{
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 286:
- *
- * "If this field (Maximum Number of Threads in 3DSTATE_PS) is changed
- * between 3DPRIMITIVE commands, a PIPE_CONTROL command with Stall at
- * Pixel Scoreboard set is required to be issued."
- */
- const uint32_t dw1 = GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL;
-
- ILO_DEV_ASSERT(r->dev, 7, 7.5);
-
- if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
- ilo_render_pipe_control(r, dw1);
-}
-
-static void
-gen7_wa_post_ps_and_later(struct ilo_render *r)
-{
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 276:
- *
- * "The driver must make sure a PIPE_CONTROL with the Depth Stall
- * Enable bit set after all the following states are programmed:
- *
- * - 3DSTATE_PS
- * - 3DSTATE_VIEWPORT_STATE_POINTERS_CC
- * - 3DSTATE_CONSTANT_PS
- * - 3DSTATE_BINDING_TABLE_POINTERS_PS
- * - 3DSTATE_SAMPLER_STATE_POINTERS_PS
- * - 3DSTATE_CC_STATE_POINTERS
- * - 3DSTATE_BLEND_STATE_POINTERS
- * - 3DSTATE_DEPTH_STENCIL_STATE_POINTERS"
- */
- const uint32_t dw1 = GEN6_PIPE_CONTROL_DEPTH_STALL;
-
- ILO_DEV_ASSERT(r->dev, 7, 7);
-
- r->state.deferred_pipe_control_dw1 |= dw1;
-}
-
-#define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
-
-void
-gen7_draw_common_urb(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_URB_{VS,GS,HS,DS} */
- if (session->urb_delta.dirty & (ILO_STATE_URB_3DSTATE_URB_VS |
- ILO_STATE_URB_3DSTATE_URB_HS |
- ILO_STATE_URB_3DSTATE_URB_DS |
- ILO_STATE_URB_3DSTATE_URB_GS)) {
- if (ilo_dev_gen(r->dev) == ILO_GEN(7))
- gen7_wa_pre_vs(r);
-
- gen7_3DSTATE_URB_VS(r->builder, &vec->urb);
- gen7_3DSTATE_URB_GS(r->builder, &vec->urb);
- gen7_3DSTATE_URB_HS(r->builder, &vec->urb);
- gen7_3DSTATE_URB_DS(r->builder, &vec->urb);
- }
-}
-
-void
-gen7_draw_common_pcb_alloc(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_PUSH_CONSTANT_ALLOC_{VS,PS} */
- if (session->urb_delta.dirty &
- (ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_VS |
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_HS |
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_DS |
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_GS |
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_PS)) {
- gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(r->builder, &vec->urb);
- gen7_3DSTATE_PUSH_CONSTANT_ALLOC_GS(r->builder, &vec->urb);
- gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(r->builder, &vec->urb);
-
- if (ilo_dev_gen(r->dev) == ILO_GEN(7))
- gen7_wa_post_3dstate_push_constant_alloc_ps(r);
- }
-}
-
-void
-gen7_draw_common_pointers_1(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_VIEWPORT_STATE_POINTERS_{CC,SF_CLIP} */
- if (session->viewport_changed) {
- gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(r->builder,
- r->state.CC_VIEWPORT);
-
- gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(r->builder,
- r->state.SF_CLIP_VIEWPORT);
- }
-}
-
-void
-gen7_draw_common_pointers_2(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_BLEND_STATE_POINTERS */
- if (session->blend_changed) {
- gen7_3DSTATE_BLEND_STATE_POINTERS(r->builder,
- r->state.BLEND_STATE);
- }
-
- /* 3DSTATE_CC_STATE_POINTERS */
- if (session->cc_changed) {
- gen7_3DSTATE_CC_STATE_POINTERS(r->builder,
- r->state.COLOR_CALC_STATE);
- }
-
- /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS */
- if (ilo_dev_gen(r->dev) < ILO_GEN(8) && session->dsa_changed) {
- gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(r->builder,
- r->state.DEPTH_STENCIL_STATE);
- }
-}
-
-void
-gen7_draw_vs(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- const bool emit_3dstate_binding_table = session->binding_table_vs_changed;
- const bool emit_3dstate_sampler_state = session->sampler_vs_changed;
- /* see gen6_draw_vs() */
- const bool emit_3dstate_constant_vs = session->pcb_vs_changed;
- const bool emit_3dstate_vs = (DIRTY(VS) || r->instruction_bo_changed);
-
- /* emit depth stall before any of the VS commands */
- if (ilo_dev_gen(r->dev) == ILO_GEN(7)) {
- if (emit_3dstate_binding_table || emit_3dstate_sampler_state ||
- emit_3dstate_constant_vs || emit_3dstate_vs)
- gen7_wa_pre_vs(r);
- }
-
- /* 3DSTATE_BINDING_TABLE_POINTERS_VS */
- if (emit_3dstate_binding_table) {
- gen7_3DSTATE_BINDING_TABLE_POINTERS_VS(r->builder,
- r->state.vs.BINDING_TABLE_STATE);
- }
-
- /* 3DSTATE_SAMPLER_STATE_POINTERS_VS */
- if (emit_3dstate_sampler_state) {
- gen7_3DSTATE_SAMPLER_STATE_POINTERS_VS(r->builder,
- r->state.vs.SAMPLER_STATE);
- }
-
- /* 3DSTATE_CONSTANT_VS */
- if (emit_3dstate_constant_vs) {
- gen7_3DSTATE_CONSTANT_VS(r->builder,
- &r->state.vs.PUSH_CONSTANT_BUFFER,
- &r->state.vs.PUSH_CONSTANT_BUFFER_size,
- 1);
- }
-
- /* 3DSTATE_VS */
- if (emit_3dstate_vs) {
- const union ilo_shader_cso *cso = ilo_shader_get_kernel_cso(vec->vs);
- const uint32_t kernel_offset = ilo_shader_get_kernel_offset(vec->vs);
-
- if (ilo_dev_gen(r->dev) >= ILO_GEN(8)) {
- gen8_3DSTATE_VS(r->builder, &cso->vs,
- kernel_offset, r->vs_scratch.bo);
- } else {
- gen6_3DSTATE_VS(r->builder, &cso->vs,
- kernel_offset, r->vs_scratch.bo);
- }
- }
-}
-
-void
-gen7_draw_hs(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_CONSTANT_HS and 3DSTATE_HS */
- if (r->hw_ctx_changed) {
- const struct ilo_state_hs *hs = &vec->disabled_hs;
- const uint32_t kernel_offset = 0;
-
- gen7_3DSTATE_CONSTANT_HS(r->builder, 0, 0, 0);
-
- if (ilo_dev_gen(r->dev) >= ILO_GEN(8))
- gen8_3DSTATE_HS(r->builder, hs, kernel_offset, NULL);
- else
- gen7_3DSTATE_HS(r->builder, hs, kernel_offset, NULL);
- }
-
- /* 3DSTATE_BINDING_TABLE_POINTERS_HS */
- if (r->hw_ctx_changed)
- gen7_3DSTATE_BINDING_TABLE_POINTERS_HS(r->builder, 0);
-}
-
-void
-gen7_draw_te(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_TE */
- if (r->hw_ctx_changed) {
- const struct ilo_state_ds *ds = &vec->disabled_ds;
- gen7_3DSTATE_TE(r->builder, ds);
- }
-}
-
-void
-gen7_draw_ds(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_CONSTANT_DS and 3DSTATE_DS */
- if (r->hw_ctx_changed) {
- const struct ilo_state_ds *ds = &vec->disabled_ds;
- const uint32_t kernel_offset = 0;
-
- gen7_3DSTATE_CONSTANT_DS(r->builder, 0, 0, 0);
-
- if (ilo_dev_gen(r->dev) >= ILO_GEN(8))
- gen8_3DSTATE_DS(r->builder, ds, kernel_offset, NULL);
- else
- gen7_3DSTATE_DS(r->builder, ds, kernel_offset, NULL);
- }
-
- /* 3DSTATE_BINDING_TABLE_POINTERS_DS */
- if (r->hw_ctx_changed)
- gen7_3DSTATE_BINDING_TABLE_POINTERS_DS(r->builder, 0);
-
-}
-
-void
-gen7_draw_gs(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_CONSTANT_GS and 3DSTATE_GS */
- if (r->hw_ctx_changed) {
- const struct ilo_state_gs *gs = &vec->disabled_gs;
- const uint32_t kernel_offset = 0;
-
- gen7_3DSTATE_CONSTANT_GS(r->builder, 0, 0, 0);
-
- if (ilo_dev_gen(r->dev) >= ILO_GEN(8))
- gen8_3DSTATE_GS(r->builder, gs, kernel_offset, NULL);
- else
- gen7_3DSTATE_GS(r->builder, gs, kernel_offset, NULL);
- }
-
- /* 3DSTATE_BINDING_TABLE_POINTERS_GS */
- if (session->binding_table_gs_changed) {
- gen7_3DSTATE_BINDING_TABLE_POINTERS_GS(r->builder,
- r->state.gs.BINDING_TABLE_STATE);
- }
-}
-
-void
-gen7_draw_sol(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- const struct ilo_state_sol *sol;
- const struct ilo_shader_state *shader;
- bool dirty_sh = false;
-
- if (vec->gs) {
- shader = vec->gs;
- dirty_sh = DIRTY(GS);
- }
- else {
- shader = vec->vs;
- dirty_sh = DIRTY(VS);
- }
-
- sol = ilo_shader_get_kernel_sol(shader);
-
- /* 3DSTATE_SO_BUFFER */
- if ((DIRTY(SO) || dirty_sh || r->batch_bo_changed) &&
- vec->so.enabled) {
- int i;
-
- for (i = 0; i < ILO_STATE_SOL_MAX_BUFFER_COUNT; i++) {
- const struct pipe_stream_output_target *target =
- (i < vec->so.count && vec->so.states[i]) ?
- vec->so.states[i] : NULL;
- const struct ilo_state_sol_buffer *sb = (target) ?
- &((const struct ilo_stream_output_target *) target)->sb :
- &vec->so.dummy_sb;
-
- if (ilo_dev_gen(r->dev) >= ILO_GEN(8))
- gen8_3DSTATE_SO_BUFFER(r->builder, sol, sb, i);
- else
- gen7_3DSTATE_SO_BUFFER(r->builder, sol, sb, i);
- }
- }
-
- /* 3DSTATE_SO_DECL_LIST */
- if (dirty_sh && vec->so.enabled)
- gen7_3DSTATE_SO_DECL_LIST(r->builder, sol);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 196-197:
- *
- * "Anytime the SOL unit MMIO registers or non-pipeline state are
- * written, the SOL unit needs to receive a pipeline state update with
- * SOL unit dirty state for information programmed in MMIO/NP to get
- * loaded into the SOL unit.
- *
- * The SOL unit incorrectly double buffers MMIO/NP registers and only
- * moves them into the design for usage when control topology is
- * received with the SOL unit dirty state.
- *
- * If the state does not change, need to resend the same state.
- *
- * Because of corruption, software must flush the whole fixed function
- * pipeline when 3DSTATE_STREAMOUT changes state."
- *
- * The first and fourth paragraphs are gone on Gen7.5+.
- */
-
- /* 3DSTATE_STREAMOUT */
- gen7_3DSTATE_STREAMOUT(r->builder, sol);
-}
-
-static void
-gen7_draw_sf(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_SBE */
- if (DIRTY(FS)) {
- const struct ilo_state_sbe *sbe = ilo_shader_get_kernel_sbe(vec->fs);
- gen7_3DSTATE_SBE(r->builder, sbe);
- }
-
- /* 3DSTATE_SF */
- if (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_SF) {
- if (ilo_dev_gen(r->dev) == ILO_GEN(7))
- gen7_wa_pre_3dstate_sf_depth_bias(r);
-
- gen7_3DSTATE_SF(r->builder, &vec->rasterizer->rs);
- }
-}
-
-static void
-gen7_draw_wm(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- const union ilo_shader_cso *cso = ilo_shader_get_kernel_cso(vec->fs);
- const uint32_t kernel_offset = ilo_shader_get_kernel_offset(vec->fs);
-
- /* 3DSTATE_WM */
- if (DIRTY(FS) || (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_WM))
- gen7_3DSTATE_WM(r->builder, &vec->rasterizer->rs, &cso->ps);
-
- /* 3DSTATE_BINDING_TABLE_POINTERS_PS */
- if (session->binding_table_fs_changed) {
- gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(r->builder,
- r->state.wm.BINDING_TABLE_STATE);
- }
-
- /* 3DSTATE_SAMPLER_STATE_POINTERS_PS */
- if (session->sampler_fs_changed) {
- gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(r->builder,
- r->state.wm.SAMPLER_STATE);
- }
-
- /* 3DSTATE_CONSTANT_PS */
- if (session->pcb_fs_changed) {
- gen7_3DSTATE_CONSTANT_PS(r->builder,
- &r->state.wm.PUSH_CONSTANT_BUFFER,
- &r->state.wm.PUSH_CONSTANT_BUFFER_size,
- 1);
- }
-
- /* 3DSTATE_PS */
- if (DIRTY(FS) || r->instruction_bo_changed) {
- if (r->hw_ctx_changed)
- gen7_wa_pre_3dstate_ps_max_threads(r);
-
- gen7_3DSTATE_PS(r->builder, &cso->ps, kernel_offset, r->fs_scratch.bo);
- }
-
- /* 3DSTATE_SCISSOR_STATE_POINTERS */
- if (session->scissor_changed) {
- gen6_3DSTATE_SCISSOR_STATE_POINTERS(r->builder,
- r->state.SCISSOR_RECT);
- }
-
- {
- const bool emit_3dstate_ps = (DIRTY(FS) || DIRTY(BLEND));
- const bool emit_3dstate_depth_buffer =
- (DIRTY(FB) || DIRTY(DSA) || r->state_bo_changed);
-
- if (ilo_dev_gen(r->dev) == ILO_GEN(7)) {
- /* XXX what is the best way to know if this workaround is needed? */
- if (emit_3dstate_ps ||
- session->pcb_fs_changed ||
- session->viewport_changed ||
- session->binding_table_fs_changed ||
- session->sampler_fs_changed ||
- session->cc_changed ||
- session->blend_changed ||
- session->dsa_changed)
- gen7_wa_post_ps_and_later(r);
- }
-
- if (emit_3dstate_depth_buffer)
- gen7_wa_pre_depth(r);
- }
-
- /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
- if (DIRTY(FB) || r->batch_bo_changed) {
- const struct ilo_state_zs *zs;
- uint32_t clear_params;
-
- if (vec->fb.state.zsbuf) {
- const struct ilo_surface_cso *surface =
- (const struct ilo_surface_cso *) vec->fb.state.zsbuf;
- const struct ilo_texture_slice *slice =
- ilo_texture_get_slice(ilo_texture(surface->base.texture),
- surface->base.u.tex.level, surface->base.u.tex.first_layer);
-
- assert(!surface->is_rt);
- zs = &surface->u.zs;
- clear_params = slice->clear_value;
- }
- else {
- zs = &vec->fb.null_zs;
- clear_params = 0;
- }
-
- gen6_3DSTATE_DEPTH_BUFFER(r->builder, zs);
- gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder, zs);
- gen6_3DSTATE_STENCIL_BUFFER(r->builder, zs);
- gen7_3DSTATE_CLEAR_PARAMS(r->builder, clear_params);
- }
-}
-
-static void
-gen7_draw_wm_multisample(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_MULTISAMPLE */
- if (DIRTY(FB) || (session->rs_delta.dirty &
- ILO_STATE_RASTER_3DSTATE_MULTISAMPLE)) {
- const uint8_t sample_count = (vec->fb.num_samples > 4) ? 8 :
- (vec->fb.num_samples > 1) ? 4 : 1;
-
- gen7_wa_pre_3dstate_multisample(r);
-
- gen6_3DSTATE_MULTISAMPLE(r->builder, &vec->rasterizer->rs,
- &r->sample_pattern, sample_count);
- }
-
- /* 3DSTATE_SAMPLE_MASK */
- if (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_SAMPLE_MASK)
- gen6_3DSTATE_SAMPLE_MASK(r->builder, &vec->rasterizer->rs);
-}
-
-void
-ilo_render_emit_draw_commands_gen7(struct ilo_render *render,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- ILO_DEV_ASSERT(render->dev, 7, 7.5);
-
- /*
- * We try to keep the order of the commands match, as closely as possible,
- * that of the classic i965 driver. It allows us to compare the command
- * streams easily.
- */
- gen6_draw_common_select(render, vec, session);
- gen6_draw_common_sip(render, vec, session);
- gen6_draw_vf_statistics(render, vec, session);
- gen7_draw_common_pcb_alloc(render, vec, session);
- gen6_draw_common_base_address(render, vec, session);
- gen7_draw_common_pointers_1(render, vec, session);
- gen7_draw_common_urb(render, vec, session);
- gen7_draw_common_pointers_2(render, vec, session);
- gen7_draw_wm_multisample(render, vec, session);
- gen7_draw_gs(render, vec, session);
- gen7_draw_hs(render, vec, session);
- gen7_draw_te(render, vec, session);
- gen7_draw_ds(render, vec, session);
- gen7_draw_vs(render, vec, session);
- gen7_draw_sol(render, vec, session);
- gen6_draw_clip(render, vec, session);
- gen7_draw_sf(render, vec, session);
- gen7_draw_wm(render, vec, session);
- gen6_draw_wm_raster(render, vec, session);
- gen6_draw_sf_rect(render, vec, session);
- gen6_draw_vf(render, vec, session);
-
- ilo_render_3dprimitive(render, &vec->draw_info);
-}
-
-static void
-gen7_rectlist_pcb_alloc(struct ilo_render *r,
- const struct ilo_blitter *blitter)
-{
- gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(r->builder, &blitter->urb);
- gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(r->builder, &blitter->urb);
-
- if (ilo_dev_gen(r->dev) == ILO_GEN(7))
- gen7_wa_post_3dstate_push_constant_alloc_ps(r);
-}
-
-static void
-gen7_rectlist_urb(struct ilo_render *r,
- const struct ilo_blitter *blitter)
-{
- gen7_3DSTATE_URB_VS(r->builder, &blitter->urb);
- gen7_3DSTATE_URB_GS(r->builder, &blitter->urb);
- gen7_3DSTATE_URB_HS(r->builder, &blitter->urb);
- gen7_3DSTATE_URB_DS(r->builder, &blitter->urb);
-}
-
-static void
-gen7_rectlist_vs_to_sf(struct ilo_render *r,
- const struct ilo_blitter *blitter)
-{
- gen7_3DSTATE_CONSTANT_VS(r->builder, NULL, NULL, 0);
- gen6_3DSTATE_VS(r->builder, &blitter->vs, 0, NULL);
-
- gen7_3DSTATE_CONSTANT_HS(r->builder, NULL, NULL, 0);
- gen7_3DSTATE_HS(r->builder, &blitter->hs, 0, NULL);
-
- gen7_3DSTATE_TE(r->builder, &blitter->ds);
-
- gen7_3DSTATE_CONSTANT_DS(r->builder, NULL, NULL, 0);
- gen7_3DSTATE_DS(r->builder, &blitter->ds, 0, NULL);
-
- gen7_3DSTATE_CONSTANT_GS(r->builder, NULL, NULL, 0);
- gen7_3DSTATE_GS(r->builder, &blitter->gs, 0, NULL);
-
- gen7_3DSTATE_STREAMOUT(r->builder, &blitter->sol);
-
- gen6_3DSTATE_CLIP(r->builder, &blitter->fb.rs);
-
- if (ilo_dev_gen(r->dev) == ILO_GEN(7))
- gen7_wa_pre_3dstate_sf_depth_bias(r);
-
- gen7_3DSTATE_SF(r->builder, &blitter->fb.rs);
- gen7_3DSTATE_SBE(r->builder, &blitter->sbe);
-}
-
-static void
-gen7_rectlist_wm(struct ilo_render *r,
- const struct ilo_blitter *blitter)
-{
- gen7_3DSTATE_WM(r->builder, &blitter->fb.rs, &blitter->ps);
-
- gen7_3DSTATE_CONSTANT_PS(r->builder, NULL, NULL, 0);
-
- gen7_wa_pre_3dstate_ps_max_threads(r);
- gen7_3DSTATE_PS(r->builder, &blitter->ps, 0, NULL);
-}
-
-static void
-gen7_rectlist_wm_depth(struct ilo_render *r,
- const struct ilo_blitter *blitter)
-{
- gen7_wa_pre_depth(r);
-
- if (blitter->uses & (ILO_BLITTER_USE_FB_DEPTH |
- ILO_BLITTER_USE_FB_STENCIL))
- gen6_3DSTATE_DEPTH_BUFFER(r->builder, &blitter->fb.dst.u.zs);
-
- if (blitter->uses & ILO_BLITTER_USE_FB_DEPTH) {
- gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder,
- &blitter->fb.dst.u.zs);
- }
-
- if (blitter->uses & ILO_BLITTER_USE_FB_STENCIL) {
- gen6_3DSTATE_STENCIL_BUFFER(r->builder,
- &blitter->fb.dst.u.zs);
- }
-
- gen7_3DSTATE_CLEAR_PARAMS(r->builder,
- blitter->depth_clear_value);
-}
-
-static void
-gen7_rectlist_wm_multisample(struct ilo_render *r,
- const struct ilo_blitter *blitter)
-{
- const uint8_t sample_count = (blitter->fb.num_samples > 4) ? 8 :
- (blitter->fb.num_samples > 1) ? 4 : 1;
-
- gen7_wa_pre_3dstate_multisample(r);
-
- gen6_3DSTATE_MULTISAMPLE(r->builder, &blitter->fb.rs,
- &r->sample_pattern, sample_count);
-
- gen6_3DSTATE_SAMPLE_MASK(r->builder, &blitter->fb.rs);
-}
-
-void
-ilo_render_emit_rectlist_commands_gen7(struct ilo_render *r,
- const struct ilo_blitter *blitter,
- const struct ilo_render_rectlist_session *session)
-{
- ILO_DEV_ASSERT(r->dev, 7, 7.5);
-
- gen7_rectlist_wm_multisample(r, blitter);
-
- gen6_state_base_address(r->builder, true);
-
- gen6_user_3DSTATE_VERTEX_BUFFERS(r->builder,
- session->vb_start, session->vb_end,
- sizeof(blitter->vertices[0]));
-
- gen6_3DSTATE_VERTEX_ELEMENTS(r->builder, &blitter->vf);
-
- gen7_rectlist_pcb_alloc(r, blitter);
-
- /* needed for any VS-related commands */
- if (ilo_dev_gen(r->dev) == ILO_GEN(7))
- gen7_wa_pre_vs(r);
-
- gen7_rectlist_urb(r, blitter);
-
- if (blitter->uses & ILO_BLITTER_USE_DSA) {
- gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(r->builder,
- r->state.DEPTH_STENCIL_STATE);
- }
-
- if (blitter->uses & ILO_BLITTER_USE_CC) {
- gen7_3DSTATE_CC_STATE_POINTERS(r->builder,
- r->state.COLOR_CALC_STATE);
- }
-
- gen7_rectlist_vs_to_sf(r, blitter);
- gen7_rectlist_wm(r, blitter);
-
- if (blitter->uses & ILO_BLITTER_USE_VIEWPORT) {
- gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(r->builder,
- r->state.CC_VIEWPORT);
- }
-
- gen7_rectlist_wm_depth(r, blitter);
-
- gen6_3DSTATE_DRAWING_RECTANGLE(r->builder, 0, 0,
- blitter->fb.width, blitter->fb.height);
-
- if (ilo_dev_gen(r->dev) == ILO_GEN(7))
- gen7_wa_post_ps_and_later(r);
-
- ilo_render_3dprimitive(r, &blitter->draw_info);
-}
-
-int
-ilo_render_get_draw_commands_len_gen7(const struct ilo_render *render,
- const struct ilo_state_vector *vec)
-{
- static int len;
-
- ILO_DEV_ASSERT(render->dev, 7, 7.5);
-
- if (!len) {
- len += GEN7_3DSTATE_URB_ANY__SIZE * 4;
- len += GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_ANY__SIZE * 5;
- len += GEN6_3DSTATE_CONSTANT_ANY__SIZE * 5;
- len += GEN7_3DSTATE_POINTERS_ANY__SIZE * (5 + 5 + 4);
- len += GEN7_3DSTATE_SO_BUFFER__SIZE * 4;
- len += GEN6_PIPE_CONTROL__SIZE * 5;
-
- len +=
- GEN6_STATE_BASE_ADDRESS__SIZE +
- GEN6_STATE_SIP__SIZE +
- GEN6_3DSTATE_VF_STATISTICS__SIZE +
- GEN6_PIPELINE_SELECT__SIZE +
- GEN6_3DSTATE_CLEAR_PARAMS__SIZE +
- GEN6_3DSTATE_DEPTH_BUFFER__SIZE +
- GEN6_3DSTATE_STENCIL_BUFFER__SIZE +
- GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE +
- GEN6_3DSTATE_VERTEX_BUFFERS__SIZE +
- GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE +
- GEN6_3DSTATE_INDEX_BUFFER__SIZE +
- GEN75_3DSTATE_VF__SIZE +
- GEN6_3DSTATE_VS__SIZE +
- GEN6_3DSTATE_GS__SIZE +
- GEN6_3DSTATE_CLIP__SIZE +
- GEN6_3DSTATE_SF__SIZE +
- GEN6_3DSTATE_WM__SIZE +
- GEN6_3DSTATE_SAMPLE_MASK__SIZE +
- GEN7_3DSTATE_HS__SIZE +
- GEN7_3DSTATE_TE__SIZE +
- GEN7_3DSTATE_DS__SIZE +
- GEN7_3DSTATE_STREAMOUT__SIZE +
- GEN7_3DSTATE_SBE__SIZE +
- GEN7_3DSTATE_PS__SIZE +
- GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE +
- GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE +
- GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE +
- GEN6_3DSTATE_LINE_STIPPLE__SIZE +
- GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE +
- GEN6_3DSTATE_MULTISAMPLE__SIZE +
- GEN7_3DSTATE_SO_DECL_LIST__SIZE +
- GEN6_3DPRIMITIVE__SIZE;
- }
-
- return len;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "genhw/genhw.h"
-#include "core/ilo_builder_3d.h"
-#include "core/ilo_builder_render.h"
-
-#include "ilo_blitter.h"
-#include "ilo_resource.h"
-#include "ilo_shader.h"
-#include "ilo_state.h"
-#include "ilo_render_gen.h"
-
-static void
-gen8_wa_pre_depth(struct ilo_render *r)
-{
- ILO_DEV_ASSERT(r->dev, 8, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 315:
- *
- * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
- * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
- * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
- * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
- * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
- * Depth Flush Bit set, followed by another pipelined depth stall
- * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
- * guarantee that the pipeline from WM onwards is already flushed
- * (e.g., via a preceding MI_FLUSH)."
- */
- ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
- ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH);
- ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
-}
-
-#define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
-
-static void
-gen8_draw_sf(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_RASTER */
- if (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_RASTER)
- gen8_3DSTATE_RASTER(r->builder, &vec->rasterizer->rs);
-
- /* 3DSTATE_SBE and 3DSTATE_SBE_SWIZ */
- if (DIRTY(FS)) {
- const struct ilo_state_sbe *sbe = ilo_shader_get_kernel_sbe(vec->fs);
-
- gen8_3DSTATE_SBE(r->builder, sbe);
- gen8_3DSTATE_SBE_SWIZ(r->builder, sbe);
- }
-
- /* 3DSTATE_SF */
- if (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_SF)
- gen7_3DSTATE_SF(r->builder, &vec->rasterizer->rs);
-}
-
-static void
-gen8_draw_wm(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- const union ilo_shader_cso *cso = ilo_shader_get_kernel_cso(vec->fs);
- const uint32_t kernel_offset = ilo_shader_get_kernel_offset(vec->fs);
-
- /* 3DSTATE_WM */
- if (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_WM)
- gen8_3DSTATE_WM(r->builder, &vec->rasterizer->rs);
-
- if (session->cc_delta.dirty & ILO_STATE_CC_3DSTATE_WM_DEPTH_STENCIL)
- gen8_3DSTATE_WM_DEPTH_STENCIL(r->builder, &vec->blend->cc);
-
- /* 3DSTATE_WM_HZ_OP and 3DSTATE_WM_CHROMAKEY */
- if (r->hw_ctx_changed) {
- gen8_disable_3DSTATE_WM_HZ_OP(r->builder);
- gen8_3DSTATE_WM_CHROMAKEY(r->builder);
- }
-
- /* 3DSTATE_BINDING_TABLE_POINTERS_PS */
- if (session->binding_table_fs_changed) {
- gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(r->builder,
- r->state.wm.BINDING_TABLE_STATE);
- }
-
- /* 3DSTATE_SAMPLER_STATE_POINTERS_PS */
- if (session->sampler_fs_changed) {
- gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(r->builder,
- r->state.wm.SAMPLER_STATE);
- }
-
- /* 3DSTATE_CONSTANT_PS */
- if (session->pcb_fs_changed) {
- gen7_3DSTATE_CONSTANT_PS(r->builder,
- &r->state.wm.PUSH_CONSTANT_BUFFER,
- &r->state.wm.PUSH_CONSTANT_BUFFER_size,
- 1);
- }
-
- /* 3DSTATE_PS */
- if (DIRTY(FS) || r->instruction_bo_changed)
- gen8_3DSTATE_PS(r->builder, &cso->ps, kernel_offset, r->fs_scratch.bo);
-
- /* 3DSTATE_PS_EXTRA */
- if (DIRTY(FS))
- gen8_3DSTATE_PS_EXTRA(r->builder, &cso->ps);
-
- /* 3DSTATE_PS_BLEND */
- if (session->cc_delta.dirty & ILO_STATE_CC_3DSTATE_PS_BLEND)
- gen8_3DSTATE_PS_BLEND(r->builder, &vec->blend->cc);
-
- /* 3DSTATE_SCISSOR_STATE_POINTERS */
- if (session->scissor_changed) {
- gen6_3DSTATE_SCISSOR_STATE_POINTERS(r->builder,
- r->state.SCISSOR_RECT);
- }
-
- /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
- if (DIRTY(FB) || r->batch_bo_changed) {
- const struct ilo_state_zs *zs;
- uint32_t clear_params;
-
- if (vec->fb.state.zsbuf) {
- const struct ilo_surface_cso *surface =
- (const struct ilo_surface_cso *) vec->fb.state.zsbuf;
- const struct ilo_texture_slice *slice =
- ilo_texture_get_slice(ilo_texture(surface->base.texture),
- surface->base.u.tex.level, surface->base.u.tex.first_layer);
-
- assert(!surface->is_rt);
- zs = &surface->u.zs;
- clear_params = slice->clear_value;
- }
- else {
- zs = &vec->fb.null_zs;
- clear_params = 0;
- }
-
- gen8_wa_pre_depth(r);
-
- gen6_3DSTATE_DEPTH_BUFFER(r->builder, zs);
- gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder, zs);
- gen6_3DSTATE_STENCIL_BUFFER(r->builder, zs);
- gen7_3DSTATE_CLEAR_PARAMS(r->builder, clear_params);
- }
-}
-
-static void
-gen8_draw_wm_sample_pattern(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_SAMPLE_PATTERN */
- if (r->hw_ctx_changed)
- gen8_3DSTATE_SAMPLE_PATTERN(r->builder, &r->sample_pattern);
-}
-
-static void
-gen8_draw_wm_multisample(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_MULTISAMPLE */
- if (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_MULTISAMPLE)
- gen8_3DSTATE_MULTISAMPLE(r->builder, &vec->rasterizer->rs);
-
- /* 3DSTATE_SAMPLE_MASK */
- if (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_SAMPLE_MASK)
- gen6_3DSTATE_SAMPLE_MASK(r->builder, &vec->rasterizer->rs);
-}
-
-static void
-gen8_draw_vf(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- /* 3DSTATE_INDEX_BUFFER */
- if ((session->vf_delta.dirty & ILO_STATE_VF_3DSTATE_INDEX_BUFFER) ||
- DIRTY(IB) || r->batch_bo_changed)
- gen8_3DSTATE_INDEX_BUFFER(r->builder, &vec->ve->vf, &vec->ib.ib);
-
- /* 3DSTATE_VF */
- if (session->vf_delta.dirty & ILO_STATE_VF_3DSTATE_VF)
- gen75_3DSTATE_VF(r->builder, &vec->ve->vf);
-
- /* 3DSTATE_VERTEX_BUFFERS */
- if ((session->vf_delta.dirty & ILO_STATE_VF_3DSTATE_VERTEX_BUFFERS) ||
- DIRTY(VB) || DIRTY(VE) || r->batch_bo_changed) {
- gen6_3DSTATE_VERTEX_BUFFERS(r->builder, &vec->ve->vf,
- vec->vb.vb, vec->ve->vb_count);
- }
-
- /* 3DSTATE_VERTEX_ELEMENTS */
- if (session->vf_delta.dirty & ILO_STATE_VF_3DSTATE_VERTEX_ELEMENTS)
- gen6_3DSTATE_VERTEX_ELEMENTS(r->builder, &vec->ve->vf);
-
- gen8_3DSTATE_VF_TOPOLOGY(r->builder, vec->draw_info.topology);
-
- if (session->vf_delta.dirty & ILO_STATE_VF_3DSTATE_VF_INSTANCING) {
- const uint8_t attr_count = ilo_state_vf_get_attr_count(&vec->ve->vf);
- uint8_t i;
-
- for (i = 0; i < attr_count; i++)
- gen8_3DSTATE_VF_INSTANCING(r->builder, &vec->ve->vf, i);
- }
-
- if (session->vf_delta.dirty & ILO_STATE_VF_3DSTATE_VF_SGVS)
- gen8_3DSTATE_VF_SGVS(r->builder, &vec->ve->vf);
-}
-
-void
-ilo_render_emit_draw_commands_gen8(struct ilo_render *render,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- ILO_DEV_ASSERT(render->dev, 8, 8);
-
- /*
- * We try to keep the order of the commands match, as closely as possible,
- * that of the classic i965 driver. It allows us to compare the command
- * streams easily.
- */
- gen6_draw_common_select(render, vec, session);
- gen6_draw_common_sip(render, vec, session);
- gen6_draw_vf_statistics(render, vec, session);
- gen8_draw_wm_sample_pattern(render, vec, session);
- gen6_draw_common_base_address(render, vec, session);
- gen7_draw_common_pointers_1(render, vec, session);
- gen7_draw_common_pcb_alloc(render, vec, session);
- gen7_draw_common_urb(render, vec, session);
- gen7_draw_common_pointers_2(render, vec, session);
- gen8_draw_wm_multisample(render, vec, session);
- gen7_draw_gs(render, vec, session);
- gen7_draw_hs(render, vec, session);
- gen7_draw_te(render, vec, session);
- gen7_draw_ds(render, vec, session);
- gen7_draw_vs(render, vec, session);
- gen7_draw_sol(render, vec, session);
- gen6_draw_clip(render, vec, session);
- gen8_draw_sf(render, vec, session);
- gen8_draw_wm(render, vec, session);
- gen6_draw_wm_raster(render, vec, session);
- gen6_draw_sf_rect(render, vec, session);
- gen8_draw_vf(render, vec, session);
-
- ilo_render_3dprimitive(render, &vec->draw_info);
-}
-
-int
-ilo_render_get_draw_commands_len_gen8(const struct ilo_render *render,
- const struct ilo_state_vector *vec)
-{
- static int len;
-
- ILO_DEV_ASSERT(render->dev, 8, 8);
-
- if (!len) {
- len += GEN7_3DSTATE_URB_ANY__SIZE * 4;
- len += GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_ANY__SIZE * 5;
- len += GEN6_3DSTATE_CONSTANT_ANY__SIZE * 5;
- len += GEN7_3DSTATE_POINTERS_ANY__SIZE * (5 + 5 + 4);
- len += GEN7_3DSTATE_SO_BUFFER__SIZE * 4;
- len += GEN6_PIPE_CONTROL__SIZE * 5;
-
- len +=
- GEN6_STATE_BASE_ADDRESS__SIZE +
- GEN6_STATE_SIP__SIZE +
- GEN6_3DSTATE_VF_STATISTICS__SIZE +
- GEN6_PIPELINE_SELECT__SIZE +
- GEN6_3DSTATE_CLEAR_PARAMS__SIZE +
- GEN6_3DSTATE_DEPTH_BUFFER__SIZE +
- GEN6_3DSTATE_STENCIL_BUFFER__SIZE +
- GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE +
- GEN6_3DSTATE_VERTEX_BUFFERS__SIZE +
- GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE +
- GEN6_3DSTATE_INDEX_BUFFER__SIZE +
- GEN75_3DSTATE_VF__SIZE +
- GEN6_3DSTATE_VS__SIZE +
- GEN6_3DSTATE_GS__SIZE +
- GEN6_3DSTATE_CLIP__SIZE +
- GEN6_3DSTATE_SF__SIZE +
- GEN6_3DSTATE_WM__SIZE +
- GEN6_3DSTATE_SAMPLE_MASK__SIZE +
- GEN7_3DSTATE_HS__SIZE +
- GEN7_3DSTATE_TE__SIZE +
- GEN7_3DSTATE_DS__SIZE +
- GEN7_3DSTATE_STREAMOUT__SIZE +
- GEN7_3DSTATE_SBE__SIZE +
- GEN7_3DSTATE_PS__SIZE +
- GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE +
- GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE +
- GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE +
- GEN6_3DSTATE_LINE_STIPPLE__SIZE +
- GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE +
- GEN6_3DSTATE_MULTISAMPLE__SIZE +
- GEN7_3DSTATE_SO_DECL_LIST__SIZE +
- GEN6_3DPRIMITIVE__SIZE;
-
- len +=
- GEN8_3DSTATE_VF_INSTANCING__SIZE * 33 +
- GEN8_3DSTATE_VF_SGVS__SIZE +
- GEN8_3DSTATE_VF_TOPOLOGY__SIZE +
- GEN8_3DSTATE_SBE_SWIZ__SIZE +
- GEN8_3DSTATE_RASTER__SIZE +
- GEN8_3DSTATE_WM_CHROMAKEY__SIZE +
- GEN8_3DSTATE_WM_DEPTH_STENCIL__SIZE +
- GEN8_3DSTATE_WM_HZ_OP__SIZE +
- GEN8_3DSTATE_PS_EXTRA__SIZE +
- GEN8_3DSTATE_PS_BLEND__SIZE +
- GEN8_3DSTATE_SAMPLE_PATTERN__SIZE;
- }
-
- return len;
-}
-
-int
-ilo_render_get_rectlist_commands_len_gen8(const struct ilo_render *render,
- const struct ilo_blitter *blitter)
-{
- ILO_DEV_ASSERT(render->dev, 8, 8);
-
- return 96;
-}
-
-void
-ilo_render_emit_rectlist_commands_gen8(struct ilo_render *r,
- const struct ilo_blitter *blitter,
- const struct ilo_render_rectlist_session *session)
-{
- ILO_DEV_ASSERT(r->dev, 8, 8);
-
- gen8_wa_pre_depth(r);
-
- if (blitter->uses & (ILO_BLITTER_USE_FB_DEPTH |
- ILO_BLITTER_USE_FB_STENCIL))
- gen6_3DSTATE_DEPTH_BUFFER(r->builder, &blitter->fb.dst.u.zs);
-
- if (blitter->uses & ILO_BLITTER_USE_FB_DEPTH) {
- gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder,
- &blitter->fb.dst.u.zs);
- }
-
- if (blitter->uses & ILO_BLITTER_USE_FB_STENCIL) {
- gen6_3DSTATE_STENCIL_BUFFER(r->builder,
- &blitter->fb.dst.u.zs);
- }
-
- gen7_3DSTATE_CLEAR_PARAMS(r->builder,
- blitter->depth_clear_value);
-
- gen6_3DSTATE_DRAWING_RECTANGLE(r->builder, 0, 0,
- blitter->fb.width, blitter->fb.height);
-
- gen8_3DSTATE_WM_HZ_OP(r->builder, &blitter->fb.rs,
- blitter->fb.width, blitter->fb.height);
-
- ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_WRITE_IMM);
-
- gen8_disable_3DSTATE_WM_HZ_OP(r->builder);
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "genhw/genhw.h"
-#include "core/ilo_builder_media.h"
-#include "core/ilo_builder_mi.h"
-#include "core/ilo_builder_render.h"
-
-#include "ilo_shader.h"
-#include "ilo_state.h"
-#include "ilo_render_gen.h"
-
-struct gen7_l3_config {
- int slm;
- int urb;
- int rest;
- int dc;
- int ro;
- int is;
- int c;
- int t;
-};
-
-/*
- * From the Ivy Bridge PRM, volume 1 part 7, page 10:
- *
- * "Normal L3/URB mode (non-SLM mode), uses all 4 banks of L3 equally to
- * distribute cycles. The following allocation is a suggested programming
- * model. Note all numbers below are given in KBytes."
- *
- * From the Haswell PRM, volume 7, page 662:
- *
- * "The configuration for {SLM = 0,URB = 224,DC = 32,RO = 256,IS = 0,C =
- * 0,T =0, SUM 512} was validated as a later supported configuration and
- * can be utilized if desired."
- */
-static const struct gen7_l3_config gen7_l3_non_slm_configs[] = {
- /* SLM URB Rest DC RO I/S C T */
- [0] = { 0, 256, 0, 0, 256, 0, 0, 0, },
- [1] = { 0, 256, 0, 128, 128, 0, 0, 0, },
- [2] = { 0, 256, 0, 32, 0, 64, 32, 128, },
- [3] = { 0, 224, 0, 64, 0, 64, 32, 128, },
- [4] = { 0, 224, 0, 128, 0, 64, 32, 64, },
- [5] = { 0, 224, 0, 64, 0, 128, 32, 64, },
- [6] = { 0, 224, 0, 0, 0, 128, 32, 128, },
- [7] = { 0, 256, 0, 0, 0, 128, 0, 128, },
-
- [8] = { 0, 224, 0, 32, 256, 0, 0, 0, },
-};
-
-/*
- * From the Ivy Bridge PRM, volume 1 part 7, page 11:
- *
- * "With the existence of Shared Local Memory, a 64KB chunk from each of
- * the 2 L3 banks will be reserved for SLM usage. The remaining cache
- * space is divided between the remaining clients. SLM allocation is done
- * via reducing the number of ways on the two banks from 64 to 32."
- *
- * From the Haswell PRM, volume 7, page 662:
- *
- * "The configuration for {SLM = 128,URB = 128,DC = 0,RO = 256,IS = 0,C =
- * 0,T =0, SUM 512} was validated as a later supported configuration and
- * can be utilized if desired. For this configuration, global atomics
- * must be programmed to be in GTI."
- */
-static const struct gen7_l3_config gen7_l3_slm_configs[] = {
- /* SLM URB Rest DC RO I/S C T */
- [0] = { 128, 128, 0, 128, 128, 0, 0, 0, },
- [1] = { 128, 128, 0, 64, 0, 64, 64, 64, },
- [2] = { 128, 128, 0, 32, 0, 64, 32, 128, },
- [3] = { 128, 128, 0, 32, 0, 128, 32, 64, },
-
- [4] = { 128, 128, 0, 0, 256, 0, 0, 0, },
-};
-
-static void
-gen7_launch_grid_l3(struct ilo_render *r, bool use_slm)
-{
- uint32_t l3sqcreg1, l3cntlreg2, l3cntlreg3;
- const struct gen7_l3_config *conf;
-
- /*
- * This function mostly follows what beignet does. I do not know why, for
- * example, CON4DCUNC should be reset. I do not know if it should be set
- * again after launch_grid().
- */
-
- ILO_DEV_ASSERT(r->dev, 7, 7.5);
-
- if (use_slm)
- conf = &gen7_l3_slm_configs[1];
- else
- conf = &gen7_l3_non_slm_configs[4];
-
- /* unset GEN7_REG_L3SQCREG1_CON4DCUNC (without readback first) */
- if (ilo_dev_gen(r->dev) >= ILO_GEN(7.5)) {
- l3sqcreg1 = GEN75_REG_L3SQCREG1_SQGPCI_24 |
- GEN75_REG_L3SQCREG1_SQHPCI_8;
- } else {
- l3sqcreg1 = GEN7_REG_L3SQCREG1_SQGHPCI_18_6;
- }
-
- l3cntlreg2 = (conf->dc / 8) << GEN7_REG_L3CNTLREG2_DCWASS__SHIFT |
- (conf->ro / 8) << GEN7_REG_L3CNTLREG2_RDOCPL__SHIFT |
- (conf->urb / 8) << GEN7_REG_L3CNTLREG2_URBALL__SHIFT;
-
- l3cntlreg3 = (conf->t / 8) << GEN7_REG_L3CNTLREG3_TXWYALL__SHIFT |
- (conf->c / 8) << GEN7_REG_L3CNTLREG3_CTWYALL__SHIFT |
- (conf->is / 8) << GEN7_REG_L3CNTLREG3_ISWYALL__SHIFT;
-
- if (conf->slm) {
- /*
- * From the Ivy Bridge PRM, volume 1 part 7, page 11:
- *
- * "Note that URB needs to be set as low b/w client in SLM mode,
- * else the hash will fail. This is a required s/w model."
- */
- l3cntlreg2 |= GEN7_REG_L3CNTLREG2_URBSLMB |
- GEN7_REG_L3CNTLREG2_SLMMENB;
- }
-
- gen6_MI_LOAD_REGISTER_IMM(r->builder, GEN7_REG_L3SQCREG1, l3sqcreg1);
- gen6_MI_LOAD_REGISTER_IMM(r->builder, GEN7_REG_L3CNTLREG2, l3cntlreg2);
- gen6_MI_LOAD_REGISTER_IMM(r->builder, GEN7_REG_L3CNTLREG3, l3cntlreg3);
-}
-
-int
-ilo_render_get_launch_grid_commands_len(const struct ilo_render *render,
- const struct ilo_state_vector *vec)
-{
- static int len;
-
- ILO_DEV_ASSERT(render->dev, 7, 7.5);
-
- if (!len) {
- len +=
- GEN6_PIPELINE_SELECT__SIZE +
- GEN6_STATE_BASE_ADDRESS__SIZE +
- GEN6_MEDIA_VFE_STATE__SIZE +
- GEN6_MEDIA_CURBE_LOAD__SIZE +
- GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD__SIZE +
- GEN6_MEDIA_STATE_FLUSH__SIZE;
-
- len += ilo_render_get_flush_len(render) * 3;
-
- if (ilo_dev_gen(render->dev) >= ILO_GEN(7)) {
- len += GEN6_MI_LOAD_REGISTER_IMM__SIZE * 3 * 2;
- len += GEN7_GPGPU_WALKER__SIZE;
- }
- }
-
- return len;
-}
-
-void
-ilo_render_emit_launch_grid_commands(struct ilo_render *render,
- const struct ilo_state_vector *vec,
- const struct ilo_render_launch_grid_session *session)
-{
- const unsigned batch_used = ilo_builder_batch_used(render->builder);
- const uint32_t pcb = render->state.cs.PUSH_CONSTANT_BUFFER;
- const int pcb_size = render->state.cs.PUSH_CONSTANT_BUFFER_size;
- int simd_size;
- bool use_slm;
-
- ILO_DEV_ASSERT(render->dev, 7, 7.5);
-
- simd_size = ilo_shader_get_kernel_param(vec->cs, ILO_KERNEL_CS_SIMD_SIZE);
- use_slm = ilo_shader_get_kernel_param(vec->cs, ILO_KERNEL_CS_LOCAL_SIZE);
-
- ilo_render_emit_flush(render);
-
- if (ilo_dev_gen(render->dev) >= ILO_GEN(7)) {
- gen7_launch_grid_l3(render, use_slm);
- ilo_render_emit_flush(render);
-
- gen6_PIPELINE_SELECT(render->builder,
- GEN7_PIPELINE_SELECT_DW0_SELECT_GPGPU);
- } else {
- gen6_PIPELINE_SELECT(render->builder,
- GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA);
- }
-
- gen6_state_base_address(render->builder, true);
-
- gen6_MEDIA_VFE_STATE(render->builder, &session->compute);
-
- if (pcb_size)
- gen6_MEDIA_CURBE_LOAD(render->builder, pcb, pcb_size);
-
- gen6_MEDIA_INTERFACE_DESCRIPTOR_LOAD(render->builder,
- session->idrt, session->idrt_size);
-
- gen7_GPGPU_WALKER(render->builder, session->thread_group_offset,
- session->thread_group_dim, session->thread_group_size, simd_size);
-
- gen6_MEDIA_STATE_FLUSH(render->builder);
-
- if (ilo_dev_gen(render->dev) >= ILO_GEN(7) && use_slm) {
- ilo_render_emit_flush(render);
- gen7_launch_grid_l3(render, false);
- }
-
- assert(ilo_builder_batch_used(render->builder) <= batch_used +
- ilo_render_get_launch_grid_commands_len(render, vec));
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "core/ilo_builder_3d.h"
-
-#include "ilo_common.h"
-#include "ilo_blitter.h"
-#include "ilo_resource.h"
-#include "ilo_shader.h"
-#include "ilo_state.h"
-#include "ilo_render_gen.h"
-
-#define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
-
-static inline uint32_t
-gen6_so_SURFACE_STATE(struct ilo_builder *builder,
- const struct pipe_stream_output_target *so,
- const struct pipe_stream_output_info *so_info,
- int so_index)
-{
- struct ilo_state_surface_buffer_info info;
- struct ilo_state_surface surf;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- memset(&info, 0, sizeof(info));
-
- info.vma = ilo_resource_get_vma(so->buffer);
- info.offset = so->buffer_offset + so_info->output[so_index].dst_offset * 4;
- info.size = so->buffer_size - so_info->output[so_index].dst_offset * 4;
-
- info.access = ILO_STATE_SURFACE_ACCESS_DP_SVB;
-
- switch (so_info->output[so_index].num_components) {
- case 1:
- info.format = GEN6_FORMAT_R32_FLOAT;
- info.format_size = 4;
- break;
- case 2:
- info.format = GEN6_FORMAT_R32G32_FLOAT;
- info.format_size = 8;
- break;
- case 3:
- info.format = GEN6_FORMAT_R32G32B32_FLOAT;
- info.format_size = 12;
- break;
- case 4:
- info.format = GEN6_FORMAT_R32G32B32A32_FLOAT;
- info.format_size = 16;
- break;
- default:
- assert(!"unexpected SO components length");
- info.format = GEN6_FORMAT_R32_FLOAT;
- info.format_size = 4;
- break;
- }
-
- info.struct_size =
- so_info->stride[so_info->output[so_index].output_buffer] * 4;
-
- memset(&surf, 0, sizeof(surf));
- ilo_state_surface_init_for_buffer(&surf, builder->dev, &info);
-
- return gen6_SURFACE_STATE(builder, &surf);
-}
-
-static void
-gen6_emit_draw_surface_rt(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- const struct ilo_shader_state *fs = vec->fs;
- const struct ilo_fb_state *fb = &vec->fb;
- uint32_t *surface_state;
- int base, count, i;
-
- ILO_DEV_ASSERT(r->dev, 6, 8);
-
- if (!DIRTY(FS) && !DIRTY(FB))
- return;
- if (!fs)
- return;
-
- session->binding_table_fs_changed = true;
-
- base = ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_SURFACE_RT_BASE);
- count = ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_SURFACE_RT_COUNT);
-
- /* SURFACE_STATEs for render targets */
- surface_state = &r->state.wm.SURFACE_STATE[base];
- for (i = 0; i < count; i++) {
- if (i < fb->state.nr_cbufs && fb->state.cbufs[i]) {
- const struct ilo_surface_cso *surface =
- (const struct ilo_surface_cso *) fb->state.cbufs[i];
-
- assert(surface->is_rt);
- surface_state[i] = gen6_SURFACE_STATE(r->builder, &surface->u.rt);
- } else {
- surface_state[i] = gen6_SURFACE_STATE(r->builder, &fb->null_rt);
- }
- }
-}
-
-static void
-gen6_emit_draw_surface_so(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- const struct ilo_shader_state *vs = vec->vs;
- const struct ilo_shader_state *gs = vec->gs;
- const struct ilo_so_state *so = &vec->so;
- const struct pipe_stream_output_info *so_info;
- uint32_t *surface_state;
- int base, count, i;
-
- ILO_DEV_ASSERT(r->dev, 6, 6);
-
- if (!DIRTY(VS) && !DIRTY(GS) && !DIRTY(SO))
- return;
-
- if (gs) {
- so_info = ilo_shader_get_kernel_so_info(gs);
- base = ilo_shader_get_kernel_param(gs,
- ILO_KERNEL_GS_GEN6_SURFACE_SO_BASE);
- count = ilo_shader_get_kernel_param(gs,
- ILO_KERNEL_GS_GEN6_SURFACE_SO_COUNT);
- } else if (vs) {
- so_info = ilo_shader_get_kernel_so_info(vs);
- base = 0;
- count = ilo_shader_get_kernel_param(vs,
- ILO_KERNEL_VS_GEN6_SO_SURFACE_COUNT);
- } else {
- return;
- }
-
- session->binding_table_gs_changed = true;
-
- /* SURFACE_STATEs for stream output targets */
- surface_state = &r->state.gs.SURFACE_STATE[base];
- for (i = 0; i < count; i++) {
- if (so_info && i < so_info->num_outputs &&
- so_info->output[i].output_buffer < so->count &&
- so->states[so_info->output[i].output_buffer]) {
- const struct pipe_stream_output_target *so_target =
- so->states[so_info->output[i].output_buffer];
-
- surface_state[i] = gen6_so_SURFACE_STATE(r->builder,
- so_target, so_info, i);
- } else {
- surface_state[i] = 0;
- }
- }
-}
-
-static void
-gen6_emit_draw_surface_view(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- int shader_type,
- struct ilo_render_draw_session *session)
-{
- const struct ilo_view_state *view = &vec->view[shader_type];
- const struct ilo_shader_state *sh;
- uint32_t *surface_state;
- int base, count, i;
-
- ILO_DEV_ASSERT(r->dev, 6, 8);
-
- switch (shader_type) {
- case PIPE_SHADER_VERTEX:
- if (!DIRTY(VS) && !DIRTY(VIEW_VS))
- return;
- if (!vec->vs)
- return;
-
- sh = vec->vs;
- surface_state = r->state.vs.SURFACE_STATE;
- session->binding_table_vs_changed = true;
- break;
- case PIPE_SHADER_FRAGMENT:
- if (!DIRTY(FS) && !DIRTY(VIEW_FS))
- return;
- if (!vec->fs)
- return;
-
- sh = vec->fs;
- surface_state = r->state.wm.SURFACE_STATE;
- session->binding_table_fs_changed = true;
- break;
- default:
- return;
- break;
- }
-
- base = ilo_shader_get_kernel_param(sh, ILO_KERNEL_SURFACE_TEX_BASE);
- count = ilo_shader_get_kernel_param(sh, ILO_KERNEL_SURFACE_TEX_COUNT);
-
- /* SURFACE_STATEs for sampler views */
- surface_state += base;
- for (i = 0; i < count; i++) {
- if (i < view->count && view->states[i]) {
- const struct ilo_view_cso *cso =
- (const struct ilo_view_cso *) view->states[i];
-
- surface_state[i] = gen6_SURFACE_STATE(r->builder, &cso->surface);
- } else {
- surface_state[i] = 0;
- }
- }
-}
-
-static void
-gen6_emit_draw_surface_const(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- int shader_type,
- struct ilo_render_draw_session *session)
-{
- const struct ilo_cbuf_state *cbuf = &vec->cbuf[shader_type];
- const struct ilo_shader_state *sh;
- uint32_t *surface_state;
- int base, count, i;
-
- ILO_DEV_ASSERT(r->dev, 6, 8);
-
- switch (shader_type) {
- case PIPE_SHADER_VERTEX:
- if (!DIRTY(VS) && !DIRTY(CBUF))
- return;
- if (!vec->vs)
- return;
-
- sh = vec->vs;
- surface_state = r->state.vs.SURFACE_STATE;
- session->binding_table_vs_changed = true;
- break;
- case PIPE_SHADER_FRAGMENT:
- if (!DIRTY(FS) && !DIRTY(CBUF))
- return;
- if (!vec->fs)
- return;
-
- sh = vec->fs;
- surface_state = r->state.wm.SURFACE_STATE;
- session->binding_table_fs_changed = true;
- break;
- default:
- return;
- break;
- }
-
- base = ilo_shader_get_kernel_param(sh, ILO_KERNEL_SURFACE_CONST_BASE);
- count = ilo_shader_get_kernel_param(sh, ILO_KERNEL_SURFACE_CONST_COUNT);
-
- /* SURFACE_STATEs for constant buffers */
- surface_state += base;
- for (i = 0; i < count; i++) {
- const struct ilo_cbuf_cso *cso = &cbuf->cso[i];
-
- if (cso->resource)
- surface_state[i] = gen6_SURFACE_STATE(r->builder, &cso->surface);
- else
- surface_state[i] = 0;
- }
-}
-
-static void
-gen6_emit_draw_surface_binding_tables(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- int shader_type,
- struct ilo_render_draw_session *session)
-{
- int count;
-
- ILO_DEV_ASSERT(r->dev, 6, 8);
-
- /* BINDING_TABLE_STATE */
- switch (shader_type) {
- case PIPE_SHADER_VERTEX:
- if (!session->binding_table_vs_changed)
- return;
- if (!vec->vs)
- return;
-
- count = ilo_shader_get_kernel_param(vec->vs,
- ILO_KERNEL_SURFACE_TOTAL_COUNT);
-
- r->state.vs.BINDING_TABLE_STATE = gen6_BINDING_TABLE_STATE(r->builder,
- r->state.vs.SURFACE_STATE, count);
- break;
- case PIPE_SHADER_GEOMETRY:
- if (!session->binding_table_gs_changed)
- return;
- if (vec->gs) {
- count = ilo_shader_get_kernel_param(vec->gs,
- ILO_KERNEL_SURFACE_TOTAL_COUNT);
- } else if (ilo_dev_gen(r->dev) == ILO_GEN(6) && vec->vs) {
- count = ilo_shader_get_kernel_param(vec->vs,
- ILO_KERNEL_VS_GEN6_SO_SURFACE_COUNT);
- } else {
- return;
- }
-
- r->state.gs.BINDING_TABLE_STATE = gen6_BINDING_TABLE_STATE(r->builder,
- r->state.gs.SURFACE_STATE, count);
- break;
- case PIPE_SHADER_FRAGMENT:
- if (!session->binding_table_fs_changed)
- return;
- if (!vec->fs)
- return;
-
- count = ilo_shader_get_kernel_param(vec->fs,
- ILO_KERNEL_SURFACE_TOTAL_COUNT);
-
- r->state.wm.BINDING_TABLE_STATE = gen6_BINDING_TABLE_STATE(r->builder,
- r->state.wm.SURFACE_STATE, count);
- break;
- default:
- break;
- }
-}
-
-#undef DIRTY
-
-int
-ilo_render_get_draw_surface_states_len(const struct ilo_render *render,
- const struct ilo_state_vector *vec)
-{
- int sh_type, len;
-
- ILO_DEV_ASSERT(render->dev, 6, 8);
-
- len = 0;
-
- for (sh_type = 0; sh_type < PIPE_SHADER_TYPES; sh_type++) {
- const int alignment =
- (ilo_dev_gen(render->dev) >= ILO_GEN(8) ? 64 : 32) / 4;
- int num_surfaces = 0;
-
- switch (sh_type) {
- case PIPE_SHADER_VERTEX:
- if (vec->vs) {
- num_surfaces = ilo_shader_get_kernel_param(vec->vs,
- ILO_KERNEL_SURFACE_TOTAL_COUNT);
-
- if (ilo_dev_gen(render->dev) == ILO_GEN(6)) {
- num_surfaces += ilo_shader_get_kernel_param(vec->vs,
- ILO_KERNEL_VS_GEN6_SO_SURFACE_COUNT);
- }
- }
- break;
- case PIPE_SHADER_GEOMETRY:
- if (vec->gs) {
- num_surfaces = ilo_shader_get_kernel_param(vec->gs,
- ILO_KERNEL_SURFACE_TOTAL_COUNT);
- }
- break;
- case PIPE_SHADER_FRAGMENT:
- if (vec->fs) {
- num_surfaces = ilo_shader_get_kernel_param(vec->fs,
- ILO_KERNEL_SURFACE_TOTAL_COUNT);
- }
- break;
- default:
- break;
- }
-
- /* BINDING_TABLE_STATE and SURFACE_STATEs */
- if (num_surfaces) {
- len += align(num_surfaces, alignment) +
- align(GEN6_SURFACE_STATE__SIZE, alignment) * num_surfaces;
- }
- }
-
- return len;
-}
-
-void
-ilo_render_emit_draw_surface_states(struct ilo_render *render,
- const struct ilo_state_vector *vec,
- struct ilo_render_draw_session *session)
-{
- const unsigned surface_used = ilo_builder_surface_used(render->builder);
- int shader_type;
-
- ILO_DEV_ASSERT(render->dev, 6, 8);
-
- /*
- * upload all SURAFCE_STATEs together so that we know there are minimal
- * paddings
- */
-
- gen6_emit_draw_surface_rt(render, vec, session);
-
- if (ilo_dev_gen(render->dev) == ILO_GEN(6))
- gen6_emit_draw_surface_so(render, vec, session);
-
- for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
- gen6_emit_draw_surface_view(render, vec, shader_type, session);
- gen6_emit_draw_surface_const(render, vec, shader_type, session);
- }
-
- /* this must be called after all SURFACE_STATEs have been uploaded */
- for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
- gen6_emit_draw_surface_binding_tables(render, vec,
- shader_type, session);
- }
-
- assert(ilo_builder_surface_used(render->builder) <= surface_used +
- ilo_render_get_draw_surface_states_len(render, vec));
-}
-
-static void
-gen6_emit_launch_grid_surface_view(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_launch_grid_session *session)
-{
- const struct ilo_shader_state *cs = vec->cs;
- const struct ilo_view_state *view = &vec->view[PIPE_SHADER_COMPUTE];
- uint32_t *surface_state = r->state.cs.SURFACE_STATE;
- int base, count, i;
-
- ILO_DEV_ASSERT(r->dev, 7, 7.5);
-
- base = ilo_shader_get_kernel_param(cs, ILO_KERNEL_SURFACE_TEX_BASE);
- count = ilo_shader_get_kernel_param(cs, ILO_KERNEL_SURFACE_TEX_COUNT);
-
- /* SURFACE_STATEs for sampler views */
- surface_state += base;
- for (i = 0; i < count; i++) {
- if (i < view->count && view->states[i]) {
- const struct ilo_view_cso *cso =
- (const struct ilo_view_cso *) view->states[i];
-
- surface_state[i] = gen6_SURFACE_STATE(r->builder, &cso->surface);
- } else {
- surface_state[i] = 0;
- }
- }
-}
-
-static void
-gen6_emit_launch_grid_surface_const(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_launch_grid_session *session)
-{
- const struct ilo_shader_state *cs = vec->cs;
- uint32_t *surface_state = r->state.cs.SURFACE_STATE;
- struct ilo_state_surface_buffer_info info;
- struct ilo_state_surface surf;
- int base, count;
-
- ILO_DEV_ASSERT(r->dev, 7, 7.5);
-
- base = ilo_shader_get_kernel_param(cs, ILO_KERNEL_SURFACE_CONST_BASE);
- count = ilo_shader_get_kernel_param(cs, ILO_KERNEL_SURFACE_CONST_COUNT);
-
- if (!count)
- return;
-
- memset(&info, 0, sizeof(info));
-
- info.vma = ilo_resource_get_vma(session->input->buffer);
- info.offset = session->input->buffer_offset;
- info.size = session->input->buffer_size;
-
- info.access = ILO_STATE_SURFACE_ACCESS_DP_UNTYPED;
- info.format = GEN6_FORMAT_RAW;
- info.format_size = 1;
- info.struct_size = 1;
- info.readonly = true;
-
- memset(&surf, 0, sizeof(surf));
- ilo_state_surface_init_for_buffer(&surf, r->dev, &info);
-
- assert(count == 1 && session->input->buffer);
- surface_state[base] = gen6_SURFACE_STATE(r->builder, &surf);
-}
-
-static void
-gen6_emit_launch_grid_surface_cs_resource(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_launch_grid_session *session)
-{
- ILO_DEV_ASSERT(r->dev, 7, 7.5);
-
- /* TODO */
- assert(!vec->cs_resource.count);
-}
-
-static void
-gen6_emit_launch_grid_surface_global(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_launch_grid_session *session)
-{
- const struct ilo_shader_state *cs = vec->cs;
- const struct ilo_global_binding_cso *bindings =
- util_dynarray_begin(&vec->global_binding.bindings);
- uint32_t *surface_state = r->state.cs.SURFACE_STATE;
- int base, count, i;
-
- ILO_DEV_ASSERT(r->dev, 7, 7.5);
-
- base = ilo_shader_get_kernel_param(cs, ILO_KERNEL_CS_SURFACE_GLOBAL_BASE);
- count = ilo_shader_get_kernel_param(cs, ILO_KERNEL_CS_SURFACE_GLOBAL_COUNT);
-
- if (!count)
- return;
-
- if (base + count > ARRAY_SIZE(r->state.cs.SURFACE_STATE)) {
- ilo_warn("too many global bindings\n");
- count = ARRAY_SIZE(r->state.cs.SURFACE_STATE) - base;
- }
-
- /* SURFACE_STATEs for global bindings */
- surface_state += base;
- for (i = 0; i < count; i++) {
- if (i < vec->global_binding.count && bindings[i].resource) {
- struct ilo_state_surface_buffer_info info;
- struct ilo_state_surface surf;
-
- assert(bindings[i].resource->target == PIPE_BUFFER);
-
- memset(&info, 0, sizeof(info));
-
- info.vma = ilo_resource_get_vma(bindings[i].resource);
- info.size = info.vma->vm_size;
-
- info.access = ILO_STATE_SURFACE_ACCESS_DP_UNTYPED;
- info.format = GEN6_FORMAT_RAW;
- info.format_size = 1;
- info.struct_size = 1;
-
- memset(&surf, 0, sizeof(surf));
- ilo_state_surface_init_for_buffer(&surf, r->dev, &info);
-
- surface_state[i] = gen6_SURFACE_STATE(r->builder, &surf);
- } else {
- surface_state[i] = 0;
- }
- }
-}
-
-static void
-gen6_emit_launch_grid_surface_binding_table(struct ilo_render *r,
- const struct ilo_state_vector *vec,
- struct ilo_render_launch_grid_session *session)
-{
- const struct ilo_shader_state *cs = vec->cs;
- int count;
-
- ILO_DEV_ASSERT(r->dev, 7, 7.5);
-
- count = ilo_shader_get_kernel_param(cs, ILO_KERNEL_SURFACE_TOTAL_COUNT);
- if (count) {
- r->state.cs.BINDING_TABLE_STATE = gen6_BINDING_TABLE_STATE(r->builder,
- r->state.cs.SURFACE_STATE, count);
- }
-}
-
-int
-ilo_render_get_launch_grid_surface_states_len(const struct ilo_render *render,
- const struct ilo_state_vector *vec)
-{
- const int alignment = 32 / 4;
- int num_surfaces;
- int len = 0;
-
- ILO_DEV_ASSERT(render->dev, 7, 7.5);
-
- num_surfaces = ilo_shader_get_kernel_param(vec->cs,
- ILO_KERNEL_SURFACE_TOTAL_COUNT);
-
- /* BINDING_TABLE_STATE and SURFACE_STATEs */
- if (num_surfaces) {
- len += align(num_surfaces, alignment) +
- align(GEN6_SURFACE_STATE__SIZE, alignment) * num_surfaces;
- }
-
- return len;
-}
-
-void
-ilo_render_emit_launch_grid_surface_states(struct ilo_render *render,
- const struct ilo_state_vector *vec,
- struct ilo_render_launch_grid_session *session)
-{
- const unsigned surface_used = ilo_builder_surface_used(render->builder);
-
- ILO_DEV_ASSERT(render->dev, 7, 7.5);
-
- /* idrt depends on the binding table */
- assert(!session->idrt_size);
-
- gen6_emit_launch_grid_surface_view(render, vec, session);
- gen6_emit_launch_grid_surface_const(render, vec, session);
- gen6_emit_launch_grid_surface_cs_resource(render, vec, session);
- gen6_emit_launch_grid_surface_global(render, vec, session);
- gen6_emit_launch_grid_surface_binding_table(render, vec, session);
-
- assert(ilo_builder_surface_used(render->builder) <= surface_used +
- ilo_render_get_launch_grid_surface_states_len(render, vec));
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "core/ilo_state_vf.h"
-#include "core/ilo_state_sol.h"
-#include "core/ilo_state_surface.h"
-
-#include "ilo_screen.h"
-#include "ilo_format.h"
-#include "ilo_resource.h"
-
-/*
- * From the Ivy Bridge PRM, volume 1 part 1, page 105:
- *
- * "In addition to restrictions on maximum height, width, and depth,
- * surfaces are also restricted to a maximum size in bytes. This
- * maximum is 2 GB for all products and all surface types."
- */
-static const size_t ilo_max_resource_size = 1u << 31;
-
-static const char *
-resource_get_bo_name(const struct pipe_resource *templ)
-{
- static const char *target_names[PIPE_MAX_TEXTURE_TYPES] = {
- [PIPE_BUFFER] = "buf",
- [PIPE_TEXTURE_1D] = "tex-1d",
- [PIPE_TEXTURE_2D] = "tex-2d",
- [PIPE_TEXTURE_3D] = "tex-3d",
- [PIPE_TEXTURE_CUBE] = "tex-cube",
- [PIPE_TEXTURE_RECT] = "tex-rect",
- [PIPE_TEXTURE_1D_ARRAY] = "tex-1d-array",
- [PIPE_TEXTURE_2D_ARRAY] = "tex-2d-array",
- [PIPE_TEXTURE_CUBE_ARRAY] = "tex-cube-array",
- };
- const char *name = target_names[templ->target];
-
- if (templ->target == PIPE_BUFFER) {
- switch (templ->bind) {
- case PIPE_BIND_VERTEX_BUFFER:
- name = "buf-vb";
- break;
- case PIPE_BIND_INDEX_BUFFER:
- name = "buf-ib";
- break;
- case PIPE_BIND_CONSTANT_BUFFER:
- name = "buf-cb";
- break;
- case PIPE_BIND_STREAM_OUTPUT:
- name = "buf-so";
- break;
- default:
- break;
- }
- }
-
- return name;
-}
-
-static bool
-resource_get_cpu_init(const struct pipe_resource *templ)
-{
- return (templ->bind & (PIPE_BIND_DEPTH_STENCIL |
- PIPE_BIND_RENDER_TARGET |
- PIPE_BIND_STREAM_OUTPUT)) ? false : true;
-}
-
-static enum gen_surface_type
-get_surface_type(enum pipe_texture_target target)
-{
- switch (target) {
- case PIPE_TEXTURE_1D:
- case PIPE_TEXTURE_1D_ARRAY:
- return GEN6_SURFTYPE_1D;
- case PIPE_TEXTURE_2D:
- case PIPE_TEXTURE_RECT:
- case PIPE_TEXTURE_2D_ARRAY:
- return GEN6_SURFTYPE_2D;
- case PIPE_TEXTURE_3D:
- return GEN6_SURFTYPE_3D;
- case PIPE_TEXTURE_CUBE:
- case PIPE_TEXTURE_CUBE_ARRAY:
- return GEN6_SURFTYPE_CUBE;
- default:
- assert(!"unknown texture target");
- return GEN6_SURFTYPE_NULL;
- }
-}
-
-static enum pipe_format
-resource_get_image_format(const struct pipe_resource *templ,
- const struct ilo_dev *dev,
- bool *separate_stencil_ret)
-{
- enum pipe_format format = templ->format;
- bool separate_stencil;
-
- /* silently promote ETC1 */
- if (templ->format == PIPE_FORMAT_ETC1_RGB8)
- format = PIPE_FORMAT_R8G8B8X8_UNORM;
-
- /* separate stencil buffers */
- separate_stencil = false;
- if ((templ->bind & PIPE_BIND_DEPTH_STENCIL) &&
- util_format_is_depth_and_stencil(templ->format)) {
- switch (templ->format) {
- case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
- /* Gen6 requires HiZ to be available for all levels */
- if (ilo_dev_gen(dev) >= ILO_GEN(7) || templ->last_level == 0) {
- format = PIPE_FORMAT_Z32_FLOAT;
- separate_stencil = true;
- }
- break;
- case PIPE_FORMAT_Z24_UNORM_S8_UINT:
- format = PIPE_FORMAT_Z24X8_UNORM;
- separate_stencil = true;
- break;
- default:
- break;
- }
- }
-
- if (separate_stencil_ret)
- *separate_stencil_ret = separate_stencil;
-
- return format;
-}
-
-static inline enum gen_surface_format
-pipe_to_surface_format(const struct ilo_dev *dev, enum pipe_format format)
-{
- switch (format) {
- case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
- return GEN6_FORMAT_R32_FLOAT_X8X24_TYPELESS;
- case PIPE_FORMAT_Z32_FLOAT:
- return GEN6_FORMAT_R32_FLOAT;
- case PIPE_FORMAT_Z24_UNORM_S8_UINT:
- case PIPE_FORMAT_Z24X8_UNORM:
- return GEN6_FORMAT_R24_UNORM_X8_TYPELESS;
- case PIPE_FORMAT_Z16_UNORM:
- return GEN6_FORMAT_R16_UNORM;
- case PIPE_FORMAT_S8_UINT:
- return GEN6_FORMAT_R8_UINT;
- default:
- return ilo_format_translate_color(dev, format);
- }
-}
-
-static void
-resource_get_image_info(const struct pipe_resource *templ,
- const struct ilo_dev *dev,
- enum pipe_format image_format,
- struct ilo_image_info *info)
-{
- memset(info, 0, sizeof(*info));
-
- info->type = get_surface_type(templ->target);
-
- info->format = pipe_to_surface_format(dev, image_format);
- info->interleaved_stencil = util_format_is_depth_and_stencil(image_format);
- info->is_integer = util_format_is_pure_integer(image_format);
- info->compressed = util_format_is_compressed(image_format);
- info->block_width = util_format_get_blockwidth(image_format);
- info->block_height = util_format_get_blockheight(image_format);
- info->block_size = util_format_get_blocksize(image_format);
-
- info->width = templ->width0;
- info->height = templ->height0;
- info->depth = templ->depth0;
- info->array_size = templ->array_size;
- info->level_count = templ->last_level + 1;
- info->sample_count = (templ->nr_samples) ? templ->nr_samples : 1;
-
- info->aux_disable = (templ->usage == PIPE_USAGE_STAGING);
-
- if (templ->bind & PIPE_BIND_LINEAR)
- info->valid_tilings = 1 << GEN6_TILING_NONE;
-
- /*
- * Tiled images must be mapped via GTT to get a linear view. Prefer linear
- * images when the image size is greater than one-fourth of the mappable
- * aperture.
- */
- if (templ->usage == PIPE_USAGE_STAGING)
- info->prefer_linear_threshold = dev->aperture_mappable / 4;
-
- info->bind_surface_sampler = (templ->bind & PIPE_BIND_SAMPLER_VIEW);
- info->bind_surface_dp_render = (templ->bind & PIPE_BIND_RENDER_TARGET);
- info->bind_surface_dp_typed = (templ->bind &
- (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_COMPUTE_RESOURCE));
- info->bind_zs = (templ->bind & PIPE_BIND_DEPTH_STENCIL);
- info->bind_scanout = (templ->bind & PIPE_BIND_SCANOUT);
- info->bind_cursor = (templ->bind & PIPE_BIND_CURSOR);
-}
-
-static enum gen_surface_tiling
-winsys_to_surface_tiling(enum intel_tiling_mode tiling)
-{
- switch (tiling) {
- case INTEL_TILING_NONE:
- return GEN6_TILING_NONE;
- case INTEL_TILING_X:
- return GEN6_TILING_X;
- case INTEL_TILING_Y:
- return GEN6_TILING_Y;
- default:
- assert(!"unknown tiling");
- return GEN6_TILING_NONE;
- }
-}
-
-static inline enum intel_tiling_mode
-surface_to_winsys_tiling(enum gen_surface_tiling tiling)
-{
- switch (tiling) {
- case GEN6_TILING_NONE:
- return INTEL_TILING_NONE;
- case GEN6_TILING_X:
- return INTEL_TILING_X;
- case GEN6_TILING_Y:
- return INTEL_TILING_Y;
- default:
- assert(!"unknown tiling");
- return GEN6_TILING_NONE;
- }
-}
-
-static void
-tex_free_slices(struct ilo_texture *tex)
-{
- FREE(tex->slices[0]);
-}
-
-static bool
-tex_alloc_slices(struct ilo_texture *tex)
-{
- const struct pipe_resource *templ = &tex->base;
- struct ilo_texture_slice *slices;
- int depth, lv;
-
- /* sum the depths of all levels */
- depth = 0;
- for (lv = 0; lv <= templ->last_level; lv++)
- depth += u_minify(templ->depth0, lv);
-
- /*
- * There are (depth * tex->base.array_size) slices in total. Either depth
- * is one (non-3D) or templ->array_size is one (non-array), but it does
- * not matter.
- */
- slices = CALLOC(depth * templ->array_size, sizeof(*slices));
- if (!slices)
- return false;
-
- tex->slices[0] = slices;
-
- /* point to the respective positions in the buffer */
- for (lv = 1; lv <= templ->last_level; lv++) {
- tex->slices[lv] = tex->slices[lv - 1] +
- u_minify(templ->depth0, lv - 1) * templ->array_size;
- }
-
- return true;
-}
-
-static bool
-tex_create_bo(struct ilo_texture *tex)
-{
- struct ilo_screen *is = ilo_screen(tex->base.screen);
- const char *name = resource_get_bo_name(&tex->base);
- const bool cpu_init = resource_get_cpu_init(&tex->base);
- struct intel_bo *bo;
-
- bo = intel_winsys_alloc_bo(is->dev.winsys, name,
- tex->image.bo_stride * tex->image.bo_height, cpu_init);
-
- /* set the tiling for transfer and export */
- if (bo && (tex->image.tiling == GEN6_TILING_X ||
- tex->image.tiling == GEN6_TILING_Y)) {
- const enum intel_tiling_mode tiling =
- surface_to_winsys_tiling(tex->image.tiling);
-
- if (intel_bo_set_tiling(bo, tiling, tex->image.bo_stride)) {
- intel_bo_unref(bo);
- bo = NULL;
- }
- }
- if (!bo)
- return false;
-
- intel_bo_unref(tex->vma.bo);
- ilo_vma_set_bo(&tex->vma, &is->dev, bo, 0);
-
- return true;
-}
-
-static bool
-tex_create_separate_stencil(struct ilo_texture *tex)
-{
- struct pipe_resource templ = tex->base;
- struct pipe_resource *s8;
-
- /*
- * Unless PIPE_BIND_DEPTH_STENCIL is set, the resource may have other
- * tilings. But that should be fine since it will never be bound as the
- * stencil buffer, and our transfer code can handle all tilings.
- */
- templ.format = PIPE_FORMAT_S8_UINT;
-
- /* no stencil texturing */
- templ.bind &= ~PIPE_BIND_SAMPLER_VIEW;
-
- s8 = tex->base.screen->resource_create(tex->base.screen, &templ);
- if (!s8)
- return false;
-
- tex->separate_s8 = ilo_texture(s8);
-
- assert(tex->separate_s8->image_format == PIPE_FORMAT_S8_UINT);
-
- return true;
-}
-
-static bool
-tex_create_hiz(struct ilo_texture *tex)
-{
- const struct pipe_resource *templ = &tex->base;
- const uint32_t size = tex->image.aux.bo_stride * tex->image.aux.bo_height;
- struct ilo_screen *is = ilo_screen(tex->base.screen);
- struct intel_bo *bo;
-
- bo = intel_winsys_alloc_bo(is->dev.winsys, "hiz texture", size, false);
- if (!bo)
- return false;
-
- ilo_vma_init(&tex->aux_vma, &is->dev, size, 4096);
- ilo_vma_set_bo(&tex->aux_vma, &is->dev, bo, 0);
-
- if (tex->imported) {
- unsigned lv;
-
- for (lv = 0; lv <= templ->last_level; lv++) {
- if (tex->image.aux.enables & (1 << lv)) {
- const unsigned num_slices = (templ->target == PIPE_TEXTURE_3D) ?
- u_minify(templ->depth0, lv) : templ->array_size;
- /* this will trigger HiZ resolves */
- const unsigned flags = ILO_TEXTURE_CPU_WRITE;
-
- ilo_texture_set_slice_flags(tex, lv, 0, num_slices, flags, flags);
- }
- }
- }
-
- return true;
-}
-
-static bool
-tex_create_mcs(struct ilo_texture *tex)
-{
- const uint32_t size = tex->image.aux.bo_stride * tex->image.aux.bo_height;
- struct ilo_screen *is = ilo_screen(tex->base.screen);
- struct intel_bo *bo;
-
- assert(tex->image.aux.enables == (1 << (tex->base.last_level + 1)) - 1);
-
- bo = intel_winsys_alloc_bo(is->dev.winsys, "mcs texture", size, false);
- if (!bo)
- return false;
-
- ilo_vma_init(&tex->aux_vma, &is->dev, size, 4096);
- ilo_vma_set_bo(&tex->aux_vma, &is->dev, bo, 0);
-
- return true;
-}
-
-static void
-tex_destroy(struct ilo_texture *tex)
-{
- if (tex->separate_s8)
- tex_destroy(tex->separate_s8);
-
- intel_bo_unref(tex->vma.bo);
- intel_bo_unref(tex->aux_vma.bo);
-
- tex_free_slices(tex);
- FREE(tex);
-}
-
-static bool
-tex_alloc_bos(struct ilo_texture *tex)
-{
- if (!tex->imported && !tex_create_bo(tex))
- return false;
-
- switch (tex->image.aux.type) {
- case ILO_IMAGE_AUX_HIZ:
- if (!tex_create_hiz(tex))
- return false;
- break;
- case ILO_IMAGE_AUX_MCS:
- if (!tex_create_mcs(tex))
- return false;
- break;
- default:
- break;
- }
-
- return true;
-}
-
-static struct intel_bo *
-tex_import_handle(struct ilo_texture *tex,
- const struct winsys_handle *handle,
- struct ilo_image_info *info)
-{
- struct ilo_screen *is = ilo_screen(tex->base.screen);
- const struct pipe_resource *templ = &tex->base;
- const char *name = resource_get_bo_name(&tex->base);
- enum intel_tiling_mode tiling;
- unsigned long pitch;
- struct intel_bo *bo;
-
- bo = intel_winsys_import_handle(is->dev.winsys, name, handle,
- tex->image.bo_height, &tiling, &pitch);
- /* modify image info */
- if (bo) {
- const uint8_t valid_tilings = 1 << winsys_to_surface_tiling(tiling);
-
- if (info->valid_tilings && !(info->valid_tilings & valid_tilings)) {
- intel_bo_unref(bo);
- return NULL;
- }
-
- info->valid_tilings = valid_tilings;
- info->force_bo_stride = pitch;
-
- /* assume imported RTs are also scanouts */
- if (!info->bind_scanout)
- info->bind_scanout = (templ->usage & PIPE_BIND_RENDER_TARGET);
- }
-
- return bo;
-}
-
-static bool
-tex_init_image(struct ilo_texture *tex,
- const struct winsys_handle *handle,
- bool *separate_stencil)
-{
- struct ilo_screen *is = ilo_screen(tex->base.screen);
- const struct pipe_resource *templ = &tex->base;
- struct ilo_image *img = &tex->image;
- struct intel_bo *imported_bo = NULL;
- struct ilo_image_info info;
-
- tex->image_format = resource_get_image_format(templ,
- &is->dev, separate_stencil);
- resource_get_image_info(templ, &is->dev, tex->image_format, &info);
-
- if (handle) {
- imported_bo = tex_import_handle(tex, handle, &info);
- if (!imported_bo)
- return false;
- }
-
- if (!ilo_image_init(img, &is->dev, &info)) {
- intel_bo_unref(imported_bo);
- return false;
- }
-
- /*
- * HiZ requires 8x4 alignment and some levels might need HiZ disabled. It
- * is generally fine except on Gen6, where HiZ and separate stencil must be
- * enabled together. For PIPE_FORMAT_Z24X8_UNORM with separate stencil, we
- * can live with stencil values being interleaved for levels where HiZ is
- * disabled. But it is not the case for PIPE_FORMAT_Z32_FLOAT with
- * separate stencil. If HiZ was disabled for a level, we had to change the
- * format to PIPE_FORMAT_Z32_FLOAT_S8X24_UINT for the level and that format
- * had a different bpp. In other words, HiZ has to be available for all
- * levels.
- */
- if (ilo_dev_gen(&is->dev) == ILO_GEN(6) &&
- templ->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT &&
- tex->image_format == PIPE_FORMAT_Z32_FLOAT &&
- img->aux.enables != (1 << templ->last_level)) {
- tex->image_format = templ->format;
- info.format = pipe_to_surface_format(&is->dev, tex->image_format);
- info.interleaved_stencil = true;
-
- memset(img, 0, sizeof(*img));
- if (!ilo_image_init(img, &is->dev, &info)) {
- intel_bo_unref(imported_bo);
- return false;
- }
- }
-
- if (img->bo_height > ilo_max_resource_size / img->bo_stride ||
- !ilo_vma_init(&tex->vma, &is->dev, img->bo_stride * img->bo_height,
- 4096)) {
- intel_bo_unref(imported_bo);
- return false;
- }
-
- if (imported_bo) {
- ilo_vma_set_bo(&tex->vma, &is->dev, imported_bo, 0);
- tex->imported = true;
- }
-
- if (templ->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT) {
- /* require on-the-fly tiling/untiling or format conversion */
- if (img->tiling == GEN8_TILING_W || *separate_stencil ||
- tex->image_format != templ->format)
- return false;
- }
-
- if (!tex_alloc_slices(tex))
- return false;
-
- return true;
-}
-
-static struct pipe_resource *
-tex_create(struct pipe_screen *screen,
- const struct pipe_resource *templ,
- const struct winsys_handle *handle)
-{
- struct ilo_texture *tex;
- bool separate_stencil;
-
- tex = CALLOC_STRUCT(ilo_texture);
- if (!tex)
- return NULL;
-
- tex->base = *templ;
- tex->base.screen = screen;
- pipe_reference_init(&tex->base.reference, 1);
-
- if (!tex_init_image(tex, handle, &separate_stencil)) {
- FREE(tex);
- return NULL;
- }
-
- if (!tex_alloc_bos(tex) ||
- (separate_stencil && !tex_create_separate_stencil(tex))) {
- tex_destroy(tex);
- return NULL;
- }
-
- return &tex->base;
-}
-
-static bool
-tex_get_handle(struct ilo_texture *tex, struct winsys_handle *handle)
-{
- struct ilo_screen *is = ilo_screen(tex->base.screen);
- enum intel_tiling_mode tiling;
- int err;
-
- /* must match what tex_create_bo() sets */
- if (tex->image.tiling == GEN8_TILING_W)
- tiling = INTEL_TILING_NONE;
- else
- tiling = surface_to_winsys_tiling(tex->image.tiling);
-
- err = intel_winsys_export_handle(is->dev.winsys, tex->vma.bo, tiling,
- tex->image.bo_stride, tex->image.bo_height, handle);
-
- return !err;
-}
-
-static bool
-buf_create_bo(struct ilo_buffer_resource *buf)
-{
- struct ilo_screen *is = ilo_screen(buf->base.screen);
- const char *name = resource_get_bo_name(&buf->base);
- const bool cpu_init = resource_get_cpu_init(&buf->base);
- struct intel_bo *bo;
-
- bo = intel_winsys_alloc_bo(is->dev.winsys, name, buf->bo_size, cpu_init);
- if (!bo)
- return false;
-
- intel_bo_unref(buf->vma.bo);
- ilo_vma_set_bo(&buf->vma, &is->dev, bo, 0);
-
- return true;
-}
-
-static void
-buf_destroy(struct ilo_buffer_resource *buf)
-{
- intel_bo_unref(buf->vma.bo);
- FREE(buf);
-}
-
-static struct pipe_resource *
-buf_create(struct pipe_screen *screen, const struct pipe_resource *templ)
-{
- const struct ilo_screen *is = ilo_screen(screen);
- struct ilo_buffer_resource *buf;
- uint32_t alignment;
- unsigned size;
-
- buf = CALLOC_STRUCT(ilo_buffer_resource);
- if (!buf)
- return NULL;
-
- buf->base = *templ;
- buf->base.screen = screen;
- pipe_reference_init(&buf->base.reference, 1);
-
- size = templ->width0;
-
- /*
- * As noted in ilo_format_translate(), we treat some 3-component formats as
- * 4-component formats to work around hardware limitations. Imagine the
- * case where the vertex buffer holds a single PIPE_FORMAT_R16G16B16_FLOAT
- * vertex, and buf->bo_size is 6. The hardware would fail to fetch it at
- * boundary check because the vertex buffer is expected to hold a
- * PIPE_FORMAT_R16G16B16A16_FLOAT vertex and that takes at least 8 bytes.
- *
- * For the workaround to work, we should add 2 to the bo size. But that
- * would waste a page when the bo size is already page aligned. Let's
- * round it to page size for now and revisit this when needed.
- */
- if ((templ->bind & PIPE_BIND_VERTEX_BUFFER) &&
- ilo_dev_gen(&is->dev) < ILO_GEN(7.5))
- size = align(size, 4096);
-
- if (templ->bind & PIPE_BIND_VERTEX_BUFFER)
- size = ilo_state_vertex_buffer_size(&is->dev, size, &alignment);
- if (templ->bind & PIPE_BIND_INDEX_BUFFER)
- size = ilo_state_index_buffer_size(&is->dev, size, &alignment);
- if (templ->bind & PIPE_BIND_STREAM_OUTPUT)
- size = ilo_state_sol_buffer_size(&is->dev, size, &alignment);
-
- buf->bo_size = size;
- ilo_vma_init(&buf->vma, &is->dev, buf->bo_size, 4096);
-
- if (buf->bo_size < templ->width0 || buf->bo_size > ilo_max_resource_size ||
- !buf_create_bo(buf)) {
- FREE(buf);
- return NULL;
- }
-
- return &buf->base;
-}
-
-static boolean
-ilo_can_create_resource(struct pipe_screen *screen,
- const struct pipe_resource *templ)
-{
- struct ilo_screen *is = ilo_screen(screen);
- enum pipe_format image_format;
- struct ilo_image_info info;
- struct ilo_image img;
-
- if (templ->target == PIPE_BUFFER)
- return (templ->width0 <= ilo_max_resource_size);
-
- image_format = resource_get_image_format(templ, &is->dev, NULL);
- resource_get_image_info(templ, &is->dev, image_format, &info);
-
- memset(&img, 0, sizeof(img));
- ilo_image_init(&img, &ilo_screen(screen)->dev, &info);
-
- /* as in tex_init_image() */
- if (ilo_dev_gen(&is->dev) == ILO_GEN(6) &&
- templ->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT &&
- image_format == PIPE_FORMAT_Z32_FLOAT &&
- img.aux.enables != (1 << templ->last_level)) {
- info.format = pipe_to_surface_format(&is->dev, templ->format);
- info.interleaved_stencil = true;
- memset(&img, 0, sizeof(img));
- ilo_image_init(&img, &ilo_screen(screen)->dev, &info);
- }
-
- return (img.bo_height <= ilo_max_resource_size / img.bo_stride);
-}
-
-static struct pipe_resource *
-ilo_resource_create(struct pipe_screen *screen,
- const struct pipe_resource *templ)
-{
- if (templ->target == PIPE_BUFFER)
- return buf_create(screen, templ);
- else
- return tex_create(screen, templ, NULL);
-}
-
-static struct pipe_resource *
-ilo_resource_from_handle(struct pipe_screen *screen,
- const struct pipe_resource *templ,
- struct winsys_handle *handle,
- unsigned usage)
-{
- if (templ->target == PIPE_BUFFER)
- return NULL;
- else
- return tex_create(screen, templ, handle);
-}
-
-static boolean
-ilo_resource_get_handle(struct pipe_screen *screen,
- struct pipe_context *ctx,
- struct pipe_resource *res,
- struct winsys_handle *handle,
- unsigned usage)
-{
- if (res->target == PIPE_BUFFER)
- return false;
- else
- return tex_get_handle(ilo_texture(res), handle);
-
-}
-
-static void
-ilo_resource_destroy(struct pipe_screen *screen,
- struct pipe_resource *res)
-{
- if (res->target == PIPE_BUFFER)
- buf_destroy((struct ilo_buffer_resource *) res);
- else
- tex_destroy(ilo_texture(res));
-}
-
-/**
- * Initialize resource-related functions.
- */
-void
-ilo_init_resource_functions(struct ilo_screen *is)
-{
- is->base.can_create_resource = ilo_can_create_resource;
- is->base.resource_create = ilo_resource_create;
- is->base.resource_from_handle = ilo_resource_from_handle;
- is->base.resource_get_handle = ilo_resource_get_handle;
- is->base.resource_destroy = ilo_resource_destroy;
-}
-
-bool
-ilo_resource_rename_bo(struct pipe_resource *res)
-{
- if (res->target == PIPE_BUFFER) {
- return buf_create_bo((struct ilo_buffer_resource *) res);
- } else {
- struct ilo_texture *tex = ilo_texture(res);
-
- /* an imported texture cannot be renamed */
- if (tex->imported)
- return false;
-
- return tex_create_bo(tex);
- }
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_RESOURCE_H
-#define ILO_RESOURCE_H
-
-#include "core/intel_winsys.h"
-#include "core/ilo_image.h"
-#include "core/ilo_vma.h"
-
-#include "ilo_common.h"
-#include "ilo_screen.h"
-
-enum ilo_texture_flags {
- /*
- * Possible writers of a texture. There can be at most one writer at any
- * time.
- *
- * Wine set in resolve flags (in ilo_blit_resolve_slices()), they indicate
- * the new writer. When set in slice flags (ilo_texture_slice::flags),
- * they indicate the writer since last resolve.
- */
- ILO_TEXTURE_RENDER_WRITE = 1 << 0,
- ILO_TEXTURE_BLT_WRITE = 1 << 1,
- ILO_TEXTURE_CPU_WRITE = 1 << 2,
-
- /*
- * Possible readers of a texture. There may be multiple readers at any
- * time.
- *
- * When set in resolve flags, they indicate the new readers. They are
- * never set in slice flags.
- */
- ILO_TEXTURE_RENDER_READ = 1 << 3,
- ILO_TEXTURE_BLT_READ = 1 << 4,
- ILO_TEXTURE_CPU_READ = 1 << 5,
-
- /*
- * Set when the texture is cleared.
- *
- * When set in resolve flags, the new writer will clear. When set in slice
- * flags, the slice has been cleared to ilo_texture_slice::clear_value.
- */
- ILO_TEXTURE_CLEAR = 1 << 6,
-};
-
-/**
- * A 3D image slice, cube face, or array layer.
- */
-struct ilo_texture_slice {
- unsigned flags;
-
- /*
- * Slice clear value. It is served for two purposes
- *
- * - the clear value used in commands such as 3DSTATE_CLEAR_PARAMS
- * - the clear value when ILO_TEXTURE_CLEAR is set
- *
- * Since commands such as 3DSTATE_CLEAR_PARAMS expect a single clear value
- * for all slices, ilo_blit_resolve_slices() will silently make all slices
- * to have the same clear value.
- */
- uint32_t clear_value;
-};
-
-struct ilo_texture {
- struct pipe_resource base;
-
- bool imported;
-
- enum pipe_format image_format;
- struct ilo_image image;
- struct ilo_vma vma;
- struct ilo_vma aux_vma;
-
- /* XXX thread-safety */
- struct ilo_texture_slice *slices[PIPE_MAX_TEXTURE_LEVELS];
-
- struct ilo_texture *separate_s8;
-};
-
-struct ilo_buffer_resource {
- struct pipe_resource base;
-
- uint32_t bo_size;
- struct ilo_vma vma;
-};
-
-static inline struct ilo_buffer_resource *
-ilo_buffer_resource(struct pipe_resource *res)
-{
- return (struct ilo_buffer_resource *)
- ((res && res->target == PIPE_BUFFER) ? res : NULL);
-}
-
-static inline struct ilo_texture *
-ilo_texture(struct pipe_resource *res)
-{
- return (struct ilo_texture *)
- ((res && res->target != PIPE_BUFFER) ? res : NULL);
-}
-
-void
-ilo_init_resource_functions(struct ilo_screen *is);
-
-bool
-ilo_resource_rename_bo(struct pipe_resource *res);
-
-/**
- * Return the VMA of the resource.
- */
-static inline const struct ilo_vma *
-ilo_resource_get_vma(struct pipe_resource *res)
-{
- return (res->target == PIPE_BUFFER) ?
- &((struct ilo_buffer_resource *) res)->vma :
- &((struct ilo_texture *) res)->vma;
-}
-
-static inline struct ilo_texture_slice *
-ilo_texture_get_slice(const struct ilo_texture *tex,
- unsigned level, unsigned slice)
-{
- assert(level <= tex->base.last_level);
- assert(slice < ((tex->base.target == PIPE_TEXTURE_3D) ?
- u_minify(tex->base.depth0, level) : tex->base.array_size));
-
- return &tex->slices[level][slice];
-}
-
-static inline void
-ilo_texture_set_slice_flags(struct ilo_texture *tex, unsigned level,
- unsigned first_slice, unsigned num_slices,
- unsigned mask, unsigned value)
-{
- const struct ilo_texture_slice *last =
- ilo_texture_get_slice(tex, level, first_slice + num_slices - 1);
- struct ilo_texture_slice *slice =
- ilo_texture_get_slice(tex, level, first_slice);
-
- while (slice <= last) {
- slice->flags = (slice->flags & ~mask) | (value & mask);
- slice++;
- }
-}
-
-static inline void
-ilo_texture_set_slice_clear_value(struct ilo_texture *tex, unsigned level,
- unsigned first_slice, unsigned num_slices,
- uint32_t clear_value)
-{
- const struct ilo_texture_slice *last =
- ilo_texture_get_slice(tex, level, first_slice + num_slices - 1);
- struct ilo_texture_slice *slice =
- ilo_texture_get_slice(tex, level, first_slice);
-
- while (slice <= last) {
- slice->clear_value = clear_value;
- slice++;
- }
-}
-
-#endif /* ILO_RESOURCE_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "pipe/p_state.h"
-#include "os/os_misc.h"
-#include "util/u_format_s3tc.h"
-#include "vl/vl_decoder.h"
-#include "vl/vl_video_buffer.h"
-#include "genhw/genhw.h" /* for GEN6_REG_TIMESTAMP */
-#include "core/intel_winsys.h"
-
-#include "ilo_context.h"
-#include "ilo_format.h"
-#include "ilo_resource.h"
-#include "ilo_transfer.h" /* for ILO_TRANSFER_MAP_BUFFER_ALIGNMENT */
-#include "ilo_public.h"
-#include "ilo_screen.h"
-
-struct pipe_fence_handle {
- struct pipe_reference reference;
- struct intel_bo *seqno_bo;
-};
-
-static float
-ilo_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
-{
- switch (param) {
- case PIPE_CAPF_MAX_LINE_WIDTH:
- /* in U3.7, defined in 3DSTATE_SF */
- return 7.0f;
- case PIPE_CAPF_MAX_LINE_WIDTH_AA:
- /* line width minus one, which is reserved for AA region */
- return 6.0f;
- case PIPE_CAPF_MAX_POINT_WIDTH:
- /* in U8.3, defined in 3DSTATE_SF */
- return 255.0f;
- case PIPE_CAPF_MAX_POINT_WIDTH_AA:
- /* same as point width, as we ignore rasterizer->point_smooth */
- return 255.0f;
- case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
- /* [2.0, 16.0], defined in SAMPLER_STATE */
- return 16.0f;
- case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
- /* [-16.0, 16.0), defined in SAMPLER_STATE */
- return 15.0f;
- case PIPE_CAPF_GUARD_BAND_LEFT:
- case PIPE_CAPF_GUARD_BAND_TOP:
- case PIPE_CAPF_GUARD_BAND_RIGHT:
- case PIPE_CAPF_GUARD_BAND_BOTTOM:
- /* what are these for? */
- return 0.0f;
-
- default:
- return 0.0f;
- }
-}
-
-static int
-ilo_get_shader_param(struct pipe_screen *screen, unsigned shader,
- enum pipe_shader_cap param)
-{
- switch (shader) {
- case PIPE_SHADER_FRAGMENT:
- case PIPE_SHADER_VERTEX:
- case PIPE_SHADER_GEOMETRY:
- break;
- default:
- return 0;
- }
-
- switch (param) {
- /* the limits are copied from the classic driver */
- case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
- return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 16384;
- case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
- return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
- case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
- return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
- case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
- return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
- case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
- return UINT_MAX;
- case PIPE_SHADER_CAP_MAX_INPUTS:
- case PIPE_SHADER_CAP_MAX_OUTPUTS:
- /* this is limited by how many attributes SF can remap */
- return 16;
- case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
- return 1024 * sizeof(float[4]);
- case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
- return ILO_MAX_CONST_BUFFERS;
- case PIPE_SHADER_CAP_MAX_TEMPS:
- return 256;
- case PIPE_SHADER_CAP_MAX_PREDS:
- return 0;
- case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
- return 1;
- case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
- return 0;
- case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
- return 0;
- case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
- return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
- case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
- return 1;
- case PIPE_SHADER_CAP_SUBROUTINES:
- return 0;
- case PIPE_SHADER_CAP_INTEGERS:
- return 1;
- case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
- return ILO_MAX_SAMPLERS;
- case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
- return ILO_MAX_SAMPLER_VIEWS;
- case PIPE_SHADER_CAP_PREFERRED_IR:
- return PIPE_SHADER_IR_TGSI;
- case PIPE_SHADER_CAP_SUPPORTED_IRS:
- return 0;
- case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
- return 1;
- case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
- return 32;
-
- default:
- return 0;
- }
-}
-
-static int
-ilo_get_video_param(struct pipe_screen *screen,
- enum pipe_video_profile profile,
- enum pipe_video_entrypoint entrypoint,
- enum pipe_video_cap param)
-{
- switch (param) {
- case PIPE_VIDEO_CAP_SUPPORTED:
- return vl_profile_supported(screen, profile, entrypoint);
- case PIPE_VIDEO_CAP_NPOT_TEXTURES:
- return 1;
- case PIPE_VIDEO_CAP_MAX_WIDTH:
- case PIPE_VIDEO_CAP_MAX_HEIGHT:
- return vl_video_buffer_max_size(screen);
- case PIPE_VIDEO_CAP_PREFERED_FORMAT:
- return PIPE_FORMAT_NV12;
- case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
- return 1;
- case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
- return 1;
- case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
- return 0;
- case PIPE_VIDEO_CAP_MAX_LEVEL:
- return vl_level_supported(screen, profile);
- default:
- return 0;
- }
-}
-
-static int
-ilo_get_compute_param(struct pipe_screen *screen,
- enum pipe_shader_ir ir_type,
- enum pipe_compute_cap param,
- void *ret)
-{
- struct ilo_screen *is = ilo_screen(screen);
- union {
- const char *ir_target;
- uint64_t grid_dimension;
- uint64_t max_grid_size[3];
- uint64_t max_block_size[3];
- uint64_t max_threads_per_block;
- uint64_t max_global_size;
- uint64_t max_local_size;
- uint64_t max_private_size;
- uint64_t max_input_size;
- uint64_t max_mem_alloc_size;
- uint32_t max_clock_frequency;
- uint32_t max_compute_units;
- uint32_t images_supported;
- uint32_t subgroup_size;
- uint32_t address_bits;
- } val;
- const void *ptr;
- int size;
-
- switch (param) {
- case PIPE_COMPUTE_CAP_IR_TARGET:
- val.ir_target = "ilog";
-
- ptr = val.ir_target;
- size = strlen(val.ir_target) + 1;
- break;
- case PIPE_COMPUTE_CAP_GRID_DIMENSION:
- val.grid_dimension = ARRAY_SIZE(val.max_grid_size);
-
- ptr = &val.grid_dimension;
- size = sizeof(val.grid_dimension);
- break;
- case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
- val.max_grid_size[0] = 0xffffffffu;
- val.max_grid_size[1] = 0xffffffffu;
- val.max_grid_size[2] = 0xffffffffu;
-
- ptr = &val.max_grid_size;
- size = sizeof(val.max_grid_size);
- break;
- case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
- val.max_block_size[0] = 1024;
- val.max_block_size[1] = 1024;
- val.max_block_size[2] = 1024;
-
- ptr = &val.max_block_size;
- size = sizeof(val.max_block_size);
- break;
-
- case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
- val.max_threads_per_block = 1024;
-
- ptr = &val.max_threads_per_block;
- size = sizeof(val.max_threads_per_block);
- break;
- case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
- /* \see ilo_max_resource_size */
- val.max_global_size = 1u << 31;
-
- ptr = &val.max_global_size;
- size = sizeof(val.max_global_size);
- break;
- case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
- /* Shared Local Memory Size of INTERFACE_DESCRIPTOR_DATA */
- val.max_local_size = 64 * 1024;
-
- ptr = &val.max_local_size;
- size = sizeof(val.max_local_size);
- break;
- case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
- /* scratch size */
- val.max_private_size = 12 * 1024;
-
- ptr = &val.max_private_size;
- size = sizeof(val.max_private_size);
- break;
- case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
- val.max_input_size = 1024;
-
- ptr = &val.max_input_size;
- size = sizeof(val.max_input_size);
- break;
- case PIPE_COMPUTE_CAP_ADDRESS_BITS:
- val.address_bits = 32;
- ptr = &val.address_bits;
- size = sizeof(val.address_bits);
- break;
- case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
- val.max_mem_alloc_size = 1u << 31;
-
- ptr = &val.max_mem_alloc_size;
- size = sizeof(val.max_mem_alloc_size);
- break;
- case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
- val.max_clock_frequency = 1000;
-
- ptr = &val.max_clock_frequency;
- size = sizeof(val.max_clock_frequency);
- break;
- case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
- val.max_compute_units = is->dev.eu_count;
-
- ptr = &val.max_compute_units;
- size = sizeof(val.max_compute_units);
- break;
- case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
- val.images_supported = 1;
-
- ptr = &val.images_supported;
- size = sizeof(val.images_supported);
- break;
- case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
- /* best case is actually SIMD32 */
- val.subgroup_size = 16;
-
- ptr = &val.subgroup_size;
- size = sizeof(val.subgroup_size);
- break;
- case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
- /* fallthrough */
- default:
- ptr = NULL;
- size = 0;
- break;
- }
-
- if (ret)
- memcpy(ret, ptr, size);
-
- return size;
-}
-
-static int
-ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
-{
- struct ilo_screen *is = ilo_screen(screen);
-
- switch (param) {
- case PIPE_CAP_NPOT_TEXTURES:
- case PIPE_CAP_TWO_SIDED_STENCIL:
- return true;
- case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
- return 0; /* TODO */
- case PIPE_CAP_ANISOTROPIC_FILTER:
- case PIPE_CAP_POINT_SPRITE:
- return true;
- case PIPE_CAP_MAX_RENDER_TARGETS:
- return ILO_MAX_DRAW_BUFFERS;
- case PIPE_CAP_OCCLUSION_QUERY:
- case PIPE_CAP_QUERY_TIME_ELAPSED:
- case PIPE_CAP_TEXTURE_SHADOW_MAP:
- case PIPE_CAP_TEXTURE_SWIZZLE: /* must be supported for shadow map */
- return true;
- case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
- /*
- * As defined in SURFACE_STATE, we have
- *
- * Max WxHxD for 2D and CUBE Max WxHxD for 3D
- * GEN6 8192x8192x512 2048x2048x2048
- * GEN7 16384x16384x2048 2048x2048x2048
- */
- return (ilo_dev_gen(&is->dev) >= ILO_GEN(7)) ? 15 : 14;
- case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
- return 12;
- case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
- return (ilo_dev_gen(&is->dev) >= ILO_GEN(7)) ? 15 : 14;
- case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
- return false;
- case PIPE_CAP_BLEND_EQUATION_SEPARATE:
- case PIPE_CAP_SM3:
- return true;
- case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
- if (ilo_dev_gen(&is->dev) >= ILO_GEN(7) && !is->dev.has_gen7_sol_reset)
- return 0;
- return ILO_MAX_SO_BUFFERS;
- case PIPE_CAP_PRIMITIVE_RESTART:
- return true;
- case PIPE_CAP_INDEP_BLEND_ENABLE:
- case PIPE_CAP_INDEP_BLEND_FUNC:
- return true;
- case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
- return (ilo_dev_gen(&is->dev) >= ILO_GEN(7.5)) ? 2048 : 512;
- case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
- case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
- case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
- case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
- case PIPE_CAP_DEPTH_CLIP_DISABLE:
- return true;
- case PIPE_CAP_SHADER_STENCIL_EXPORT:
- return false;
- case PIPE_CAP_TGSI_INSTANCEID:
- case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
- return true;
- case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
- return false;
- case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
- return true;
- case PIPE_CAP_SEAMLESS_CUBE_MAP:
- case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
- return true;
- case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
- case PIPE_CAP_MIN_TEXEL_OFFSET:
- return -8;
- case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
- case PIPE_CAP_MAX_TEXEL_OFFSET:
- return 7;
- case PIPE_CAP_CONDITIONAL_RENDER:
- case PIPE_CAP_TEXTURE_BARRIER:
- return true;
- case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
- return ILO_MAX_SO_BINDINGS / ILO_MAX_SO_BUFFERS;
- case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
- return ILO_MAX_SO_BINDINGS;
- case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
- case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
- if (ilo_dev_gen(&is->dev) >= ILO_GEN(7))
- return is->dev.has_gen7_sol_reset;
- else
- return false; /* TODO */
- case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
- return false;
- case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
- return true;
- case PIPE_CAP_VERTEX_COLOR_CLAMPED:
- return false;
- case PIPE_CAP_GLSL_FEATURE_LEVEL:
- return 140;
- case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
- case PIPE_CAP_USER_VERTEX_BUFFERS:
- return false;
- case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
- case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
- case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
- return false;
- case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
- return 2048;
- case PIPE_CAP_COMPUTE:
- return false; /* TODO */
- case PIPE_CAP_USER_INDEX_BUFFERS:
- case PIPE_CAP_USER_CONSTANT_BUFFERS:
- return true;
- case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
- /* imposed by OWord (Dual) Block Read */
- return 16;
- case PIPE_CAP_START_INSTANCE:
- return true;
- case PIPE_CAP_QUERY_TIMESTAMP:
- return is->dev.has_timestamp;
- case PIPE_CAP_TEXTURE_MULTISAMPLE:
- return false; /* TODO */
- case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
- return ILO_TRANSFER_MAP_BUFFER_ALIGNMENT;
- case PIPE_CAP_CUBE_MAP_ARRAY:
- case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
- return true;
- case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
- return 0;
- case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
- return 1;
- case PIPE_CAP_TGSI_TEXCOORD:
- return false;
- case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
- case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
- return true;
- case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
- return 0;
- case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
- /* a GEN6_SURFTYPE_BUFFER can have up to 2^27 elements */
- return 1 << 27;
- case PIPE_CAP_MAX_VIEWPORTS:
- return ILO_MAX_VIEWPORTS;
- case PIPE_CAP_ENDIANNESS:
- return PIPE_ENDIAN_LITTLE;
- case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
- case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
- return true;
- case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
- case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
- case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
- case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
- case PIPE_CAP_TEXTURE_GATHER_SM5:
- return 0;
- case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
- case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
- case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
- return true;
- case PIPE_CAP_FAKE_SW_MSAA:
- case PIPE_CAP_TEXTURE_QUERY_LOD:
- case PIPE_CAP_SAMPLE_SHADING:
- case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
- case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
- case PIPE_CAP_MAX_VERTEX_STREAMS:
- case PIPE_CAP_DRAW_INDIRECT:
- case PIPE_CAP_MULTI_DRAW_INDIRECT:
- case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
- case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
- case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
- case PIPE_CAP_SAMPLER_VIEW_TARGET:
- case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
- case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
- case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
- case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
- case PIPE_CAP_DEPTH_BOUNDS_TEST:
- case PIPE_CAP_TGSI_TXQS:
- case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
- case PIPE_CAP_SHAREABLE_SHADERS:
- case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
- case PIPE_CAP_CLEAR_TEXTURE:
- case PIPE_CAP_DRAW_PARAMETERS:
- case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
- case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
- case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
- case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
- case PIPE_CAP_INVALIDATE_BUFFER:
- case PIPE_CAP_GENERATE_MIPMAP:
- case PIPE_CAP_STRING_MARKER:
- case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
- case PIPE_CAP_QUERY_BUFFER_OBJECT:
- case PIPE_CAP_QUERY_MEMORY_INFO:
- case PIPE_CAP_PCI_GROUP:
- case PIPE_CAP_PCI_BUS:
- case PIPE_CAP_PCI_DEVICE:
- case PIPE_CAP_PCI_FUNCTION:
- case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
- case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
- case PIPE_CAP_CULL_DISTANCE:
- case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
- case PIPE_CAP_TGSI_VOTE:
- case PIPE_CAP_MAX_WINDOW_RECTANGLES:
- case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
- case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
- case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
- case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
- case PIPE_CAP_NATIVE_FENCE_FD:
- case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
- case PIPE_CAP_TGSI_FS_FBFETCH:
- case PIPE_CAP_TGSI_MUL_ZERO_WINS:
- case PIPE_CAP_INT64:
- return 0;
-
- case PIPE_CAP_VENDOR_ID:
- return 0x8086;
- case PIPE_CAP_DEVICE_ID:
- return is->dev.devid;
- case PIPE_CAP_ACCELERATED:
- return true;
- case PIPE_CAP_VIDEO_MEMORY: {
- /* Once a batch uses more than 75% of the maximum mappable size, we
- * assume that there's some fragmentation, and we start doing extra
- * flushing, etc. That's the big cliff apps will care about.
- */
- const uint64_t gpu_memory = is->dev.aperture_total * 3 / 4;
- uint64_t system_memory;
-
- if (!os_get_total_physical_memory(&system_memory))
- return 0;
-
- return (int) (MIN2(gpu_memory, system_memory) >> 20);
- }
- case PIPE_CAP_UMA:
- return true;
- case PIPE_CAP_CLIP_HALFZ:
- return true;
- case PIPE_CAP_VERTEXID_NOBASE:
- return false;
- case PIPE_CAP_POLYGON_OFFSET_CLAMP:
- return true;
-
- default:
- return 0;
- }
-}
-
-static const char *
-ilo_get_vendor(struct pipe_screen *screen)
-{
- return "LunarG, Inc.";
-}
-
-static const char *
-ilo_get_device_vendor(struct pipe_screen *screen)
-{
- return "Intel";
-}
-
-static const char *
-ilo_get_name(struct pipe_screen *screen)
-{
- struct ilo_screen *is = ilo_screen(screen);
- const char *chipset = NULL;
-
- if (gen_is_chv(is->dev.devid)) {
- chipset = "Intel(R) Cherryview";
- } else if (gen_is_bdw(is->dev.devid)) {
- /* this is likely wrong */
- if (gen_is_desktop(is->dev.devid))
- chipset = "Intel(R) Broadwell Desktop";
- else if (gen_is_mobile(is->dev.devid))
- chipset = "Intel(R) Broadwell Mobile";
- else if (gen_is_server(is->dev.devid))
- chipset = "Intel(R) Broadwell Server";
- } else if (gen_is_vlv(is->dev.devid)) {
- chipset = "Intel(R) Bay Trail";
- } else if (gen_is_hsw(is->dev.devid)) {
- if (gen_is_desktop(is->dev.devid))
- chipset = "Intel(R) Haswell Desktop";
- else if (gen_is_mobile(is->dev.devid))
- chipset = "Intel(R) Haswell Mobile";
- else if (gen_is_server(is->dev.devid))
- chipset = "Intel(R) Haswell Server";
- } else if (gen_is_ivb(is->dev.devid)) {
- if (gen_is_desktop(is->dev.devid))
- chipset = "Intel(R) Ivybridge Desktop";
- else if (gen_is_mobile(is->dev.devid))
- chipset = "Intel(R) Ivybridge Mobile";
- else if (gen_is_server(is->dev.devid))
- chipset = "Intel(R) Ivybridge Server";
- } else if (gen_is_snb(is->dev.devid)) {
- if (gen_is_desktop(is->dev.devid))
- chipset = "Intel(R) Sandybridge Desktop";
- else if (gen_is_mobile(is->dev.devid))
- chipset = "Intel(R) Sandybridge Mobile";
- else if (gen_is_server(is->dev.devid))
- chipset = "Intel(R) Sandybridge Server";
- }
-
- if (!chipset)
- chipset = "Unknown Intel Chipset";
-
- return chipset;
-}
-
-static uint64_t
-ilo_get_timestamp(struct pipe_screen *screen)
-{
- struct ilo_screen *is = ilo_screen(screen);
- union {
- uint64_t val;
- uint32_t dw[2];
- } timestamp;
-
- intel_winsys_read_reg(is->dev.winsys, GEN6_REG_TIMESTAMP, ×tamp.val);
-
- /*
- * From the Ivy Bridge PRM, volume 1 part 3, page 107:
- *
- * "Note: This timestamp register reflects the value of the PCU TSC.
- * The PCU TSC counts 10ns increments; this timestamp reflects bits
- * 38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
- * hours)."
- *
- * However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
- * of the timestamp. We will have to live with a timestamp that rolls over
- * every ~343 seconds.
- *
- * See also brw_get_timestamp().
- */
- return (uint64_t) timestamp.dw[1] * 80;
-}
-
-static boolean
-ilo_is_format_supported(struct pipe_screen *screen,
- enum pipe_format format,
- enum pipe_texture_target target,
- unsigned sample_count,
- unsigned bindings)
-{
- struct ilo_screen *is = ilo_screen(screen);
- const struct ilo_dev *dev = &is->dev;
-
- if (!util_format_is_supported(format, bindings))
- return false;
-
- /* no MSAA support yet */
- if (sample_count > 1)
- return false;
-
- if ((bindings & PIPE_BIND_DEPTH_STENCIL) &&
- !ilo_format_support_zs(dev, format))
- return false;
-
- if ((bindings & PIPE_BIND_RENDER_TARGET) &&
- !ilo_format_support_rt(dev, format))
- return false;
-
- if ((bindings & PIPE_BIND_SAMPLER_VIEW) &&
- !ilo_format_support_sampler(dev, format))
- return false;
-
- if ((bindings & PIPE_BIND_VERTEX_BUFFER) &&
- !ilo_format_support_vb(dev, format))
- return false;
-
- return true;
-}
-
-static boolean
-ilo_is_video_format_supported(struct pipe_screen *screen,
- enum pipe_format format,
- enum pipe_video_profile profile,
- enum pipe_video_entrypoint entrypoint)
-{
- return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
-}
-
-static void
-ilo_screen_fence_reference(struct pipe_screen *screen,
- struct pipe_fence_handle **ptr,
- struct pipe_fence_handle *fence)
-{
- struct pipe_fence_handle *old;
-
- if (likely(ptr)) {
- old = *ptr;
- *ptr = fence;
- } else {
- old = NULL;
- }
-
- STATIC_ASSERT(&((struct pipe_fence_handle *) NULL)->reference == NULL);
- if (pipe_reference(&old->reference, &fence->reference)) {
- intel_bo_unref(old->seqno_bo);
- FREE(old);
- }
-}
-
-static boolean
-ilo_screen_fence_finish(struct pipe_screen *screen,
- struct pipe_context *ctx,
- struct pipe_fence_handle *fence,
- uint64_t timeout)
-{
- const int64_t wait_timeout = (timeout > INT64_MAX) ? -1 : timeout;
- bool signaled;
-
- signaled = (!fence->seqno_bo ||
- intel_bo_wait(fence->seqno_bo, wait_timeout) == 0);
-
- /* XXX not thread safe */
- if (signaled && fence->seqno_bo) {
- intel_bo_unref(fence->seqno_bo);
- fence->seqno_bo = NULL;
- }
-
- return signaled;
-}
-
-/**
- * Create a fence for \p bo. When \p bo is not NULL, it must be submitted
- * before waited on or checked.
- */
-struct pipe_fence_handle *
-ilo_screen_fence_create(struct pipe_screen *screen, struct intel_bo *bo)
-{
- struct pipe_fence_handle *fence;
-
- fence = CALLOC_STRUCT(pipe_fence_handle);
- if (!fence)
- return NULL;
-
- pipe_reference_init(&fence->reference, 1);
-
- fence->seqno_bo = intel_bo_ref(bo);
-
- return fence;
-}
-
-static void
-ilo_screen_destroy(struct pipe_screen *screen)
-{
- struct ilo_screen *is = ilo_screen(screen);
-
- intel_winsys_destroy(is->dev.winsys);
-
- FREE(is);
-}
-
-struct pipe_screen *
-ilo_screen_create(struct intel_winsys *ws)
-{
- struct ilo_screen *is;
-
- ilo_debug_init("ILO_DEBUG");
-
- is = CALLOC_STRUCT(ilo_screen);
- if (!is)
- return NULL;
-
- if (!ilo_dev_init(&is->dev, ws)) {
- FREE(is);
- return NULL;
- }
-
- util_format_s3tc_init();
-
- is->base.destroy = ilo_screen_destroy;
- is->base.get_name = ilo_get_name;
- is->base.get_vendor = ilo_get_vendor;
- is->base.get_device_vendor = ilo_get_device_vendor;
- is->base.get_param = ilo_get_param;
- is->base.get_paramf = ilo_get_paramf;
- is->base.get_shader_param = ilo_get_shader_param;
- is->base.get_video_param = ilo_get_video_param;
- is->base.get_compute_param = ilo_get_compute_param;
-
- is->base.get_timestamp = ilo_get_timestamp;
-
- is->base.is_format_supported = ilo_is_format_supported;
- is->base.is_video_format_supported = ilo_is_video_format_supported;
-
- is->base.flush_frontbuffer = NULL;
-
- is->base.fence_reference = ilo_screen_fence_reference;
- is->base.fence_finish = ilo_screen_fence_finish;
-
- is->base.get_driver_query_info = NULL;
-
- ilo_init_context_functions(is);
- ilo_init_resource_functions(is);
-
- return &is->base;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_SCREEN_H
-#define ILO_SCREEN_H
-
-#include "pipe/p_screen.h"
-
-#include "ilo_common.h"
-
-struct intel_bo;
-
-struct ilo_fence;
-
-struct ilo_screen {
- struct pipe_screen base;
-
- struct ilo_dev dev;
-};
-
-static inline struct ilo_screen *
-ilo_screen(struct pipe_screen *screen)
-{
- return (struct ilo_screen *) screen;
-}
-
-struct pipe_fence_handle *
-ilo_screen_fence_create(struct pipe_screen *screen, struct intel_bo *bo);
-
-#endif /* ILO_SCREEN_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "genhw/genhw.h" /* for SBE setup */
-#include "core/ilo_builder.h"
-#include "core/intel_winsys.h"
-#include "shader/ilo_shader_internal.h"
-#include "tgsi/tgsi_parse.h"
-
-#include "ilo_state.h"
-#include "ilo_shader.h"
-
-struct ilo_shader_cache {
- struct list_head shaders;
- struct list_head changed;
-
- int max_vs_scratch_size;
- int max_gs_scratch_size;
- int max_fs_scratch_size;
-};
-
-/**
- * Create a shader cache. A shader cache can manage shaders and upload them
- * to a bo as a whole.
- */
-struct ilo_shader_cache *
-ilo_shader_cache_create(void)
-{
- struct ilo_shader_cache *shc;
-
- shc = CALLOC_STRUCT(ilo_shader_cache);
- if (!shc)
- return NULL;
-
- list_inithead(&shc->shaders);
- list_inithead(&shc->changed);
-
- return shc;
-}
-
-/**
- * Destroy a shader cache.
- */
-void
-ilo_shader_cache_destroy(struct ilo_shader_cache *shc)
-{
- FREE(shc);
-}
-
-/**
- * Add a shader to the cache.
- */
-void
-ilo_shader_cache_add(struct ilo_shader_cache *shc,
- struct ilo_shader_state *shader)
-{
- struct ilo_shader *sh;
-
- shader->cache = shc;
- LIST_FOR_EACH_ENTRY(sh, &shader->variants, list)
- sh->uploaded = false;
-
- list_add(&shader->list, &shc->changed);
-}
-
-/**
- * Remove a shader from the cache.
- */
-void
-ilo_shader_cache_remove(struct ilo_shader_cache *shc,
- struct ilo_shader_state *shader)
-{
- list_del(&shader->list);
- shader->cache = NULL;
-}
-
-/**
- * Notify the cache that a managed shader has changed.
- */
-static void
-ilo_shader_cache_notify_change(struct ilo_shader_cache *shc,
- struct ilo_shader_state *shader)
-{
- if (shader->cache == shc) {
- list_del(&shader->list);
- list_add(&shader->list, &shc->changed);
- }
-}
-
-/**
- * Upload managed shaders to the bo. Only shaders that are changed or added
- * after the last upload are uploaded.
- */
-void
-ilo_shader_cache_upload(struct ilo_shader_cache *shc,
- struct ilo_builder *builder)
-{
- struct ilo_shader_state *shader, *next;
-
- LIST_FOR_EACH_ENTRY_SAFE(shader, next, &shc->changed, list) {
- struct ilo_shader *sh;
-
- LIST_FOR_EACH_ENTRY(sh, &shader->variants, list) {
- int scratch_size, *cur_max;
-
- if (sh->uploaded)
- continue;
-
- sh->cache_offset = ilo_builder_instruction_write(builder,
- sh->kernel_size, sh->kernel);
-
- sh->uploaded = true;
-
- switch (shader->info.type) {
- case PIPE_SHADER_VERTEX:
- scratch_size = ilo_state_vs_get_scratch_size(&sh->cso.vs);
- cur_max = &shc->max_vs_scratch_size;
- break;
- case PIPE_SHADER_GEOMETRY:
- scratch_size = ilo_state_gs_get_scratch_size(&sh->cso.gs);
- cur_max = &shc->max_gs_scratch_size;
- break;
- case PIPE_SHADER_FRAGMENT:
- scratch_size = ilo_state_ps_get_scratch_size(&sh->cso.ps);
- cur_max = &shc->max_fs_scratch_size;
- break;
- default:
- assert(!"unknown shader type");
- scratch_size = 0;
- cur_max = &shc->max_vs_scratch_size;
- break;
- }
-
- if (*cur_max < scratch_size)
- *cur_max = scratch_size;
- }
-
- list_del(&shader->list);
- list_add(&shader->list, &shc->shaders);
- }
-}
-
-/**
- * Invalidate all shaders so that they get uploaded in next
- * ilo_shader_cache_upload().
- */
-void
-ilo_shader_cache_invalidate(struct ilo_shader_cache *shc)
-{
- struct ilo_shader_state *shader, *next;
-
- LIST_FOR_EACH_ENTRY_SAFE(shader, next, &shc->shaders, list) {
- list_del(&shader->list);
- list_add(&shader->list, &shc->changed);
- }
-
- LIST_FOR_EACH_ENTRY(shader, &shc->changed, list) {
- struct ilo_shader *sh;
-
- LIST_FOR_EACH_ENTRY(sh, &shader->variants, list)
- sh->uploaded = false;
- }
-
- shc->max_vs_scratch_size = 0;
- shc->max_gs_scratch_size = 0;
- shc->max_fs_scratch_size = 0;
-}
-
-void
-ilo_shader_cache_get_max_scratch_sizes(const struct ilo_shader_cache *shc,
- int *vs_scratch_size,
- int *gs_scratch_size,
- int *fs_scratch_size)
-{
- *vs_scratch_size = shc->max_vs_scratch_size;
- *gs_scratch_size = shc->max_gs_scratch_size;
- *fs_scratch_size = shc->max_fs_scratch_size;
-}
-
-/**
- * Initialize a shader variant.
- */
-void
-ilo_shader_variant_init(struct ilo_shader_variant *variant,
- const struct ilo_shader_info *info,
- const struct ilo_state_vector *vec)
-{
- int num_views, i;
-
- memset(variant, 0, sizeof(*variant));
-
- switch (info->type) {
- case PIPE_SHADER_VERTEX:
- variant->u.vs.rasterizer_discard =
- vec->rasterizer->state.rasterizer_discard;
- variant->u.vs.num_ucps =
- util_last_bit(vec->rasterizer->state.clip_plane_enable);
- break;
- case PIPE_SHADER_GEOMETRY:
- variant->u.gs.rasterizer_discard =
- vec->rasterizer->state.rasterizer_discard;
- variant->u.gs.num_inputs = vec->vs->shader->out.count;
- for (i = 0; i < vec->vs->shader->out.count; i++) {
- variant->u.gs.semantic_names[i] =
- vec->vs->shader->out.semantic_names[i];
- variant->u.gs.semantic_indices[i] =
- vec->vs->shader->out.semantic_indices[i];
- }
- break;
- case PIPE_SHADER_FRAGMENT:
- variant->u.fs.flatshade =
- (info->has_color_interp && vec->rasterizer->state.flatshade);
- variant->u.fs.fb_height = (info->has_pos) ?
- vec->fb.state.height : 1;
- variant->u.fs.num_cbufs = vec->fb.state.nr_cbufs;
- break;
- default:
- assert(!"unknown shader type");
- break;
- }
-
- /* use PCB unless constant buffer 0 is not in user buffer */
- if ((vec->cbuf[info->type].enabled_mask & 0x1) &&
- !vec->cbuf[info->type].cso[0].user_buffer)
- variant->use_pcb = false;
- else
- variant->use_pcb = true;
-
- num_views = vec->view[info->type].count;
- assert(info->num_samplers <= num_views);
-
- variant->num_sampler_views = info->num_samplers;
- for (i = 0; i < info->num_samplers; i++) {
- const struct pipe_sampler_view *view = vec->view[info->type].states[i];
- const struct ilo_sampler_cso *sampler = vec->sampler[info->type].cso[i];
-
- if (view) {
- variant->sampler_view_swizzles[i].r = view->swizzle_r;
- variant->sampler_view_swizzles[i].g = view->swizzle_g;
- variant->sampler_view_swizzles[i].b = view->swizzle_b;
- variant->sampler_view_swizzles[i].a = view->swizzle_a;
- }
- else if (info->shadow_samplers & (1 << i)) {
- variant->sampler_view_swizzles[i].r = PIPE_SWIZZLE_X;
- variant->sampler_view_swizzles[i].g = PIPE_SWIZZLE_X;
- variant->sampler_view_swizzles[i].b = PIPE_SWIZZLE_X;
- variant->sampler_view_swizzles[i].a = PIPE_SWIZZLE_1;
- }
- else {
- variant->sampler_view_swizzles[i].r = PIPE_SWIZZLE_X;
- variant->sampler_view_swizzles[i].g = PIPE_SWIZZLE_Y;
- variant->sampler_view_swizzles[i].b = PIPE_SWIZZLE_Z;
- variant->sampler_view_swizzles[i].a = PIPE_SWIZZLE_W;
- }
-
- /*
- * When non-nearest filter and PIPE_TEX_WRAP_CLAMP wrap mode is used,
- * the HW wrap mode is set to GEN6_TEXCOORDMODE_CLAMP_BORDER, and we
- * need to manually saturate the texture coordinates.
- */
- if (sampler) {
- variant->saturate_tex_coords[0] |= sampler->saturate_s << i;
- variant->saturate_tex_coords[1] |= sampler->saturate_t << i;
- variant->saturate_tex_coords[2] |= sampler->saturate_r << i;
- }
- }
-}
-
-/**
- * Guess the shader variant, knowing that the context may still change.
- */
-static void
-ilo_shader_variant_guess(struct ilo_shader_variant *variant,
- const struct ilo_shader_info *info,
- const struct ilo_state_vector *vec)
-{
- int i;
-
- memset(variant, 0, sizeof(*variant));
-
- switch (info->type) {
- case PIPE_SHADER_VERTEX:
- break;
- case PIPE_SHADER_GEOMETRY:
- break;
- case PIPE_SHADER_FRAGMENT:
- variant->u.fs.flatshade = false;
- variant->u.fs.fb_height = (info->has_pos) ?
- vec->fb.state.height : 1;
- variant->u.fs.num_cbufs = 1;
- break;
- default:
- assert(!"unknown shader type");
- break;
- }
-
- variant->use_pcb = true;
-
- variant->num_sampler_views = info->num_samplers;
- for (i = 0; i < info->num_samplers; i++) {
- if (info->shadow_samplers & (1 << i)) {
- variant->sampler_view_swizzles[i].r = PIPE_SWIZZLE_X;
- variant->sampler_view_swizzles[i].g = PIPE_SWIZZLE_X;
- variant->sampler_view_swizzles[i].b = PIPE_SWIZZLE_X;
- variant->sampler_view_swizzles[i].a = PIPE_SWIZZLE_1;
- }
- else {
- variant->sampler_view_swizzles[i].r = PIPE_SWIZZLE_X;
- variant->sampler_view_swizzles[i].g = PIPE_SWIZZLE_Y;
- variant->sampler_view_swizzles[i].b = PIPE_SWIZZLE_Z;
- variant->sampler_view_swizzles[i].a = PIPE_SWIZZLE_W;
- }
- }
-}
-
-
-/**
- * Parse a TGSI instruction for the shader info.
- */
-static void
-ilo_shader_info_parse_inst(struct ilo_shader_info *info,
- const struct tgsi_full_instruction *inst)
-{
- int i;
-
- /* look for edgeflag passthrough */
- if (info->edgeflag_out >= 0 &&
- inst->Instruction.Opcode == TGSI_OPCODE_MOV &&
- inst->Dst[0].Register.File == TGSI_FILE_OUTPUT &&
- inst->Dst[0].Register.Index == info->edgeflag_out) {
-
- assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
- info->edgeflag_in = inst->Src[0].Register.Index;
- }
-
- if (inst->Instruction.Texture) {
- bool shadow;
-
- switch (inst->Texture.Texture) {
- case TGSI_TEXTURE_SHADOW1D:
- case TGSI_TEXTURE_SHADOW2D:
- case TGSI_TEXTURE_SHADOWRECT:
- case TGSI_TEXTURE_SHADOW1D_ARRAY:
- case TGSI_TEXTURE_SHADOW2D_ARRAY:
- case TGSI_TEXTURE_SHADOWCUBE:
- case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
- shadow = true;
- break;
- default:
- shadow = false;
- break;
- }
-
- for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
- const struct tgsi_full_src_register *src = &inst->Src[i];
-
- if (src->Register.File == TGSI_FILE_SAMPLER) {
- const int idx = src->Register.Index;
-
- if (idx >= info->num_samplers)
- info->num_samplers = idx + 1;
-
- if (shadow)
- info->shadow_samplers |= 1 << idx;
- }
- }
- }
-}
-
-/**
- * Parse a TGSI property for the shader info.
- */
-static void
-ilo_shader_info_parse_prop(struct ilo_shader_info *info,
- const struct tgsi_full_property *prop)
-{
- switch (prop->Property.PropertyName) {
- case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
- info->fs_color0_writes_all_cbufs = prop->u[0].Data;
- break;
- default:
- break;
- }
-}
-
-/**
- * Parse a TGSI declaration for the shader info.
- */
-static void
-ilo_shader_info_parse_decl(struct ilo_shader_info *info,
- const struct tgsi_full_declaration *decl)
-{
- switch (decl->Declaration.File) {
- case TGSI_FILE_INPUT:
- if (decl->Declaration.Interpolate &&
- decl->Interp.Interpolate == TGSI_INTERPOLATE_COLOR)
- info->has_color_interp = true;
- if (decl->Declaration.Semantic &&
- decl->Semantic.Name == TGSI_SEMANTIC_POSITION)
- info->has_pos = true;
- break;
- case TGSI_FILE_OUTPUT:
- if (decl->Declaration.Semantic &&
- decl->Semantic.Name == TGSI_SEMANTIC_EDGEFLAG)
- info->edgeflag_out = decl->Range.First;
- break;
- case TGSI_FILE_CONSTANT:
- {
- const int idx = (decl->Declaration.Dimension) ?
- decl->Dim.Index2D : 0;
- if (info->constant_buffer_count <= idx)
- info->constant_buffer_count = idx + 1;
- }
- break;
- case TGSI_FILE_SYSTEM_VALUE:
- if (decl->Declaration.Semantic &&
- decl->Semantic.Name == TGSI_SEMANTIC_INSTANCEID)
- info->has_instanceid = true;
- if (decl->Declaration.Semantic &&
- decl->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
- info->has_vertexid = true;
- break;
- default:
- break;
- }
-}
-
-static void
-ilo_shader_info_parse_tokens(struct ilo_shader_info *info)
-{
- struct tgsi_parse_context parse;
-
- info->edgeflag_in = -1;
- info->edgeflag_out = -1;
-
- tgsi_parse_init(&parse, info->tokens);
- while (!tgsi_parse_end_of_tokens(&parse)) {
- const union tgsi_full_token *token;
-
- tgsi_parse_token(&parse);
- token = &parse.FullToken;
-
- switch (token->Token.Type) {
- case TGSI_TOKEN_TYPE_DECLARATION:
- ilo_shader_info_parse_decl(info, &token->FullDeclaration);
- break;
- case TGSI_TOKEN_TYPE_INSTRUCTION:
- ilo_shader_info_parse_inst(info, &token->FullInstruction);
- break;
- case TGSI_TOKEN_TYPE_PROPERTY:
- ilo_shader_info_parse_prop(info, &token->FullProperty);
- break;
- default:
- break;
- }
- }
- tgsi_parse_free(&parse);
-}
-
-/**
- * Create a shader state.
- */
-static struct ilo_shader_state *
-ilo_shader_state_create(const struct ilo_dev *dev,
- const struct ilo_state_vector *vec,
- int type, const void *templ)
-{
- struct ilo_shader_state *state;
- struct ilo_shader_variant variant;
-
- state = CALLOC_STRUCT(ilo_shader_state);
- if (!state)
- return NULL;
-
- state->info.dev = dev;
- state->info.type = type;
-
- if (type == PIPE_SHADER_COMPUTE) {
- const struct pipe_compute_state *c =
- (const struct pipe_compute_state *) templ;
-
- state->info.tokens = tgsi_dup_tokens(c->prog);
- state->info.compute.req_local_mem = c->req_local_mem;
- state->info.compute.req_private_mem = c->req_private_mem;
- state->info.compute.req_input_mem = c->req_input_mem;
- }
- else {
- const struct pipe_shader_state *s =
- (const struct pipe_shader_state *) templ;
-
- state->info.tokens = tgsi_dup_tokens(s->tokens);
- state->info.stream_output = s->stream_output;
- }
-
- list_inithead(&state->variants);
-
- ilo_shader_info_parse_tokens(&state->info);
-
- /* guess and compile now */
- ilo_shader_variant_guess(&variant, &state->info, vec);
- if (!ilo_shader_state_use_variant(state, &variant)) {
- ilo_shader_destroy(state);
- return NULL;
- }
-
- return state;
-}
-
-/**
- * Add a compiled shader to the shader state.
- */
-static void
-ilo_shader_state_add_shader(struct ilo_shader_state *state,
- struct ilo_shader *sh)
-{
- list_add(&sh->list, &state->variants);
- state->num_variants++;
- state->total_size += sh->kernel_size;
-
- if (state->cache)
- ilo_shader_cache_notify_change(state->cache, state);
-}
-
-/**
- * Remove a compiled shader from the shader state.
- */
-static void
-ilo_shader_state_remove_shader(struct ilo_shader_state *state,
- struct ilo_shader *sh)
-{
- list_del(&sh->list);
- state->num_variants--;
- state->total_size -= sh->kernel_size;
-}
-
-/**
- * Garbage collect shader variants in the shader state.
- */
-static void
-ilo_shader_state_gc(struct ilo_shader_state *state)
-{
- /* activate when the variants take up more than 4KiB of space */
- const int limit = 4 * 1024;
- struct ilo_shader *sh, *next;
-
- if (state->total_size < limit)
- return;
-
- /* remove from the tail as the most recently ones are at the head */
- LIST_FOR_EACH_ENTRY_SAFE_REV(sh, next, &state->variants, list) {
- ilo_shader_state_remove_shader(state, sh);
- ilo_shader_destroy_kernel(sh);
-
- if (state->total_size <= limit / 2)
- break;
- }
-}
-
-/**
- * Search for a shader variant.
- */
-static struct ilo_shader *
-ilo_shader_state_search_variant(struct ilo_shader_state *state,
- const struct ilo_shader_variant *variant)
-{
- struct ilo_shader *sh = NULL, *tmp;
-
- LIST_FOR_EACH_ENTRY(tmp, &state->variants, list) {
- if (memcmp(&tmp->variant, variant, sizeof(*variant)) == 0) {
- sh = tmp;
- break;
- }
- }
-
- return sh;
-}
-
-static void
-init_shader_urb(const struct ilo_shader *kernel,
- const struct ilo_shader_state *state,
- struct ilo_state_shader_urb_info *urb)
-{
- urb->cv_input_attr_count = kernel->in.count;
- urb->read_base = 0;
- urb->read_count = kernel->in.count;
-
- urb->output_attr_count = kernel->out.count;
- urb->user_cull_enables = 0x0;
- urb->user_clip_enables = 0x0;
-}
-
-static void
-init_shader_kernel(const struct ilo_shader *kernel,
- const struct ilo_shader_state *state,
- struct ilo_state_shader_kernel_info *kern)
-{
- kern->offset = 0;
- kern->grf_start = kernel->in.start_grf;
- kern->pcb_attr_count =
- (kernel->pcb.cbuf0_size + kernel->pcb.clip_state_size + 15) / 16;
-}
-
-static void
-init_shader_resource(const struct ilo_shader *kernel,
- const struct ilo_shader_state *state,
- struct ilo_state_shader_resource_info *resource)
-{
- resource->sampler_count = state->info.num_samplers;
- resource->surface_count = 0;
- resource->has_uav = false;
-}
-
-static void
-init_vs(struct ilo_shader *kernel,
- const struct ilo_shader_state *state)
-{
- struct ilo_state_vs_info info;
-
- memset(&info, 0, sizeof(info));
-
- init_shader_urb(kernel, state, &info.urb);
- init_shader_kernel(kernel, state, &info.kernel);
- init_shader_resource(kernel, state, &info.resource);
- info.per_thread_scratch_size = kernel->per_thread_scratch_size;
- info.dispatch_enable = true;
- info.stats_enable = true;
-
- if (ilo_dev_gen(state->info.dev) == ILO_GEN(6) && kernel->stream_output) {
- struct ilo_state_gs_info gs_info;
-
- memset(&gs_info, 0, sizeof(gs_info));
-
- gs_info.urb.cv_input_attr_count = kernel->out.count;
- gs_info.urb.read_count = kernel->out.count;
- gs_info.kernel.grf_start = kernel->gs_start_grf;
- gs_info.sol.sol_enable = true;
- gs_info.sol.stats_enable = true;
- gs_info.sol.render_disable = kernel->variant.u.vs.rasterizer_discard;
- gs_info.sol.svbi_post_inc = kernel->svbi_post_inc;
- gs_info.sol.tristrip_reorder = GEN7_REORDER_LEADING;
- gs_info.dispatch_enable = true;
- gs_info.stats_enable = true;
-
- ilo_state_vs_init(&kernel->cso.vs_sol.vs, state->info.dev, &info);
- ilo_state_gs_init(&kernel->cso.vs_sol.sol, state->info.dev, &gs_info);
- } else {
- ilo_state_vs_init(&kernel->cso.vs, state->info.dev, &info);
- }
-}
-
-static void
-init_gs(struct ilo_shader *kernel,
- const struct ilo_shader_state *state)
-{
- const struct pipe_stream_output_info *so_info = &state->info.stream_output;
- struct ilo_state_gs_info info;
-
- memset(&info, 0, sizeof(info));
-
- init_shader_urb(kernel, state, &info.urb);
- init_shader_kernel(kernel, state, &info.kernel);
- init_shader_resource(kernel, state, &info.resource);
- info.per_thread_scratch_size = kernel->per_thread_scratch_size;
- info.dispatch_enable = true;
- info.stats_enable = true;
-
- if (so_info->num_outputs > 0) {
- info.sol.sol_enable = true;
- info.sol.stats_enable = true;
- info.sol.render_disable = kernel->variant.u.gs.rasterizer_discard;
- info.sol.tristrip_reorder = GEN7_REORDER_LEADING;
- }
-
- ilo_state_gs_init(&kernel->cso.gs, state->info.dev, &info);
-}
-
-static void
-init_ps(struct ilo_shader *kernel,
- const struct ilo_shader_state *state)
-{
- struct ilo_state_ps_info info;
-
- memset(&info, 0, sizeof(info));
-
- init_shader_kernel(kernel, state, &info.kernel_8);
- init_shader_resource(kernel, state, &info.resource);
-
- info.per_thread_scratch_size = kernel->per_thread_scratch_size;
- info.io.has_rt_write = true;
- info.io.posoffset = GEN6_POSOFFSET_NONE;
- info.io.attr_count = kernel->in.count;
- info.io.use_z = kernel->in.has_pos;
- info.io.use_w = kernel->in.has_pos;
- info.io.use_coverage_mask = false;
- info.io.pscdepth = (kernel->out.has_pos) ?
- GEN7_PSCDEPTH_ON : GEN7_PSCDEPTH_OFF;
- info.io.write_pixel_mask = kernel->has_kill;
- info.io.write_omask = false;
-
- info.params.sample_mask = 0x1;
- info.params.earlyz_control_psexec = false;
- info.params.alpha_may_kill = false;
- info.params.dual_source_blending = false;
- info.params.has_writeable_rt = true;
-
- info.valid_kernels = GEN6_PS_DISPATCH_8;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 284:
- *
- * "(MSDISPMODE_PERSAMPLE) This is the high-quality multisample mode
- * where (over and above PERPIXEL mode) the PS is run for each covered
- * sample. This mode is also used for "normal" non-multisample
- * rendering (aka 1X), given Number of Multisamples is programmed to
- * NUMSAMPLES_1."
- */
- info.per_sample_dispatch = true;
-
- info.rt_clear_enable = false;
- info.rt_resolve_enable = false;
- info.cv_per_sample_interp = false;
- info.cv_has_earlyz_op = false;
- info.sample_count_one = true;
- info.cv_has_depth_buffer = true;
-
- ilo_state_ps_init(&kernel->cso.ps, state->info.dev, &info);
-
- /* remember current parameters */
- kernel->ps_params = info.params;
-}
-
-static void
-init_sol(struct ilo_shader *kernel,
- const struct ilo_dev *dev,
- const struct pipe_stream_output_info *so_info,
- bool rasterizer_discard)
-{
- struct ilo_state_sol_decl_info decls[4][PIPE_MAX_SO_OUTPUTS];
- unsigned buf_offsets[PIPE_MAX_SO_BUFFERS];
- struct ilo_state_sol_info info;
- unsigned i;
-
- if (!so_info->num_outputs) {
- ilo_state_sol_init_disabled(&kernel->sol, dev, rasterizer_discard);
- return;
- }
-
- memset(&info, 0, sizeof(info));
- info.data = kernel->sol_data;
- info.data_size = sizeof(kernel->sol_data);
- info.sol_enable = true;
- info.stats_enable = true;
- info.tristrip_reorder = GEN7_REORDER_TRAILING;
- info.render_disable = rasterizer_discard;
- info.render_stream = 0;
-
- for (i = 0; i < 4; i++) {
- info.buffer_strides[i] = so_info->stride[i] * 4;
-
- info.streams[i].cv_vue_attr_count = kernel->out.count;
- info.streams[i].decls = decls[i];
- }
-
- memset(decls, 0, sizeof(decls));
- memset(buf_offsets, 0, sizeof(buf_offsets));
- for (i = 0; i < so_info->num_outputs; i++) {
- const unsigned stream = so_info->output[i].stream;
- const unsigned buffer = so_info->output[i].output_buffer;
- struct ilo_state_sol_decl_info *decl;
- unsigned attr;
-
- /* figure out which attribute is sourced */
- for (attr = 0; attr < kernel->out.count; attr++) {
- const int reg_idx = kernel->out.register_indices[attr];
- if (reg_idx == so_info->output[i].register_index)
- break;
- }
- if (attr >= kernel->out.count) {
- assert(!"stream output an undefined register");
- attr = 0;
- }
-
- if (info.streams[stream].vue_read_count < attr + 1)
- info.streams[stream].vue_read_count = attr + 1;
-
- /* pad with holes first */
- while (buf_offsets[buffer] < so_info->output[i].dst_offset) {
- int num_dwords;
-
- num_dwords = so_info->output[i].dst_offset - buf_offsets[buffer];
- if (num_dwords > 4)
- num_dwords = 4;
-
- assert(info.streams[stream].decl_count < ARRAY_SIZE(decls[stream]));
- decl = &decls[stream][info.streams[stream].decl_count];
-
- decl->attr = 0;
- decl->is_hole = true;
- decl->component_base = 0;
- decl->component_count = num_dwords;
- decl->buffer = buffer;
-
- info.streams[stream].decl_count++;
- buf_offsets[buffer] += num_dwords;
- }
- assert(buf_offsets[buffer] == so_info->output[i].dst_offset);
-
- assert(info.streams[stream].decl_count < ARRAY_SIZE(decls[stream]));
- decl = &decls[stream][info.streams[stream].decl_count];
-
- decl->attr = attr;
- decl->is_hole = false;
- /* PSIZE is at W channel */
- if (kernel->out.semantic_names[attr] == TGSI_SEMANTIC_PSIZE) {
- assert(so_info->output[i].start_component == 0);
- assert(so_info->output[i].num_components == 1);
- decl->component_base = 3;
- decl->component_count = 1;
- } else {
- decl->component_base = so_info->output[i].start_component;
- decl->component_count = so_info->output[i].num_components;
- }
- decl->buffer = buffer;
-
- info.streams[stream].decl_count++;
- buf_offsets[buffer] += so_info->output[i].num_components;
- }
-
- ilo_state_sol_init(&kernel->sol, dev, &info);
-}
-
-/**
- * Add a shader variant to the shader state.
- */
-static struct ilo_shader *
-ilo_shader_state_add_variant(struct ilo_shader_state *state,
- const struct ilo_shader_variant *variant)
-{
- bool rasterizer_discard = false;
- struct ilo_shader *sh;
-
- switch (state->info.type) {
- case PIPE_SHADER_VERTEX:
- sh = ilo_shader_compile_vs(state, variant);
- rasterizer_discard = variant->u.vs.rasterizer_discard;
- break;
- case PIPE_SHADER_FRAGMENT:
- sh = ilo_shader_compile_fs(state, variant);
- break;
- case PIPE_SHADER_GEOMETRY:
- sh = ilo_shader_compile_gs(state, variant);
- rasterizer_discard = variant->u.gs.rasterizer_discard;
- break;
- case PIPE_SHADER_COMPUTE:
- sh = ilo_shader_compile_cs(state, variant);
- break;
- default:
- sh = NULL;
- break;
- }
- if (!sh) {
- assert(!"failed to compile shader");
- return NULL;
- }
-
- sh->variant = *variant;
-
- init_sol(sh, state->info.dev, &state->info.stream_output,
- rasterizer_discard);
-
- ilo_shader_state_add_shader(state, sh);
-
- return sh;
-}
-
-/**
- * Update state->shader to point to a variant. If the variant does not exist,
- * it will be added first.
- */
-bool
-ilo_shader_state_use_variant(struct ilo_shader_state *state,
- const struct ilo_shader_variant *variant)
-{
- struct ilo_shader *sh;
- bool construct_cso = false;
-
- sh = ilo_shader_state_search_variant(state, variant);
- if (!sh) {
- ilo_shader_state_gc(state);
-
- sh = ilo_shader_state_add_variant(state, variant);
- if (!sh)
- return false;
-
- construct_cso = true;
- }
-
- /* move to head */
- if (state->variants.next != &sh->list) {
- list_del(&sh->list);
- list_add(&sh->list, &state->variants);
- }
-
- state->shader = sh;
-
- if (construct_cso) {
- switch (state->info.type) {
- case PIPE_SHADER_VERTEX:
- init_vs(sh, state);
- break;
- case PIPE_SHADER_GEOMETRY:
- init_gs(sh, state);
- break;
- case PIPE_SHADER_FRAGMENT:
- init_ps(sh, state);
- break;
- default:
- break;
- }
- }
-
- return true;
-}
-
-struct ilo_shader_state *
-ilo_shader_create_vs(const struct ilo_dev *dev,
- const struct pipe_shader_state *state,
- const struct ilo_state_vector *precompile)
-{
- struct ilo_shader_state *shader;
-
- shader = ilo_shader_state_create(dev, precompile,
- PIPE_SHADER_VERTEX, state);
-
- /* states used in ilo_shader_variant_init() */
- shader->info.non_orthogonal_states = ILO_DIRTY_VIEW_VS |
- ILO_DIRTY_RASTERIZER |
- ILO_DIRTY_CBUF;
-
- return shader;
-}
-
-struct ilo_shader_state *
-ilo_shader_create_gs(const struct ilo_dev *dev,
- const struct pipe_shader_state *state,
- const struct ilo_state_vector *precompile)
-{
- struct ilo_shader_state *shader;
-
- shader = ilo_shader_state_create(dev, precompile,
- PIPE_SHADER_GEOMETRY, state);
-
- /* states used in ilo_shader_variant_init() */
- shader->info.non_orthogonal_states = ILO_DIRTY_VIEW_GS |
- ILO_DIRTY_VS |
- ILO_DIRTY_RASTERIZER |
- ILO_DIRTY_CBUF;
-
- return shader;
-}
-
-struct ilo_shader_state *
-ilo_shader_create_fs(const struct ilo_dev *dev,
- const struct pipe_shader_state *state,
- const struct ilo_state_vector *precompile)
-{
- struct ilo_shader_state *shader;
-
- shader = ilo_shader_state_create(dev, precompile,
- PIPE_SHADER_FRAGMENT, state);
-
- /* states used in ilo_shader_variant_init() */
- shader->info.non_orthogonal_states = ILO_DIRTY_VIEW_FS |
- ILO_DIRTY_RASTERIZER |
- ILO_DIRTY_FB |
- ILO_DIRTY_CBUF;
-
- return shader;
-}
-
-struct ilo_shader_state *
-ilo_shader_create_cs(const struct ilo_dev *dev,
- const struct pipe_compute_state *state,
- const struct ilo_state_vector *precompile)
-{
- struct ilo_shader_state *shader;
-
- shader = ilo_shader_state_create(dev, precompile,
- PIPE_SHADER_COMPUTE, state);
-
- shader->info.non_orthogonal_states = 0;
-
- return shader;
-}
-
-/**
- * Destroy a shader state.
- */
-void
-ilo_shader_destroy(struct ilo_shader_state *shader)
-{
- struct ilo_shader *sh, *next;
-
- LIST_FOR_EACH_ENTRY_SAFE(sh, next, &shader->variants, list)
- ilo_shader_destroy_kernel(sh);
-
- FREE((struct tgsi_token *) shader->info.tokens);
- FREE(shader);
-}
-
-/**
- * Select a kernel for the given context. This will compile a new kernel if
- * none of the existing kernels work with the context.
- *
- * \param ilo the context
- * \param dirty states of the context that are considered changed
- * \return true if a different kernel is selected
- */
-bool
-ilo_shader_select_kernel(struct ilo_shader_state *shader,
- const struct ilo_state_vector *vec,
- uint32_t dirty)
-{
- struct ilo_shader_variant variant;
- bool changed = false;
-
- if (shader->info.non_orthogonal_states & dirty) {
- const struct ilo_shader * const old = shader->shader;
-
- ilo_shader_variant_init(&variant, &shader->info, vec);
- ilo_shader_state_use_variant(shader, &variant);
- changed = (shader->shader != old);
- }
-
- if (shader->info.type == PIPE_SHADER_FRAGMENT) {
- struct ilo_shader *kernel = shader->shader;
-
- if (kernel->ps_params.sample_mask != vec->sample_mask ||
- kernel->ps_params.alpha_may_kill != vec->blend->alpha_may_kill) {
- kernel->ps_params.sample_mask = vec->sample_mask;
- kernel->ps_params.alpha_may_kill = vec->blend->alpha_may_kill;
-
- ilo_state_ps_set_params(&kernel->cso.ps, shader->info.dev,
- &kernel->ps_params);
-
- changed = true;
- }
- }
-
- return changed;
-}
-
-static int
-route_attr(const int *semantics, const int *indices, int len,
- int semantic, int index)
-{
- int i;
-
- for (i = 0; i < len; i++) {
- if (semantics[i] == semantic && indices[i] == index)
- return i;
- }
-
- /* failed to match for COLOR, try BCOLOR */
- if (semantic == TGSI_SEMANTIC_COLOR) {
- for (i = 0; i < len; i++) {
- if (semantics[i] == TGSI_SEMANTIC_BCOLOR && indices[i] == index)
- return i;
- }
- }
-
- return -1;
-}
-
-/**
- * Select a routing for the given source shader and rasterizer state.
- *
- * \return true if a different routing is selected
- */
-bool
-ilo_shader_select_kernel_sbe(struct ilo_shader_state *shader,
- const struct ilo_shader_state *source,
- const struct ilo_rasterizer_state *rasterizer)
-{
- const bool is_point = true;
- const bool light_twoside = rasterizer->state.light_twoside;
- const uint32_t sprite_coord_enable = rasterizer->state.sprite_coord_enable;
- const int sprite_coord_mode = rasterizer->state.sprite_coord_mode;
- struct ilo_shader *kernel = shader->shader;
- struct ilo_kernel_routing *routing = &kernel->routing;
- struct ilo_state_sbe_swizzle_info swizzles[ILO_STATE_SBE_MAX_SWIZZLE_COUNT];
- struct ilo_state_sbe_info info;
- const int *src_semantics, *src_indices;
- int src_skip, src_len, src_slot;
- int dst_len, dst_slot;
-
- assert(kernel);
-
- if (source) {
- assert(source->shader);
-
- src_semantics = source->shader->out.semantic_names;
- src_indices = source->shader->out.semantic_indices;
- src_len = source->shader->out.count;
- src_skip = 0;
-
- assert(src_len >= 2 &&
- src_semantics[0] == TGSI_SEMANTIC_PSIZE &&
- src_semantics[1] == TGSI_SEMANTIC_POSITION);
-
- /*
- * skip PSIZE and POSITION (how about the optional CLIPDISTs?), unless
- * they are all the source shader has and FS needs to read some
- * attributes.
- */
- if (src_len > 2 || !kernel->in.count) {
- src_semantics += 2;
- src_indices += 2;
- src_len -= 2;
- src_skip = 2;
- }
- } else {
- src_semantics = kernel->in.semantic_names;
- src_indices = kernel->in.semantic_indices;
- src_len = kernel->in.count;
- src_skip = 0;
- }
-
- /* no change */
- if (routing->initialized &&
- routing->is_point == is_point &&
- routing->light_twoside == light_twoside &&
- routing->sprite_coord_enable == sprite_coord_enable &&
- routing->sprite_coord_mode == sprite_coord_mode &&
- routing->src_len <= src_len &&
- !memcmp(routing->src_semantics, src_semantics,
- sizeof(src_semantics[0]) * routing->src_len) &&
- !memcmp(routing->src_indices, src_indices,
- sizeof(src_indices[0]) * routing->src_len))
- return false;
-
- routing->is_point = is_point;
- routing->light_twoside = light_twoside;
- routing->sprite_coord_enable = sprite_coord_enable;
- routing->sprite_coord_mode = sprite_coord_mode;
-
- assert(kernel->in.count <= ARRAY_SIZE(swizzles));
- dst_len = MIN2(kernel->in.count, ARRAY_SIZE(swizzles));
-
- memset(&swizzles, 0, sizeof(swizzles));
- memset(&info, 0, sizeof(info));
-
- info.attr_count = dst_len;
- info.cv_vue_attr_count = src_skip + src_len;
- info.vue_read_base = src_skip;
- info.vue_read_count = 0;
- info.has_min_read_count = true;
- info.swizzle_enable = false;
- info.swizzle_16_31 = false;
- info.swizzle_count = 0;
- info.swizzles = swizzles;
- info.const_interp_enables = kernel->in.const_interp_enable;
- info.point_sprite_enables = 0x0;
- info.point_sprite_origin_lower_left =
- (sprite_coord_mode == PIPE_SPRITE_COORD_LOWER_LEFT);
- info.cv_is_point = is_point;
-
- for (dst_slot = 0; dst_slot < dst_len; dst_slot++) {
- const int semantic = kernel->in.semantic_names[dst_slot];
- const int index = kernel->in.semantic_indices[dst_slot];
-
- if (semantic == TGSI_SEMANTIC_GENERIC &&
- (sprite_coord_enable & (1 << index)))
- info.point_sprite_enables |= 1 << dst_slot;
-
- if (source) {
- src_slot = route_attr(src_semantics, src_indices, src_len,
- semantic, index);
-
- /*
- * The source shader stage does not output this attribute. The value
- * is supposed to be undefined, unless the attribute goes through
- * point sprite replacement or the attribute is
- * TGSI_SEMANTIC_POSITION. In all cases, we do not care which source
- * attribute is picked.
- *
- * We should update the kernel code and omit the output of
- * TGSI_SEMANTIC_POSITION here.
- */
- if (src_slot < 0)
- src_slot = 0;
- } else {
- src_slot = dst_slot;
- }
-
- /* use the following slot for two-sided lighting */
- if (semantic == TGSI_SEMANTIC_COLOR && light_twoside &&
- src_slot + 1 < src_len &&
- src_semantics[src_slot + 1] == TGSI_SEMANTIC_BCOLOR &&
- src_indices[src_slot + 1] == index) {
- swizzles[dst_slot].attr_select = GEN6_INPUTATTR_FACING;
- swizzles[dst_slot].attr = src_slot;
- info.swizzle_enable = true;
- src_slot++;
- } else {
- swizzles[dst_slot].attr_select = GEN6_INPUTATTR_NORMAL;
- swizzles[dst_slot].attr = src_slot;
- if (src_slot != dst_slot)
- info.swizzle_enable = true;
- }
-
- swizzles[dst_slot].force_zeros = false;
-
- if (info.vue_read_count < src_slot + 1)
- info.vue_read_count = src_slot + 1;
- }
-
- if (info.swizzle_enable)
- info.swizzle_count = dst_len;
-
- if (routing->initialized)
- ilo_state_sbe_set_info(&routing->sbe, shader->info.dev, &info);
- else
- ilo_state_sbe_init(&routing->sbe, shader->info.dev, &info);
-
- routing->src_len = info.vue_read_count;
- memcpy(routing->src_semantics, src_semantics,
- sizeof(src_semantics[0]) * routing->src_len);
- memcpy(routing->src_indices, src_indices,
- sizeof(src_indices[0]) * routing->src_len);
-
- routing->initialized = true;
-
- return true;
-}
-
-/**
- * Return the cache offset of the selected kernel. This must be called after
- * ilo_shader_select_kernel() and ilo_shader_cache_upload().
- */
-uint32_t
-ilo_shader_get_kernel_offset(const struct ilo_shader_state *shader)
-{
- const struct ilo_shader *kernel = shader->shader;
-
- assert(kernel && kernel->uploaded);
-
- return kernel->cache_offset;
-}
-
-/**
- * Query a kernel parameter for the selected kernel.
- */
-int
-ilo_shader_get_kernel_param(const struct ilo_shader_state *shader,
- enum ilo_kernel_param param)
-{
- const struct ilo_shader *kernel = shader->shader;
- int val;
-
- assert(kernel);
-
- switch (param) {
- case ILO_KERNEL_INPUT_COUNT:
- val = kernel->in.count;
- break;
- case ILO_KERNEL_OUTPUT_COUNT:
- val = kernel->out.count;
- break;
- case ILO_KERNEL_SAMPLER_COUNT:
- val = shader->info.num_samplers;
- break;
- case ILO_KERNEL_SKIP_CBUF0_UPLOAD:
- val = kernel->skip_cbuf0_upload;
- break;
- case ILO_KERNEL_PCB_CBUF0_SIZE:
- val = kernel->pcb.cbuf0_size;
- break;
-
- case ILO_KERNEL_SURFACE_TOTAL_COUNT:
- val = kernel->bt.total_count;
- break;
- case ILO_KERNEL_SURFACE_TEX_BASE:
- val = kernel->bt.tex_base;
- break;
- case ILO_KERNEL_SURFACE_TEX_COUNT:
- val = kernel->bt.tex_count;
- break;
- case ILO_KERNEL_SURFACE_CONST_BASE:
- val = kernel->bt.const_base;
- break;
- case ILO_KERNEL_SURFACE_CONST_COUNT:
- val = kernel->bt.const_count;
- break;
- case ILO_KERNEL_SURFACE_RES_BASE:
- val = kernel->bt.res_base;
- break;
- case ILO_KERNEL_SURFACE_RES_COUNT:
- val = kernel->bt.res_count;
- break;
-
- case ILO_KERNEL_VS_INPUT_INSTANCEID:
- val = shader->info.has_instanceid;
- break;
- case ILO_KERNEL_VS_INPUT_VERTEXID:
- val = shader->info.has_vertexid;
- break;
- case ILO_KERNEL_VS_INPUT_EDGEFLAG:
- if (shader->info.edgeflag_in >= 0) {
- /* we rely on the state tracker here */
- assert(shader->info.edgeflag_in == kernel->in.count - 1);
- val = true;
- }
- else {
- val = false;
- }
- break;
- case ILO_KERNEL_VS_PCB_UCP_SIZE:
- val = kernel->pcb.clip_state_size;
- break;
- case ILO_KERNEL_VS_GEN6_SO:
- val = kernel->stream_output;
- break;
- case ILO_KERNEL_VS_GEN6_SO_POINT_OFFSET:
- val = kernel->gs_offsets[0];
- break;
- case ILO_KERNEL_VS_GEN6_SO_LINE_OFFSET:
- val = kernel->gs_offsets[1];
- break;
- case ILO_KERNEL_VS_GEN6_SO_TRI_OFFSET:
- val = kernel->gs_offsets[2];
- break;
- case ILO_KERNEL_VS_GEN6_SO_SURFACE_COUNT:
- val = kernel->gs_bt_so_count;
- break;
-
- case ILO_KERNEL_GS_DISCARD_ADJACENCY:
- val = kernel->in.discard_adj;
- break;
- case ILO_KERNEL_GS_GEN6_SVBI_POST_INC:
- val = kernel->svbi_post_inc;
- break;
- case ILO_KERNEL_GS_GEN6_SURFACE_SO_BASE:
- val = kernel->bt.gen6_so_base;
- break;
- case ILO_KERNEL_GS_GEN6_SURFACE_SO_COUNT:
- val = kernel->bt.gen6_so_count;
- break;
-
- case ILO_KERNEL_FS_BARYCENTRIC_INTERPOLATIONS:
- val = kernel->in.barycentric_interpolation_mode;
- break;
- case ILO_KERNEL_FS_DISPATCH_16_OFFSET:
- val = 0;
- break;
- case ILO_KERNEL_FS_SURFACE_RT_BASE:
- val = kernel->bt.rt_base;
- break;
- case ILO_KERNEL_FS_SURFACE_RT_COUNT:
- val = kernel->bt.rt_count;
- break;
-
- case ILO_KERNEL_CS_LOCAL_SIZE:
- val = shader->info.compute.req_local_mem;
- break;
- case ILO_KERNEL_CS_PRIVATE_SIZE:
- val = shader->info.compute.req_private_mem;
- break;
- case ILO_KERNEL_CS_INPUT_SIZE:
- val = shader->info.compute.req_input_mem;
- break;
- case ILO_KERNEL_CS_SIMD_SIZE:
- val = 16;
- break;
- case ILO_KERNEL_CS_SURFACE_GLOBAL_BASE:
- val = kernel->bt.global_base;
- break;
- case ILO_KERNEL_CS_SURFACE_GLOBAL_COUNT:
- val = kernel->bt.global_count;
- break;
-
- default:
- assert(!"unknown kernel parameter");
- val = 0;
- break;
- }
-
- return val;
-}
-
-/**
- * Return the CSO of the selected kernel.
- */
-const union ilo_shader_cso *
-ilo_shader_get_kernel_cso(const struct ilo_shader_state *shader)
-{
- const struct ilo_shader *kernel = shader->shader;
-
- assert(kernel);
-
- return &kernel->cso;
-}
-
-/**
- * Return the SO info of the selected kernel.
- */
-const struct pipe_stream_output_info *
-ilo_shader_get_kernel_so_info(const struct ilo_shader_state *shader)
-{
- return &shader->info.stream_output;
-}
-
-const struct ilo_state_sol *
-ilo_shader_get_kernel_sol(const struct ilo_shader_state *shader)
-{
- const struct ilo_shader *kernel = shader->shader;
-
- assert(kernel);
-
- return &kernel->sol;
-}
-
-/**
- * Return the routing info of the selected kernel.
- */
-const struct ilo_state_sbe *
-ilo_shader_get_kernel_sbe(const struct ilo_shader_state *shader)
-{
- const struct ilo_shader *kernel = shader->shader;
-
- assert(kernel);
-
- return &kernel->routing.sbe;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_SHADER_H
-#define ILO_SHADER_H
-
-#include "core/ilo_state_shader.h"
-
-#include "ilo_common.h"
-
-enum ilo_kernel_param {
- ILO_KERNEL_INPUT_COUNT,
- ILO_KERNEL_OUTPUT_COUNT,
- ILO_KERNEL_SAMPLER_COUNT,
- ILO_KERNEL_SKIP_CBUF0_UPLOAD,
- ILO_KERNEL_PCB_CBUF0_SIZE,
-
- ILO_KERNEL_SURFACE_TOTAL_COUNT,
- ILO_KERNEL_SURFACE_TEX_BASE,
- ILO_KERNEL_SURFACE_TEX_COUNT,
- ILO_KERNEL_SURFACE_CONST_BASE,
- ILO_KERNEL_SURFACE_CONST_COUNT,
- ILO_KERNEL_SURFACE_RES_BASE,
- ILO_KERNEL_SURFACE_RES_COUNT,
-
- ILO_KERNEL_VS_INPUT_INSTANCEID,
- ILO_KERNEL_VS_INPUT_VERTEXID,
- ILO_KERNEL_VS_INPUT_EDGEFLAG,
- ILO_KERNEL_VS_PCB_UCP_SIZE,
- ILO_KERNEL_VS_GEN6_SO,
- ILO_KERNEL_VS_GEN6_SO_POINT_OFFSET,
- ILO_KERNEL_VS_GEN6_SO_LINE_OFFSET,
- ILO_KERNEL_VS_GEN6_SO_TRI_OFFSET,
- ILO_KERNEL_VS_GEN6_SO_SURFACE_COUNT,
-
- ILO_KERNEL_GS_DISCARD_ADJACENCY,
- ILO_KERNEL_GS_GEN6_SVBI_POST_INC,
- ILO_KERNEL_GS_GEN6_SURFACE_SO_BASE,
- ILO_KERNEL_GS_GEN6_SURFACE_SO_COUNT,
-
- ILO_KERNEL_FS_BARYCENTRIC_INTERPOLATIONS,
- ILO_KERNEL_FS_DISPATCH_16_OFFSET,
- ILO_KERNEL_FS_SURFACE_RT_BASE,
- ILO_KERNEL_FS_SURFACE_RT_COUNT,
-
- ILO_KERNEL_CS_LOCAL_SIZE,
- ILO_KERNEL_CS_PRIVATE_SIZE,
- ILO_KERNEL_CS_INPUT_SIZE,
- ILO_KERNEL_CS_SIMD_SIZE,
- ILO_KERNEL_CS_SURFACE_GLOBAL_BASE,
- ILO_KERNEL_CS_SURFACE_GLOBAL_COUNT,
-
- ILO_KERNEL_PARAM_COUNT,
-};
-
-struct intel_bo;
-struct ilo_builder;
-struct ilo_rasterizer_state;
-struct ilo_shader_cache;
-struct ilo_shader_state;
-struct ilo_state_sbe;
-struct ilo_state_sol;
-struct ilo_state_vector;
-
-union ilo_shader_cso {
- struct ilo_state_vs vs;
- struct ilo_state_hs hs;
- struct ilo_state_ds ds;
- struct ilo_state_gs gs;
- struct ilo_state_ps ps;
-
- struct {
- struct ilo_state_vs vs;
- struct ilo_state_gs sol;
- } vs_sol;
-};
-
-struct ilo_shader_cache *
-ilo_shader_cache_create(void);
-
-void
-ilo_shader_cache_destroy(struct ilo_shader_cache *shc);
-
-void
-ilo_shader_cache_add(struct ilo_shader_cache *shc,
- struct ilo_shader_state *shader);
-
-void
-ilo_shader_cache_remove(struct ilo_shader_cache *shc,
- struct ilo_shader_state *shader);
-
-void
-ilo_shader_cache_upload(struct ilo_shader_cache *shc,
- struct ilo_builder *builder);
-
-void
-ilo_shader_cache_invalidate(struct ilo_shader_cache *shc);
-
-void
-ilo_shader_cache_get_max_scratch_sizes(const struct ilo_shader_cache *shc,
- int *vs_scratch_size,
- int *gs_scratch_size,
- int *fs_scratch_size);
-
-struct ilo_shader_state *
-ilo_shader_create_vs(const struct ilo_dev *dev,
- const struct pipe_shader_state *state,
- const struct ilo_state_vector *precompile);
-
-struct ilo_shader_state *
-ilo_shader_create_gs(const struct ilo_dev *dev,
- const struct pipe_shader_state *state,
- const struct ilo_state_vector *precompile);
-
-struct ilo_shader_state *
-ilo_shader_create_fs(const struct ilo_dev *dev,
- const struct pipe_shader_state *state,
- const struct ilo_state_vector *precompile);
-
-struct ilo_shader_state *
-ilo_shader_create_cs(const struct ilo_dev *dev,
- const struct pipe_compute_state *state,
- const struct ilo_state_vector *precompile);
-
-void
-ilo_shader_destroy(struct ilo_shader_state *shader);
-
-bool
-ilo_shader_select_kernel(struct ilo_shader_state *shader,
- const struct ilo_state_vector *vec,
- uint32_t dirty);
-
-bool
-ilo_shader_select_kernel_sbe(struct ilo_shader_state *shader,
- const struct ilo_shader_state *source,
- const struct ilo_rasterizer_state *rasterizer);
-
-uint32_t
-ilo_shader_get_kernel_offset(const struct ilo_shader_state *shader);
-
-int
-ilo_shader_get_kernel_param(const struct ilo_shader_state *shader,
- enum ilo_kernel_param param);
-
-const union ilo_shader_cso *
-ilo_shader_get_kernel_cso(const struct ilo_shader_state *shader);
-
-const struct pipe_stream_output_info *
-ilo_shader_get_kernel_so_info(const struct ilo_shader_state *shader);
-
-const struct ilo_state_sol *
-ilo_shader_get_kernel_sol(const struct ilo_shader_state *shader);
-
-const struct ilo_state_sbe *
-ilo_shader_get_kernel_sbe(const struct ilo_shader_state *shader);
-
-#endif /* ILO_SHADER_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "util/u_dual_blend.h"
-#include "util/u_dynarray.h"
-#include "util/u_framebuffer.h"
-#include "util/u_helpers.h"
-#include "util/u_resource.h"
-#include "util/u_upload_mgr.h"
-
-#include "ilo_context.h"
-#include "ilo_format.h"
-#include "ilo_resource.h"
-#include "ilo_shader.h"
-#include "ilo_state.h"
-
-/**
- * Translate a pipe primitive type to the matching hardware primitive type.
- */
-static enum gen_3dprim_type
-ilo_translate_draw_mode(unsigned mode)
-{
- static const enum gen_3dprim_type prim_mapping[PIPE_PRIM_MAX] = {
- [PIPE_PRIM_POINTS] = GEN6_3DPRIM_POINTLIST,
- [PIPE_PRIM_LINES] = GEN6_3DPRIM_LINELIST,
- [PIPE_PRIM_LINE_LOOP] = GEN6_3DPRIM_LINELOOP,
- [PIPE_PRIM_LINE_STRIP] = GEN6_3DPRIM_LINESTRIP,
- [PIPE_PRIM_TRIANGLES] = GEN6_3DPRIM_TRILIST,
- [PIPE_PRIM_TRIANGLE_STRIP] = GEN6_3DPRIM_TRISTRIP,
- [PIPE_PRIM_TRIANGLE_FAN] = GEN6_3DPRIM_TRIFAN,
- [PIPE_PRIM_QUADS] = GEN6_3DPRIM_QUADLIST,
- [PIPE_PRIM_QUAD_STRIP] = GEN6_3DPRIM_QUADSTRIP,
- [PIPE_PRIM_POLYGON] = GEN6_3DPRIM_POLYGON,
- [PIPE_PRIM_LINES_ADJACENCY] = GEN6_3DPRIM_LINELIST_ADJ,
- [PIPE_PRIM_LINE_STRIP_ADJACENCY] = GEN6_3DPRIM_LINESTRIP_ADJ,
- [PIPE_PRIM_TRIANGLES_ADJACENCY] = GEN6_3DPRIM_TRILIST_ADJ,
- [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = GEN6_3DPRIM_TRISTRIP_ADJ,
- };
-
- assert(prim_mapping[mode]);
-
- return prim_mapping[mode];
-}
-
-static enum gen_index_format
-ilo_translate_index_size(unsigned index_size)
-{
- switch (index_size) {
- case 1: return GEN6_INDEX_BYTE;
- case 2: return GEN6_INDEX_WORD;
- case 4: return GEN6_INDEX_DWORD;
- default:
- assert(!"unknown index size");
- return GEN6_INDEX_BYTE;
- }
-}
-
-static enum gen_mip_filter
-ilo_translate_mip_filter(unsigned filter)
-{
- switch (filter) {
- case PIPE_TEX_MIPFILTER_NEAREST: return GEN6_MIPFILTER_NEAREST;
- case PIPE_TEX_MIPFILTER_LINEAR: return GEN6_MIPFILTER_LINEAR;
- case PIPE_TEX_MIPFILTER_NONE: return GEN6_MIPFILTER_NONE;
- default:
- assert(!"unknown mipfilter");
- return GEN6_MIPFILTER_NONE;
- }
-}
-
-static int
-ilo_translate_img_filter(unsigned filter)
-{
- switch (filter) {
- case PIPE_TEX_FILTER_NEAREST: return GEN6_MAPFILTER_NEAREST;
- case PIPE_TEX_FILTER_LINEAR: return GEN6_MAPFILTER_LINEAR;
- default:
- assert(!"unknown sampler filter");
- return GEN6_MAPFILTER_NEAREST;
- }
-}
-
-static enum gen_texcoord_mode
-ilo_translate_address_wrap(unsigned wrap)
-{
- switch (wrap) {
- case PIPE_TEX_WRAP_CLAMP: return GEN8_TEXCOORDMODE_HALF_BORDER;
- case PIPE_TEX_WRAP_REPEAT: return GEN6_TEXCOORDMODE_WRAP;
- case PIPE_TEX_WRAP_CLAMP_TO_EDGE: return GEN6_TEXCOORDMODE_CLAMP;
- case PIPE_TEX_WRAP_CLAMP_TO_BORDER: return GEN6_TEXCOORDMODE_CLAMP_BORDER;
- case PIPE_TEX_WRAP_MIRROR_REPEAT: return GEN6_TEXCOORDMODE_MIRROR;
- case PIPE_TEX_WRAP_MIRROR_CLAMP:
- case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
- case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
- default:
- assert(!"unknown sampler wrap mode");
- return GEN6_TEXCOORDMODE_WRAP;
- }
-}
-
-static enum gen_aniso_ratio
-ilo_translate_max_anisotropy(unsigned max_anisotropy)
-{
- switch (max_anisotropy) {
- case 0: case 1: case 2: return GEN6_ANISORATIO_2;
- case 3: case 4: return GEN6_ANISORATIO_4;
- case 5: case 6: return GEN6_ANISORATIO_6;
- case 7: case 8: return GEN6_ANISORATIO_8;
- case 9: case 10: return GEN6_ANISORATIO_10;
- case 11: case 12: return GEN6_ANISORATIO_12;
- case 13: case 14: return GEN6_ANISORATIO_14;
- default: return GEN6_ANISORATIO_16;
- }
-}
-
-static enum gen_prefilter_op
-ilo_translate_shadow_func(unsigned func)
-{
- /*
- * For PIPE_FUNC_x, the reference value is on the left-hand side of the
- * comparison, and 1.0 is returned when the comparison is true.
- *
- * For GEN6_PREFILTEROP_x, the reference value is on the right-hand side of
- * the comparison, and 0.0 is returned when the comparison is true.
- */
- switch (func) {
- case PIPE_FUNC_NEVER: return GEN6_PREFILTEROP_ALWAYS;
- case PIPE_FUNC_LESS: return GEN6_PREFILTEROP_LEQUAL;
- case PIPE_FUNC_EQUAL: return GEN6_PREFILTEROP_NOTEQUAL;
- case PIPE_FUNC_LEQUAL: return GEN6_PREFILTEROP_LESS;
- case PIPE_FUNC_GREATER: return GEN6_PREFILTEROP_GEQUAL;
- case PIPE_FUNC_NOTEQUAL: return GEN6_PREFILTEROP_EQUAL;
- case PIPE_FUNC_GEQUAL: return GEN6_PREFILTEROP_GREATER;
- case PIPE_FUNC_ALWAYS: return GEN6_PREFILTEROP_NEVER;
- default:
- assert(!"unknown shadow compare function");
- return GEN6_PREFILTEROP_NEVER;
- }
-}
-
-static enum gen_front_winding
-ilo_translate_front_ccw(unsigned front_ccw)
-{
- return (front_ccw) ? GEN6_FRONTWINDING_CCW : GEN6_FRONTWINDING_CW;
-}
-
-static enum gen_cull_mode
-ilo_translate_cull_face(unsigned cull_face)
-{
- switch (cull_face) {
- case PIPE_FACE_NONE: return GEN6_CULLMODE_NONE;
- case PIPE_FACE_FRONT: return GEN6_CULLMODE_FRONT;
- case PIPE_FACE_BACK: return GEN6_CULLMODE_BACK;
- case PIPE_FACE_FRONT_AND_BACK: return GEN6_CULLMODE_BOTH;
- default:
- assert(!"unknown face culling");
- return GEN6_CULLMODE_NONE;
- }
-}
-
-static enum gen_fill_mode
-ilo_translate_poly_mode(unsigned poly_mode)
-{
- switch (poly_mode) {
- case PIPE_POLYGON_MODE_FILL: return GEN6_FILLMODE_SOLID;
- case PIPE_POLYGON_MODE_LINE: return GEN6_FILLMODE_WIREFRAME;
- case PIPE_POLYGON_MODE_POINT: return GEN6_FILLMODE_POINT;
- default:
- assert(!"unknown polygon mode");
- return GEN6_FILLMODE_SOLID;
- }
-}
-
-static enum gen_pixel_location
-ilo_translate_half_pixel_center(bool half_pixel_center)
-{
- return (half_pixel_center) ? GEN6_PIXLOC_CENTER : GEN6_PIXLOC_UL_CORNER;
-}
-
-static enum gen_compare_function
-ilo_translate_compare_func(unsigned func)
-{
- switch (func) {
- case PIPE_FUNC_NEVER: return GEN6_COMPAREFUNCTION_NEVER;
- case PIPE_FUNC_LESS: return GEN6_COMPAREFUNCTION_LESS;
- case PIPE_FUNC_EQUAL: return GEN6_COMPAREFUNCTION_EQUAL;
- case PIPE_FUNC_LEQUAL: return GEN6_COMPAREFUNCTION_LEQUAL;
- case PIPE_FUNC_GREATER: return GEN6_COMPAREFUNCTION_GREATER;
- case PIPE_FUNC_NOTEQUAL: return GEN6_COMPAREFUNCTION_NOTEQUAL;
- case PIPE_FUNC_GEQUAL: return GEN6_COMPAREFUNCTION_GEQUAL;
- case PIPE_FUNC_ALWAYS: return GEN6_COMPAREFUNCTION_ALWAYS;
- default:
- assert(!"unknown compare function");
- return GEN6_COMPAREFUNCTION_NEVER;
- }
-}
-
-static enum gen_stencil_op
-ilo_translate_stencil_op(unsigned stencil_op)
-{
- switch (stencil_op) {
- case PIPE_STENCIL_OP_KEEP: return GEN6_STENCILOP_KEEP;
- case PIPE_STENCIL_OP_ZERO: return GEN6_STENCILOP_ZERO;
- case PIPE_STENCIL_OP_REPLACE: return GEN6_STENCILOP_REPLACE;
- case PIPE_STENCIL_OP_INCR: return GEN6_STENCILOP_INCRSAT;
- case PIPE_STENCIL_OP_DECR: return GEN6_STENCILOP_DECRSAT;
- case PIPE_STENCIL_OP_INCR_WRAP: return GEN6_STENCILOP_INCR;
- case PIPE_STENCIL_OP_DECR_WRAP: return GEN6_STENCILOP_DECR;
- case PIPE_STENCIL_OP_INVERT: return GEN6_STENCILOP_INVERT;
- default:
- assert(!"unknown stencil op");
- return GEN6_STENCILOP_KEEP;
- }
-}
-
-static enum gen_logic_op
-ilo_translate_logicop(unsigned logicop)
-{
- switch (logicop) {
- case PIPE_LOGICOP_CLEAR: return GEN6_LOGICOP_CLEAR;
- case PIPE_LOGICOP_NOR: return GEN6_LOGICOP_NOR;
- case PIPE_LOGICOP_AND_INVERTED: return GEN6_LOGICOP_AND_INVERTED;
- case PIPE_LOGICOP_COPY_INVERTED: return GEN6_LOGICOP_COPY_INVERTED;
- case PIPE_LOGICOP_AND_REVERSE: return GEN6_LOGICOP_AND_REVERSE;
- case PIPE_LOGICOP_INVERT: return GEN6_LOGICOP_INVERT;
- case PIPE_LOGICOP_XOR: return GEN6_LOGICOP_XOR;
- case PIPE_LOGICOP_NAND: return GEN6_LOGICOP_NAND;
- case PIPE_LOGICOP_AND: return GEN6_LOGICOP_AND;
- case PIPE_LOGICOP_EQUIV: return GEN6_LOGICOP_EQUIV;
- case PIPE_LOGICOP_NOOP: return GEN6_LOGICOP_NOOP;
- case PIPE_LOGICOP_OR_INVERTED: return GEN6_LOGICOP_OR_INVERTED;
- case PIPE_LOGICOP_COPY: return GEN6_LOGICOP_COPY;
- case PIPE_LOGICOP_OR_REVERSE: return GEN6_LOGICOP_OR_REVERSE;
- case PIPE_LOGICOP_OR: return GEN6_LOGICOP_OR;
- case PIPE_LOGICOP_SET: return GEN6_LOGICOP_SET;
- default:
- assert(!"unknown logicop function");
- return GEN6_LOGICOP_CLEAR;
- }
-}
-
-static int
-ilo_translate_blend_func(unsigned blend)
-{
- switch (blend) {
- case PIPE_BLEND_ADD: return GEN6_BLENDFUNCTION_ADD;
- case PIPE_BLEND_SUBTRACT: return GEN6_BLENDFUNCTION_SUBTRACT;
- case PIPE_BLEND_REVERSE_SUBTRACT: return GEN6_BLENDFUNCTION_REVERSE_SUBTRACT;
- case PIPE_BLEND_MIN: return GEN6_BLENDFUNCTION_MIN;
- case PIPE_BLEND_MAX: return GEN6_BLENDFUNCTION_MAX;
- default:
- assert(!"unknown blend function");
- return GEN6_BLENDFUNCTION_ADD;
- }
-}
-
-static int
-ilo_translate_blend_factor(unsigned factor)
-{
- switch (factor) {
- case PIPE_BLENDFACTOR_ONE: return GEN6_BLENDFACTOR_ONE;
- case PIPE_BLENDFACTOR_SRC_COLOR: return GEN6_BLENDFACTOR_SRC_COLOR;
- case PIPE_BLENDFACTOR_SRC_ALPHA: return GEN6_BLENDFACTOR_SRC_ALPHA;
- case PIPE_BLENDFACTOR_DST_ALPHA: return GEN6_BLENDFACTOR_DST_ALPHA;
- case PIPE_BLENDFACTOR_DST_COLOR: return GEN6_BLENDFACTOR_DST_COLOR;
- case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: return GEN6_BLENDFACTOR_SRC_ALPHA_SATURATE;
- case PIPE_BLENDFACTOR_CONST_COLOR: return GEN6_BLENDFACTOR_CONST_COLOR;
- case PIPE_BLENDFACTOR_CONST_ALPHA: return GEN6_BLENDFACTOR_CONST_ALPHA;
- case PIPE_BLENDFACTOR_SRC1_COLOR: return GEN6_BLENDFACTOR_SRC1_COLOR;
- case PIPE_BLENDFACTOR_SRC1_ALPHA: return GEN6_BLENDFACTOR_SRC1_ALPHA;
- case PIPE_BLENDFACTOR_ZERO: return GEN6_BLENDFACTOR_ZERO;
- case PIPE_BLENDFACTOR_INV_SRC_COLOR: return GEN6_BLENDFACTOR_INV_SRC_COLOR;
- case PIPE_BLENDFACTOR_INV_SRC_ALPHA: return GEN6_BLENDFACTOR_INV_SRC_ALPHA;
- case PIPE_BLENDFACTOR_INV_DST_ALPHA: return GEN6_BLENDFACTOR_INV_DST_ALPHA;
- case PIPE_BLENDFACTOR_INV_DST_COLOR: return GEN6_BLENDFACTOR_INV_DST_COLOR;
- case PIPE_BLENDFACTOR_INV_CONST_COLOR: return GEN6_BLENDFACTOR_INV_CONST_COLOR;
- case PIPE_BLENDFACTOR_INV_CONST_ALPHA: return GEN6_BLENDFACTOR_INV_CONST_ALPHA;
- case PIPE_BLENDFACTOR_INV_SRC1_COLOR: return GEN6_BLENDFACTOR_INV_SRC1_COLOR;
- case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: return GEN6_BLENDFACTOR_INV_SRC1_ALPHA;
- default:
- assert(!"unknown blend factor");
- return GEN6_BLENDFACTOR_ONE;
- }
-}
-
-static void
-finalize_shader_states(struct ilo_state_vector *vec)
-{
- unsigned type;
-
- for (type = 0; type < PIPE_SHADER_TYPES; type++) {
- struct ilo_shader_state *shader;
- uint32_t state;
-
- switch (type) {
- case PIPE_SHADER_VERTEX:
- shader = vec->vs;
- state = ILO_DIRTY_VS;
- break;
- case PIPE_SHADER_GEOMETRY:
- shader = vec->gs;
- state = ILO_DIRTY_GS;
- break;
- case PIPE_SHADER_FRAGMENT:
- shader = vec->fs;
- state = ILO_DIRTY_FS;
- break;
- default:
- shader = NULL;
- state = 0;
- break;
- }
-
- if (!shader)
- continue;
-
- /* compile if the shader or the states it depends on changed */
- if (vec->dirty & state) {
- ilo_shader_select_kernel(shader, vec, ILO_DIRTY_ALL);
- }
- else if (ilo_shader_select_kernel(shader, vec, vec->dirty)) {
- /* mark the state dirty if a new kernel is selected */
- vec->dirty |= state;
- }
-
- /* need to setup SBE for FS */
- if (type == PIPE_SHADER_FRAGMENT && vec->dirty &
- (state | ILO_DIRTY_GS | ILO_DIRTY_VS | ILO_DIRTY_RASTERIZER)) {
- if (ilo_shader_select_kernel_sbe(shader,
- (vec->gs) ? vec->gs : vec->vs, vec->rasterizer))
- vec->dirty |= state;
- }
- }
-}
-
-static void
-finalize_cbuf_state(struct ilo_context *ilo,
- struct ilo_cbuf_state *cbuf,
- const struct ilo_shader_state *sh)
-{
- uint32_t upload_mask = cbuf->enabled_mask;
-
- /* skip CBUF0 if the kernel does not need it */
- upload_mask &=
- ~ilo_shader_get_kernel_param(sh, ILO_KERNEL_SKIP_CBUF0_UPLOAD);
-
- while (upload_mask) {
- unsigned offset, i;
-
- i = u_bit_scan(&upload_mask);
- /* no need to upload */
- if (cbuf->cso[i].resource)
- continue;
-
- u_upload_data(ilo->uploader, 0, cbuf->cso[i].info.size, 16,
- cbuf->cso[i].user_buffer, &offset, &cbuf->cso[i].resource);
-
- cbuf->cso[i].info.vma = ilo_resource_get_vma(cbuf->cso[i].resource);
- cbuf->cso[i].info.offset = offset;
-
- memset(&cbuf->cso[i].surface, 0, sizeof(cbuf->cso[i].surface));
- ilo_state_surface_init_for_buffer(&cbuf->cso[i].surface,
- ilo->dev, &cbuf->cso[i].info);
-
- ilo->state_vector.dirty |= ILO_DIRTY_CBUF;
- }
-}
-
-static void
-finalize_constant_buffers(struct ilo_context *ilo)
-{
- struct ilo_state_vector *vec = &ilo->state_vector;
-
- if (vec->dirty & (ILO_DIRTY_CBUF | ILO_DIRTY_VS))
- finalize_cbuf_state(ilo, &vec->cbuf[PIPE_SHADER_VERTEX], vec->vs);
-
- if (ilo->state_vector.dirty & (ILO_DIRTY_CBUF | ILO_DIRTY_FS))
- finalize_cbuf_state(ilo, &vec->cbuf[PIPE_SHADER_FRAGMENT], vec->fs);
-}
-
-static void
-finalize_index_buffer(struct ilo_context *ilo)
-{
- const struct ilo_dev *dev = ilo->dev;
- struct ilo_state_vector *vec = &ilo->state_vector;
- const bool need_upload = (vec->draw->indexed &&
- (vec->ib.state.user_buffer ||
- vec->ib.state.offset % vec->ib.state.index_size));
- struct pipe_resource *current_hw_res = NULL;
- struct ilo_state_index_buffer_info info;
- int64_t vertex_start_bias = 0;
-
- if (!(vec->dirty & ILO_DIRTY_IB) && !need_upload)
- return;
-
- /* make sure vec->ib.hw_resource changes when reallocated */
- pipe_resource_reference(¤t_hw_res, vec->ib.hw_resource);
-
- if (need_upload) {
- const unsigned offset = vec->ib.state.index_size * vec->draw->start;
- const unsigned size = vec->ib.state.index_size * vec->draw->count;
- unsigned hw_offset;
-
- if (vec->ib.state.user_buffer) {
- u_upload_data(ilo->uploader, 0, size, 16,
- vec->ib.state.user_buffer + offset,
- &hw_offset, &vec->ib.hw_resource);
- } else {
- u_upload_buffer(ilo->uploader, 0,
- vec->ib.state.offset + offset, size, 16, vec->ib.state.buffer,
- &hw_offset, &vec->ib.hw_resource);
- }
-
- /* the HW offset should be aligned */
- assert(hw_offset % vec->ib.state.index_size == 0);
- vertex_start_bias = hw_offset / vec->ib.state.index_size;
-
- /*
- * INDEX[vec->draw->start] in the original buffer is INDEX[0] in the HW
- * resource
- */
- vertex_start_bias -= vec->draw->start;
- } else {
- pipe_resource_reference(&vec->ib.hw_resource, vec->ib.state.buffer);
-
- /* note that index size may be zero when the draw is not indexed */
- if (vec->draw->indexed)
- vertex_start_bias = vec->ib.state.offset / vec->ib.state.index_size;
- }
-
- vec->draw_info.vertex_start += vertex_start_bias;
-
- /* treat the IB as clean if the HW states do not change */
- if (vec->ib.hw_resource == current_hw_res &&
- vec->ib.hw_index_size == vec->ib.state.index_size)
- vec->dirty &= ~ILO_DIRTY_IB;
- else
- vec->ib.hw_index_size = vec->ib.state.index_size;
-
- pipe_resource_reference(¤t_hw_res, NULL);
-
- memset(&info, 0, sizeof(info));
- if (vec->ib.hw_resource) {
- info.vma = ilo_resource_get_vma(vec->ib.hw_resource);
- info.size = info.vma->vm_size;
- info.format = ilo_translate_index_size(vec->ib.hw_index_size);
- }
-
- ilo_state_index_buffer_set_info(&vec->ib.ib, dev, &info);
-}
-
-static void
-finalize_vertex_elements(struct ilo_context *ilo)
-{
- const struct ilo_dev *dev = ilo->dev;
- struct ilo_state_vector *vec = &ilo->state_vector;
- struct ilo_ve_state *ve = vec->ve;
- const bool last_element_edge_flag = (vec->vs &&
- ilo_shader_get_kernel_param(vec->vs, ILO_KERNEL_VS_INPUT_EDGEFLAG));
- const bool prepend_vertexid = (vec->vs &&
- ilo_shader_get_kernel_param(vec->vs, ILO_KERNEL_VS_INPUT_VERTEXID));
- const bool prepend_instanceid = (vec->vs &&
- ilo_shader_get_kernel_param(vec->vs,
- ILO_KERNEL_VS_INPUT_INSTANCEID));
- const enum gen_index_format index_format = (vec->draw->indexed) ?
- ilo_translate_index_size(vec->ib.state.index_size) : GEN6_INDEX_DWORD;
-
- /* check for non-orthogonal states */
- if (ve->vf_params.cv_topology != vec->draw_info.topology ||
- ve->vf_params.prepend_vertexid != prepend_vertexid ||
- ve->vf_params.prepend_instanceid != prepend_instanceid ||
- ve->vf_params.last_element_edge_flag != last_element_edge_flag ||
- ve->vf_params.cv_index_format != index_format ||
- ve->vf_params.cut_index_enable != vec->draw->primitive_restart ||
- ve->vf_params.cut_index != vec->draw->restart_index) {
- ve->vf_params.cv_topology = vec->draw_info.topology;
- ve->vf_params.prepend_vertexid = prepend_vertexid;
- ve->vf_params.prepend_instanceid = prepend_instanceid;
- ve->vf_params.last_element_edge_flag = last_element_edge_flag;
- ve->vf_params.cv_index_format = index_format;
- ve->vf_params.cut_index_enable = vec->draw->primitive_restart;
- ve->vf_params.cut_index = vec->draw->restart_index;
-
- ilo_state_vf_set_params(&ve->vf, dev, &ve->vf_params);
-
- vec->dirty |= ILO_DIRTY_VE;
- }
-}
-
-static void
-finalize_vertex_buffers(struct ilo_context *ilo)
-{
- const struct ilo_dev *dev = ilo->dev;
- struct ilo_state_vector *vec = &ilo->state_vector;
- struct ilo_state_vertex_buffer_info info;
- unsigned i;
-
- if (!(vec->dirty & (ILO_DIRTY_VE | ILO_DIRTY_VB)))
- return;
-
- memset(&info, 0, sizeof(info));
-
- for (i = 0; i < vec->ve->vb_count; i++) {
- const unsigned pipe_idx = vec->ve->vb_mapping[i];
- const struct pipe_vertex_buffer *cso = &vec->vb.states[pipe_idx];
-
- if (cso->buffer) {
- info.vma = ilo_resource_get_vma(cso->buffer);
- info.offset = cso->buffer_offset;
- info.size = info.vma->vm_size - cso->buffer_offset;
-
- info.stride = cso->stride;
- } else {
- memset(&info, 0, sizeof(info));
- }
-
- ilo_state_vertex_buffer_set_info(&vec->vb.vb[i], dev, &info);
- }
-}
-
-static void
-finalize_urb(struct ilo_context *ilo)
-{
- const uint16_t attr_size = sizeof(uint32_t) * 4;
- const struct ilo_dev *dev = ilo->dev;
- struct ilo_state_vector *vec = &ilo->state_vector;
- struct ilo_state_urb_info info;
-
- if (!(vec->dirty & (ILO_DIRTY_VE | ILO_DIRTY_VS |
- ILO_DIRTY_GS | ILO_DIRTY_FS)))
- return;
-
- memset(&info, 0, sizeof(info));
-
- info.ve_entry_size = attr_size * ilo_state_vf_get_attr_count(&vec->ve->vf);
-
- if (vec->vs) {
- info.vs_const_data = (bool)
- (ilo_shader_get_kernel_param(vec->vs, ILO_KERNEL_PCB_CBUF0_SIZE) +
- ilo_shader_get_kernel_param(vec->vs, ILO_KERNEL_VS_PCB_UCP_SIZE));
- info.vs_entry_size = attr_size *
- ilo_shader_get_kernel_param(vec->vs, ILO_KERNEL_OUTPUT_COUNT);
- }
-
- if (vec->gs) {
- info.gs_const_data = (bool)
- ilo_shader_get_kernel_param(vec->gs, ILO_KERNEL_PCB_CBUF0_SIZE);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 189:
- *
- * "All outputs of a GS thread will be stored in the single GS
- * thread output URB entry."
- *
- * TODO
- */
- info.gs_entry_size = attr_size *
- ilo_shader_get_kernel_param(vec->gs, ILO_KERNEL_OUTPUT_COUNT);
- }
-
- if (vec->fs) {
- info.ps_const_data = (bool)
- ilo_shader_get_kernel_param(vec->fs, ILO_KERNEL_PCB_CBUF0_SIZE);
- }
-
- ilo_state_urb_set_info(&vec->urb, dev, &info);
-}
-
-static void
-finalize_viewport(struct ilo_context *ilo)
-{
- const struct ilo_dev *dev = ilo->dev;
- struct ilo_state_vector *vec = &ilo->state_vector;
-
- if (vec->dirty & ILO_DIRTY_VIEWPORT) {
- ilo_state_viewport_set_params(&vec->viewport.vp,
- dev, &vec->viewport.params, false);
- } else if (vec->dirty & ILO_DIRTY_SCISSOR) {
- ilo_state_viewport_set_params(&vec->viewport.vp,
- dev, &vec->viewport.params, true);
- vec->dirty |= ILO_DIRTY_VIEWPORT;
- }
-}
-
-static bool
-can_enable_gb_test(const struct ilo_rasterizer_state *rasterizer,
- const struct ilo_viewport_state *viewport,
- const struct ilo_fb_state *fb)
-{
- unsigned i;
-
- /*
- * There are several reasons that guard band test should be disabled
- *
- * - GL wide points (to avoid partially visibie object)
- * - GL wide or AA lines (to avoid partially visibie object)
- * - missing 2D clipping
- */
- if (rasterizer->state.point_size_per_vertex ||
- rasterizer->state.point_size > 1.0f ||
- rasterizer->state.line_width > 1.0f ||
- rasterizer->state.line_smooth)
- return false;
-
- for (i = 0; i < viewport->params.count; i++) {
- const struct ilo_state_viewport_matrix_info *mat =
- &viewport->matrices[i];
- float min_x, max_x, min_y, max_y;
-
- min_x = -1.0f * fabsf(mat->scale[0]) + mat->translate[0];
- max_x = 1.0f * fabsf(mat->scale[0]) + mat->translate[0];
- min_y = -1.0f * fabsf(mat->scale[1]) + mat->translate[1];
- max_y = 1.0f * fabsf(mat->scale[1]) + mat->translate[1];
-
- if (min_x > 0.0f || max_x < fb->state.width ||
- min_y > 0.0f || max_y < fb->state.height)
- return false;
- }
-
- return true;
-}
-
-static void
-finalize_rasterizer(struct ilo_context *ilo)
-{
- const struct ilo_dev *dev = ilo->dev;
- struct ilo_state_vector *vec = &ilo->state_vector;
- struct ilo_rasterizer_state *rasterizer = vec->rasterizer;
- struct ilo_state_raster_info *info = &vec->rasterizer->info;
- const bool gb_test_enable =
- can_enable_gb_test(rasterizer, &vec->viewport, &vec->fb);
- const bool multisample =
- (rasterizer->state.multisample && vec->fb.num_samples > 1);
- const uint8_t barycentric_interps = ilo_shader_get_kernel_param(vec->fs,
- ILO_KERNEL_FS_BARYCENTRIC_INTERPOLATIONS);
-
- /* check for non-orthogonal states */
- if (info->clip.viewport_count != vec->viewport.params.count ||
- info->clip.gb_test_enable != gb_test_enable ||
- info->setup.msaa_enable != multisample ||
- info->setup.line_msaa_enable != multisample ||
- info->tri.depth_offset_format != vec->fb.depth_offset_format ||
- info->scan.sample_count != vec->fb.num_samples ||
- info->scan.sample_mask != vec->sample_mask ||
- info->scan.barycentric_interps != barycentric_interps ||
- info->params.any_integer_rt != vec->fb.has_integer_rt ||
- info->params.hiz_enable != vec->fb.has_hiz) {
- info->clip.viewport_count = vec->viewport.params.count;
- info->clip.gb_test_enable = gb_test_enable;
- info->setup.msaa_enable = multisample;
- info->setup.line_msaa_enable = multisample;
- info->tri.depth_offset_format = vec->fb.depth_offset_format;
- info->scan.sample_count = vec->fb.num_samples;
- info->scan.sample_mask = vec->sample_mask;
- info->scan.barycentric_interps = barycentric_interps;
- info->params.any_integer_rt = vec->fb.has_integer_rt;
- info->params.hiz_enable = vec->fb.has_hiz;
-
- ilo_state_raster_set_info(&rasterizer->rs, dev, &rasterizer->info);
-
- vec->dirty |= ILO_DIRTY_RASTERIZER;
- }
-}
-
-static bool
-finalize_blend_rt(struct ilo_context *ilo)
-{
- struct ilo_state_vector *vec = &ilo->state_vector;
- const struct ilo_fb_state *fb = &vec->fb;
- struct ilo_blend_state *blend = vec->blend;
- struct ilo_state_cc_blend_info *info = &vec->blend->info.blend;
- bool changed = false;
- unsigned i;
-
- if (!(vec->dirty & (ILO_DIRTY_FB | ILO_DIRTY_BLEND)))
- return false;
-
- /* set up one for dummy RT writes */
- if (!fb->state.nr_cbufs) {
- if (info->rt != &blend->dummy_rt) {
- info->rt = &blend->dummy_rt;
- info->rt_count = 1;
- changed = true;
- }
-
- return changed;
- }
-
- if (info->rt != blend->effective_rt ||
- info->rt_count != fb->state.nr_cbufs) {
- info->rt = blend->effective_rt;
- info->rt_count = fb->state.nr_cbufs;
- changed = true;
- }
-
- for (i = 0; i < fb->state.nr_cbufs; i++) {
- const struct ilo_fb_blend_caps *caps = &fb->blend_caps[i];
- struct ilo_state_cc_blend_rt_info *rt = &blend->effective_rt[i];
- /* ignore logicop when not UNORM */
- const bool logicop_enable =
- (blend->rt[i].logicop_enable && caps->is_unorm);
-
- if (rt->cv_is_unorm != caps->is_unorm ||
- rt->cv_is_integer != caps->is_integer ||
- rt->logicop_enable != logicop_enable ||
- rt->force_dst_alpha_one != caps->force_dst_alpha_one) {
- rt->cv_is_unorm = caps->is_unorm;
- rt->cv_is_integer = caps->is_integer;
- rt->logicop_enable = logicop_enable;
- rt->force_dst_alpha_one = caps->force_dst_alpha_one;
-
- changed = true;
- }
- }
-
- return changed;
-}
-
-static void
-finalize_blend(struct ilo_context *ilo)
-{
- const struct ilo_dev *dev = ilo->dev;
- struct ilo_state_vector *vec = &ilo->state_vector;
- struct ilo_blend_state *blend = vec->blend;
- struct ilo_state_cc_info *info = &blend->info;
- const bool sample_count_one = (vec->fb.num_samples <= 1);
- const bool float_source0_alpha =
- (!vec->fb.state.nr_cbufs || !vec->fb.state.cbufs[0] ||
- !util_format_is_pure_integer(vec->fb.state.cbufs[0]->format));
-
- /* check for non-orthogonal states */
- if (finalize_blend_rt(ilo) ||
- info->alpha.cv_sample_count_one != sample_count_one ||
- info->alpha.cv_float_source0_alpha != float_source0_alpha ||
- info->alpha.test_enable != vec->dsa->alpha_test ||
- info->alpha.test_func != vec->dsa->alpha_func ||
- memcmp(&info->stencil, &vec->dsa->stencil, sizeof(info->stencil)) ||
- memcmp(&info->depth, &vec->dsa->depth, sizeof(info->depth)) ||
- memcmp(&info->params, &vec->cc_params, sizeof(info->params))) {
- info->alpha.cv_sample_count_one = sample_count_one;
- info->alpha.cv_float_source0_alpha = float_source0_alpha;
- info->alpha.test_enable = vec->dsa->alpha_test;
- info->alpha.test_func = vec->dsa->alpha_func;
- info->stencil = vec->dsa->stencil;
- info->depth = vec->dsa->depth;
- info->params = vec->cc_params;
-
- ilo_state_cc_set_info(&blend->cc, dev, info);
-
- blend->alpha_may_kill = (info->alpha.alpha_to_coverage ||
- info->alpha.test_enable);
-
- vec->dirty |= ILO_DIRTY_BLEND;
- }
-}
-
-/**
- * Finalize states. Some states depend on other states and are
- * incomplete/invalid until finalized.
- */
-void
-ilo_finalize_3d_states(struct ilo_context *ilo,
- const struct pipe_draw_info *draw)
-{
- ilo->state_vector.draw = draw;
-
- ilo->state_vector.draw_info.topology = ilo_translate_draw_mode(draw->mode);
- ilo->state_vector.draw_info.indexed = draw->indexed;
- ilo->state_vector.draw_info.vertex_count = draw->count;
- ilo->state_vector.draw_info.vertex_start = draw->start;
- ilo->state_vector.draw_info.instance_count = draw->instance_count;
- ilo->state_vector.draw_info.instance_start = draw->start_instance;
- ilo->state_vector.draw_info.vertex_base = draw->index_bias;
-
- finalize_blend(ilo);
- finalize_shader_states(&ilo->state_vector);
- finalize_constant_buffers(ilo);
- finalize_index_buffer(ilo);
- finalize_vertex_elements(ilo);
- finalize_vertex_buffers(ilo);
-
- finalize_urb(ilo);
- finalize_rasterizer(ilo);
- finalize_viewport(ilo);
-
- u_upload_unmap(ilo->uploader);
-}
-
-static void
-finalize_global_binding(struct ilo_state_vector *vec)
-{
- struct ilo_shader_state *cs = vec->cs;
- int base, count, shift;
- int i;
-
- count = ilo_shader_get_kernel_param(cs,
- ILO_KERNEL_CS_SURFACE_GLOBAL_COUNT);
- if (!count)
- return;
-
- base = ilo_shader_get_kernel_param(cs, ILO_KERNEL_CS_SURFACE_GLOBAL_BASE);
- shift = 32 - util_last_bit(base + count - 1);
-
- if (count > vec->global_binding.count)
- count = vec->global_binding.count;
-
- for (i = 0; i < count; i++) {
- struct ilo_global_binding_cso *cso =
- util_dynarray_element(&vec->global_binding.bindings,
- struct ilo_global_binding_cso, i);
- const uint32_t offset = *cso->handle & ((1 << shift) - 1);
-
- *cso->handle = ((base + i) << shift) | offset;
- }
-}
-
-void
-ilo_finalize_compute_states(struct ilo_context *ilo)
-{
- finalize_global_binding(&ilo->state_vector);
-}
-
-static void *
-ilo_create_blend_state(struct pipe_context *pipe,
- const struct pipe_blend_state *state)
-{
- const struct ilo_dev *dev = ilo_context(pipe)->dev;
- struct ilo_state_cc_info *info;
- struct ilo_blend_state *blend;
- int i;
-
- blend = CALLOC_STRUCT(ilo_blend_state);
- assert(blend);
-
- info = &blend->info;
-
- info->alpha.cv_float_source0_alpha = true;
- info->alpha.cv_sample_count_one = true;
- info->alpha.alpha_to_one = state->alpha_to_one;
- info->alpha.alpha_to_coverage = state->alpha_to_coverage;
- info->alpha.test_enable = false;
- info->alpha.test_func = GEN6_COMPAREFUNCTION_ALWAYS;
-
- info->stencil.cv_has_buffer = true;
- info->depth.cv_has_buffer= true;
-
- info->blend.rt = blend->effective_rt;
- info->blend.rt_count = 1;
- info->blend.dither_enable = state->dither;
-
- for (i = 0; i < ARRAY_SIZE(blend->rt); i++) {
- const struct pipe_rt_blend_state *rt = &state->rt[i];
- struct ilo_state_cc_blend_rt_info *rt_info = &blend->rt[i];
-
- rt_info->cv_has_buffer = true;
- rt_info->cv_is_unorm = true;
- rt_info->cv_is_integer = false;
-
- /* logic op takes precedence over blending */
- if (state->logicop_enable) {
- rt_info->logicop_enable = true;
- rt_info->logicop_func = ilo_translate_logicop(state->logicop_func);
- } else if (rt->blend_enable) {
- rt_info->blend_enable = true;
-
- rt_info->rgb_src = ilo_translate_blend_factor(rt->rgb_src_factor);
- rt_info->rgb_dst = ilo_translate_blend_factor(rt->rgb_dst_factor);
- rt_info->rgb_func = ilo_translate_blend_func(rt->rgb_func);
-
- rt_info->a_src = ilo_translate_blend_factor(rt->alpha_src_factor);
- rt_info->a_dst = ilo_translate_blend_factor(rt->alpha_dst_factor);
- rt_info->a_func = ilo_translate_blend_func(rt->alpha_func);
- }
-
- if (!(rt->colormask & PIPE_MASK_A))
- rt_info->argb_write_disables |= (1 << 3);
- if (!(rt->colormask & PIPE_MASK_R))
- rt_info->argb_write_disables |= (1 << 2);
- if (!(rt->colormask & PIPE_MASK_G))
- rt_info->argb_write_disables |= (1 << 1);
- if (!(rt->colormask & PIPE_MASK_B))
- rt_info->argb_write_disables |= (1 << 0);
-
- if (!state->independent_blend_enable) {
- for (i = 1; i < ARRAY_SIZE(blend->rt); i++)
- blend->rt[i] = *rt_info;
- break;
- }
- }
-
- memcpy(blend->effective_rt, blend->rt, sizeof(blend->rt));
-
- blend->dummy_rt.argb_write_disables = 0xf;
-
- if (!ilo_state_cc_init(&blend->cc, dev, &blend->info)) {
- FREE(blend);
- return NULL;
- }
-
- blend->dual_blend = util_blend_state_is_dual(state, 0);
-
- return blend;
-}
-
-static void
-ilo_bind_blend_state(struct pipe_context *pipe, void *state)
-{
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
-
- vec->blend = state;
-
- vec->dirty |= ILO_DIRTY_BLEND;
-}
-
-static void
-ilo_delete_blend_state(struct pipe_context *pipe, void *state)
-{
- FREE(state);
-}
-
-static void *
-ilo_create_sampler_state(struct pipe_context *pipe,
- const struct pipe_sampler_state *state)
-{
- const struct ilo_dev *dev = ilo_context(pipe)->dev;
- struct ilo_sampler_cso *sampler;
- struct ilo_state_sampler_info info;
- struct ilo_state_sampler_border_info border;
-
- sampler = CALLOC_STRUCT(ilo_sampler_cso);
- assert(sampler);
-
- memset(&info, 0, sizeof(info));
-
- info.non_normalized = !state->normalized_coords;
- if (state->normalized_coords) {
- info.lod_bias = state->lod_bias;
- info.min_lod = state->min_lod;
- info.max_lod = state->max_lod;
-
- info.mip_filter = ilo_translate_mip_filter(state->min_mip_filter);
- } else {
- /* work around a bug in util_blitter */
- info.mip_filter = GEN6_MIPFILTER_NONE;
- }
-
- if (state->max_anisotropy) {
- info.min_filter = GEN6_MAPFILTER_ANISOTROPIC;
- info.mag_filter = GEN6_MAPFILTER_ANISOTROPIC;
- } else {
- info.min_filter = ilo_translate_img_filter(state->min_img_filter);
- info.mag_filter = ilo_translate_img_filter(state->mag_img_filter);
- }
-
- info.max_anisotropy = ilo_translate_max_anisotropy(state->max_anisotropy);
-
- /* use LOD 0 when no mipmapping (see sampler_set_gen6_SAMPLER_STATE()) */
- if (info.mip_filter == GEN6_MIPFILTER_NONE && info.min_lod > 0.0f) {
- info.min_lod = 0.0f;
- info.mag_filter = info.min_filter;
- }
-
- if (state->seamless_cube_map) {
- if (state->min_img_filter == PIPE_TEX_FILTER_NEAREST ||
- state->mag_img_filter == PIPE_TEX_FILTER_NEAREST) {
- info.tcx_ctrl = GEN6_TEXCOORDMODE_CLAMP;
- info.tcy_ctrl = GEN6_TEXCOORDMODE_CLAMP;
- info.tcz_ctrl = GEN6_TEXCOORDMODE_CLAMP;
- } else {
- info.tcx_ctrl = GEN6_TEXCOORDMODE_CUBE;
- info.tcy_ctrl = GEN6_TEXCOORDMODE_CUBE;
- info.tcz_ctrl = GEN6_TEXCOORDMODE_CUBE;
- }
- } else {
- info.tcx_ctrl = ilo_translate_address_wrap(state->wrap_s);
- info.tcy_ctrl = ilo_translate_address_wrap(state->wrap_t);
- info.tcz_ctrl = ilo_translate_address_wrap(state->wrap_r);
-
- if (ilo_dev_gen(dev) < ILO_GEN(8)) {
- /*
- * For nearest filtering, PIPE_TEX_WRAP_CLAMP means
- * PIPE_TEX_WRAP_CLAMP_TO_EDGE; for linear filtering,
- * PIPE_TEX_WRAP_CLAMP means PIPE_TEX_WRAP_CLAMP_TO_BORDER while
- * additionally clamping the texture coordinates to [0.0, 1.0].
- *
- * PIPE_TEX_WRAP_CLAMP is not supported natively until Gen8. The
- * clamping has to be taken care of in the shaders. There are two
- * filters here, but let the minification one has a say.
- */
- const bool clamp_is_to_edge =
- (state->min_img_filter == PIPE_TEX_FILTER_NEAREST);
-
- if (clamp_is_to_edge) {
- if (info.tcx_ctrl == GEN8_TEXCOORDMODE_HALF_BORDER)
- info.tcx_ctrl = GEN6_TEXCOORDMODE_CLAMP;
- if (info.tcy_ctrl == GEN8_TEXCOORDMODE_HALF_BORDER)
- info.tcy_ctrl = GEN6_TEXCOORDMODE_CLAMP;
- if (info.tcz_ctrl == GEN8_TEXCOORDMODE_HALF_BORDER)
- info.tcz_ctrl = GEN6_TEXCOORDMODE_CLAMP;
- } else {
- if (info.tcx_ctrl == GEN8_TEXCOORDMODE_HALF_BORDER) {
- info.tcx_ctrl = GEN6_TEXCOORDMODE_CLAMP_BORDER;
- sampler->saturate_s = true;
- }
- if (info.tcy_ctrl == GEN8_TEXCOORDMODE_HALF_BORDER) {
- info.tcy_ctrl = GEN6_TEXCOORDMODE_CLAMP_BORDER;
- sampler->saturate_t = true;
- }
- if (info.tcz_ctrl == GEN8_TEXCOORDMODE_HALF_BORDER) {
- info.tcz_ctrl = GEN6_TEXCOORDMODE_CLAMP_BORDER;
- sampler->saturate_r = true;
- }
- }
- }
- }
-
- if (state->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE)
- info.shadow_func = ilo_translate_shadow_func(state->compare_func);
-
- ilo_state_sampler_init(&sampler->sampler, dev, &info);
-
- memset(&border, 0, sizeof(border));
- memcpy(border.rgba.f, state->border_color.f, sizeof(border.rgba.f));
-
- ilo_state_sampler_border_init(&sampler->border, dev, &border);
-
- return sampler;
-}
-
-static void
-ilo_bind_sampler_states(struct pipe_context *pipe,
- enum pipe_shader_type shader,
- unsigned start, unsigned count, void **samplers)
-{
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
- struct ilo_sampler_state *dst = &vec->sampler[shader];
- bool changed = false;
- unsigned i;
-
- assert(start + count <= ARRAY_SIZE(dst->cso));
-
- if (samplers) {
- for (i = 0; i < count; i++) {
- if (dst->cso[start + i] != samplers[i]) {
- dst->cso[start + i] = samplers[i];
-
- /*
- * This function is sometimes called to reduce the number of bound
- * samplers. Do not consider that as a state change (and create a
- * new array of SAMPLER_STATE).
- */
- if (samplers[i])
- changed = true;
- }
- }
- }
- else {
- for (i = 0; i < count; i++)
- dst->cso[start + i] = NULL;
- }
-
- if (changed) {
- switch (shader) {
- case PIPE_SHADER_VERTEX:
- vec->dirty |= ILO_DIRTY_SAMPLER_VS;
- break;
- case PIPE_SHADER_GEOMETRY:
- vec->dirty |= ILO_DIRTY_SAMPLER_GS;
- break;
- case PIPE_SHADER_FRAGMENT:
- vec->dirty |= ILO_DIRTY_SAMPLER_FS;
- break;
- case PIPE_SHADER_COMPUTE:
- vec->dirty |= ILO_DIRTY_SAMPLER_CS;
- break;
- }
- }
-}
-
-static void
-ilo_delete_sampler_state(struct pipe_context *pipe, void *state)
-{
- FREE(state);
-}
-
-static void *
-ilo_create_rasterizer_state(struct pipe_context *pipe,
- const struct pipe_rasterizer_state *state)
-{
- const struct ilo_dev *dev = ilo_context(pipe)->dev;
- struct ilo_rasterizer_state *rast;
- struct ilo_state_raster_info *info;
-
- rast = CALLOC_STRUCT(ilo_rasterizer_state);
- assert(rast);
-
- rast->state = *state;
-
- info = &rast->info;
-
- info->clip.clip_enable = true;
- info->clip.stats_enable = true;
- info->clip.viewport_count = 1;
- info->clip.force_rtaindex_zero = true;
- info->clip.user_clip_enables = state->clip_plane_enable;
- info->clip.gb_test_enable = true;
- info->clip.xy_test_enable = true;
- info->clip.z_far_enable = state->depth_clip;
- info->clip.z_near_enable = state->depth_clip;
- info->clip.z_near_zero = state->clip_halfz;
-
- info->setup.first_vertex_provoking = state->flatshade_first;
- info->setup.viewport_transform = true;
- info->setup.scissor_enable = state->scissor;
- info->setup.msaa_enable = false;
- info->setup.line_msaa_enable = false;
- info->point.aa_enable = state->point_smooth;
- info->point.programmable_width = state->point_size_per_vertex;
- info->line.aa_enable = state->line_smooth;
- info->line.stipple_enable = state->line_stipple_enable;
- info->line.giq_enable = true;
- info->line.giq_last_pixel = state->line_last_pixel;
- info->tri.front_winding = ilo_translate_front_ccw(state->front_ccw);
- info->tri.cull_mode = ilo_translate_cull_face(state->cull_face);
- info->tri.fill_mode_front = ilo_translate_poly_mode(state->fill_front);
- info->tri.fill_mode_back = ilo_translate_poly_mode(state->fill_back);
- info->tri.depth_offset_format = GEN6_ZFORMAT_D24_UNORM_X8_UINT;
- info->tri.depth_offset_solid = state->offset_tri;
- info->tri.depth_offset_wireframe = state->offset_line;
- info->tri.depth_offset_point = state->offset_point;
- info->tri.poly_stipple_enable = state->poly_stipple_enable;
-
- info->scan.stats_enable = true;
- info->scan.sample_count = 1;
- info->scan.pixloc =
- ilo_translate_half_pixel_center(state->half_pixel_center);
- info->scan.sample_mask = ~0u;
- info->scan.zw_interp = GEN6_ZW_INTERP_PIXEL;
- info->scan.barycentric_interps = GEN6_INTERP_PERSPECTIVE_PIXEL;
- info->scan.earlyz_control = GEN7_EDSC_NORMAL;
- info->scan.earlyz_op = ILO_STATE_RASTER_EARLYZ_NORMAL;
- info->scan.earlyz_stencil_clear = false;
-
- info->params.any_integer_rt = false;
- info->params.hiz_enable = true;
- info->params.point_width =
- (state->point_size == 0.0f) ? 1.0f : state->point_size;
- info->params.line_width =
- (state->line_width == 0.0f) ? 1.0f : state->line_width;
-
- info->params.depth_offset_scale = state->offset_scale;
- /*
- * Scale the constant term. The minimum representable value used by the HW
- * is not large enouch to be the minimum resolvable difference.
- */
- info->params.depth_offset_const = state->offset_units * 2.0f;
- info->params.depth_offset_clamp = state->offset_clamp;
-
- ilo_state_raster_init(&rast->rs, dev, info);
-
- return rast;
-}
-
-static void
-ilo_bind_rasterizer_state(struct pipe_context *pipe, void *state)
-{
- const struct ilo_dev *dev = ilo_context(pipe)->dev;
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
-
- vec->rasterizer = state;
-
- if (vec->rasterizer) {
- struct ilo_state_line_stipple_info info;
-
- info.pattern = vec->rasterizer->state.line_stipple_pattern;
- info.repeat_count = vec->rasterizer->state.line_stipple_factor + 1;
-
- ilo_state_line_stipple_set_info(&vec->line_stipple, dev, &info);
- }
-
- vec->dirty |= ILO_DIRTY_RASTERIZER;
-}
-
-static void
-ilo_delete_rasterizer_state(struct pipe_context *pipe, void *state)
-{
- FREE(state);
-}
-
-static void *
-ilo_create_depth_stencil_alpha_state(struct pipe_context *pipe,
- const struct pipe_depth_stencil_alpha_state *state)
-{
- struct ilo_dsa_state *dsa;
- int i;
-
- dsa = CALLOC_STRUCT(ilo_dsa_state);
- assert(dsa);
-
- dsa->depth.cv_has_buffer = true;
- dsa->depth.test_enable = state->depth.enabled;
- dsa->depth.write_enable = state->depth.writemask;
- dsa->depth.test_func = ilo_translate_compare_func(state->depth.func);
-
- dsa->stencil.cv_has_buffer = true;
- for (i = 0; i < ARRAY_SIZE(state->stencil); i++) {
- const struct pipe_stencil_state *stencil = &state->stencil[i];
- struct ilo_state_cc_stencil_op_info *op;
-
- if (!stencil->enabled)
- break;
-
- if (i == 0) {
- dsa->stencil.test_enable = true;
- dsa->stencil_front.test_mask = stencil->valuemask;
- dsa->stencil_front.write_mask = stencil->writemask;
-
- op = &dsa->stencil.front;
- } else {
- dsa->stencil.twosided_enable = true;
- dsa->stencil_back.test_mask = stencil->valuemask;
- dsa->stencil_back.write_mask = stencil->writemask;
-
- op = &dsa->stencil.back;
- }
-
- op->test_func = ilo_translate_compare_func(stencil->func);
- op->fail_op = ilo_translate_stencil_op(stencil->fail_op);
- op->zfail_op = ilo_translate_stencil_op(stencil->zfail_op);
- op->zpass_op = ilo_translate_stencil_op(stencil->zpass_op);
- }
-
- dsa->alpha_test = state->alpha.enabled;
- dsa->alpha_ref = state->alpha.ref_value;
- dsa->alpha_func = ilo_translate_compare_func(state->alpha.func);
-
- return dsa;
-}
-
-static void
-ilo_bind_depth_stencil_alpha_state(struct pipe_context *pipe, void *state)
-{
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
-
- vec->dsa = state;
- if (vec->dsa) {
- vec->cc_params.alpha_ref = vec->dsa->alpha_ref;
- vec->cc_params.stencil_front.test_mask =
- vec->dsa->stencil_front.test_mask;
- vec->cc_params.stencil_front.write_mask =
- vec->dsa->stencil_front.write_mask;
- vec->cc_params.stencil_back.test_mask =
- vec->dsa->stencil_back.test_mask;
- vec->cc_params.stencil_back.write_mask =
- vec->dsa->stencil_back.write_mask;
- }
-
- vec->dirty |= ILO_DIRTY_DSA;
-}
-
-static void
-ilo_delete_depth_stencil_alpha_state(struct pipe_context *pipe, void *state)
-{
- FREE(state);
-}
-
-static void *
-ilo_create_fs_state(struct pipe_context *pipe,
- const struct pipe_shader_state *state)
-{
- struct ilo_context *ilo = ilo_context(pipe);
- struct ilo_shader_state *shader;
-
- shader = ilo_shader_create_fs(ilo->dev, state, &ilo->state_vector);
- assert(shader);
-
- ilo_shader_cache_add(ilo->shader_cache, shader);
-
- return shader;
-}
-
-static void
-ilo_bind_fs_state(struct pipe_context *pipe, void *state)
-{
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
-
- vec->fs = state;
-
- vec->dirty |= ILO_DIRTY_FS;
-}
-
-static void
-ilo_delete_fs_state(struct pipe_context *pipe, void *state)
-{
- struct ilo_context *ilo = ilo_context(pipe);
- struct ilo_shader_state *fs = (struct ilo_shader_state *) state;
-
- ilo_shader_cache_remove(ilo->shader_cache, fs);
- ilo_shader_destroy(fs);
-}
-
-static void *
-ilo_create_vs_state(struct pipe_context *pipe,
- const struct pipe_shader_state *state)
-{
- struct ilo_context *ilo = ilo_context(pipe);
- struct ilo_shader_state *shader;
-
- shader = ilo_shader_create_vs(ilo->dev, state, &ilo->state_vector);
- assert(shader);
-
- ilo_shader_cache_add(ilo->shader_cache, shader);
-
- return shader;
-}
-
-static void
-ilo_bind_vs_state(struct pipe_context *pipe, void *state)
-{
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
-
- vec->vs = state;
-
- vec->dirty |= ILO_DIRTY_VS;
-}
-
-static void
-ilo_delete_vs_state(struct pipe_context *pipe, void *state)
-{
- struct ilo_context *ilo = ilo_context(pipe);
- struct ilo_shader_state *vs = (struct ilo_shader_state *) state;
-
- ilo_shader_cache_remove(ilo->shader_cache, vs);
- ilo_shader_destroy(vs);
-}
-
-static void *
-ilo_create_gs_state(struct pipe_context *pipe,
- const struct pipe_shader_state *state)
-{
- struct ilo_context *ilo = ilo_context(pipe);
- struct ilo_shader_state *shader;
-
- shader = ilo_shader_create_gs(ilo->dev, state, &ilo->state_vector);
- assert(shader);
-
- ilo_shader_cache_add(ilo->shader_cache, shader);
-
- return shader;
-}
-
-static void
-ilo_bind_gs_state(struct pipe_context *pipe, void *state)
-{
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
-
- /* util_blitter may set this unnecessarily */
- if (vec->gs == state)
- return;
-
- vec->gs = state;
-
- vec->dirty |= ILO_DIRTY_GS;
-}
-
-static void
-ilo_delete_gs_state(struct pipe_context *pipe, void *state)
-{
- struct ilo_context *ilo = ilo_context(pipe);
- struct ilo_shader_state *gs = (struct ilo_shader_state *) state;
-
- ilo_shader_cache_remove(ilo->shader_cache, gs);
- ilo_shader_destroy(gs);
-}
-
-static void *
-ilo_create_vertex_elements_state(struct pipe_context *pipe,
- unsigned num_elements,
- const struct pipe_vertex_element *elements)
-{
- const struct ilo_dev *dev = ilo_context(pipe)->dev;
- struct ilo_state_vf_element_info vf_elements[PIPE_MAX_ATTRIBS];
- unsigned instance_divisors[PIPE_MAX_ATTRIBS];
- struct ilo_state_vf_info vf_info;
- struct ilo_ve_state *ve;
- unsigned i;
-
- ve = CALLOC_STRUCT(ilo_ve_state);
- assert(ve);
-
- for (i = 0; i < num_elements; i++) {
- const struct pipe_vertex_element *elem = &elements[i];
- struct ilo_state_vf_element_info *attr = &vf_elements[i];
- unsigned hw_idx;
-
- /*
- * map the pipe vb to the hardware vb, which has a fixed instance
- * divisor
- */
- for (hw_idx = 0; hw_idx < ve->vb_count; hw_idx++) {
- if (ve->vb_mapping[hw_idx] == elem->vertex_buffer_index &&
- instance_divisors[hw_idx] == elem->instance_divisor)
- break;
- }
-
- /* create one if there is no matching hardware vb */
- if (hw_idx >= ve->vb_count) {
- hw_idx = ve->vb_count++;
-
- ve->vb_mapping[hw_idx] = elem->vertex_buffer_index;
- instance_divisors[hw_idx] = elem->instance_divisor;
- }
-
- attr->buffer = hw_idx;
- attr->vertex_offset = elem->src_offset;
- attr->format = ilo_format_translate_vertex(dev, elem->src_format);
- attr->format_size = util_format_get_blocksize(elem->src_format);
- attr->component_count = util_format_get_nr_components(elem->src_format);
- attr->is_integer = util_format_is_pure_integer(elem->src_format);
-
- attr->instancing_enable = (elem->instance_divisor != 0);
- attr->instancing_step_rate = elem->instance_divisor;
- }
-
- memset(&vf_info, 0, sizeof(vf_info));
- vf_info.data = ve->vf_data;
- vf_info.data_size = sizeof(ve->vf_data);
- vf_info.elements = vf_elements;
- vf_info.element_count = num_elements;
- /* vf_info.params and ve->vf_params are both zeroed */
-
- if (!ilo_state_vf_init(&ve->vf, dev, &vf_info)) {
- FREE(ve);
- return NULL;
- }
-
- return ve;
-}
-
-static void
-ilo_bind_vertex_elements_state(struct pipe_context *pipe, void *state)
-{
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
-
- vec->ve = state;
-
- vec->dirty |= ILO_DIRTY_VE;
-}
-
-static void
-ilo_delete_vertex_elements_state(struct pipe_context *pipe, void *state)
-{
- struct ilo_ve_state *ve = state;
-
- FREE(ve);
-}
-
-static void
-ilo_set_blend_color(struct pipe_context *pipe,
- const struct pipe_blend_color *state)
-{
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
-
- memcpy(vec->cc_params.blend_rgba, state->color, sizeof(state->color));
-
- vec->dirty |= ILO_DIRTY_BLEND_COLOR;
-}
-
-static void
-ilo_set_stencil_ref(struct pipe_context *pipe,
- const struct pipe_stencil_ref *state)
-{
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
-
- /* util_blitter may set this unnecessarily */
- if (!memcmp(&vec->stencil_ref, state, sizeof(*state)))
- return;
-
- vec->stencil_ref = *state;
-
- vec->cc_params.stencil_front.test_ref = state->ref_value[0];
- vec->cc_params.stencil_back.test_ref = state->ref_value[1];
-
- vec->dirty |= ILO_DIRTY_STENCIL_REF;
-}
-
-static void
-ilo_set_sample_mask(struct pipe_context *pipe,
- unsigned sample_mask)
-{
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
-
- /* util_blitter may set this unnecessarily */
- if (vec->sample_mask == sample_mask)
- return;
-
- vec->sample_mask = sample_mask;
-
- vec->dirty |= ILO_DIRTY_SAMPLE_MASK;
-}
-
-static void
-ilo_set_clip_state(struct pipe_context *pipe,
- const struct pipe_clip_state *state)
-{
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
-
- vec->clip = *state;
-
- vec->dirty |= ILO_DIRTY_CLIP;
-}
-
-static void
-ilo_set_constant_buffer(struct pipe_context *pipe,
- uint shader, uint index,
- const struct pipe_constant_buffer *buf)
-{
- const struct ilo_dev *dev = ilo_context(pipe)->dev;
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
- struct ilo_cbuf_state *cbuf = &vec->cbuf[shader];
- const unsigned count = 1;
- unsigned i;
-
- assert(shader < ARRAY_SIZE(vec->cbuf));
- assert(index + count <= ARRAY_SIZE(vec->cbuf[shader].cso));
-
- if (buf) {
- for (i = 0; i < count; i++) {
- struct ilo_cbuf_cso *cso = &cbuf->cso[index + i];
-
- pipe_resource_reference(&cso->resource, buf[i].buffer);
-
- cso->info.access = ILO_STATE_SURFACE_ACCESS_DP_DATA;
- cso->info.format = GEN6_FORMAT_R32G32B32A32_FLOAT;
- cso->info.format_size = 16;
- cso->info.struct_size = 16;
- cso->info.readonly = true;
- cso->info.size = buf[i].buffer_size;
-
- if (buf[i].buffer) {
- cso->info.vma = ilo_resource_get_vma(buf[i].buffer);
- cso->info.offset = buf[i].buffer_offset;
-
- memset(&cso->surface, 0, sizeof(cso->surface));
- ilo_state_surface_init_for_buffer(&cso->surface, dev, &cso->info);
-
- cso->user_buffer = NULL;
-
- cbuf->enabled_mask |= 1 << (index + i);
- } else if (buf[i].user_buffer) {
- cso->info.vma = NULL;
- /* buffer_offset does not apply for user buffer */
- cso->user_buffer = buf[i].user_buffer;
-
- cbuf->enabled_mask |= 1 << (index + i);
- } else {
- cso->info.vma = NULL;
- cso->info.size = 0;
- cso->user_buffer = NULL;
-
- cbuf->enabled_mask &= ~(1 << (index + i));
- }
- }
- } else {
- for (i = 0; i < count; i++) {
- struct ilo_cbuf_cso *cso = &cbuf->cso[index + i];
-
- pipe_resource_reference(&cso->resource, NULL);
-
- cso->info.vma = NULL;
- cso->info.size = 0;
- cso->user_buffer = NULL;
-
- cbuf->enabled_mask &= ~(1 << (index + i));
- }
- }
-
- vec->dirty |= ILO_DIRTY_CBUF;
-}
-
-static void
-fb_set_blend_caps(const struct ilo_dev *dev,
- enum pipe_format format,
- struct ilo_fb_blend_caps *caps)
-{
- const struct util_format_description *desc =
- util_format_description(format);
- const int ch = util_format_get_first_non_void_channel(format);
-
- memset(caps, 0, sizeof(*caps));
-
- if (format == PIPE_FORMAT_NONE || desc->is_mixed)
- return;
-
- caps->is_unorm = (ch >= 0 && desc->channel[ch].normalized &&
- desc->channel[ch].type == UTIL_FORMAT_TYPE_UNSIGNED &&
- desc->colorspace == UTIL_FORMAT_COLORSPACE_RGB);
- caps->is_integer = util_format_is_pure_integer(format);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 365:
- *
- * "Logic Ops are only supported on *_UNORM surfaces (excluding _SRGB
- * variants), otherwise Logic Ops must be DISABLED."
- *
- * According to the classic driver, this is lifted on Gen8+.
- */
- caps->can_logicop = (ilo_dev_gen(dev) >= ILO_GEN(8) || caps->is_unorm);
-
- /* no blending for pure integer formats */
- caps->can_blend = !caps->is_integer;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 382:
- *
- * "Alpha Test can only be enabled if Pixel Shader outputs a float
- * alpha value."
- */
- caps->can_alpha_test = !caps->is_integer;
-
- caps->force_dst_alpha_one =
- (ilo_format_translate_render(dev, format) !=
- ilo_format_translate_color(dev, format));
-
- /* sanity check */
- if (caps->force_dst_alpha_one) {
- enum pipe_format render_format;
-
- switch (format) {
- case PIPE_FORMAT_B8G8R8X8_UNORM:
- render_format = PIPE_FORMAT_B8G8R8A8_UNORM;
- break;
- default:
- render_format = PIPE_FORMAT_NONE;
- break;
- }
-
- assert(ilo_format_translate_render(dev, format) ==
- ilo_format_translate_color(dev, render_format));
- }
-}
-
-static void
-ilo_set_framebuffer_state(struct pipe_context *pipe,
- const struct pipe_framebuffer_state *state)
-{
- const struct ilo_dev *dev = ilo_context(pipe)->dev;
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
- struct ilo_fb_state *fb = &vec->fb;
- const struct pipe_surface *first_surf = NULL;
- int i;
-
- util_copy_framebuffer_state(&fb->state, state);
-
- fb->has_integer_rt = false;
- for (i = 0; i < state->nr_cbufs; i++) {
- if (state->cbufs[i]) {
- fb_set_blend_caps(dev, state->cbufs[i]->format, &fb->blend_caps[i]);
-
- fb->has_integer_rt |= fb->blend_caps[i].is_integer;
-
- if (!first_surf)
- first_surf = state->cbufs[i];
- } else {
- fb_set_blend_caps(dev, PIPE_FORMAT_NONE, &fb->blend_caps[i]);
- }
- }
-
- if (!first_surf && state->zsbuf)
- first_surf = state->zsbuf;
-
- fb->num_samples = (first_surf) ? first_surf->texture->nr_samples : 1;
- if (!fb->num_samples)
- fb->num_samples = 1;
-
- if (state->zsbuf) {
- const struct ilo_surface_cso *cso =
- (const struct ilo_surface_cso *) state->zsbuf;
- const struct ilo_texture *tex = ilo_texture(cso->base.texture);
-
- fb->has_hiz = cso->u.zs.hiz_vma;
- fb->depth_offset_format =
- ilo_format_translate_depth(dev, tex->image_format);
- } else {
- fb->has_hiz = false;
- fb->depth_offset_format = GEN6_ZFORMAT_D32_FLOAT;
- }
-
- /*
- * The PRMs list several restrictions when the framebuffer has more than
- * one surface. It seems they are actually lifted on GEN6+.
- */
-
- vec->dirty |= ILO_DIRTY_FB;
-}
-
-static void
-ilo_set_polygon_stipple(struct pipe_context *pipe,
- const struct pipe_poly_stipple *state)
-{
- const struct ilo_dev *dev = ilo_context(pipe)->dev;
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
- struct ilo_state_poly_stipple_info info;
- int i;
-
- for (i = 0; i < 32; i++)
- info.pattern[i] = state->stipple[i];
-
- ilo_state_poly_stipple_set_info(&vec->poly_stipple, dev, &info);
-
- vec->dirty |= ILO_DIRTY_POLY_STIPPLE;
-}
-
-static void
-ilo_set_scissor_states(struct pipe_context *pipe,
- unsigned start_slot,
- unsigned num_scissors,
- const struct pipe_scissor_state *scissors)
-{
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
- unsigned i;
-
- for (i = 0; i < num_scissors; i++) {
- struct ilo_state_viewport_scissor_info *info =
- &vec->viewport.scissors[start_slot + i];
-
- if (scissors[i].minx < scissors[i].maxx &&
- scissors[i].miny < scissors[i].maxy) {
- info->min_x = scissors[i].minx;
- info->min_y = scissors[i].miny;
- info->max_x = scissors[i].maxx - 1;
- info->max_y = scissors[i].maxy - 1;
- } else {
- info->min_x = 1;
- info->min_y = 1;
- info->max_x = 0;
- info->max_y = 0;
- }
- }
-
- vec->dirty |= ILO_DIRTY_SCISSOR;
-}
-
-static void
-ilo_set_viewport_states(struct pipe_context *pipe,
- unsigned start_slot,
- unsigned num_viewports,
- const struct pipe_viewport_state *viewports)
-{
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
-
- if (viewports) {
- unsigned i;
-
- for (i = 0; i < num_viewports; i++) {
- struct ilo_state_viewport_matrix_info *info =
- &vec->viewport.matrices[start_slot + i];
-
- memcpy(info->scale, viewports[i].scale, sizeof(info->scale));
- memcpy(info->translate, viewports[i].translate,
- sizeof(info->translate));
- }
-
- if (vec->viewport.params.count < start_slot + num_viewports)
- vec->viewport.params.count = start_slot + num_viewports;
-
- /* need to save viewport 0 for util_blitter */
- if (!start_slot && num_viewports)
- vec->viewport.viewport0 = viewports[0];
- }
- else {
- if (vec->viewport.params.count <= start_slot + num_viewports &&
- vec->viewport.params.count > start_slot)
- vec->viewport.params.count = start_slot;
- }
-
- vec->dirty |= ILO_DIRTY_VIEWPORT;
-}
-
-static void
-ilo_set_sampler_views(struct pipe_context *pipe, enum pipe_shader_type shader,
- unsigned start, unsigned count,
- struct pipe_sampler_view **views)
-{
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
- struct ilo_view_state *dst = &vec->view[shader];
- unsigned i;
-
- assert(start + count <= ARRAY_SIZE(dst->states));
-
- if (views) {
- for (i = 0; i < count; i++)
- pipe_sampler_view_reference(&dst->states[start + i], views[i]);
- }
- else {
- for (i = 0; i < count; i++)
- pipe_sampler_view_reference(&dst->states[start + i], NULL);
- }
-
- if (dst->count <= start + count) {
- if (views)
- count += start;
- else
- count = start;
-
- while (count > 0 && !dst->states[count - 1])
- count--;
-
- dst->count = count;
- }
-
- switch (shader) {
- case PIPE_SHADER_VERTEX:
- vec->dirty |= ILO_DIRTY_VIEW_VS;
- break;
- case PIPE_SHADER_GEOMETRY:
- vec->dirty |= ILO_DIRTY_VIEW_GS;
- break;
- case PIPE_SHADER_FRAGMENT:
- vec->dirty |= ILO_DIRTY_VIEW_FS;
- break;
- case PIPE_SHADER_COMPUTE:
- vec->dirty |= ILO_DIRTY_VIEW_CS;
- break;
- default:
- assert(!"unexpected shader type");
- break;
- }
-}
-
-static void
-ilo_set_shader_images(struct pipe_context *pipe, enum pipe_shader_type shader,
- unsigned start, unsigned count,
- const struct pipe_image_view *views)
-{
-#if 0
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
- struct ilo_resource_state *dst = &vec->resource;
- unsigned i;
-
- assert(start + count <= ARRAY_SIZE(dst->states));
-
- if (surfaces) {
- for (i = 0; i < count; i++)
- pipe_surface_reference(&dst->states[start + i], surfaces[i]);
- }
- else {
- for (i = 0; i < count; i++)
- pipe_surface_reference(&dst->states[start + i], NULL);
- }
-
- if (dst->count <= start + count) {
- if (surfaces)
- count += start;
- else
- count = start;
-
- while (count > 0 && !dst->states[count - 1])
- count--;
-
- dst->count = count;
- }
-
- vec->dirty |= ILO_DIRTY_RESOURCE;
-#endif
-}
-
-static void
-ilo_set_vertex_buffers(struct pipe_context *pipe,
- unsigned start_slot, unsigned num_buffers,
- const struct pipe_vertex_buffer *buffers)
-{
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
- unsigned i;
-
- /* no PIPE_CAP_USER_VERTEX_BUFFERS */
- if (buffers) {
- for (i = 0; i < num_buffers; i++)
- assert(!buffers[i].user_buffer);
- }
-
- util_set_vertex_buffers_mask(vec->vb.states,
- &vec->vb.enabled_mask, buffers, start_slot, num_buffers);
-
- vec->dirty |= ILO_DIRTY_VB;
-}
-
-static void
-ilo_set_index_buffer(struct pipe_context *pipe,
- const struct pipe_index_buffer *state)
-{
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
-
- if (state) {
- pipe_resource_reference(&vec->ib.state.buffer, state->buffer);
- vec->ib.state = *state;
- } else {
- pipe_resource_reference(&vec->ib.state.buffer, NULL);
- memset(&vec->ib.state, 0, sizeof(vec->ib.state));
- }
-
- vec->dirty |= ILO_DIRTY_IB;
-}
-
-static struct pipe_stream_output_target *
-ilo_create_stream_output_target(struct pipe_context *pipe,
- struct pipe_resource *res,
- unsigned buffer_offset,
- unsigned buffer_size)
-{
- const struct ilo_dev *dev = ilo_context(pipe)->dev;
- struct ilo_stream_output_target *target;
- struct ilo_state_sol_buffer_info info;
-
- target = CALLOC_STRUCT(ilo_stream_output_target);
- assert(target);
-
- pipe_reference_init(&target->base.reference, 1);
- pipe_resource_reference(&target->base.buffer, res);
- target->base.context = pipe;
- target->base.buffer_offset = buffer_offset;
- target->base.buffer_size = buffer_size;
-
- memset(&info, 0, sizeof(info));
- info.vma = ilo_resource_get_vma(res);
- info.offset = buffer_offset;
- info.size = buffer_size;
-
- ilo_state_sol_buffer_init(&target->sb, dev, &info);
-
- return &target->base;
-}
-
-static void
-ilo_set_stream_output_targets(struct pipe_context *pipe,
- unsigned num_targets,
- struct pipe_stream_output_target **targets,
- const unsigned *offset)
-{
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
- unsigned i;
- unsigned append_bitmask = 0;
-
- if (!targets)
- num_targets = 0;
-
- /* util_blitter may set this unnecessarily */
- if (!vec->so.count && !num_targets)
- return;
-
- for (i = 0; i < num_targets; i++) {
- pipe_so_target_reference(&vec->so.states[i], targets[i]);
- if (offset[i] == (unsigned)-1)
- append_bitmask |= 1 << i;
- }
-
- for (; i < vec->so.count; i++)
- pipe_so_target_reference(&vec->so.states[i], NULL);
-
- vec->so.count = num_targets;
- vec->so.append_bitmask = append_bitmask;
-
- vec->so.enabled = (vec->so.count > 0);
-
- vec->dirty |= ILO_DIRTY_SO;
-}
-
-static void
-ilo_stream_output_target_destroy(struct pipe_context *pipe,
- struct pipe_stream_output_target *target)
-{
- pipe_resource_reference(&target->buffer, NULL);
- FREE(target);
-}
-
-static struct pipe_sampler_view *
-ilo_create_sampler_view(struct pipe_context *pipe,
- struct pipe_resource *res,
- const struct pipe_sampler_view *templ)
-{
- const struct ilo_dev *dev = ilo_context(pipe)->dev;
- struct ilo_view_cso *view;
-
- view = CALLOC_STRUCT(ilo_view_cso);
- assert(view);
-
- view->base = *templ;
- pipe_reference_init(&view->base.reference, 1);
- view->base.texture = NULL;
- pipe_resource_reference(&view->base.texture, res);
- view->base.context = pipe;
-
- if (res->target == PIPE_BUFFER) {
- struct ilo_state_surface_buffer_info info;
-
- memset(&info, 0, sizeof(info));
- info.vma = ilo_resource_get_vma(res);
- info.offset = templ->u.buf.offset;
- info.size = templ->u.buf.size;
- info.access = ILO_STATE_SURFACE_ACCESS_SAMPLER;
- info.format = ilo_format_translate_color(dev, templ->format);
- info.format_size = util_format_get_blocksize(templ->format);
- info.struct_size = info.format_size;
- info.readonly = true;
-
- ilo_state_surface_init_for_buffer(&view->surface, dev, &info);
- } else {
- struct ilo_texture *tex = ilo_texture(res);
- struct ilo_state_surface_image_info info;
-
- /* warn about degraded performance because of a missing binding flag */
- if (tex->image.tiling == GEN6_TILING_NONE &&
- !(tex->base.bind & PIPE_BIND_SAMPLER_VIEW)) {
- ilo_warn("creating sampler view for a resource "
- "not created for sampling\n");
- }
-
- memset(&info, 0, sizeof(info));
-
- info.img = &tex->image;
- info.level_base = templ->u.tex.first_level;
- info.level_count = templ->u.tex.last_level -
- templ->u.tex.first_level + 1;
- info.slice_base = templ->u.tex.first_layer;
- info.slice_count = templ->u.tex.last_layer -
- templ->u.tex.first_layer + 1;
-
- info.vma = &tex->vma;
- info.access = ILO_STATE_SURFACE_ACCESS_SAMPLER;
- info.type = tex->image.type;
-
- if (templ->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT &&
- tex->separate_s8) {
- info.format = ilo_format_translate_texture(dev,
- PIPE_FORMAT_Z32_FLOAT);
- } else {
- info.format = ilo_format_translate_texture(dev, templ->format);
- }
-
- info.is_array = util_resource_is_array_texture(&tex->base);
- info.readonly = true;
-
- ilo_state_surface_init_for_image(&view->surface, dev, &info);
- }
-
- return &view->base;
-}
-
-static void
-ilo_sampler_view_destroy(struct pipe_context *pipe,
- struct pipe_sampler_view *view)
-{
- pipe_resource_reference(&view->texture, NULL);
- FREE(view);
-}
-
-static struct pipe_surface *
-ilo_create_surface(struct pipe_context *pipe,
- struct pipe_resource *res,
- const struct pipe_surface *templ)
-{
- const struct ilo_dev *dev = ilo_context(pipe)->dev;
- struct ilo_texture *tex = ilo_texture(res);
- struct ilo_surface_cso *surf;
-
- surf = CALLOC_STRUCT(ilo_surface_cso);
- assert(surf);
-
- surf->base = *templ;
- pipe_reference_init(&surf->base.reference, 1);
- surf->base.texture = NULL;
- pipe_resource_reference(&surf->base.texture, &tex->base);
-
- surf->base.context = pipe;
- surf->base.width = u_minify(tex->base.width0, templ->u.tex.level);
- surf->base.height = u_minify(tex->base.height0, templ->u.tex.level);
-
- surf->is_rt = !util_format_is_depth_or_stencil(templ->format);
-
- if (surf->is_rt) {
- struct ilo_state_surface_image_info info;
-
- /* relax this? */
- assert(tex->base.target != PIPE_BUFFER);
-
- memset(&info, 0, sizeof(info));
-
- info.img = &tex->image;
- info.level_base = templ->u.tex.level;
- info.level_count = 1;
- info.slice_base = templ->u.tex.first_layer;
- info.slice_count = templ->u.tex.last_layer -
- templ->u.tex.first_layer + 1;
-
- info.vma = &tex->vma;
- if (ilo_image_can_enable_aux(&tex->image, templ->u.tex.level))
- info.aux_vma = &tex->aux_vma;
-
- info.access = ILO_STATE_SURFACE_ACCESS_DP_RENDER;
-
- info.type = (tex->image.type == GEN6_SURFTYPE_CUBE) ?
- GEN6_SURFTYPE_2D : tex->image.type;
-
- info.format = ilo_format_translate_render(dev, templ->format);
- info.is_array = util_resource_is_array_texture(&tex->base);
-
- ilo_state_surface_init_for_image(&surf->u.rt, dev, &info);
- } else {
- struct ilo_state_zs_info info;
-
- assert(res->target != PIPE_BUFFER);
-
- memset(&info, 0, sizeof(info));
-
- if (templ->format == PIPE_FORMAT_S8_UINT) {
- info.s_vma = &tex->vma;
- info.s_img = &tex->image;
- } else {
- info.z_vma = &tex->vma;
- info.z_img = &tex->image;
-
- if (tex->separate_s8) {
- info.s_vma = &tex->separate_s8->vma;
- info.s_img = &tex->separate_s8->image;
- }
-
- if (ilo_image_can_enable_aux(&tex->image, templ->u.tex.level))
- info.hiz_vma = &tex->aux_vma;
- }
-
- info.level = templ->u.tex.level;
- info.slice_base = templ->u.tex.first_layer;
- info.slice_count = templ->u.tex.last_layer -
- templ->u.tex.first_layer + 1;
-
- info.type = (tex->image.type == GEN6_SURFTYPE_CUBE) ?
- GEN6_SURFTYPE_2D : tex->image.type;
-
- info.format = ilo_format_translate_depth(dev, tex->image_format);
- if (ilo_dev_gen(dev) == ILO_GEN(6) && !info.hiz_vma &&
- tex->image_format == PIPE_FORMAT_Z24X8_UNORM)
- info.format = GEN6_ZFORMAT_D24_UNORM_S8_UINT;
-
- ilo_state_zs_init(&surf->u.zs, dev, &info);
- }
-
- return &surf->base;
-}
-
-static void
-ilo_surface_destroy(struct pipe_context *pipe,
- struct pipe_surface *surface)
-{
- pipe_resource_reference(&surface->texture, NULL);
- FREE(surface);
-}
-
-static void *
-ilo_create_compute_state(struct pipe_context *pipe,
- const struct pipe_compute_state *state)
-{
- struct ilo_context *ilo = ilo_context(pipe);
- struct ilo_shader_state *shader;
-
- shader = ilo_shader_create_cs(ilo->dev, state, &ilo->state_vector);
- assert(shader);
-
- ilo_shader_cache_add(ilo->shader_cache, shader);
-
- return shader;
-}
-
-static void
-ilo_bind_compute_state(struct pipe_context *pipe, void *state)
-{
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
-
- vec->cs = state;
-
- vec->dirty |= ILO_DIRTY_CS;
-}
-
-static void
-ilo_delete_compute_state(struct pipe_context *pipe, void *state)
-{
- struct ilo_context *ilo = ilo_context(pipe);
- struct ilo_shader_state *cs = (struct ilo_shader_state *) state;
-
- ilo_shader_cache_remove(ilo->shader_cache, cs);
- ilo_shader_destroy(cs);
-}
-
-static void
-ilo_set_compute_resources(struct pipe_context *pipe,
- unsigned start, unsigned count,
- struct pipe_surface **surfaces)
-{
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
- struct ilo_resource_state *dst = &vec->cs_resource;
- unsigned i;
-
- assert(start + count <= ARRAY_SIZE(dst->states));
-
- if (surfaces) {
- for (i = 0; i < count; i++)
- pipe_surface_reference(&dst->states[start + i], surfaces[i]);
- }
- else {
- for (i = 0; i < count; i++)
- pipe_surface_reference(&dst->states[start + i], NULL);
- }
-
- if (dst->count <= start + count) {
- if (surfaces)
- count += start;
- else
- count = start;
-
- while (count > 0 && !dst->states[count - 1])
- count--;
-
- dst->count = count;
- }
-
- vec->dirty |= ILO_DIRTY_CS_RESOURCE;
-}
-
-static void
-ilo_set_global_binding(struct pipe_context *pipe,
- unsigned start, unsigned count,
- struct pipe_resource **resources,
- uint32_t **handles)
-{
- struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector;
- struct ilo_global_binding_cso *dst;
- unsigned i;
-
- /* make room */
- if (vec->global_binding.count < start + count) {
- if (resources) {
- const unsigned old_size = vec->global_binding.bindings.size;
- const unsigned new_size = sizeof(*dst) * (start + count);
-
- if (old_size < new_size) {
- util_dynarray_resize(&vec->global_binding.bindings, new_size);
- memset(vec->global_binding.bindings.data + old_size, 0,
- new_size - old_size);
- }
- } else {
- count = vec->global_binding.count - start;
- }
- }
-
- dst = util_dynarray_element(&vec->global_binding.bindings,
- struct ilo_global_binding_cso, start);
-
- if (resources) {
- for (i = 0; i < count; i++) {
- pipe_resource_reference(&dst[i].resource, resources[i]);
- dst[i].handle = handles[i];
- }
- } else {
- for (i = 0; i < count; i++) {
- pipe_resource_reference(&dst[i].resource, NULL);
- dst[i].handle = NULL;
- }
- }
-
- if (vec->global_binding.count <= start + count) {
- dst = util_dynarray_begin(&vec->global_binding.bindings);
-
- if (resources)
- count += start;
- else
- count = start;
-
- while (count > 0 && !dst[count - 1].resource)
- count--;
-
- vec->global_binding.count = count;
- }
-
- vec->dirty |= ILO_DIRTY_GLOBAL_BINDING;
-}
-
-/**
- * Initialize state-related functions.
- */
-void
-ilo_init_state_functions(struct ilo_context *ilo)
-{
- STATIC_ASSERT(ILO_STATE_COUNT <= 32);
-
- ilo->base.create_blend_state = ilo_create_blend_state;
- ilo->base.bind_blend_state = ilo_bind_blend_state;
- ilo->base.delete_blend_state = ilo_delete_blend_state;
- ilo->base.create_sampler_state = ilo_create_sampler_state;
- ilo->base.bind_sampler_states = ilo_bind_sampler_states;
- ilo->base.delete_sampler_state = ilo_delete_sampler_state;
- ilo->base.create_rasterizer_state = ilo_create_rasterizer_state;
- ilo->base.bind_rasterizer_state = ilo_bind_rasterizer_state;
- ilo->base.delete_rasterizer_state = ilo_delete_rasterizer_state;
- ilo->base.create_depth_stencil_alpha_state = ilo_create_depth_stencil_alpha_state;
- ilo->base.bind_depth_stencil_alpha_state = ilo_bind_depth_stencil_alpha_state;
- ilo->base.delete_depth_stencil_alpha_state = ilo_delete_depth_stencil_alpha_state;
- ilo->base.create_fs_state = ilo_create_fs_state;
- ilo->base.bind_fs_state = ilo_bind_fs_state;
- ilo->base.delete_fs_state = ilo_delete_fs_state;
- ilo->base.create_vs_state = ilo_create_vs_state;
- ilo->base.bind_vs_state = ilo_bind_vs_state;
- ilo->base.delete_vs_state = ilo_delete_vs_state;
- ilo->base.create_gs_state = ilo_create_gs_state;
- ilo->base.bind_gs_state = ilo_bind_gs_state;
- ilo->base.delete_gs_state = ilo_delete_gs_state;
- ilo->base.create_vertex_elements_state = ilo_create_vertex_elements_state;
- ilo->base.bind_vertex_elements_state = ilo_bind_vertex_elements_state;
- ilo->base.delete_vertex_elements_state = ilo_delete_vertex_elements_state;
-
- ilo->base.set_blend_color = ilo_set_blend_color;
- ilo->base.set_stencil_ref = ilo_set_stencil_ref;
- ilo->base.set_sample_mask = ilo_set_sample_mask;
- ilo->base.set_clip_state = ilo_set_clip_state;
- ilo->base.set_constant_buffer = ilo_set_constant_buffer;
- ilo->base.set_framebuffer_state = ilo_set_framebuffer_state;
- ilo->base.set_polygon_stipple = ilo_set_polygon_stipple;
- ilo->base.set_scissor_states = ilo_set_scissor_states;
- ilo->base.set_viewport_states = ilo_set_viewport_states;
- ilo->base.set_sampler_views = ilo_set_sampler_views;
- ilo->base.set_shader_images = ilo_set_shader_images;
- ilo->base.set_vertex_buffers = ilo_set_vertex_buffers;
- ilo->base.set_index_buffer = ilo_set_index_buffer;
-
- ilo->base.create_stream_output_target = ilo_create_stream_output_target;
- ilo->base.stream_output_target_destroy = ilo_stream_output_target_destroy;
- ilo->base.set_stream_output_targets = ilo_set_stream_output_targets;
-
- ilo->base.create_sampler_view = ilo_create_sampler_view;
- ilo->base.sampler_view_destroy = ilo_sampler_view_destroy;
-
- ilo->base.create_surface = ilo_create_surface;
- ilo->base.surface_destroy = ilo_surface_destroy;
-
- ilo->base.create_compute_state = ilo_create_compute_state;
- ilo->base.bind_compute_state = ilo_bind_compute_state;
- ilo->base.delete_compute_state = ilo_delete_compute_state;
- ilo->base.set_compute_resources = ilo_set_compute_resources;
- ilo->base.set_global_binding = ilo_set_global_binding;
-}
-
-void
-ilo_state_vector_init(const struct ilo_dev *dev,
- struct ilo_state_vector *vec)
-{
- struct ilo_state_urb_info urb_info;
-
- vec->sample_mask = ~0u;
-
- ilo_state_viewport_init_data_only(&vec->viewport.vp, dev,
- vec->viewport.vp_data, sizeof(vec->viewport.vp_data));
- assert(vec->viewport.vp.array_size >= ILO_MAX_VIEWPORTS);
-
- vec->viewport.params.matrices = vec->viewport.matrices;
- vec->viewport.params.scissors = vec->viewport.scissors;
-
- ilo_state_hs_init_disabled(&vec->disabled_hs, dev);
- ilo_state_ds_init_disabled(&vec->disabled_ds, dev);
- ilo_state_gs_init_disabled(&vec->disabled_gs, dev);
-
- ilo_state_sol_buffer_init_disabled(&vec->so.dummy_sb, dev);
-
- ilo_state_surface_init_for_null(&vec->fb.null_rt, dev);
- ilo_state_zs_init_for_null(&vec->fb.null_zs, dev);
-
- ilo_state_sampler_init_disabled(&vec->disabled_sampler, dev);
-
- memset(&urb_info, 0, sizeof(urb_info));
- ilo_state_urb_init(&vec->urb, dev, &urb_info);
-
- util_dynarray_init(&vec->global_binding.bindings);
-
- vec->dirty = ILO_DIRTY_ALL;
-}
-
-void
-ilo_state_vector_cleanup(struct ilo_state_vector *vec)
-{
- unsigned i, sh;
-
- for (i = 0; i < ARRAY_SIZE(vec->vb.states); i++) {
- if (vec->vb.enabled_mask & (1 << i))
- pipe_resource_reference(&vec->vb.states[i].buffer, NULL);
- }
-
- pipe_resource_reference(&vec->ib.state.buffer, NULL);
- pipe_resource_reference(&vec->ib.hw_resource, NULL);
-
- for (i = 0; i < vec->so.count; i++)
- pipe_so_target_reference(&vec->so.states[i], NULL);
-
- for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
- for (i = 0; i < vec->view[sh].count; i++) {
- struct pipe_sampler_view *view = vec->view[sh].states[i];
- pipe_sampler_view_reference(&view, NULL);
- }
-
- for (i = 0; i < ARRAY_SIZE(vec->cbuf[sh].cso); i++) {
- struct ilo_cbuf_cso *cbuf = &vec->cbuf[sh].cso[i];
- pipe_resource_reference(&cbuf->resource, NULL);
- }
- }
-
- for (i = 0; i < vec->resource.count; i++)
- pipe_surface_reference(&vec->resource.states[i], NULL);
-
- for (i = 0; i < vec->fb.state.nr_cbufs; i++)
- pipe_surface_reference(&vec->fb.state.cbufs[i], NULL);
-
- if (vec->fb.state.zsbuf)
- pipe_surface_reference(&vec->fb.state.zsbuf, NULL);
-
- for (i = 0; i < vec->cs_resource.count; i++)
- pipe_surface_reference(&vec->cs_resource.states[i], NULL);
-
- for (i = 0; i < vec->global_binding.count; i++) {
- struct ilo_global_binding_cso *cso =
- util_dynarray_element(&vec->global_binding.bindings,
- struct ilo_global_binding_cso, i);
- pipe_resource_reference(&cso->resource, NULL);
- }
-
- util_dynarray_fini(&vec->global_binding.bindings);
-}
-
-/**
- * Mark all states that have the resource dirty.
- */
-void
-ilo_state_vector_resource_renamed(struct ilo_state_vector *vec,
- struct pipe_resource *res)
-{
- uint32_t states = 0;
- unsigned sh, i;
-
- if (res->target == PIPE_BUFFER) {
- uint32_t vb_mask = vec->vb.enabled_mask;
-
- while (vb_mask) {
- const unsigned idx = u_bit_scan(&vb_mask);
-
- if (vec->vb.states[idx].buffer == res) {
- states |= ILO_DIRTY_VB;
- break;
- }
- }
-
- if (vec->ib.state.buffer == res) {
- states |= ILO_DIRTY_IB;
-
- /*
- * finalize_index_buffer() has an optimization that clears
- * ILO_DIRTY_IB when the HW states do not change. However, it fails
- * to flush the VF cache when the HW states do not change, but the
- * contents of the IB has changed. Here, we set the index size to an
- * invalid value to avoid the optimization.
- */
- vec->ib.hw_index_size = 0;
- }
-
- for (i = 0; i < vec->so.count; i++) {
- if (vec->so.states[i]->buffer == res) {
- states |= ILO_DIRTY_SO;
- break;
- }
- }
- }
-
- for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
- for (i = 0; i < vec->view[sh].count; i++) {
- struct ilo_view_cso *cso = (struct ilo_view_cso *) vec->view[sh].states[i];
-
- if (cso->base.texture == res) {
- static const unsigned view_dirty_bits[PIPE_SHADER_TYPES] = {
- [PIPE_SHADER_VERTEX] = ILO_DIRTY_VIEW_VS,
- [PIPE_SHADER_FRAGMENT] = ILO_DIRTY_VIEW_FS,
- [PIPE_SHADER_GEOMETRY] = ILO_DIRTY_VIEW_GS,
- [PIPE_SHADER_COMPUTE] = ILO_DIRTY_VIEW_CS,
- };
-
- states |= view_dirty_bits[sh];
- break;
- }
- }
-
- if (res->target == PIPE_BUFFER) {
- for (i = 0; i < ARRAY_SIZE(vec->cbuf[sh].cso); i++) {
- struct ilo_cbuf_cso *cbuf = &vec->cbuf[sh].cso[i];
-
- if (cbuf->resource == res) {
- states |= ILO_DIRTY_CBUF;
- break;
- }
- }
- }
- }
-
- for (i = 0; i < vec->resource.count; i++) {
- struct ilo_surface_cso *cso =
- (struct ilo_surface_cso *) vec->resource.states[i];
-
- if (cso->base.texture == res) {
- states |= ILO_DIRTY_RESOURCE;
- break;
- }
- }
-
- /* for now? */
- if (res->target != PIPE_BUFFER) {
- for (i = 0; i < vec->fb.state.nr_cbufs; i++) {
- struct ilo_surface_cso *cso =
- (struct ilo_surface_cso *) vec->fb.state.cbufs[i];
- if (cso && cso->base.texture == res) {
- states |= ILO_DIRTY_FB;
- break;
- }
- }
-
- if (vec->fb.state.zsbuf && vec->fb.state.zsbuf->texture == res)
- states |= ILO_DIRTY_FB;
- }
-
- for (i = 0; i < vec->cs_resource.count; i++) {
- struct ilo_surface_cso *cso =
- (struct ilo_surface_cso *) vec->cs_resource.states[i];
- if (cso->base.texture == res) {
- states |= ILO_DIRTY_CS_RESOURCE;
- break;
- }
- }
-
- for (i = 0; i < vec->global_binding.count; i++) {
- struct ilo_global_binding_cso *cso =
- util_dynarray_element(&vec->global_binding.bindings,
- struct ilo_global_binding_cso, i);
-
- if (cso->resource == res) {
- states |= ILO_DIRTY_GLOBAL_BINDING;
- break;
- }
- }
-
- vec->dirty |= states;
-}
-
-void
-ilo_state_vector_dump_dirty(const struct ilo_state_vector *vec)
-{
- static const char *state_names[ILO_STATE_COUNT] = {
- [ILO_STATE_VB] = "VB",
- [ILO_STATE_VE] = "VE",
- [ILO_STATE_IB] = "IB",
- [ILO_STATE_VS] = "VS",
- [ILO_STATE_GS] = "GS",
- [ILO_STATE_SO] = "SO",
- [ILO_STATE_CLIP] = "CLIP",
- [ILO_STATE_VIEWPORT] = "VIEWPORT",
- [ILO_STATE_SCISSOR] = "SCISSOR",
- [ILO_STATE_RASTERIZER] = "RASTERIZER",
- [ILO_STATE_POLY_STIPPLE] = "POLY_STIPPLE",
- [ILO_STATE_SAMPLE_MASK] = "SAMPLE_MASK",
- [ILO_STATE_FS] = "FS",
- [ILO_STATE_DSA] = "DSA",
- [ILO_STATE_STENCIL_REF] = "STENCIL_REF",
- [ILO_STATE_BLEND] = "BLEND",
- [ILO_STATE_BLEND_COLOR] = "BLEND_COLOR",
- [ILO_STATE_FB] = "FB",
- [ILO_STATE_SAMPLER_VS] = "SAMPLER_VS",
- [ILO_STATE_SAMPLER_GS] = "SAMPLER_GS",
- [ILO_STATE_SAMPLER_FS] = "SAMPLER_FS",
- [ILO_STATE_SAMPLER_CS] = "SAMPLER_CS",
- [ILO_STATE_VIEW_VS] = "VIEW_VS",
- [ILO_STATE_VIEW_GS] = "VIEW_GS",
- [ILO_STATE_VIEW_FS] = "VIEW_FS",
- [ILO_STATE_VIEW_CS] = "VIEW_CS",
- [ILO_STATE_CBUF] = "CBUF",
- [ILO_STATE_RESOURCE] = "RESOURCE",
- [ILO_STATE_CS] = "CS",
- [ILO_STATE_CS_RESOURCE] = "CS_RESOURCE",
- [ILO_STATE_GLOBAL_BINDING] = "GLOBAL_BINDING",
- };
- uint32_t dirty = vec->dirty;
-
- if (!dirty) {
- ilo_printf("no state is dirty\n");
- return;
- }
-
- dirty &= (1U << ILO_STATE_COUNT) - 1;
-
- ilo_printf("%2d states are dirty:", util_bitcount(dirty));
- while (dirty) {
- const enum ilo_state state = u_bit_scan(&dirty);
- ilo_printf(" %s", state_names[state]);
- }
- ilo_printf("\n");
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_STATE_H
-#define ILO_STATE_H
-
-#include "core/ilo_builder_3d.h" /* for gen6_3dprimitive_info */
-#include "core/ilo_state_cc.h"
-#include "core/ilo_state_compute.h"
-#include "core/ilo_state_raster.h"
-#include "core/ilo_state_sampler.h"
-#include "core/ilo_state_sbe.h"
-#include "core/ilo_state_shader.h"
-#include "core/ilo_state_sol.h"
-#include "core/ilo_state_surface.h"
-#include "core/ilo_state_urb.h"
-#include "core/ilo_state_vf.h"
-#include "core/ilo_state_viewport.h"
-#include "core/ilo_state_zs.h"
-#include "pipe/p_state.h"
-#include "util/u_dynarray.h"
-
-#include "ilo_common.h"
-
-/**
- * \see brw_context.h
- */
-#define ILO_MAX_DRAW_BUFFERS 8
-#define ILO_MAX_CONST_BUFFERS (1 + 12)
-#define ILO_MAX_SAMPLER_VIEWS 16
-#define ILO_MAX_SAMPLERS 16
-#define ILO_MAX_SO_BINDINGS 64
-#define ILO_MAX_SO_BUFFERS 4
-#define ILO_MAX_VIEWPORTS 1
-
-#define ILO_MAX_SURFACES 256
-
-/**
- * States that we track.
- *
- * XXX Do we want to count each sampler or vertex buffer as a state? If that
- * is the case, there are simply not enough bits.
- *
- * XXX We want to treat primitive type and depth clear value as states, but
- * there are not enough bits.
- */
-enum ilo_state {
- ILO_STATE_VB,
- ILO_STATE_VE,
- ILO_STATE_IB,
- ILO_STATE_VS,
- ILO_STATE_GS,
- ILO_STATE_SO,
- ILO_STATE_CLIP,
- ILO_STATE_VIEWPORT,
- ILO_STATE_SCISSOR,
- ILO_STATE_RASTERIZER,
- ILO_STATE_POLY_STIPPLE,
- ILO_STATE_SAMPLE_MASK,
- ILO_STATE_FS,
- ILO_STATE_DSA,
- ILO_STATE_STENCIL_REF,
- ILO_STATE_BLEND,
- ILO_STATE_BLEND_COLOR,
- ILO_STATE_FB,
-
- ILO_STATE_SAMPLER_VS,
- ILO_STATE_SAMPLER_GS,
- ILO_STATE_SAMPLER_FS,
- ILO_STATE_SAMPLER_CS,
- ILO_STATE_VIEW_VS,
- ILO_STATE_VIEW_GS,
- ILO_STATE_VIEW_FS,
- ILO_STATE_VIEW_CS,
- ILO_STATE_CBUF,
- ILO_STATE_RESOURCE,
-
- ILO_STATE_CS,
- ILO_STATE_CS_RESOURCE,
- ILO_STATE_GLOBAL_BINDING,
-
- ILO_STATE_COUNT,
-};
-
-/**
- * Dirty flags of the states.
- */
-enum ilo_dirty_flags {
- ILO_DIRTY_VB = 1 << ILO_STATE_VB,
- ILO_DIRTY_VE = 1 << ILO_STATE_VE,
- ILO_DIRTY_IB = 1 << ILO_STATE_IB,
- ILO_DIRTY_VS = 1 << ILO_STATE_VS,
- ILO_DIRTY_GS = 1 << ILO_STATE_GS,
- ILO_DIRTY_SO = 1 << ILO_STATE_SO,
- ILO_DIRTY_CLIP = 1 << ILO_STATE_CLIP,
- ILO_DIRTY_VIEWPORT = 1 << ILO_STATE_VIEWPORT,
- ILO_DIRTY_SCISSOR = 1 << ILO_STATE_SCISSOR,
- ILO_DIRTY_RASTERIZER = 1 << ILO_STATE_RASTERIZER,
- ILO_DIRTY_POLY_STIPPLE = 1 << ILO_STATE_POLY_STIPPLE,
- ILO_DIRTY_SAMPLE_MASK = 1 << ILO_STATE_SAMPLE_MASK,
- ILO_DIRTY_FS = 1 << ILO_STATE_FS,
- ILO_DIRTY_DSA = 1 << ILO_STATE_DSA,
- ILO_DIRTY_STENCIL_REF = 1 << ILO_STATE_STENCIL_REF,
- ILO_DIRTY_BLEND = 1 << ILO_STATE_BLEND,
- ILO_DIRTY_BLEND_COLOR = 1 << ILO_STATE_BLEND_COLOR,
- ILO_DIRTY_FB = 1 << ILO_STATE_FB,
- ILO_DIRTY_SAMPLER_VS = 1 << ILO_STATE_SAMPLER_VS,
- ILO_DIRTY_SAMPLER_GS = 1 << ILO_STATE_SAMPLER_GS,
- ILO_DIRTY_SAMPLER_FS = 1 << ILO_STATE_SAMPLER_FS,
- ILO_DIRTY_SAMPLER_CS = 1 << ILO_STATE_SAMPLER_CS,
- ILO_DIRTY_VIEW_VS = 1 << ILO_STATE_VIEW_VS,
- ILO_DIRTY_VIEW_GS = 1 << ILO_STATE_VIEW_GS,
- ILO_DIRTY_VIEW_FS = 1 << ILO_STATE_VIEW_FS,
- ILO_DIRTY_VIEW_CS = 1 << ILO_STATE_VIEW_CS,
- ILO_DIRTY_CBUF = 1 << ILO_STATE_CBUF,
- ILO_DIRTY_RESOURCE = 1 << ILO_STATE_RESOURCE,
- ILO_DIRTY_CS = 1 << ILO_STATE_CS,
- ILO_DIRTY_CS_RESOURCE = 1 << ILO_STATE_CS_RESOURCE,
- ILO_DIRTY_GLOBAL_BINDING = 1 << ILO_STATE_GLOBAL_BINDING,
- ILO_DIRTY_ALL = 0xffffffff,
-};
-
-struct ilo_context;
-struct ilo_shader_state;
-
-struct ilo_ve_state {
- unsigned vb_mapping[PIPE_MAX_ATTRIBS];
- unsigned vb_count;
-
- /* these are not valid until the state is finalized */
- uint32_t vf_data[PIPE_MAX_ATTRIBS][4];
- struct ilo_state_vf_params_info vf_params;
- struct ilo_state_vf vf;
-};
-
-struct ilo_vb_state {
- struct pipe_vertex_buffer states[PIPE_MAX_ATTRIBS];
- struct ilo_state_vertex_buffer vb[PIPE_MAX_ATTRIBS];
- uint32_t enabled_mask;
-};
-
-struct ilo_ib_state {
- struct pipe_index_buffer state;
-
- /* these are not valid until the state is finalized */
- struct pipe_resource *hw_resource;
- unsigned hw_index_size;
- struct ilo_state_index_buffer ib;
-};
-
-struct ilo_cbuf_cso {
- struct pipe_resource *resource;
- struct ilo_state_surface_buffer_info info;
- struct ilo_state_surface surface;
-
- /*
- * this CSO is not so constant because user buffer needs to be uploaded in
- * finalize_constant_buffers()
- */
- const void *user_buffer;
-};
-
-struct ilo_sampler_cso {
- struct ilo_state_sampler sampler;
- struct ilo_state_sampler_border border;
- bool saturate_s;
- bool saturate_t;
- bool saturate_r;
-};
-
-struct ilo_sampler_state {
- const struct ilo_sampler_cso *cso[ILO_MAX_SAMPLERS];
-};
-
-struct ilo_cbuf_state {
- struct ilo_cbuf_cso cso[ILO_MAX_CONST_BUFFERS];
- uint32_t enabled_mask;
-};
-
-struct ilo_resource_state {
- struct pipe_surface *states[PIPE_MAX_SHADER_IMAGES];
- unsigned count;
-};
-
-struct ilo_view_cso {
- struct pipe_sampler_view base;
-
- struct ilo_state_surface surface;
-};
-
-struct ilo_view_state {
- struct pipe_sampler_view *states[ILO_MAX_SAMPLER_VIEWS];
- unsigned count;
-};
-
-struct ilo_stream_output_target {
- struct pipe_stream_output_target base;
-
- struct ilo_state_sol_buffer sb;
-};
-
-struct ilo_so_state {
- struct pipe_stream_output_target *states[ILO_MAX_SO_BUFFERS];
- unsigned count;
- unsigned append_bitmask;
-
- struct ilo_state_sol_buffer dummy_sb;
-
- bool enabled;
-};
-
-struct ilo_rasterizer_state {
- struct pipe_rasterizer_state state;
-
- /* these are invalid until finalize_rasterizer() */
- struct ilo_state_raster_info info;
- struct ilo_state_raster rs;
-};
-
-struct ilo_viewport_state {
- struct ilo_state_viewport_matrix_info matrices[ILO_MAX_VIEWPORTS];
- struct ilo_state_viewport_scissor_info scissors[ILO_MAX_VIEWPORTS];
- struct ilo_state_viewport_params_info params;
-
- struct pipe_viewport_state viewport0;
- struct pipe_scissor_state scissor0;
-
- struct ilo_state_viewport vp;
- uint32_t vp_data[20 * ILO_MAX_VIEWPORTS];
-};
-
-struct ilo_surface_cso {
- struct pipe_surface base;
-
- bool is_rt;
- union {
- struct ilo_state_surface rt;
- struct ilo_state_zs zs;
- } u;
-};
-
-struct ilo_fb_state {
- struct pipe_framebuffer_state state;
-
- struct ilo_state_surface null_rt;
- struct ilo_state_zs null_zs;
-
- struct ilo_fb_blend_caps {
- bool is_unorm;
- bool is_integer;
- bool force_dst_alpha_one;
-
- bool can_logicop;
- bool can_blend;
- bool can_alpha_test;
- } blend_caps[PIPE_MAX_COLOR_BUFS];
-
- unsigned num_samples;
-
- bool has_integer_rt;
- bool has_hiz;
- enum gen_depth_format depth_offset_format;
-};
-
-struct ilo_dsa_state {
- struct ilo_state_cc_depth_info depth;
-
- struct ilo_state_cc_stencil_info stencil;
- struct {
- uint8_t test_mask;
- uint8_t write_mask;
- } stencil_front, stencil_back;
-
- bool alpha_test;
- float alpha_ref;
- enum gen_compare_function alpha_func;
-};
-
-struct ilo_blend_state {
- struct ilo_state_cc_blend_rt_info rt[PIPE_MAX_COLOR_BUFS];
- struct ilo_state_cc_blend_rt_info dummy_rt;
- bool dual_blend;
-
- /* these are invalid until finalize_blend() */
- struct ilo_state_cc_blend_rt_info effective_rt[PIPE_MAX_COLOR_BUFS];
- struct ilo_state_cc_info info;
- struct ilo_state_cc cc;
- bool alpha_may_kill;
-};
-
-struct ilo_global_binding_cso {
- struct pipe_resource *resource;
- uint32_t *handle;
-};
-
-/*
- * In theory, we would like a "virtual" bo that serves as the global memory
- * region. The virtual bo would reserve a region in the GTT aperture, but the
- * pages of it would come from those of the global bindings.
- *
- * The virtual bo would be created in launch_grid(). The global bindings
- * would be added to the virtual bo. A SURFACE_STATE for the virtual bo would
- * be created. The handles returned by set_global_binding() would be offsets
- * into the virtual bo.
- *
- * But for now, we will create a SURFACE_STATE for each of the bindings. The
- * handle of a global binding consists of the offset and the binding table
- * index.
- */
-struct ilo_global_binding {
- struct util_dynarray bindings;
- unsigned count;
-};
-
-struct ilo_state_vector {
- const struct pipe_draw_info *draw;
- struct gen6_3dprimitive_info draw_info;
-
- uint32_t dirty;
-
- struct ilo_vb_state vb;
- struct ilo_ve_state *ve;
- struct ilo_ib_state ib;
-
- struct ilo_shader_state *vs;
- struct ilo_shader_state *gs;
-
- struct ilo_state_hs disabled_hs;
- struct ilo_state_ds disabled_ds;
- struct ilo_state_gs disabled_gs;
-
- struct ilo_so_state so;
-
- struct pipe_clip_state clip;
-
- struct ilo_viewport_state viewport;
-
- struct ilo_rasterizer_state *rasterizer;
-
- struct ilo_state_line_stipple line_stipple;
- struct ilo_state_poly_stipple poly_stipple;
- unsigned sample_mask;
-
- struct ilo_shader_state *fs;
-
- struct ilo_state_cc_params_info cc_params;
- struct pipe_stencil_ref stencil_ref;
- const struct ilo_dsa_state *dsa;
- struct ilo_blend_state *blend;
-
- struct ilo_fb_state fb;
-
- struct ilo_state_urb urb;
-
- /* shader resources */
- struct ilo_sampler_state sampler[PIPE_SHADER_TYPES];
- struct ilo_view_state view[PIPE_SHADER_TYPES];
- struct ilo_cbuf_state cbuf[PIPE_SHADER_TYPES];
- struct ilo_resource_state resource;
-
- struct ilo_state_sampler disabled_sampler;
-
- /* GPGPU */
- struct ilo_shader_state *cs;
- struct ilo_resource_state cs_resource;
- struct ilo_global_binding global_binding;
-};
-
-void
-ilo_init_state_functions(struct ilo_context *ilo);
-
-void
-ilo_finalize_3d_states(struct ilo_context *ilo,
- const struct pipe_draw_info *draw);
-
-void
-ilo_finalize_compute_states(struct ilo_context *ilo);
-
-void
-ilo_state_vector_init(const struct ilo_dev *dev,
- struct ilo_state_vector *vec);
-
-void
-ilo_state_vector_cleanup(struct ilo_state_vector *vec);
-
-void
-ilo_state_vector_resource_renamed(struct ilo_state_vector *vec,
- struct pipe_resource *res);
-
-void
-ilo_state_vector_dump_dirty(const struct ilo_state_vector *vec);
-
-#endif /* ILO_STATE_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "util/u_surface.h"
-#include "util/u_transfer.h"
-#include "util/u_format_etc.h"
-
-#include "ilo_blit.h"
-#include "ilo_blitter.h"
-#include "ilo_cp.h"
-#include "ilo_context.h"
-#include "ilo_resource.h"
-#include "ilo_state.h"
-#include "ilo_transfer.h"
-
-/*
- * For buffers that are not busy, we want to map/unmap them directly. For
- * those that are busy, we have to worry about synchronization. We could wait
- * for GPU to finish, but there are cases where we could avoid waiting.
- *
- * - When PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE is set, the contents of the
- * buffer can be discarded. We can replace the backing bo by a new one of
- * the same size (renaming).
- * - When PIPE_TRANSFER_DISCARD_RANGE is set, the contents of the mapped
- * range can be discarded. We can allocate and map a staging bo on
- * mapping, and (pipelined-)copy it over to the real bo on unmapping.
- * - When PIPE_TRANSFER_FLUSH_EXPLICIT is set, there is no reading and only
- * flushed regions need to be written. We can still allocate and map a
- * staging bo, but should copy only the flushed regions over.
- *
- * However, there are other flags to consider.
- *
- * - When PIPE_TRANSFER_UNSYNCHRONIZED is set, we do not need to worry about
- * synchronization at all on mapping.
- * - When PIPE_TRANSFER_MAP_DIRECTLY is set, no staging area is allowed.
- * - When PIPE_TRANSFER_DONTBLOCK is set, we should fail if we have to block.
- * - When PIPE_TRANSFER_PERSISTENT is set, GPU may access the buffer while it
- * is mapped. Synchronization is done by defining memory barriers,
- * explicitly via memory_barrier() or implicitly via
- * transfer_flush_region(), as well as GPU fences.
- * - When PIPE_TRANSFER_COHERENT is set, updates by either CPU or GPU should
- * be made visible to the other side immediately. Since the kernel flushes
- * GPU caches at the end of each batch buffer, CPU always sees GPU updates.
- * We could use a coherent mapping to make all persistent mappings
- * coherent.
- *
- * These also apply to textures, except that we may additionally need to do
- * format conversion or tiling/untiling.
- */
-
-/**
- * Return a transfer method suitable for the usage. The returned method will
- * correctly block when the resource is busy.
- */
-static bool
-resource_get_transfer_method(struct pipe_resource *res,
- const struct pipe_transfer *transfer,
- enum ilo_transfer_map_method *method)
-{
- const struct ilo_screen *is = ilo_screen(res->screen);
- const unsigned usage = transfer->usage;
- enum ilo_transfer_map_method m;
- bool tiled;
-
- if (res->target == PIPE_BUFFER) {
- tiled = false;
- } else {
- struct ilo_texture *tex = ilo_texture(res);
- bool need_convert = false;
-
- /* we may need to convert on the fly */
- if (tex->image.tiling == GEN8_TILING_W || tex->separate_s8) {
- /* on GEN6, separate stencil is enabled only when HiZ is */
- if (ilo_dev_gen(&is->dev) >= ILO_GEN(7) ||
- ilo_image_can_enable_aux(&tex->image, transfer->level)) {
- m = ILO_TRANSFER_MAP_SW_ZS;
- need_convert = true;
- }
- } else if (tex->image_format != tex->base.format) {
- m = ILO_TRANSFER_MAP_SW_CONVERT;
- need_convert = true;
- }
-
- if (need_convert) {
- if (usage & (PIPE_TRANSFER_MAP_DIRECTLY | PIPE_TRANSFER_PERSISTENT))
- return false;
-
- *method = m;
- return true;
- }
-
- tiled = (tex->image.tiling != GEN6_TILING_NONE);
- }
-
- if (tiled)
- m = ILO_TRANSFER_MAP_GTT; /* to have a linear view */
- else if (is->dev.has_llc)
- m = ILO_TRANSFER_MAP_CPU; /* fast and mostly coherent */
- else if (usage & PIPE_TRANSFER_PERSISTENT)
- m = ILO_TRANSFER_MAP_GTT; /* for coherency */
- else if (usage & PIPE_TRANSFER_READ)
- m = ILO_TRANSFER_MAP_CPU; /* gtt read is too slow */
- else
- m = ILO_TRANSFER_MAP_GTT;
-
- *method = m;
-
- return true;
-}
-
-/**
- * Return true if usage allows the use of staging bo to avoid blocking.
- */
-static bool
-usage_allows_staging_bo(unsigned usage)
-{
- /* do we know how to write the data back to the resource? */
- const unsigned can_writeback = (PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE |
- PIPE_TRANSFER_DISCARD_RANGE |
- PIPE_TRANSFER_FLUSH_EXPLICIT);
- const unsigned reasons_against = (PIPE_TRANSFER_READ |
- PIPE_TRANSFER_MAP_DIRECTLY |
- PIPE_TRANSFER_PERSISTENT);
-
- return (usage & can_writeback) && !(usage & reasons_against);
-}
-
-/**
- * Allocate the staging resource. It is always linear and its size matches
- * the transfer box, with proper paddings.
- */
-static bool
-xfer_alloc_staging_res(struct ilo_transfer *xfer)
-{
- const struct pipe_resource *res = xfer->base.resource;
- const struct pipe_box *box = &xfer->base.box;
- struct pipe_resource templ;
-
- memset(&templ, 0, sizeof(templ));
-
- templ.format = res->format;
-
- if (res->target == PIPE_BUFFER) {
- templ.target = PIPE_BUFFER;
- templ.width0 =
- (box->x % ILO_TRANSFER_MAP_BUFFER_ALIGNMENT) + box->width;
- }
- else {
- /* use 2D array for any texture target */
- templ.target = PIPE_TEXTURE_2D_ARRAY;
- templ.width0 = box->width;
- }
-
- templ.height0 = box->height;
- templ.depth0 = 1;
- templ.array_size = box->depth;
- templ.nr_samples = 1;
- templ.usage = PIPE_USAGE_STAGING;
-
- if (xfer->base.usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
- templ.flags = PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
- PIPE_RESOURCE_FLAG_MAP_COHERENT;
- }
-
- xfer->staging.res = res->screen->resource_create(res->screen, &templ);
-
- if (xfer->staging.res && xfer->staging.res->target != PIPE_BUFFER) {
- assert(ilo_texture(xfer->staging.res)->image.tiling ==
- GEN6_TILING_NONE);
- }
-
- return (xfer->staging.res != NULL);
-}
-
-/**
- * Use an alternative transfer method or rename the resource to unblock an
- * otherwise blocking transfer.
- */
-static bool
-xfer_unblock(struct ilo_transfer *xfer, bool *resource_renamed)
-{
- struct pipe_resource *res = xfer->base.resource;
- bool unblocked = false, renamed = false;
-
- switch (xfer->method) {
- case ILO_TRANSFER_MAP_CPU:
- case ILO_TRANSFER_MAP_GTT:
- if (xfer->base.usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
- xfer->method = ILO_TRANSFER_MAP_GTT_ASYNC;
- unblocked = true;
- }
- else if ((xfer->base.usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) &&
- ilo_resource_rename_bo(res)) {
- renamed = true;
- unblocked = true;
- }
- else if (usage_allows_staging_bo(xfer->base.usage) &&
- xfer_alloc_staging_res(xfer)) {
- xfer->method = ILO_TRANSFER_MAP_STAGING;
- unblocked = true;
- }
- break;
- case ILO_TRANSFER_MAP_GTT_ASYNC:
- case ILO_TRANSFER_MAP_STAGING:
- unblocked = true;
- break;
- default:
- break;
- }
-
- *resource_renamed = renamed;
-
- return unblocked;
-}
-
-/**
- * Allocate the staging system buffer based on the resource format and the
- * transfer box.
- */
-static bool
-xfer_alloc_staging_sys(struct ilo_transfer *xfer)
-{
- const enum pipe_format format = xfer->base.resource->format;
- const struct pipe_box *box = &xfer->base.box;
- const unsigned alignment = 64;
-
- /* need to tell the world the layout */
- xfer->base.stride =
- align(util_format_get_stride(format, box->width), alignment);
- xfer->base.layer_stride =
- util_format_get_2d_size(format, xfer->base.stride, box->height);
-
- xfer->staging.sys =
- align_malloc(xfer->base.layer_stride * box->depth, alignment);
-
- return (xfer->staging.sys != NULL);
-}
-
-/**
- * Map according to the method. The staging system buffer should have been
- * allocated if the method requires it.
- */
-static void *
-xfer_map(struct ilo_transfer *xfer)
-{
- const struct ilo_vma *vma;
- void *ptr;
-
- switch (xfer->method) {
- case ILO_TRANSFER_MAP_CPU:
- vma = ilo_resource_get_vma(xfer->base.resource);
- ptr = intel_bo_map(vma->bo, xfer->base.usage & PIPE_TRANSFER_WRITE);
- break;
- case ILO_TRANSFER_MAP_GTT:
- vma = ilo_resource_get_vma(xfer->base.resource);
- ptr = intel_bo_map_gtt(vma->bo);
- break;
- case ILO_TRANSFER_MAP_GTT_ASYNC:
- vma = ilo_resource_get_vma(xfer->base.resource);
- ptr = intel_bo_map_gtt_async(vma->bo);
- break;
- case ILO_TRANSFER_MAP_STAGING:
- {
- const struct ilo_screen *is = ilo_screen(xfer->staging.res->screen);
-
- vma = ilo_resource_get_vma(xfer->staging.res);
-
- /*
- * We want a writable, optionally persistent and coherent, mapping
- * for a linear bo. We can call resource_get_transfer_method(), but
- * this turns out to be fairly simple.
- */
- if (is->dev.has_llc)
- ptr = intel_bo_map(vma->bo, true);
- else
- ptr = intel_bo_map_gtt(vma->bo);
-
- if (ptr && xfer->staging.res->target == PIPE_BUFFER)
- ptr += (xfer->base.box.x % ILO_TRANSFER_MAP_BUFFER_ALIGNMENT);
- }
- break;
- case ILO_TRANSFER_MAP_SW_CONVERT:
- case ILO_TRANSFER_MAP_SW_ZS:
- vma = NULL;
- ptr = xfer->staging.sys;
- break;
- default:
- assert(!"unknown mapping method");
- vma = NULL;
- ptr = NULL;
- break;
- }
-
- if (ptr && vma)
- ptr = (void *) ((char *) ptr + vma->bo_offset);
-
- return ptr;
-}
-
-/**
- * Unmap a transfer.
- */
-static void
-xfer_unmap(struct ilo_transfer *xfer)
-{
- switch (xfer->method) {
- case ILO_TRANSFER_MAP_CPU:
- case ILO_TRANSFER_MAP_GTT:
- case ILO_TRANSFER_MAP_GTT_ASYNC:
- intel_bo_unmap(ilo_resource_get_vma(xfer->base.resource)->bo);
- break;
- case ILO_TRANSFER_MAP_STAGING:
- intel_bo_unmap(ilo_resource_get_vma(xfer->staging.res)->bo);
- break;
- default:
- break;
- }
-}
-
-static void
-tex_get_box_origin(const struct ilo_texture *tex,
- unsigned level, unsigned slice,
- const struct pipe_box *box,
- unsigned *mem_x, unsigned *mem_y)
-{
- unsigned x, y;
-
- ilo_image_get_slice_pos(&tex->image, level, box->z + slice, &x, &y);
- x += box->x;
- y += box->y;
-
- ilo_image_pos_to_mem(&tex->image, x, y, mem_x, mem_y);
-}
-
-static unsigned
-tex_get_box_offset(const struct ilo_texture *tex, unsigned level,
- const struct pipe_box *box)
-{
- unsigned mem_x, mem_y;
-
- tex_get_box_origin(tex, level, 0, box, &mem_x, &mem_y);
-
- return ilo_image_mem_to_linear(&tex->image, mem_x, mem_y);
-}
-
-static unsigned
-tex_get_slice_stride(const struct ilo_texture *tex, unsigned level)
-{
- return ilo_image_get_slice_stride(&tex->image, level);
-}
-
-static unsigned
-tex_tile_x_swizzle(unsigned addr)
-{
- /*
- * From the Ivy Bridge PRM, volume 1 part 2, page 24:
- *
- * "As shown in the tiling algorithm, the new address bit[6] should be:
- *
- * Address bit[6] <= TiledAddr bit[6] XOR
- * TiledAddr bit[9] XOR
- * TiledAddr bit[10]"
- */
- return addr ^ (((addr >> 3) ^ (addr >> 4)) & 0x40);
-}
-
-static unsigned
-tex_tile_y_swizzle(unsigned addr)
-{
- /*
- * From the Ivy Bridge PRM, volume 1 part 2, page 24:
- *
- * "As shown in the tiling algorithm, The new address bit[6] becomes:
- *
- * Address bit[6] <= TiledAddr bit[6] XOR
- * TiledAddr bit[9]"
- */
- return addr ^ ((addr >> 3) & 0x40);
-}
-
-static unsigned
-tex_tile_x_offset(unsigned mem_x, unsigned mem_y,
- unsigned tiles_per_row, bool swizzle)
-{
- /*
- * From the Sandy Bridge PRM, volume 1 part 2, page 21, we know that a
- * X-major tile has 8 rows and 32 OWord columns (512 bytes). Tiles in the
- * tiled region are numbered in row-major order, starting from zero. The
- * tile number can thus be calculated as follows:
- *
- * tile = (mem_y / 8) * tiles_per_row + (mem_x / 512)
- *
- * OWords in that tile are also numbered in row-major order, starting from
- * zero. The OWord number can thus be calculated as follows:
- *
- * oword = (mem_y % 8) * 32 + ((mem_x % 512) / 16)
- *
- * and the tiled offset is
- *
- * offset = tile * 4096 + oword * 16 + (mem_x % 16)
- * = tile * 4096 + (mem_y % 8) * 512 + (mem_x % 512)
- */
- unsigned tile, offset;
-
- tile = (mem_y >> 3) * tiles_per_row + (mem_x >> 9);
- offset = tile << 12 | (mem_y & 0x7) << 9 | (mem_x & 0x1ff);
-
- return (swizzle) ? tex_tile_x_swizzle(offset) : offset;
-}
-
-static unsigned
-tex_tile_y_offset(unsigned mem_x, unsigned mem_y,
- unsigned tiles_per_row, bool swizzle)
-{
- /*
- * From the Sandy Bridge PRM, volume 1 part 2, page 22, we know that a
- * Y-major tile has 32 rows and 8 OWord columns (128 bytes). Tiles in the
- * tiled region are numbered in row-major order, starting from zero. The
- * tile number can thus be calculated as follows:
- *
- * tile = (mem_y / 32) * tiles_per_row + (mem_x / 128)
- *
- * OWords in that tile are numbered in column-major order, starting from
- * zero. The OWord number can thus be calculated as follows:
- *
- * oword = ((mem_x % 128) / 16) * 32 + (mem_y % 32)
- *
- * and the tiled offset is
- *
- * offset = tile * 4096 + oword * 16 + (mem_x % 16)
- */
- unsigned tile, oword, offset;
-
- tile = (mem_y >> 5) * tiles_per_row + (mem_x >> 7);
- oword = (mem_x & 0x70) << 1 | (mem_y & 0x1f);
- offset = tile << 12 | oword << 4 | (mem_x & 0xf);
-
- return (swizzle) ? tex_tile_y_swizzle(offset) : offset;
-}
-
-static unsigned
-tex_tile_w_offset(unsigned mem_x, unsigned mem_y,
- unsigned tiles_per_row, bool swizzle)
-{
- /*
- * From the Sandy Bridge PRM, volume 1 part 2, page 23, we know that a
- * W-major tile has 8 8x8-block rows and 8 8x8-block columns. Tiles in the
- * tiled region are numbered in row-major order, starting from zero. The
- * tile number can thus be calculated as follows:
- *
- * tile = (mem_y / 64) * tiles_per_row + (mem_x / 64)
- *
- * 8x8-blocks in that tile are numbered in column-major order, starting
- * from zero. The 8x8-block number can thus be calculated as follows:
- *
- * blk8 = ((mem_x % 64) / 8) * 8 + ((mem_y % 64) / 8)
- *
- * Each 8x8-block is divided into 4 4x4-blocks, in row-major order. Each
- * 4x4-block is further divided into 4 2x2-blocks, also in row-major order.
- * We have
- *
- * blk4 = (((mem_y % 64) / 4) & 1) * 2 + (((mem_x % 64) / 4) & 1)
- * blk2 = (((mem_y % 64) / 2) & 1) * 2 + (((mem_x % 64) / 2) & 1)
- * blk1 = (((mem_y % 64) ) & 1) * 2 + (((mem_x % 64) ) & 1)
- *
- * and the tiled offset is
- *
- * offset = tile * 4096 + blk8 * 64 + blk4 * 16 + blk2 * 4 + blk1
- */
- unsigned tile, blk8, blk4, blk2, blk1, offset;
-
- tile = (mem_y >> 6) * tiles_per_row + (mem_x >> 6);
- blk8 = ((mem_x >> 3) & 0x7) << 3 | ((mem_y >> 3) & 0x7);
- blk4 = ((mem_y >> 2) & 0x1) << 1 | ((mem_x >> 2) & 0x1);
- blk2 = ((mem_y >> 1) & 0x1) << 1 | ((mem_x >> 1) & 0x1);
- blk1 = ((mem_y ) & 0x1) << 1 | ((mem_x ) & 0x1);
- offset = tile << 12 | blk8 << 6 | blk4 << 4 | blk2 << 2 | blk1;
-
- return (swizzle) ? tex_tile_y_swizzle(offset) : offset;
-}
-
-static unsigned
-tex_tile_none_offset(unsigned mem_x, unsigned mem_y,
- unsigned tiles_per_row, bool swizzle)
-{
- return mem_y * tiles_per_row + mem_x;
-}
-
-typedef unsigned (*tex_tile_offset_func)(unsigned mem_x, unsigned mem_y,
- unsigned tiles_per_row,
- bool swizzle);
-
-static tex_tile_offset_func
-tex_tile_choose_offset_func(const struct ilo_texture *tex,
- unsigned *tiles_per_row)
-{
- switch (tex->image.tiling) {
- default:
- assert(!"unknown tiling");
- /* fall through */
- case GEN6_TILING_NONE:
- *tiles_per_row = tex->image.bo_stride;
- return tex_tile_none_offset;
- case GEN6_TILING_X:
- *tiles_per_row = tex->image.bo_stride / 512;
- return tex_tile_x_offset;
- case GEN6_TILING_Y:
- *tiles_per_row = tex->image.bo_stride / 128;
- return tex_tile_y_offset;
- case GEN8_TILING_W:
- *tiles_per_row = tex->image.bo_stride / 64;
- return tex_tile_w_offset;
- }
-}
-
-static void *
-tex_staging_sys_map_bo(struct ilo_texture *tex,
- bool for_read_back,
- bool linear_view)
-{
- const struct ilo_screen *is = ilo_screen(tex->base.screen);
- const bool prefer_cpu = (is->dev.has_llc || for_read_back);
- void *ptr;
-
- if (prefer_cpu && (tex->image.tiling == GEN6_TILING_NONE ||
- !linear_view))
- ptr = intel_bo_map(tex->vma.bo, !for_read_back);
- else
- ptr = intel_bo_map_gtt(tex->vma.bo);
-
- if (ptr)
- ptr = (void *) ((char *) ptr + tex->vma.bo_offset);
-
- return ptr;
-}
-
-static void
-tex_staging_sys_unmap_bo(struct ilo_texture *tex)
-{
- intel_bo_unmap(tex->vma.bo);
-}
-
-static bool
-tex_staging_sys_zs_read(struct ilo_texture *tex,
- const struct ilo_transfer *xfer)
-{
- const struct ilo_screen *is = ilo_screen(tex->base.screen);
- const bool swizzle = is->dev.has_address_swizzling;
- const struct pipe_box *box = &xfer->base.box;
- const uint8_t *src;
- tex_tile_offset_func tile_offset;
- unsigned tiles_per_row;
- int slice;
-
- src = tex_staging_sys_map_bo(tex, true, false);
- if (!src)
- return false;
-
- tile_offset = tex_tile_choose_offset_func(tex, &tiles_per_row);
-
- assert(tex->image.block_width == 1 && tex->image.block_height == 1);
-
- if (tex->separate_s8) {
- struct ilo_texture *s8_tex = tex->separate_s8;
- const uint8_t *s8_src;
- tex_tile_offset_func s8_tile_offset;
- unsigned s8_tiles_per_row;
- int dst_cpp, dst_s8_pos, src_cpp_used;
-
- s8_src = tex_staging_sys_map_bo(s8_tex, true, false);
- if (!s8_src) {
- tex_staging_sys_unmap_bo(tex);
- return false;
- }
-
- s8_tile_offset = tex_tile_choose_offset_func(s8_tex, &s8_tiles_per_row);
-
- if (tex->base.format == PIPE_FORMAT_Z24_UNORM_S8_UINT) {
- assert(tex->image_format == PIPE_FORMAT_Z24X8_UNORM);
-
- dst_cpp = 4;
- dst_s8_pos = 3;
- src_cpp_used = 3;
- }
- else {
- assert(tex->base.format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT);
- assert(tex->image_format == PIPE_FORMAT_Z32_FLOAT);
-
- dst_cpp = 8;
- dst_s8_pos = 4;
- src_cpp_used = 4;
- }
-
- for (slice = 0; slice < box->depth; slice++) {
- unsigned mem_x, mem_y, s8_mem_x, s8_mem_y;
- uint8_t *dst;
- int i, j;
-
- tex_get_box_origin(tex, xfer->base.level, slice,
- box, &mem_x, &mem_y);
- tex_get_box_origin(s8_tex, xfer->base.level, slice,
- box, &s8_mem_x, &s8_mem_y);
-
- dst = xfer->staging.sys + xfer->base.layer_stride * slice;
-
- for (i = 0; i < box->height; i++) {
- unsigned x = mem_x, s8_x = s8_mem_x;
- uint8_t *d = dst;
-
- for (j = 0; j < box->width; j++) {
- const unsigned offset =
- tile_offset(x, mem_y, tiles_per_row, swizzle);
- const unsigned s8_offset =
- s8_tile_offset(s8_x, s8_mem_y, s8_tiles_per_row, swizzle);
-
- memcpy(d, src + offset, src_cpp_used);
- d[dst_s8_pos] = s8_src[s8_offset];
-
- d += dst_cpp;
- x += tex->image.block_size;
- s8_x++;
- }
-
- dst += xfer->base.stride;
- mem_y++;
- s8_mem_y++;
- }
- }
-
- tex_staging_sys_unmap_bo(s8_tex);
- }
- else {
- assert(tex->image_format == PIPE_FORMAT_S8_UINT);
-
- for (slice = 0; slice < box->depth; slice++) {
- unsigned mem_x, mem_y;
- uint8_t *dst;
- int i, j;
-
- tex_get_box_origin(tex, xfer->base.level, slice,
- box, &mem_x, &mem_y);
-
- dst = xfer->staging.sys + xfer->base.layer_stride * slice;
-
- for (i = 0; i < box->height; i++) {
- unsigned x = mem_x;
- uint8_t *d = dst;
-
- for (j = 0; j < box->width; j++) {
- const unsigned offset =
- tile_offset(x, mem_y, tiles_per_row, swizzle);
-
- *d = src[offset];
-
- d++;
- x++;
- }
-
- dst += xfer->base.stride;
- mem_y++;
- }
- }
- }
-
- tex_staging_sys_unmap_bo(tex);
-
- return true;
-}
-
-static bool
-tex_staging_sys_zs_write(struct ilo_texture *tex,
- const struct ilo_transfer *xfer)
-{
- const struct ilo_screen *is = ilo_screen(tex->base.screen);
- const bool swizzle = is->dev.has_address_swizzling;
- const struct pipe_box *box = &xfer->base.box;
- uint8_t *dst;
- tex_tile_offset_func tile_offset;
- unsigned tiles_per_row;
- int slice;
-
- dst = tex_staging_sys_map_bo(tex, false, false);
- if (!dst)
- return false;
-
- tile_offset = tex_tile_choose_offset_func(tex, &tiles_per_row);
-
- assert(tex->image.block_width == 1 && tex->image.block_height == 1);
-
- if (tex->separate_s8) {
- struct ilo_texture *s8_tex = tex->separate_s8;
- uint8_t *s8_dst;
- tex_tile_offset_func s8_tile_offset;
- unsigned s8_tiles_per_row;
- int src_cpp, src_s8_pos, dst_cpp_used;
-
- s8_dst = tex_staging_sys_map_bo(s8_tex, false, false);
- if (!s8_dst) {
- tex_staging_sys_unmap_bo(s8_tex);
- return false;
- }
-
- s8_tile_offset = tex_tile_choose_offset_func(s8_tex, &s8_tiles_per_row);
-
- if (tex->base.format == PIPE_FORMAT_Z24_UNORM_S8_UINT) {
- assert(tex->image_format == PIPE_FORMAT_Z24X8_UNORM);
-
- src_cpp = 4;
- src_s8_pos = 3;
- dst_cpp_used = 3;
- }
- else {
- assert(tex->base.format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT);
- assert(tex->image_format == PIPE_FORMAT_Z32_FLOAT);
-
- src_cpp = 8;
- src_s8_pos = 4;
- dst_cpp_used = 4;
- }
-
- for (slice = 0; slice < box->depth; slice++) {
- unsigned mem_x, mem_y, s8_mem_x, s8_mem_y;
- const uint8_t *src;
- int i, j;
-
- tex_get_box_origin(tex, xfer->base.level, slice,
- box, &mem_x, &mem_y);
- tex_get_box_origin(s8_tex, xfer->base.level, slice,
- box, &s8_mem_x, &s8_mem_y);
-
- src = xfer->staging.sys + xfer->base.layer_stride * slice;
-
- for (i = 0; i < box->height; i++) {
- unsigned x = mem_x, s8_x = s8_mem_x;
- const uint8_t *s = src;
-
- for (j = 0; j < box->width; j++) {
- const unsigned offset =
- tile_offset(x, mem_y, tiles_per_row, swizzle);
- const unsigned s8_offset =
- s8_tile_offset(s8_x, s8_mem_y, s8_tiles_per_row, swizzle);
-
- memcpy(dst + offset, s, dst_cpp_used);
- s8_dst[s8_offset] = s[src_s8_pos];
-
- s += src_cpp;
- x += tex->image.block_size;
- s8_x++;
- }
-
- src += xfer->base.stride;
- mem_y++;
- s8_mem_y++;
- }
- }
-
- tex_staging_sys_unmap_bo(s8_tex);
- }
- else {
- assert(tex->image_format == PIPE_FORMAT_S8_UINT);
-
- for (slice = 0; slice < box->depth; slice++) {
- unsigned mem_x, mem_y;
- const uint8_t *src;
- int i, j;
-
- tex_get_box_origin(tex, xfer->base.level, slice,
- box, &mem_x, &mem_y);
-
- src = xfer->staging.sys + xfer->base.layer_stride * slice;
-
- for (i = 0; i < box->height; i++) {
- unsigned x = mem_x;
- const uint8_t *s = src;
-
- for (j = 0; j < box->width; j++) {
- const unsigned offset =
- tile_offset(x, mem_y, tiles_per_row, swizzle);
-
- dst[offset] = *s;
-
- s++;
- x++;
- }
-
- src += xfer->base.stride;
- mem_y++;
- }
- }
- }
-
- tex_staging_sys_unmap_bo(tex);
-
- return true;
-}
-
-static bool
-tex_staging_sys_convert_write(struct ilo_texture *tex,
- const struct ilo_transfer *xfer)
-{
- const struct pipe_box *box = &xfer->base.box;
- unsigned dst_slice_stride;
- void *dst;
- int slice;
-
- dst = tex_staging_sys_map_bo(tex, false, true);
- if (!dst)
- return false;
-
- dst += tex_get_box_offset(tex, xfer->base.level, box);
-
- /* slice stride is not always available */
- if (box->depth > 1)
- dst_slice_stride = tex_get_slice_stride(tex, xfer->base.level);
- else
- dst_slice_stride = 0;
-
- if (unlikely(tex->image_format == tex->base.format)) {
- util_copy_box(dst, tex->image_format, tex->image.bo_stride,
- dst_slice_stride, 0, 0, 0, box->width, box->height, box->depth,
- xfer->staging.sys, xfer->base.stride, xfer->base.layer_stride,
- 0, 0, 0);
-
- tex_staging_sys_unmap_bo(tex);
-
- return true;
- }
-
- switch (tex->base.format) {
- case PIPE_FORMAT_ETC1_RGB8:
- assert(tex->image_format == PIPE_FORMAT_R8G8B8X8_UNORM);
-
- for (slice = 0; slice < box->depth; slice++) {
- const void *src =
- xfer->staging.sys + xfer->base.layer_stride * slice;
-
- util_format_etc1_rgb8_unpack_rgba_8unorm(dst,
- tex->image.bo_stride, src, xfer->base.stride,
- box->width, box->height);
-
- dst += dst_slice_stride;
- }
- break;
- default:
- assert(!"unable to convert the staging data");
- break;
- }
-
- tex_staging_sys_unmap_bo(tex);
-
- return true;
-}
-
-static void
-tex_staging_sys_writeback(struct ilo_transfer *xfer)
-{
- struct ilo_texture *tex = ilo_texture(xfer->base.resource);
- bool success;
-
- if (!(xfer->base.usage & PIPE_TRANSFER_WRITE))
- return;
-
- switch (xfer->method) {
- case ILO_TRANSFER_MAP_SW_CONVERT:
- success = tex_staging_sys_convert_write(tex, xfer);
- break;
- case ILO_TRANSFER_MAP_SW_ZS:
- success = tex_staging_sys_zs_write(tex, xfer);
- break;
- default:
- assert(!"unknown mapping method");
- success = false;
- break;
- }
-
- if (!success)
- ilo_err("failed to map resource for moving staging data\n");
-}
-
-static bool
-tex_staging_sys_readback(struct ilo_transfer *xfer)
-{
- struct ilo_texture *tex = ilo_texture(xfer->base.resource);
- bool read_back = false, success;
-
- /* see if we need to read the resource back */
- if (xfer->base.usage & PIPE_TRANSFER_READ) {
- read_back = true;
- }
- else if (xfer->base.usage & PIPE_TRANSFER_WRITE) {
- const unsigned discard_flags =
- (PIPE_TRANSFER_DISCARD_RANGE | PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE);
-
- if (!(xfer->base.usage & discard_flags))
- read_back = true;
- }
-
- if (!read_back)
- return true;
-
- switch (xfer->method) {
- case ILO_TRANSFER_MAP_SW_CONVERT:
- assert(!"no on-the-fly format conversion for mapping");
- success = false;
- break;
- case ILO_TRANSFER_MAP_SW_ZS:
- success = tex_staging_sys_zs_read(tex, xfer);
- break;
- default:
- assert(!"unknown mapping method");
- success = false;
- break;
- }
-
- return success;
-}
-
-static void *
-tex_map(struct ilo_transfer *xfer)
-{
- void *ptr;
-
- switch (xfer->method) {
- case ILO_TRANSFER_MAP_CPU:
- case ILO_TRANSFER_MAP_GTT:
- case ILO_TRANSFER_MAP_GTT_ASYNC:
- ptr = xfer_map(xfer);
- if (ptr) {
- const struct ilo_texture *tex = ilo_texture(xfer->base.resource);
-
- ptr += tex_get_box_offset(tex, xfer->base.level, &xfer->base.box);
-
- /* stride is for a block row, not a texel row */
- xfer->base.stride = tex->image.bo_stride;
- /* note that slice stride is not always available */
- xfer->base.layer_stride = (xfer->base.box.depth > 1) ?
- tex_get_slice_stride(tex, xfer->base.level) : 0;
- }
- break;
- case ILO_TRANSFER_MAP_STAGING:
- ptr = xfer_map(xfer);
- if (ptr) {
- const struct ilo_texture *staging = ilo_texture(xfer->staging.res);
- xfer->base.stride = staging->image.bo_stride;
- xfer->base.layer_stride = tex_get_slice_stride(staging, 0);
- }
- break;
- case ILO_TRANSFER_MAP_SW_CONVERT:
- case ILO_TRANSFER_MAP_SW_ZS:
- if (xfer_alloc_staging_sys(xfer) && tex_staging_sys_readback(xfer))
- ptr = xfer_map(xfer);
- else
- ptr = NULL;
- break;
- default:
- assert(!"unknown mapping method");
- ptr = NULL;
- break;
- }
-
- return ptr;
-}
-
-static void *
-buf_map(struct ilo_transfer *xfer)
-{
- void *ptr;
-
- ptr = xfer_map(xfer);
- if (!ptr)
- return NULL;
-
- if (xfer->method != ILO_TRANSFER_MAP_STAGING)
- ptr += xfer->base.box.x;
-
- xfer->base.stride = 0;
- xfer->base.layer_stride = 0;
-
- assert(xfer->base.level == 0);
- assert(xfer->base.box.y == 0);
- assert(xfer->base.box.z == 0);
- assert(xfer->base.box.height == 1);
- assert(xfer->base.box.depth == 1);
-
- return ptr;
-}
-
-static void
-copy_staging_resource(struct ilo_context *ilo,
- struct ilo_transfer *xfer,
- const struct pipe_box *box)
-{
- const unsigned pad_x = (xfer->staging.res->target == PIPE_BUFFER) ?
- xfer->base.box.x % ILO_TRANSFER_MAP_BUFFER_ALIGNMENT : 0;
- struct pipe_box modified_box;
-
- assert(xfer->method == ILO_TRANSFER_MAP_STAGING && xfer->staging.res);
-
- if (!box) {
- u_box_3d(pad_x, 0, 0, xfer->base.box.width, xfer->base.box.height,
- xfer->base.box.depth, &modified_box);
- box = &modified_box;
- }
- else if (pad_x) {
- modified_box = *box;
- modified_box.x += pad_x;
- box = &modified_box;
- }
-
- ilo_blitter_blt_copy_resource(ilo->blitter,
- xfer->base.resource, xfer->base.level,
- xfer->base.box.x, xfer->base.box.y, xfer->base.box.z,
- xfer->staging.res, 0, box);
-}
-
-static bool
-is_bo_busy(struct ilo_context *ilo, struct intel_bo *bo, bool *need_submit)
-{
- const bool referenced = ilo_builder_has_reloc(&ilo->cp->builder, bo);
-
- if (need_submit)
- *need_submit = referenced;
-
- if (referenced)
- return true;
-
- return intel_bo_is_busy(bo);
-}
-
-/**
- * Choose the best mapping method, depending on the transfer usage and whether
- * the bo is busy.
- */
-static bool
-choose_transfer_method(struct ilo_context *ilo, struct ilo_transfer *xfer)
-{
- struct pipe_resource *res = xfer->base.resource;
- bool need_submit;
-
- if (!resource_get_transfer_method(res, &xfer->base, &xfer->method))
- return false;
-
- /* see if we can avoid blocking */
- if (is_bo_busy(ilo, ilo_resource_get_vma(res)->bo, &need_submit)) {
- bool resource_renamed;
-
- if (!xfer_unblock(xfer, &resource_renamed)) {
- if (xfer->base.usage & PIPE_TRANSFER_DONTBLOCK)
- return false;
-
- /* submit to make bo really busy and map() correctly blocks */
- if (need_submit)
- ilo_cp_submit(ilo->cp, "syncing for transfers");
- }
-
- if (resource_renamed)
- ilo_state_vector_resource_renamed(&ilo->state_vector, res);
- }
-
- return true;
-}
-
-static void
-buf_pwrite(struct ilo_context *ilo, struct pipe_resource *res,
- unsigned usage, int offset, int size, const void *data)
-{
- struct ilo_buffer_resource *buf = ilo_buffer_resource(res);
- bool need_submit;
-
- /* see if we can avoid blocking */
- if (is_bo_busy(ilo, buf->vma.bo, &need_submit)) {
- bool unblocked = false;
-
- if ((usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) &&
- ilo_resource_rename_bo(res)) {
- ilo_state_vector_resource_renamed(&ilo->state_vector, res);
- unblocked = true;
- }
- else {
- struct pipe_resource templ, *staging;
-
- /*
- * allocate a staging buffer to hold the data and pipelined copy it
- * over
- */
- templ = *res;
- templ.width0 = size;
- templ.usage = PIPE_USAGE_STAGING;
- templ.bind = 0;
- staging = ilo->base.screen->resource_create(ilo->base.screen, &templ);
- if (staging) {
- const struct ilo_vma *staging_vma = ilo_resource_get_vma(staging);
- struct pipe_box staging_box;
-
- /* offset by staging_vma->bo_offset for pwrite */
- intel_bo_pwrite(staging_vma->bo, staging_vma->bo_offset,
- size, data);
-
- u_box_1d(0, size, &staging_box);
- ilo_blitter_blt_copy_resource(ilo->blitter,
- res, 0, offset, 0, 0,
- staging, 0, &staging_box);
-
- pipe_resource_reference(&staging, NULL);
-
- return;
- }
- }
-
- /* submit to make bo really busy and pwrite() correctly blocks */
- if (!unblocked && need_submit)
- ilo_cp_submit(ilo->cp, "syncing for pwrites");
- }
-
- /* offset by buf->vma.bo_offset for pwrite */
- intel_bo_pwrite(buf->vma.bo, buf->vma.bo_offset + offset, size, data);
-}
-
-static void
-ilo_transfer_flush_region(struct pipe_context *pipe,
- struct pipe_transfer *transfer,
- const struct pipe_box *box)
-{
- struct ilo_context *ilo = ilo_context(pipe);
- struct ilo_transfer *xfer = ilo_transfer(transfer);
-
- /*
- * The staging resource is mapped persistently and coherently. We can copy
- * without unmapping.
- */
- if (xfer->method == ILO_TRANSFER_MAP_STAGING &&
- (xfer->base.usage & PIPE_TRANSFER_FLUSH_EXPLICIT))
- copy_staging_resource(ilo, xfer, box);
-}
-
-static void
-ilo_transfer_unmap(struct pipe_context *pipe,
- struct pipe_transfer *transfer)
-{
- struct ilo_context *ilo = ilo_context(pipe);
- struct ilo_transfer *xfer = ilo_transfer(transfer);
-
- xfer_unmap(xfer);
-
- switch (xfer->method) {
- case ILO_TRANSFER_MAP_STAGING:
- if (!(xfer->base.usage & PIPE_TRANSFER_FLUSH_EXPLICIT))
- copy_staging_resource(ilo, xfer, NULL);
- pipe_resource_reference(&xfer->staging.res, NULL);
- break;
- case ILO_TRANSFER_MAP_SW_CONVERT:
- case ILO_TRANSFER_MAP_SW_ZS:
- tex_staging_sys_writeback(xfer);
- align_free(xfer->staging.sys);
- break;
- default:
- break;
- }
-
- pipe_resource_reference(&xfer->base.resource, NULL);
-
- slab_free_st(&ilo->transfer_mempool, xfer);
-}
-
-static void *
-ilo_transfer_map(struct pipe_context *pipe,
- struct pipe_resource *res,
- unsigned level,
- unsigned usage,
- const struct pipe_box *box,
- struct pipe_transfer **transfer)
-{
- struct ilo_context *ilo = ilo_context(pipe);
- struct ilo_transfer *xfer;
- void *ptr;
-
- /* note that xfer is not zero'd */
- xfer = slab_alloc_st(&ilo->transfer_mempool);
- if (!xfer) {
- *transfer = NULL;
- return NULL;
- }
-
- xfer->base.resource = NULL;
- pipe_resource_reference(&xfer->base.resource, res);
- xfer->base.level = level;
- xfer->base.usage = usage;
- xfer->base.box = *box;
-
- ilo_blit_resolve_transfer(ilo, &xfer->base);
-
- if (choose_transfer_method(ilo, xfer)) {
- if (res->target == PIPE_BUFFER)
- ptr = buf_map(xfer);
- else
- ptr = tex_map(xfer);
- }
- else {
- ptr = NULL;
- }
-
- if (!ptr) {
- pipe_resource_reference(&xfer->base.resource, NULL);
- slab_free_st(&ilo->transfer_mempool, xfer);
- *transfer = NULL;
- return NULL;
- }
-
- *transfer = &xfer->base;
-
- return ptr;
-}
-
-static void ilo_buffer_subdata(struct pipe_context *pipe,
- struct pipe_resource *resource,
- unsigned usage, unsigned offset,
- unsigned size, const void *data)
-{
- if (usage & PIPE_TRANSFER_UNSYNCHRONIZED)
- u_default_buffer_subdata(pipe, resource, usage, offset, size, data);
- else
- buf_pwrite(ilo_context(pipe), resource, usage, offset, size, data);
-}
-
-/**
- * Initialize transfer-related functions.
- */
-void
-ilo_init_transfer_functions(struct ilo_context *ilo)
-{
- ilo->base.transfer_map = ilo_transfer_map;
- ilo->base.transfer_flush_region = ilo_transfer_flush_region;
- ilo->base.transfer_unmap = ilo_transfer_unmap;
- ilo->base.buffer_subdata = ilo_buffer_subdata;
- ilo->base.texture_subdata = u_default_texture_subdata;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_TRANSFER_H
-#define ILO_TRANSFER_H
-
-#include "pipe/p_state.h"
-
-#include "ilo_common.h"
-
-/*
- * Direct mappings are always page aligned, but ILO_TRANSFER_MAP_STAGING is
- * not.
- */
-#define ILO_TRANSFER_MAP_BUFFER_ALIGNMENT 64
-
-enum ilo_transfer_map_method {
- /* map() / map_gtt() / map_gtt_async() */
- ILO_TRANSFER_MAP_CPU,
- ILO_TRANSFER_MAP_GTT,
- ILO_TRANSFER_MAP_GTT_ASYNC,
-
- /* use staging resource */
- ILO_TRANSFER_MAP_STAGING,
-
- /* use staging system buffer */
- ILO_TRANSFER_MAP_SW_CONVERT,
- ILO_TRANSFER_MAP_SW_ZS,
-};
-
-struct ilo_transfer {
- struct pipe_transfer base;
-
- enum ilo_transfer_map_method method;
- /* pipe_resource, system memory, or garbage depending on the method */
- union {
- struct pipe_resource *res;
- void *sys;
- } staging;
-};
-
-struct ilo_context;
-
-static inline struct ilo_transfer *
-ilo_transfer(struct pipe_transfer *transfer)
-{
- return (struct ilo_transfer *) transfer;
-}
-
-void
-ilo_init_transfer_functions(struct ilo_context *ilo);
-
-#endif /* ILO_TRANSFER_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "vl/vl_decoder.h"
-#include "vl/vl_video_buffer.h"
-
-#include "ilo_context.h"
-#include "ilo_video.h"
-
-/*
- * Nothing here. We could make use of the video codec engine someday.
- */
-
-static struct pipe_video_codec *
-ilo_create_video_decoder(struct pipe_context *pipe,
- const struct pipe_video_codec *templ)
-{
- return vl_create_decoder(pipe, templ);
-}
-
-static struct pipe_video_buffer *
-ilo_create_video_buffer(struct pipe_context *pipe,
- const struct pipe_video_buffer *templ)
-{
- return vl_video_buffer_create(pipe, templ);
-}
-
-/**
- * Initialize video-related functions.
- */
-void
-ilo_init_video_functions(struct ilo_context *ilo)
-{
- ilo->base.create_video_codec = ilo_create_video_decoder;
- ilo->base.create_video_buffer = ilo_create_video_buffer;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_VIDEO_H
-#define ILO_VIDEO_H
-
-#include "ilo_common.h"
-
-struct ilo_context;
-
-void
-ilo_init_video_functions(struct ilo_context *ilo);
-
-#endif /* ILO_VIDEO_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "toy_compiler.h"
-#include "toy_helpers.h"
-#include "toy_legalize.h"
-#include "toy_optimize.h"
-#include "ilo_shader_internal.h"
-
-struct cs_compile_context {
- struct ilo_shader *shader;
- const struct ilo_shader_variant *variant;
-
- struct toy_compiler tc;
-
- int first_free_grf;
- int last_free_grf;
-
- int num_grf_per_vrf;
-
- int first_free_mrf;
- int last_free_mrf;
-};
-
-/**
- * Compile the shader.
- */
-static bool
-cs_compile(struct cs_compile_context *ccc)
-{
- struct toy_compiler *tc = &ccc->tc;
- struct ilo_shader *sh = ccc->shader;
-
- toy_compiler_legalize_for_ra(tc);
- toy_compiler_optimize(tc);
- toy_compiler_allocate_registers(tc,
- ccc->first_free_grf,
- ccc->last_free_grf,
- ccc->num_grf_per_vrf);
- toy_compiler_legalize_for_asm(tc);
-
- if (tc->fail) {
- ilo_err("failed to legalize FS instructions: %s\n", tc->reason);
- return false;
- }
-
- if (ilo_debug & ILO_DEBUG_CS) {
- ilo_printf("legalized instructions:\n");
- toy_compiler_dump(tc);
- ilo_printf("\n");
- }
-
- if (true) {
- sh->kernel = toy_compiler_assemble(tc, &sh->kernel_size);
- } else {
- static const uint32_t microcode[] = {
- /* fill in the microcode here */
- 0x0, 0x0, 0x0, 0x0,
- };
- const bool swap = true;
-
- sh->kernel_size = sizeof(microcode);
- sh->kernel = MALLOC(sh->kernel_size);
-
- if (sh->kernel) {
- const int num_dwords = sizeof(microcode) / 4;
- const uint32_t *src = microcode;
- uint32_t *dst = (uint32_t *) sh->kernel;
- int i;
-
- for (i = 0; i < num_dwords; i += 4) {
- if (swap) {
- dst[i + 0] = src[i + 3];
- dst[i + 1] = src[i + 2];
- dst[i + 2] = src[i + 1];
- dst[i + 3] = src[i + 0];
- }
- else {
- memcpy(dst, src, 16);
- }
- }
- }
- }
-
- if (!sh->kernel) {
- ilo_err("failed to compile CS: %s\n", tc->reason);
- return false;
- }
-
- if (ilo_debug & ILO_DEBUG_CS) {
- ilo_printf("disassembly:\n");
- toy_compiler_disassemble(tc->dev, sh->kernel, sh->kernel_size, false);
- ilo_printf("\n");
- }
-
- return true;
-}
-
-static void
-cs_dummy(struct cs_compile_context *ccc)
-{
- struct toy_compiler *tc = &ccc->tc;
- struct toy_dst header;
- struct toy_src r0, desc;
- struct toy_inst *inst;
-
- header = tdst_ud(tdst(TOY_FILE_MRF, ccc->first_free_mrf, 0));
- r0 = tsrc_ud(tsrc(TOY_FILE_GRF, 0, 0));
-
- inst = tc_MOV(tc, header, r0);
- inst->exec_size = GEN6_EXECSIZE_8;
- inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
-
- desc = tsrc_imm_mdesc(tc, true, 1, 0, true,
- GEN6_MSG_TS_RESOURCE_SELECT_NO_DEREF |
- GEN6_MSG_TS_REQUESTER_TYPE_ROOT |
- GEN6_MSG_TS_OPCODE_DEREF);
-
- tc_SEND(tc, tdst_null(), tsrc_from(header), desc, GEN6_SFID_SPAWNER);
-}
-
-static bool
-cs_setup(struct cs_compile_context *ccc,
- const struct ilo_shader_state *state,
- const struct ilo_shader_variant *variant)
-{
- memset(ccc, 0, sizeof(*ccc));
-
- ccc->shader = CALLOC_STRUCT(ilo_shader);
- if (!ccc->shader)
- return false;
-
- ccc->variant = variant;
-
- toy_compiler_init(&ccc->tc, state->info.dev);
-
- ccc->tc.templ.access_mode = GEN6_ALIGN_1;
- ccc->tc.templ.qtr_ctrl = GEN6_QTRCTRL_1H;
- ccc->tc.templ.exec_size = GEN6_EXECSIZE_16;
- ccc->tc.rect_linear_width = 8;
-
- ccc->first_free_grf = 1;
- ccc->last_free_grf = 127;
-
- /* m0 is reserved for system routines */
- ccc->first_free_mrf = 1;
- ccc->last_free_mrf = 15;
-
- /* instructions are compressed with GEN6_EXECSIZE_16 */
- ccc->num_grf_per_vrf = 2;
-
- if (ilo_dev_gen(ccc->tc.dev) >= ILO_GEN(7)) {
- ccc->last_free_grf -= 15;
- ccc->first_free_mrf = ccc->last_free_grf + 1;
- ccc->last_free_mrf = ccc->first_free_mrf + 14;
- }
-
- ccc->shader->in.start_grf = 1;
- ccc->shader->dispatch_16 = true;
-
- /* INPUT */
- ccc->shader->bt.const_base = 0;
- ccc->shader->bt.const_count = 1;
-
- /* a GLOBAL */
- ccc->shader->bt.global_base = 1;
- ccc->shader->bt.global_count = 1;
-
- ccc->shader->bt.total_count = 2;
-
- return true;
-}
-
-/**
- * Compile the compute shader.
- */
-struct ilo_shader *
-ilo_shader_compile_cs(const struct ilo_shader_state *state,
- const struct ilo_shader_variant *variant)
-{
- struct cs_compile_context ccc;
-
- ILO_DEV_ASSERT(state->info.dev, 7, 7.5);
-
- if (!cs_setup(&ccc, state, variant))
- return NULL;
-
- cs_dummy(&ccc);
-
- if (!cs_compile(&ccc)) {
- FREE(ccc.shader);
- ccc.shader = NULL;
- }
-
- toy_compiler_cleanup(&ccc.tc);
-
- return ccc.shader;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "tgsi/tgsi_dump.h"
-#include "tgsi/tgsi_util.h"
-#include "toy_compiler.h"
-#include "toy_tgsi.h"
-#include "toy_legalize.h"
-#include "toy_optimize.h"
-#include "toy_helpers.h"
-#include "ilo_shader_internal.h"
-
-struct fs_compile_context {
- struct ilo_shader *shader;
- const struct ilo_shader_variant *variant;
-
- struct toy_compiler tc;
- struct toy_tgsi tgsi;
-
- int const_cache;
- int dispatch_mode;
-
- struct {
- int interp_perspective_pixel;
- int interp_perspective_centroid;
- int interp_perspective_sample;
- int interp_nonperspective_pixel;
- int interp_nonperspective_centroid;
- int interp_nonperspective_sample;
- int source_depth;
- int source_w;
- int pos_offset;
- } payloads[2];
-
- int first_const_grf;
- int first_attr_grf;
- int first_free_grf;
- int last_free_grf;
-
- int num_grf_per_vrf;
-
- int first_free_mrf;
- int last_free_mrf;
-};
-
-static void
-fetch_position(struct fs_compile_context *fcc, struct toy_dst dst)
-{
- struct toy_compiler *tc = &fcc->tc;
- const struct toy_src src_z =
- tsrc(TOY_FILE_GRF, fcc->payloads[0].source_depth, 0);
- const struct toy_src src_w =
- tsrc(TOY_FILE_GRF, fcc->payloads[0].source_w, 0);
- const int fb_height =
- (fcc->variant->u.fs.fb_height) ? fcc->variant->u.fs.fb_height : 1;
- const bool origin_upper_left =
- (fcc->tgsi.props.fs_coord_origin == TGSI_FS_COORD_ORIGIN_UPPER_LEFT);
- const bool pixel_center_integer =
- (fcc->tgsi.props.fs_coord_pixel_center ==
- TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
- struct toy_src subspan_x, subspan_y;
- struct toy_dst tmp, tmp_uw;
- struct toy_dst real_dst[4];
-
- tdst_transpose(dst, real_dst);
-
- subspan_x = tsrc_uw(tsrc(TOY_FILE_GRF, 1, 2 * 4));
- subspan_x = tsrc_rect(subspan_x, TOY_RECT_240);
-
- subspan_y = tsrc_offset(subspan_x, 0, 1);
-
- tmp_uw = tdst_uw(tc_alloc_tmp(tc));
- tmp = tc_alloc_tmp(tc);
-
- /* X */
- tc_ADD(tc, tmp_uw, subspan_x, tsrc_imm_v(0x10101010));
- tc_MOV(tc, tmp, tsrc_from(tmp_uw));
- if (pixel_center_integer)
- tc_MOV(tc, real_dst[0], tsrc_from(tmp));
- else
- tc_ADD(tc, real_dst[0], tsrc_from(tmp), tsrc_imm_f(0.5f));
-
- /* Y */
- tc_ADD(tc, tmp_uw, subspan_y, tsrc_imm_v(0x11001100));
- tc_MOV(tc, tmp, tsrc_from(tmp_uw));
- if (origin_upper_left && pixel_center_integer) {
- tc_MOV(tc, real_dst[1], tsrc_from(tmp));
- }
- else {
- struct toy_src y = tsrc_from(tmp);
- float offset = 0.0f;
-
- if (!pixel_center_integer)
- offset += 0.5f;
-
- if (!origin_upper_left) {
- offset += (float) (fb_height - 1);
- y = tsrc_negate(y);
- }
-
- tc_ADD(tc, real_dst[1], y, tsrc_imm_f(offset));
- }
-
- /* Z and W */
- tc_MOV(tc, real_dst[2], src_z);
- tc_INV(tc, real_dst[3], src_w);
-}
-
-static void
-fetch_face(struct fs_compile_context *fcc, struct toy_dst dst)
-{
- struct toy_compiler *tc = &fcc->tc;
- const struct toy_src r0 = tsrc_d(tsrc(TOY_FILE_GRF, 0, 0));
- struct toy_dst tmp_f, tmp;
- struct toy_dst real_dst[4];
-
- tdst_transpose(dst, real_dst);
-
- tmp_f = tc_alloc_tmp(tc);
- tmp = tdst_d(tmp_f);
- tc_SHR(tc, tmp, tsrc_rect(r0, TOY_RECT_010), tsrc_imm_d(15));
- tc_AND(tc, tmp, tsrc_from(tmp), tsrc_imm_d(1));
- tc_MOV(tc, tmp_f, tsrc_from(tmp));
-
- /* convert to 1.0 and -1.0 */
- tc_MUL(tc, tmp_f, tsrc_from(tmp_f), tsrc_imm_f(-2.0f));
- tc_ADD(tc, real_dst[0], tsrc_from(tmp_f), tsrc_imm_f(1.0f));
-
- tc_MOV(tc, real_dst[1], tsrc_imm_f(0.0f));
- tc_MOV(tc, real_dst[2], tsrc_imm_f(0.0f));
- tc_MOV(tc, real_dst[3], tsrc_imm_f(1.0f));
-}
-
-static void
-fetch_attr(struct fs_compile_context *fcc, struct toy_dst dst, int slot)
-{
- struct toy_compiler *tc = &fcc->tc;
- struct toy_dst real_dst[4];
- bool is_const = false;
- int grf, interp, ch;
-
- tdst_transpose(dst, real_dst);
-
- grf = fcc->first_attr_grf + slot * 2;
-
- switch (fcc->tgsi.inputs[slot].interp) {
- case TGSI_INTERPOLATE_CONSTANT:
- is_const = true;
- break;
- case TGSI_INTERPOLATE_LINEAR:
- if (fcc->tgsi.inputs[slot].centroid)
- interp = fcc->payloads[0].interp_nonperspective_centroid;
- else
- interp = fcc->payloads[0].interp_nonperspective_pixel;
- break;
- case TGSI_INTERPOLATE_COLOR:
- if (fcc->variant->u.fs.flatshade) {
- is_const = true;
- break;
- }
- /* fall through */
- case TGSI_INTERPOLATE_PERSPECTIVE:
- if (fcc->tgsi.inputs[slot].centroid)
- interp = fcc->payloads[0].interp_perspective_centroid;
- else
- interp = fcc->payloads[0].interp_perspective_pixel;
- break;
- default:
- assert(!"unexpected FS interpolation");
- interp = fcc->payloads[0].interp_perspective_pixel;
- break;
- }
-
- if (is_const) {
- struct toy_src a0[4];
-
- a0[0] = tsrc(TOY_FILE_GRF, grf + 0, 3 * 4);
- a0[1] = tsrc(TOY_FILE_GRF, grf + 0, 7 * 4);
- a0[2] = tsrc(TOY_FILE_GRF, grf + 1, 3 * 4);
- a0[3] = tsrc(TOY_FILE_GRF, grf + 1, 7 * 4);
-
- for (ch = 0; ch < 4; ch++)
- tc_MOV(tc, real_dst[ch], tsrc_rect(a0[ch], TOY_RECT_010));
- }
- else {
- struct toy_src attr[4], uv;
-
- attr[0] = tsrc(TOY_FILE_GRF, grf + 0, 0);
- attr[1] = tsrc(TOY_FILE_GRF, grf + 0, 4 * 4);
- attr[2] = tsrc(TOY_FILE_GRF, grf + 1, 0);
- attr[3] = tsrc(TOY_FILE_GRF, grf + 1, 4 * 4);
-
- uv = tsrc(TOY_FILE_GRF, interp, 0);
-
- for (ch = 0; ch < 4; ch++) {
- tc_add2(tc, GEN6_OPCODE_PLN, real_dst[ch],
- tsrc_rect(attr[ch], TOY_RECT_010), uv);
- }
- }
-
- if (fcc->tgsi.inputs[slot].semantic_name == TGSI_SEMANTIC_FOG) {
- tc_MOV(tc, real_dst[1], tsrc_imm_f(0.0f));
- tc_MOV(tc, real_dst[2], tsrc_imm_f(0.0f));
- tc_MOV(tc, real_dst[3], tsrc_imm_f(1.0f));
- }
-}
-
-static void
-fs_lower_opcode_tgsi_in(struct fs_compile_context *fcc,
- struct toy_dst dst, int dim, int idx)
-{
- int slot;
-
- assert(!dim);
-
- slot = toy_tgsi_find_input(&fcc->tgsi, idx);
- if (slot < 0)
- return;
-
- switch (fcc->tgsi.inputs[slot].semantic_name) {
- case TGSI_SEMANTIC_POSITION:
- fetch_position(fcc, dst);
- break;
- case TGSI_SEMANTIC_FACE:
- fetch_face(fcc, dst);
- break;
- default:
- fetch_attr(fcc, dst, slot);
- break;
- }
-}
-
-static void
-fs_lower_opcode_tgsi_indirect_const(struct fs_compile_context *fcc,
- struct toy_dst dst, int dim,
- struct toy_src idx)
-{
- const struct toy_dst offset =
- tdst_ud(tdst(TOY_FILE_MRF, fcc->first_free_mrf, 0));
- struct toy_compiler *tc = &fcc->tc;
- unsigned simd_mode, param_size;
- struct toy_inst *inst;
- struct toy_src desc, real_src[4];
- struct toy_dst tmp, real_dst[4];
- unsigned i;
-
- tsrc_transpose(idx, real_src);
-
- /* set offset */
- inst = tc_MOV(tc, offset, real_src[0]);
- inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
-
- switch (inst->exec_size) {
- case GEN6_EXECSIZE_8:
- simd_mode = GEN6_MSG_SAMPLER_SIMD8;
- param_size = 1;
- break;
- case GEN6_EXECSIZE_16:
- simd_mode = GEN6_MSG_SAMPLER_SIMD16;
- param_size = 2;
- break;
- default:
- assert(!"unsupported execution size");
- tc_MOV(tc, dst, tsrc_imm_f(0.0f));
- return;
- break;
- }
-
- desc = tsrc_imm_mdesc_sampler(tc, param_size, param_size * 4, false,
- simd_mode,
- GEN6_MSG_SAMPLER_LD,
- 0,
- fcc->shader->bt.const_base + dim);
-
- tmp = tdst(TOY_FILE_VRF, tc_alloc_vrf(tc, param_size * 4), 0);
- inst = tc_SEND(tc, tmp, tsrc_from(offset), desc, GEN6_SFID_SAMPLER);
- inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
-
- tdst_transpose(dst, real_dst);
- for (i = 0; i < 4; i++) {
- const struct toy_src src =
- tsrc_offset(tsrc_from(tmp), param_size * i, 0);
-
- /* cast to type D to make sure these are raw moves */
- tc_MOV(tc, tdst_d(real_dst[i]), tsrc_d(src));
- }
-}
-
-static bool
-fs_lower_opcode_tgsi_const_pcb(struct fs_compile_context *fcc,
- struct toy_dst dst, int dim,
- struct toy_src idx)
-{
- const int grf = fcc->first_const_grf + idx.val32 / 2;
- const int grf_subreg = (idx.val32 & 1) * 16;
- struct toy_src src;
- struct toy_dst real_dst[4];
- unsigned i;
-
- if (!fcc->variant->use_pcb || dim != 0 || idx.file != TOY_FILE_IMM ||
- grf >= fcc->first_attr_grf)
- return false;
-
- src = tsrc_rect(tsrc(TOY_FILE_GRF, grf, grf_subreg), TOY_RECT_010);
-
- tdst_transpose(dst, real_dst);
- for (i = 0; i < 4; i++) {
- /* cast to type D to make sure these are raw moves */
- tc_MOV(&fcc->tc, tdst_d(real_dst[i]), tsrc_d(tsrc_offset(src, 0, i)));
- }
-
- return true;
-}
-
-static void
-fs_lower_opcode_tgsi_const_gen6(struct fs_compile_context *fcc,
- struct toy_dst dst, int dim, struct toy_src idx)
-{
- const struct toy_dst header =
- tdst_ud(tdst(TOY_FILE_MRF, fcc->first_free_mrf, 0));
- const struct toy_dst global_offset =
- tdst_ud(tdst(TOY_FILE_MRF, fcc->first_free_mrf, 2 * 4));
- const struct toy_src r0 = tsrc_ud(tsrc(TOY_FILE_GRF, 0, 0));
- struct toy_compiler *tc = &fcc->tc;
- unsigned msg_type, msg_ctrl, msg_len;
- struct toy_inst *inst;
- struct toy_src desc;
- struct toy_dst tmp, real_dst[4];
- unsigned i;
-
- if (fs_lower_opcode_tgsi_const_pcb(fcc, dst, dim, idx))
- return;
-
- /* set message header */
- inst = tc_MOV(tc, header, r0);
- inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
-
- /* set global offset */
- inst = tc_MOV(tc, global_offset, idx);
- inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
- inst->exec_size = GEN6_EXECSIZE_1;
- inst->src[0].rect = TOY_RECT_010;
-
- msg_type = GEN6_MSG_DP_OWORD_BLOCK_READ;
- msg_ctrl = GEN6_MSG_DP_OWORD_BLOCK_SIZE_1_LO;
- msg_len = 1;
-
- desc = tsrc_imm_mdesc_data_port(tc, false, msg_len, 1, true, false,
- msg_type, msg_ctrl, fcc->shader->bt.const_base + dim);
-
- tmp = tc_alloc_tmp(tc);
-
- tc_SEND(tc, tmp, tsrc_from(header), desc, fcc->const_cache);
-
- tdst_transpose(dst, real_dst);
- for (i = 0; i < 4; i++) {
- const struct toy_src src =
- tsrc_offset(tsrc_rect(tsrc_from(tmp), TOY_RECT_010), 0, i);
-
- /* cast to type D to make sure these are raw moves */
- tc_MOV(tc, tdst_d(real_dst[i]), tsrc_d(src));
- }
-}
-
-static void
-fs_lower_opcode_tgsi_const_gen7(struct fs_compile_context *fcc,
- struct toy_dst dst, int dim, struct toy_src idx)
-{
- struct toy_compiler *tc = &fcc->tc;
- const struct toy_dst offset =
- tdst_ud(tdst(TOY_FILE_MRF, fcc->first_free_mrf, 0));
- struct toy_src desc;
- struct toy_inst *inst;
- struct toy_dst tmp, real_dst[4];
- unsigned i;
-
- if (fs_lower_opcode_tgsi_const_pcb(fcc, dst, dim, idx))
- return;
-
- /*
- * In 4c1fdae0a01b3f92ec03b61aac1d3df500d51fc6, pull constant load was
- * changed from OWord Block Read to ld to increase performance in the
- * classic driver. Since we use the constant cache instead of the data
- * cache, I wonder if we still want to follow the classic driver.
- */
-
- /* set offset */
- inst = tc_MOV(tc, offset, tsrc_rect(idx, TOY_RECT_010));
- inst->exec_size = GEN6_EXECSIZE_8;
- inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
-
- desc = tsrc_imm_mdesc_sampler(tc, 1, 1, false,
- GEN6_MSG_SAMPLER_SIMD4X2,
- GEN6_MSG_SAMPLER_LD,
- 0,
- fcc->shader->bt.const_base + dim);
-
- tmp = tc_alloc_tmp(tc);
- inst = tc_SEND(tc, tmp, tsrc_from(offset), desc, GEN6_SFID_SAMPLER);
- inst->exec_size = GEN6_EXECSIZE_8;
- inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
-
- tdst_transpose(dst, real_dst);
- for (i = 0; i < 4; i++) {
- const struct toy_src src =
- tsrc_offset(tsrc_rect(tsrc_from(tmp), TOY_RECT_010), 0, i);
-
- /* cast to type D to make sure these are raw moves */
- tc_MOV(tc, tdst_d(real_dst[i]), tsrc_d(src));
- }
-}
-
-static void
-fs_lower_opcode_tgsi_imm(struct fs_compile_context *fcc,
- struct toy_dst dst, int idx)
-{
- const uint32_t *imm;
- struct toy_dst real_dst[4];
- int ch;
-
- imm = toy_tgsi_get_imm(&fcc->tgsi, idx, NULL);
-
- tdst_transpose(dst, real_dst);
- /* raw moves */
- for (ch = 0; ch < 4; ch++)
- tc_MOV(&fcc->tc, tdst_ud(real_dst[ch]), tsrc_imm_ud(imm[ch]));
-}
-
-static void
-fs_lower_opcode_tgsi_sv(struct fs_compile_context *fcc,
- struct toy_dst dst, int dim, int idx)
-{
- struct toy_compiler *tc = &fcc->tc;
- const struct toy_tgsi *tgsi = &fcc->tgsi;
- int slot;
-
- assert(!dim);
-
- slot = toy_tgsi_find_system_value(tgsi, idx);
- if (slot < 0)
- return;
-
- switch (tgsi->system_values[slot].semantic_name) {
- case TGSI_SEMANTIC_PRIMID:
- case TGSI_SEMANTIC_INSTANCEID:
- case TGSI_SEMANTIC_VERTEXID:
- default:
- tc_fail(tc, "unhandled system value");
- tc_MOV(tc, dst, tsrc_imm_d(0));
- break;
- }
-}
-
-static void
-fs_lower_opcode_tgsi_direct(struct fs_compile_context *fcc,
- struct toy_inst *inst)
-{
- struct toy_compiler *tc = &fcc->tc;
- int dim, idx;
-
- assert(inst->src[0].file == TOY_FILE_IMM);
- dim = inst->src[0].val32;
-
- assert(inst->src[1].file == TOY_FILE_IMM);
- idx = inst->src[1].val32;
-
- switch (inst->opcode) {
- case TOY_OPCODE_TGSI_IN:
- fs_lower_opcode_tgsi_in(fcc, inst->dst, dim, idx);
- break;
- case TOY_OPCODE_TGSI_CONST:
- if (ilo_dev_gen(tc->dev) >= ILO_GEN(7))
- fs_lower_opcode_tgsi_const_gen7(fcc, inst->dst, dim, inst->src[1]);
- else
- fs_lower_opcode_tgsi_const_gen6(fcc, inst->dst, dim, inst->src[1]);
- break;
- case TOY_OPCODE_TGSI_SV:
- fs_lower_opcode_tgsi_sv(fcc, inst->dst, dim, idx);
- break;
- case TOY_OPCODE_TGSI_IMM:
- assert(!dim);
- fs_lower_opcode_tgsi_imm(fcc, inst->dst, idx);
- break;
- default:
- tc_fail(tc, "unhandled TGSI fetch");
- break;
- }
-
- tc_discard_inst(tc, inst);
-}
-
-static void
-fs_lower_opcode_tgsi_indirect(struct fs_compile_context *fcc,
- struct toy_inst *inst)
-{
- struct toy_compiler *tc = &fcc->tc;
- enum tgsi_file_type file;
- int dim, idx;
- struct toy_src indirect_dim, indirect_idx;
-
- assert(inst->src[0].file == TOY_FILE_IMM);
- file = inst->src[0].val32;
-
- assert(inst->src[1].file == TOY_FILE_IMM);
- dim = inst->src[1].val32;
- indirect_dim = inst->src[2];
-
- assert(inst->src[3].file == TOY_FILE_IMM);
- idx = inst->src[3].val32;
- indirect_idx = inst->src[4];
-
- /* no dimension indirection */
- assert(indirect_dim.file == TOY_FILE_IMM);
- dim += indirect_dim.val32;
-
- switch (inst->opcode) {
- case TOY_OPCODE_TGSI_INDIRECT_FETCH:
- if (file == TGSI_FILE_CONSTANT) {
- if (idx) {
- struct toy_dst tmp = tc_alloc_tmp(tc);
-
- tc_ADD(tc, tmp, indirect_idx, tsrc_imm_d(idx));
- indirect_idx = tsrc_from(tmp);
- }
-
- fs_lower_opcode_tgsi_indirect_const(fcc, inst->dst, dim, indirect_idx);
- break;
- }
- /* fall through */
- case TOY_OPCODE_TGSI_INDIRECT_STORE:
- default:
- tc_fail(tc, "unhandled TGSI indirection");
- break;
- }
-
- tc_discard_inst(tc, inst);
-}
-
-/**
- * Emit instructions to move sampling parameters to the message registers.
- */
-static int
-fs_add_sampler_params_gen6(struct toy_compiler *tc, int msg_type,
- int base_mrf, int param_size,
- struct toy_src *coords, int num_coords,
- struct toy_src bias_or_lod, struct toy_src ref_or_si,
- struct toy_src *ddx, struct toy_src *ddy,
- int num_derivs)
-{
- int num_params, i;
-
- assert(num_coords <= 4);
- assert(num_derivs <= 3 && num_derivs <= num_coords);
-
-#define SAMPLER_PARAM(p) (tdst(TOY_FILE_MRF, base_mrf + (p) * param_size, 0))
- switch (msg_type) {
- case GEN6_MSG_SAMPLER_SAMPLE:
- for (i = 0; i < num_coords; i++)
- tc_MOV(tc, SAMPLER_PARAM(i), coords[i]);
- num_params = num_coords;
- break;
- case GEN6_MSG_SAMPLER_SAMPLE_B:
- case GEN6_MSG_SAMPLER_SAMPLE_L:
- for (i = 0; i < num_coords; i++)
- tc_MOV(tc, SAMPLER_PARAM(i), coords[i]);
- tc_MOV(tc, SAMPLER_PARAM(4), bias_or_lod);
- num_params = 5;
- break;
- case GEN6_MSG_SAMPLER_SAMPLE_C:
- for (i = 0; i < num_coords; i++)
- tc_MOV(tc, SAMPLER_PARAM(i), coords[i]);
- tc_MOV(tc, SAMPLER_PARAM(4), ref_or_si);
- num_params = 5;
- break;
- case GEN6_MSG_SAMPLER_SAMPLE_D:
- for (i = 0; i < num_coords; i++)
- tc_MOV(tc, SAMPLER_PARAM(i), coords[i]);
- for (i = 0; i < num_derivs; i++) {
- tc_MOV(tc, SAMPLER_PARAM(4 + i * 2), ddx[i]);
- tc_MOV(tc, SAMPLER_PARAM(5 + i * 2), ddy[i]);
- }
- num_params = 4 + num_derivs * 2;
- break;
- case GEN6_MSG_SAMPLER_SAMPLE_B_C:
- case GEN6_MSG_SAMPLER_SAMPLE_L_C:
- for (i = 0; i < num_coords; i++)
- tc_MOV(tc, SAMPLER_PARAM(i), coords[i]);
- tc_MOV(tc, SAMPLER_PARAM(4), ref_or_si);
- tc_MOV(tc, SAMPLER_PARAM(5), bias_or_lod);
- num_params = 6;
- break;
- case GEN6_MSG_SAMPLER_LD:
- assert(num_coords <= 3);
-
- for (i = 0; i < num_coords; i++)
- tc_MOV(tc, tdst_d(SAMPLER_PARAM(i)), coords[i]);
- tc_MOV(tc, tdst_d(SAMPLER_PARAM(3)), bias_or_lod);
- tc_MOV(tc, tdst_d(SAMPLER_PARAM(4)), ref_or_si);
- num_params = 5;
- break;
- case GEN6_MSG_SAMPLER_RESINFO:
- tc_MOV(tc, tdst_d(SAMPLER_PARAM(0)), bias_or_lod);
- num_params = 1;
- break;
- default:
- tc_fail(tc, "unknown sampler opcode");
- num_params = 0;
- break;
- }
-#undef SAMPLER_PARAM
-
- return num_params * param_size;
-}
-
-static int
-fs_add_sampler_params_gen7(struct toy_compiler *tc, int msg_type,
- int base_mrf, int param_size,
- struct toy_src *coords, int num_coords,
- struct toy_src bias_or_lod, struct toy_src ref_or_si,
- struct toy_src *ddx, struct toy_src *ddy,
- int num_derivs)
-{
- int num_params, i;
-
- assert(num_coords <= 4);
- assert(num_derivs <= 3 && num_derivs <= num_coords);
-
-#define SAMPLER_PARAM(p) (tdst(TOY_FILE_MRF, base_mrf + (p) * param_size, 0))
- switch (msg_type) {
- case GEN6_MSG_SAMPLER_SAMPLE:
- for (i = 0; i < num_coords; i++)
- tc_MOV(tc, SAMPLER_PARAM(i), coords[i]);
- num_params = num_coords;
- break;
- case GEN6_MSG_SAMPLER_SAMPLE_B:
- case GEN6_MSG_SAMPLER_SAMPLE_L:
- tc_MOV(tc, SAMPLER_PARAM(0), bias_or_lod);
- for (i = 0; i < num_coords; i++)
- tc_MOV(tc, SAMPLER_PARAM(1 + i), coords[i]);
- num_params = 1 + num_coords;
- break;
- case GEN6_MSG_SAMPLER_SAMPLE_C:
- tc_MOV(tc, SAMPLER_PARAM(0), ref_or_si);
- for (i = 0; i < num_coords; i++)
- tc_MOV(tc, SAMPLER_PARAM(1 + i), coords[i]);
- num_params = 1 + num_coords;
- break;
- case GEN6_MSG_SAMPLER_SAMPLE_D:
- for (i = 0; i < num_coords; i++) {
- tc_MOV(tc, SAMPLER_PARAM(i * 3), coords[i]);
- if (i < num_derivs) {
- tc_MOV(tc, SAMPLER_PARAM(i * 3 + 1), ddx[i]);
- tc_MOV(tc, SAMPLER_PARAM(i * 3 + 2), ddy[i]);
- }
- }
- num_params = num_coords * 3 - ((num_coords > num_derivs) ? 2 : 0);
- break;
- case GEN6_MSG_SAMPLER_SAMPLE_B_C:
- case GEN6_MSG_SAMPLER_SAMPLE_L_C:
- tc_MOV(tc, SAMPLER_PARAM(0), ref_or_si);
- tc_MOV(tc, SAMPLER_PARAM(1), bias_or_lod);
- for (i = 0; i < num_coords; i++)
- tc_MOV(tc, SAMPLER_PARAM(2 + i), coords[i]);
- num_params = 2 + num_coords;
- break;
- case GEN6_MSG_SAMPLER_LD:
- assert(num_coords >= 1 && num_coords <= 3);
-
- tc_MOV(tc, tdst_d(SAMPLER_PARAM(0)), coords[0]);
- tc_MOV(tc, tdst_d(SAMPLER_PARAM(1)), bias_or_lod);
- for (i = 1; i < num_coords; i++)
- tc_MOV(tc, tdst_d(SAMPLER_PARAM(1 + i)), coords[i]);
- num_params = 1 + num_coords;
- break;
- case GEN6_MSG_SAMPLER_RESINFO:
- tc_MOV(tc, tdst_d(SAMPLER_PARAM(0)), bias_or_lod);
- num_params = 1;
- break;
- default:
- tc_fail(tc, "unknown sampler opcode");
- num_params = 0;
- break;
- }
-#undef SAMPLER_PARAM
-
- return num_params * param_size;
-}
-
-/**
- * Set up message registers and return the message descriptor for sampling.
- */
-static struct toy_src
-fs_prepare_tgsi_sampling(struct fs_compile_context *fcc,
- const struct toy_inst *inst,
- int base_mrf, const uint32_t *saturate_coords,
- unsigned *ret_sampler_index)
-{
- struct toy_compiler *tc = &fcc->tc;
- unsigned simd_mode, msg_type, msg_len, sampler_index, binding_table_index;
- struct toy_src coords[4], ddx[4], ddy[4], bias_or_lod, ref_or_si;
- int num_coords, ref_pos, num_derivs;
- int sampler_src, param_size, i;
-
- switch (inst->exec_size) {
- case GEN6_EXECSIZE_8:
- simd_mode = GEN6_MSG_SAMPLER_SIMD8;
- param_size = 1;
- break;
- case GEN6_EXECSIZE_16:
- simd_mode = GEN6_MSG_SAMPLER_SIMD16;
- param_size = 2;
- break;
- default:
- tc_fail(tc, "unsupported execute size for sampling");
- return tsrc_null();
- break;
- }
-
- num_coords = tgsi_util_get_texture_coord_dim(inst->tex.target);
- ref_pos = tgsi_util_get_shadow_ref_src_index(inst->tex.target);
-
- tsrc_transpose(inst->src[0], coords);
- bias_or_lod = tsrc_null();
- ref_or_si = tsrc_null();
- num_derivs = 0;
- sampler_src = 1;
-
- /*
- * For TXD,
- *
- * src0 := (x, y, z, w)
- * src1 := ddx
- * src2 := ddy
- * src3 := sampler
- *
- * For TEX2, TXB2, and TXL2,
- *
- * src0 := (x, y, z, w)
- * src1 := (v or bias or lod, ...)
- * src2 := sampler
- *
- * For TEX, TXB, TXL, and TXP,
- *
- * src0 := (x, y, z, w or bias or lod or projection)
- * src1 := sampler
- *
- * For TXQ,
- *
- * src0 := (lod, ...)
- * src1 := sampler
- *
- * For TXQ_LZ,
- *
- * src0 := sampler
- *
- * And for TXF,
- *
- * src0 := (x, y, z, w or lod)
- * src1 := sampler
- *
- * State trackers should not generate opcode+texture combinations with
- * which the two definitions conflict (e.g., TXB with SHADOW2DARRAY).
- */
- switch (inst->opcode) {
- case TOY_OPCODE_TGSI_TEX:
- if (ref_pos >= 0) {
- assert(ref_pos < 4);
-
- msg_type = GEN6_MSG_SAMPLER_SAMPLE_C;
- ref_or_si = coords[ref_pos];
- }
- else {
- msg_type = GEN6_MSG_SAMPLER_SAMPLE;
- }
- break;
- case TOY_OPCODE_TGSI_TXD:
- if (ref_pos >= 0) {
- assert(ref_pos < 4);
-
- msg_type = GEN7_MSG_SAMPLER_SAMPLE_D_C;
- ref_or_si = coords[ref_pos];
-
- if (ilo_dev_gen(tc->dev) < ILO_GEN(7.5))
- tc_fail(tc, "TXD with shadow sampler not supported");
- }
- else {
- msg_type = GEN6_MSG_SAMPLER_SAMPLE_D;
- }
-
- tsrc_transpose(inst->src[1], ddx);
- tsrc_transpose(inst->src[2], ddy);
- num_derivs = num_coords;
- sampler_src = 3;
- break;
- case TOY_OPCODE_TGSI_TXP:
- if (ref_pos >= 0) {
- assert(ref_pos < 3);
-
- msg_type = GEN6_MSG_SAMPLER_SAMPLE_C;
- ref_or_si = coords[ref_pos];
- }
- else {
- msg_type = GEN6_MSG_SAMPLER_SAMPLE;
- }
-
- /* project the coordinates */
- {
- struct toy_dst tmp[4];
-
- tc_alloc_tmp4(tc, tmp);
-
- tc_INV(tc, tmp[3], coords[3]);
- for (i = 0; i < num_coords && i < 3; i++) {
- tc_MUL(tc, tmp[i], coords[i], tsrc_from(tmp[3]));
- coords[i] = tsrc_from(tmp[i]);
- }
-
- if (ref_pos >= i) {
- tc_MUL(tc, tmp[ref_pos], ref_or_si, tsrc_from(tmp[3]));
- ref_or_si = tsrc_from(tmp[ref_pos]);
- }
- }
- break;
- case TOY_OPCODE_TGSI_TXB:
- if (ref_pos >= 0) {
- assert(ref_pos < 3);
-
- msg_type = GEN6_MSG_SAMPLER_SAMPLE_B_C;
- ref_or_si = coords[ref_pos];
- }
- else {
- msg_type = GEN6_MSG_SAMPLER_SAMPLE_B;
- }
-
- bias_or_lod = coords[3];
- break;
- case TOY_OPCODE_TGSI_TXL:
- if (ref_pos >= 0) {
- assert(ref_pos < 3);
-
- msg_type = GEN6_MSG_SAMPLER_SAMPLE_L_C;
- ref_or_si = coords[ref_pos];
- }
- else {
- msg_type = GEN6_MSG_SAMPLER_SAMPLE_L;
- }
-
- bias_or_lod = coords[3];
- break;
- case TOY_OPCODE_TGSI_TXF:
- msg_type = GEN6_MSG_SAMPLER_LD;
-
- switch (inst->tex.target) {
- case TGSI_TEXTURE_2D_MSAA:
- case TGSI_TEXTURE_2D_ARRAY_MSAA:
- assert(ref_pos >= 0 && ref_pos < 4);
- /* lod is always 0 */
- bias_or_lod = tsrc_imm_d(0);
- ref_or_si = coords[ref_pos];
- break;
- default:
- bias_or_lod = coords[3];
- break;
- }
-
- /* offset the coordinates */
- if (!tsrc_is_null(inst->tex.offsets[0])) {
- struct toy_dst tmp[4];
- struct toy_src offsets[4];
-
- tc_alloc_tmp4(tc, tmp);
- tsrc_transpose(inst->tex.offsets[0], offsets);
-
- for (i = 0; i < num_coords; i++) {
- tc_ADD(tc, tmp[i], coords[i], offsets[i]);
- coords[i] = tsrc_from(tmp[i]);
- }
- }
-
- sampler_src = 1;
- break;
- case TOY_OPCODE_TGSI_TXQ:
- msg_type = GEN6_MSG_SAMPLER_RESINFO;
- num_coords = 0;
- bias_or_lod = coords[0];
- break;
- case TOY_OPCODE_TGSI_TXQ_LZ:
- msg_type = GEN6_MSG_SAMPLER_RESINFO;
- num_coords = 0;
- sampler_src = 0;
- break;
- case TOY_OPCODE_TGSI_TEX2:
- if (ref_pos >= 0) {
- assert(ref_pos < 5);
-
- msg_type = GEN6_MSG_SAMPLER_SAMPLE_C;
-
- if (ref_pos >= 4) {
- struct toy_src src1[4];
- tsrc_transpose(inst->src[1], src1);
- ref_or_si = src1[ref_pos - 4];
- }
- else {
- ref_or_si = coords[ref_pos];
- }
- }
- else {
- msg_type = GEN6_MSG_SAMPLER_SAMPLE;
- }
-
- sampler_src = 2;
- break;
- case TOY_OPCODE_TGSI_TXB2:
- if (ref_pos >= 0) {
- assert(ref_pos < 4);
-
- msg_type = GEN6_MSG_SAMPLER_SAMPLE_B_C;
- ref_or_si = coords[ref_pos];
- }
- else {
- msg_type = GEN6_MSG_SAMPLER_SAMPLE_B;
- }
-
- {
- struct toy_src src1[4];
- tsrc_transpose(inst->src[1], src1);
- bias_or_lod = src1[0];
- }
-
- sampler_src = 2;
- break;
- case TOY_OPCODE_TGSI_TXL2:
- if (ref_pos >= 0) {
- assert(ref_pos < 4);
-
- msg_type = GEN6_MSG_SAMPLER_SAMPLE_L_C;
- ref_or_si = coords[ref_pos];
- }
- else {
- msg_type = GEN6_MSG_SAMPLER_SAMPLE_L;
- }
-
- {
- struct toy_src src1[4];
- tsrc_transpose(inst->src[1], src1);
- bias_or_lod = src1[0];
- }
-
- sampler_src = 2;
- break;
- default:
- assert(!"unhandled sampling opcode");
- return tsrc_null();
- break;
- }
-
- assert(inst->src[sampler_src].file == TOY_FILE_IMM);
- sampler_index = inst->src[sampler_src].val32;
- binding_table_index = fcc->shader->bt.tex_base + sampler_index;
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 18:
- *
- * "Note that the (cube map) coordinates delivered to the sampling
- * engine must already have been divided by the component with the
- * largest absolute value."
- */
- switch (inst->tex.target) {
- case TGSI_TEXTURE_CUBE:
- case TGSI_TEXTURE_SHADOWCUBE:
- case TGSI_TEXTURE_CUBE_ARRAY:
- case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
- /* TXQ does not need coordinates */
- if (num_coords >= 3) {
- struct toy_dst tmp[4];
-
- tc_alloc_tmp4(tc, tmp);
-
- tc_SEL(tc, tmp[3], tsrc_absolute(coords[0]),
- tsrc_absolute(coords[1]), GEN6_COND_GE);
- tc_SEL(tc, tmp[3], tsrc_from(tmp[3]),
- tsrc_absolute(coords[2]), GEN6_COND_GE);
- tc_INV(tc, tmp[3], tsrc_from(tmp[3]));
-
- for (i = 0; i < 3; i++) {
- tc_MUL(tc, tmp[i], coords[i], tsrc_from(tmp[3]));
- coords[i] = tsrc_from(tmp[i]);
- }
- }
- break;
- }
-
- /*
- * Saturate (s, t, r). saturate_coords is set for sampler and coordinate
- * that uses linear filtering and PIPE_TEX_WRAP_CLAMP respectively. It is
- * so that sampling outside the border gets the correct colors.
- */
- for (i = 0; i < MIN2(num_coords, 3); i++) {
- bool is_rect;
-
- if (!(saturate_coords[i] & (1 << sampler_index)))
- continue;
-
- switch (inst->tex.target) {
- case TGSI_TEXTURE_RECT:
- case TGSI_TEXTURE_SHADOWRECT:
- is_rect = true;
- break;
- default:
- is_rect = false;
- break;
- }
-
- if (is_rect) {
- struct toy_src min, max;
- struct toy_dst tmp;
-
- tc_fail(tc, "GL_CLAMP with rectangle texture unsupported");
- tmp = tc_alloc_tmp(tc);
-
- /* saturate to [0, width] or [0, height] */
- /* TODO TXQ? */
- min = tsrc_imm_f(0.0f);
- max = tsrc_imm_f(2048.0f);
-
- tc_SEL(tc, tmp, coords[i], min, GEN6_COND_G);
- tc_SEL(tc, tmp, tsrc_from(tmp), max, GEN6_COND_L);
-
- coords[i] = tsrc_from(tmp);
- }
- else {
- struct toy_dst tmp;
- struct toy_inst *inst2;
-
- tmp = tc_alloc_tmp(tc);
-
- /* saturate to [0.0f, 1.0f] */
- inst2 = tc_MOV(tc, tmp, coords[i]);
- inst2->saturate = true;
-
- coords[i] = tsrc_from(tmp);
- }
- }
-
- /* set up sampler parameters */
- if (ilo_dev_gen(tc->dev) >= ILO_GEN(7)) {
- msg_len = fs_add_sampler_params_gen7(tc, msg_type, base_mrf, param_size,
- coords, num_coords, bias_or_lod, ref_or_si, ddx, ddy, num_derivs);
- }
- else {
- msg_len = fs_add_sampler_params_gen6(tc, msg_type, base_mrf, param_size,
- coords, num_coords, bias_or_lod, ref_or_si, ddx, ddy, num_derivs);
- }
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 136:
- *
- * "The maximum message length allowed to the sampler is 11. This would
- * disallow sample_d, sample_b_c, and sample_l_c with a SIMD Mode of
- * SIMD16."
- */
- if (msg_len > 11)
- tc_fail(tc, "maximum length for messages to the sampler is 11");
-
- if (ret_sampler_index)
- *ret_sampler_index = sampler_index;
-
- return tsrc_imm_mdesc_sampler(tc, msg_len, 4 * param_size,
- false, simd_mode, msg_type, sampler_index, binding_table_index);
-}
-
-static void
-fs_lower_opcode_tgsi_sampling(struct fs_compile_context *fcc,
- struct toy_inst *inst)
-{
- struct toy_compiler *tc = &fcc->tc;
- struct toy_dst dst[4], tmp[4];
- struct toy_src desc;
- unsigned sampler_index;
- int swizzles[4], i;
- bool need_filter;
-
- desc = fs_prepare_tgsi_sampling(fcc, inst,
- fcc->first_free_mrf,
- fcc->variant->saturate_tex_coords,
- &sampler_index);
-
- switch (inst->opcode) {
- case TOY_OPCODE_TGSI_TXF:
- case TOY_OPCODE_TGSI_TXQ:
- case TOY_OPCODE_TGSI_TXQ_LZ:
- need_filter = false;
- break;
- default:
- need_filter = true;
- break;
- }
-
- toy_compiler_lower_to_send(tc, inst, false, GEN6_SFID_SAMPLER);
- inst->src[0] = tsrc(TOY_FILE_MRF, fcc->first_free_mrf, 0);
- inst->src[1] = desc;
- for (i = 2; i < ARRAY_SIZE(inst->src); i++)
- inst->src[i] = tsrc_null();
-
- /* write to temps first */
- tc_alloc_tmp4(tc, tmp);
- for (i = 0; i < 4; i++)
- tmp[i].type = inst->dst.type;
- tdst_transpose(inst->dst, dst);
- inst->dst = tmp[0];
-
- tc_move_inst(tc, inst);
-
- if (need_filter) {
- assert(sampler_index < fcc->variant->num_sampler_views);
- swizzles[0] = fcc->variant->sampler_view_swizzles[sampler_index].r;
- swizzles[1] = fcc->variant->sampler_view_swizzles[sampler_index].g;
- swizzles[2] = fcc->variant->sampler_view_swizzles[sampler_index].b;
- swizzles[3] = fcc->variant->sampler_view_swizzles[sampler_index].a;
- }
- else {
- swizzles[0] = PIPE_SWIZZLE_X;
- swizzles[1] = PIPE_SWIZZLE_Y;
- swizzles[2] = PIPE_SWIZZLE_Z;
- swizzles[3] = PIPE_SWIZZLE_W;
- }
-
- /* swizzle the results */
- for (i = 0; i < 4; i++) {
- switch (swizzles[i]) {
- case PIPE_SWIZZLE_0:
- tc_MOV(tc, dst[i], tsrc_imm_f(0.0f));
- break;
- case PIPE_SWIZZLE_1:
- tc_MOV(tc, dst[i], tsrc_imm_f(1.0f));
- break;
- default:
- tc_MOV(tc, dst[i], tsrc_from(tmp[swizzles[i]]));
- break;
- }
- }
-}
-
-static void
-fs_lower_opcode_derivative(struct toy_compiler *tc, struct toy_inst *inst)
-{
- struct toy_dst dst[4];
- struct toy_src src[4];
- unsigned i;
-
- tdst_transpose(inst->dst, dst);
- tsrc_transpose(inst->src[0], src);
-
- /*
- * Every four fragments are from a 2x2 subspan, with
- *
- * fragment 1 on the top-left,
- * fragment 2 on the top-right,
- * fragment 3 on the bottom-left,
- * fragment 4 on the bottom-right.
- *
- * DDX should thus produce
- *
- * dst = src.yyww - src.xxzz
- *
- * and DDY should produce
- *
- * dst = src.zzww - src.xxyy
- *
- * But since we are in GEN6_ALIGN_1, swizzling does not work and we have to
- * play with the region parameters.
- */
- if (inst->opcode == TOY_OPCODE_DDX) {
- for (i = 0; i < 4; i++) {
- struct toy_src left, right;
-
- left = tsrc_rect(src[i], TOY_RECT_220);
- right = tsrc_offset(left, 0, 1);
-
- tc_ADD(tc, dst[i], right, tsrc_negate(left));
- }
- }
- else {
- for (i = 0; i < 4; i++) {
- struct toy_src top, bottom;
-
- /* approximate with dst = src.zzzz - src.xxxx */
- top = tsrc_rect(src[i], TOY_RECT_440);
- bottom = tsrc_offset(top, 0, 2);
-
- tc_ADD(tc, dst[i], bottom, tsrc_negate(top));
- }
- }
-
- tc_discard_inst(tc, inst);
-}
-
-static void
-fs_lower_opcode_fb_write(struct toy_compiler *tc, struct toy_inst *inst)
-{
- /* fs_write_fb() has set up the message registers */
- toy_compiler_lower_to_send(tc, inst, true,
- GEN6_SFID_DP_RC);
-}
-
-static void
-fs_lower_opcode_kil(struct toy_compiler *tc, struct toy_inst *inst)
-{
- struct toy_dst pixel_mask_dst;
- struct toy_src f0, pixel_mask;
- struct toy_inst *tmp;
-
- /* lower half of r1.7:ud */
- pixel_mask_dst = tdst_uw(tdst(TOY_FILE_GRF, 1, 7 * 4));
- pixel_mask = tsrc_rect(tsrc_from(pixel_mask_dst), TOY_RECT_010);
-
- f0 = tsrc_rect(tsrc_uw(tsrc(TOY_FILE_ARF, GEN6_ARF_F0, 0)), TOY_RECT_010);
-
- /* KILL or KILL_IF */
- if (tsrc_is_null(inst->src[0])) {
- struct toy_src dummy = tsrc_uw(tsrc(TOY_FILE_GRF, 0, 0));
- struct toy_dst f0_dst = tdst_uw(tdst(TOY_FILE_ARF, GEN6_ARF_F0, 0));
-
- /* create a mask that masks out all pixels */
- tmp = tc_MOV(tc, f0_dst, tsrc_rect(tsrc_imm_uw(0xffff), TOY_RECT_010));
- tmp->exec_size = GEN6_EXECSIZE_1;
- tmp->mask_ctrl = GEN6_MASKCTRL_NOMASK;
-
- tc_CMP(tc, tdst_null(), dummy, dummy, GEN6_COND_NZ);
-
- /* swapping the two src operands breaks glBitmap()!? */
- tmp = tc_AND(tc, pixel_mask_dst, f0, pixel_mask);
- tmp->exec_size = GEN6_EXECSIZE_1;
- tmp->mask_ctrl = GEN6_MASKCTRL_NOMASK;
- }
- else {
- struct toy_src src[4];
- unsigned i;
-
- tsrc_transpose(inst->src[0], src);
- /* mask out killed pixels */
- for (i = 0; i < 4; i++) {
- tc_CMP(tc, tdst_null(), src[i], tsrc_imm_f(0.0f),
- GEN6_COND_GE);
-
- /* swapping the two src operands breaks glBitmap()!? */
- tmp = tc_AND(tc, pixel_mask_dst, f0, pixel_mask);
- tmp->exec_size = GEN6_EXECSIZE_1;
- tmp->mask_ctrl = GEN6_MASKCTRL_NOMASK;
- }
- }
-
- tc_discard_inst(tc, inst);
-}
-
-static void
-fs_lower_virtual_opcodes(struct fs_compile_context *fcc)
-{
- struct toy_compiler *tc = &fcc->tc;
- struct toy_inst *inst;
-
- /* lower TGSI's first, as they might be lowered to other virtual opcodes */
- tc_head(tc);
- while ((inst = tc_next(tc)) != NULL) {
- switch (inst->opcode) {
- case TOY_OPCODE_TGSI_IN:
- case TOY_OPCODE_TGSI_CONST:
- case TOY_OPCODE_TGSI_SV:
- case TOY_OPCODE_TGSI_IMM:
- fs_lower_opcode_tgsi_direct(fcc, inst);
- break;
- case TOY_OPCODE_TGSI_INDIRECT_FETCH:
- case TOY_OPCODE_TGSI_INDIRECT_STORE:
- fs_lower_opcode_tgsi_indirect(fcc, inst);
- break;
- case TOY_OPCODE_TGSI_TEX:
- case TOY_OPCODE_TGSI_TXB:
- case TOY_OPCODE_TGSI_TXD:
- case TOY_OPCODE_TGSI_TXL:
- case TOY_OPCODE_TGSI_TXP:
- case TOY_OPCODE_TGSI_TXF:
- case TOY_OPCODE_TGSI_TXQ:
- case TOY_OPCODE_TGSI_TXQ_LZ:
- case TOY_OPCODE_TGSI_TEX2:
- case TOY_OPCODE_TGSI_TXB2:
- case TOY_OPCODE_TGSI_TXL2:
- case TOY_OPCODE_TGSI_SAMPLE:
- case TOY_OPCODE_TGSI_SAMPLE_I:
- case TOY_OPCODE_TGSI_SAMPLE_I_MS:
- case TOY_OPCODE_TGSI_SAMPLE_B:
- case TOY_OPCODE_TGSI_SAMPLE_C:
- case TOY_OPCODE_TGSI_SAMPLE_C_LZ:
- case TOY_OPCODE_TGSI_SAMPLE_D:
- case TOY_OPCODE_TGSI_SAMPLE_L:
- case TOY_OPCODE_TGSI_GATHER4:
- case TOY_OPCODE_TGSI_SVIEWINFO:
- case TOY_OPCODE_TGSI_SAMPLE_POS:
- case TOY_OPCODE_TGSI_SAMPLE_INFO:
- fs_lower_opcode_tgsi_sampling(fcc, inst);
- break;
- }
- }
-
- tc_head(tc);
- while ((inst = tc_next(tc)) != NULL) {
- switch (inst->opcode) {
- case TOY_OPCODE_INV:
- case TOY_OPCODE_LOG:
- case TOY_OPCODE_EXP:
- case TOY_OPCODE_SQRT:
- case TOY_OPCODE_RSQ:
- case TOY_OPCODE_SIN:
- case TOY_OPCODE_COS:
- case TOY_OPCODE_FDIV:
- case TOY_OPCODE_POW:
- case TOY_OPCODE_INT_DIV_QUOTIENT:
- case TOY_OPCODE_INT_DIV_REMAINDER:
- toy_compiler_lower_math(tc, inst);
- break;
- case TOY_OPCODE_DDX:
- case TOY_OPCODE_DDY:
- fs_lower_opcode_derivative(tc, inst);
- break;
- case TOY_OPCODE_FB_WRITE:
- fs_lower_opcode_fb_write(tc, inst);
- break;
- case TOY_OPCODE_KIL:
- fs_lower_opcode_kil(tc, inst);
- break;
- default:
- if (inst->opcode > 127)
- tc_fail(tc, "unhandled virtual opcode");
- break;
- }
- }
-}
-
-/**
- * Compile the shader.
- */
-static bool
-fs_compile(struct fs_compile_context *fcc)
-{
- struct toy_compiler *tc = &fcc->tc;
- struct ilo_shader *sh = fcc->shader;
-
- fs_lower_virtual_opcodes(fcc);
- toy_compiler_legalize_for_ra(tc);
- toy_compiler_optimize(tc);
- toy_compiler_allocate_registers(tc,
- fcc->first_free_grf,
- fcc->last_free_grf,
- fcc->num_grf_per_vrf);
- toy_compiler_legalize_for_asm(tc);
-
- if (tc->fail) {
- ilo_err("failed to legalize FS instructions: %s\n", tc->reason);
- return false;
- }
-
- if (ilo_debug & ILO_DEBUG_FS) {
- ilo_printf("legalized instructions:\n");
- toy_compiler_dump(tc);
- ilo_printf("\n");
- }
-
- if (true) {
- sh->kernel = toy_compiler_assemble(tc, &sh->kernel_size);
- }
- else {
- static const uint32_t microcode[] = {
- /* fill in the microcode here */
- 0x0, 0x0, 0x0, 0x0,
- };
- const bool swap = true;
-
- sh->kernel_size = sizeof(microcode);
- sh->kernel = MALLOC(sh->kernel_size);
-
- if (sh->kernel) {
- const int num_dwords = sizeof(microcode) / 4;
- const uint32_t *src = microcode;
- uint32_t *dst = (uint32_t *) sh->kernel;
- int i;
-
- for (i = 0; i < num_dwords; i += 4) {
- if (swap) {
- dst[i + 0] = src[i + 3];
- dst[i + 1] = src[i + 2];
- dst[i + 2] = src[i + 1];
- dst[i + 3] = src[i + 0];
- }
- else {
- memcpy(dst, src, 16);
- }
- }
- }
- }
-
- if (!sh->kernel) {
- ilo_err("failed to compile FS: %s\n", tc->reason);
- return false;
- }
-
- if (ilo_debug & ILO_DEBUG_FS) {
- ilo_printf("disassembly:\n");
- toy_compiler_disassemble(tc->dev, sh->kernel, sh->kernel_size, false);
- ilo_printf("\n");
- }
-
- return true;
-}
-
-/**
- * Emit instructions to write the color buffers (and the depth buffer).
- */
-static void
-fs_write_fb(struct fs_compile_context *fcc)
-{
- struct toy_compiler *tc = &fcc->tc;
- int base_mrf = fcc->first_free_mrf;
- const struct toy_dst header = tdst_ud(tdst(TOY_FILE_MRF, base_mrf, 0));
- bool header_present = false;
- struct toy_src desc;
- unsigned msg_type, ctrl;
- int color_slots[ILO_MAX_DRAW_BUFFERS], num_cbufs;
- int pos_slot = -1, cbuf, i;
-
- for (i = 0; i < ARRAY_SIZE(color_slots); i++)
- color_slots[i] = -1;
-
- for (i = 0; i < fcc->tgsi.num_outputs; i++) {
- if (fcc->tgsi.outputs[i].semantic_name == TGSI_SEMANTIC_COLOR) {
- assert(fcc->tgsi.outputs[i].semantic_index < ARRAY_SIZE(color_slots));
- color_slots[fcc->tgsi.outputs[i].semantic_index] = i;
- }
- else if (fcc->tgsi.outputs[i].semantic_name == TGSI_SEMANTIC_POSITION) {
- pos_slot = i;
- }
- }
-
- num_cbufs = fcc->variant->u.fs.num_cbufs;
- /* still need to send EOT (and probably depth) */
- if (!num_cbufs)
- num_cbufs = 1;
-
- /* we need the header to specify the pixel mask or render target */
- if (fcc->tgsi.uses_kill || num_cbufs > 1) {
- const struct toy_src r0 = tsrc_ud(tsrc(TOY_FILE_GRF, 0, 0));
- struct toy_inst *inst;
-
- inst = tc_MOV(tc, header, r0);
- inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
- base_mrf += fcc->num_grf_per_vrf;
-
- /* this is a two-register header */
- if (fcc->dispatch_mode == GEN6_PS_DISPATCH_8) {
- inst = tc_MOV(tc, tdst_offset(header, 1, 0), tsrc_offset(r0, 1, 0));
- inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
- base_mrf += fcc->num_grf_per_vrf;
- }
-
- header_present = true;
- }
-
- for (cbuf = 0; cbuf < num_cbufs; cbuf++) {
- const int slot =
- color_slots[(fcc->tgsi.props.fs_color0_writes_all_cbufs) ? 0 : cbuf];
- int mrf = base_mrf, vrf;
- struct toy_src src[4];
-
- if (slot >= 0) {
- const unsigned undefined_mask =
- fcc->tgsi.outputs[slot].undefined_mask;
- const int index = fcc->tgsi.outputs[slot].index;
-
- vrf = toy_tgsi_get_vrf(&fcc->tgsi, TGSI_FILE_OUTPUT, 0, index);
- if (vrf >= 0) {
- const struct toy_src tmp = tsrc(TOY_FILE_VRF, vrf, 0);
- tsrc_transpose(tmp, src);
- }
- else {
- /* use (0, 0, 0, 0) */
- tsrc_transpose(tsrc_imm_f(0.0f), src);
- }
-
- for (i = 0; i < 4; i++) {
- const struct toy_dst dst = tdst(TOY_FILE_MRF, mrf, 0);
-
- if (undefined_mask & (1 << i))
- src[i] = tsrc_imm_f(0.0f);
-
- tc_MOV(tc, dst, src[i]);
-
- mrf += fcc->num_grf_per_vrf;
- }
- }
- else {
- /* use (0, 0, 0, 0) */
- for (i = 0; i < 4; i++) {
- const struct toy_dst dst = tdst(TOY_FILE_MRF, mrf, 0);
-
- tc_MOV(tc, dst, tsrc_imm_f(0.0f));
- mrf += fcc->num_grf_per_vrf;
- }
- }
-
- /* select BLEND_STATE[rt] */
- if (cbuf > 0) {
- struct toy_inst *inst;
-
- inst = tc_MOV(tc, tdst_offset(header, 0, 2), tsrc_imm_ud(cbuf));
- inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
- inst->exec_size = GEN6_EXECSIZE_1;
- inst->src[0].rect = TOY_RECT_010;
- }
-
- if (cbuf == 0 && pos_slot >= 0) {
- const int index = fcc->tgsi.outputs[pos_slot].index;
- const struct toy_dst dst = tdst(TOY_FILE_MRF, mrf, 0);
- struct toy_src src[4];
- int vrf;
-
- vrf = toy_tgsi_get_vrf(&fcc->tgsi, TGSI_FILE_OUTPUT, 0, index);
- if (vrf >= 0) {
- const struct toy_src tmp = tsrc(TOY_FILE_VRF, vrf, 0);
- tsrc_transpose(tmp, src);
- }
- else {
- /* use (0, 0, 0, 0) */
- tsrc_transpose(tsrc_imm_f(0.0f), src);
- }
-
- /* only Z */
- tc_MOV(tc, dst, src[2]);
-
- mrf += fcc->num_grf_per_vrf;
- }
-
- msg_type = (fcc->dispatch_mode == GEN6_PS_DISPATCH_16) ?
- GEN6_MSG_DP_RT_MODE_SIMD16 >> 8 :
- GEN6_MSG_DP_RT_MODE_SIMD8_LO >> 8;
-
- ctrl = (cbuf == num_cbufs - 1) << 12 |
- msg_type << 8;
-
- desc = tsrc_imm_mdesc_data_port(tc, cbuf == num_cbufs - 1,
- mrf - fcc->first_free_mrf, 0,
- header_present, false,
- GEN6_MSG_DP_RT_WRITE,
- ctrl, fcc->shader->bt.rt_base + cbuf);
-
- tc_add2(tc, TOY_OPCODE_FB_WRITE, tdst_null(),
- tsrc(TOY_FILE_MRF, fcc->first_free_mrf, 0), desc);
- }
-}
-
-/**
- * Set up shader outputs for fixed-function units.
- */
-static void
-fs_setup_shader_out(struct ilo_shader *sh, const struct toy_tgsi *tgsi)
-{
- unsigned i;
-
- sh->out.count = tgsi->num_outputs;
- for (i = 0; i < tgsi->num_outputs; i++) {
- sh->out.register_indices[i] = tgsi->outputs[i].index;
- sh->out.semantic_names[i] = tgsi->outputs[i].semantic_name;
- sh->out.semantic_indices[i] = tgsi->outputs[i].semantic_index;
-
- if (tgsi->outputs[i].semantic_name == TGSI_SEMANTIC_POSITION)
- sh->out.has_pos = true;
- }
-}
-
-/**
- * Set up shader inputs for fixed-function units.
- */
-static void
-fs_setup_shader_in(struct ilo_shader *sh, const struct toy_tgsi *tgsi,
- bool flatshade)
-{
- unsigned i;
-
- sh->in.count = tgsi->num_inputs;
- for (i = 0; i < tgsi->num_inputs; i++) {
- sh->in.semantic_names[i] = tgsi->inputs[i].semantic_name;
- sh->in.semantic_indices[i] = tgsi->inputs[i].semantic_index;
- sh->in.interp[i] = tgsi->inputs[i].interp;
- sh->in.centroid[i] = tgsi->inputs[i].centroid;
-
- if (tgsi->inputs[i].semantic_name == TGSI_SEMANTIC_POSITION) {
- sh->in.has_pos = true;
- continue;
- }
- else if (tgsi->inputs[i].semantic_name == TGSI_SEMANTIC_FACE) {
- continue;
- }
-
- switch (tgsi->inputs[i].interp) {
- case TGSI_INTERPOLATE_CONSTANT:
- sh->in.const_interp_enable |= 1 << i;
- break;
- case TGSI_INTERPOLATE_LINEAR:
- sh->in.has_linear_interp = true;
-
- if (tgsi->inputs[i].centroid) {
- sh->in.barycentric_interpolation_mode |=
- GEN6_INTERP_NONPERSPECTIVE_CENTROID;
- }
- else {
- sh->in.barycentric_interpolation_mode |=
- GEN6_INTERP_NONPERSPECTIVE_PIXEL;
- }
- break;
- case TGSI_INTERPOLATE_COLOR:
- if (flatshade) {
- sh->in.const_interp_enable |= 1 << i;
- break;
- }
- /* fall through */
- case TGSI_INTERPOLATE_PERSPECTIVE:
- if (tgsi->inputs[i].centroid) {
- sh->in.barycentric_interpolation_mode |=
- GEN6_INTERP_PERSPECTIVE_CENTROID;
- }
- else {
- sh->in.barycentric_interpolation_mode |=
- GEN6_INTERP_PERSPECTIVE_PIXEL;
- }
- break;
- default:
- break;
- }
- }
-}
-
-static int
-fs_setup_payloads(struct fs_compile_context *fcc)
-{
- const struct ilo_shader *sh = fcc->shader;
- int grf, i;
-
- grf = 0;
-
- /* r0: header */
- grf++;
-
- /* r1-r2: coordinates and etc. */
- grf += (fcc->dispatch_mode == GEN6_PS_DISPATCH_32) ? 2 : 1;
-
- for (i = 0; i < ARRAY_SIZE(fcc->payloads); i++) {
- const int reg_scale =
- (fcc->dispatch_mode == GEN6_PS_DISPATCH_8) ? 1 : 2;
-
- /* r3-r26 or r32-r55: barycentric interpolation parameters */
- if (sh->in.barycentric_interpolation_mode &
- (GEN6_INTERP_PERSPECTIVE_PIXEL)) {
- fcc->payloads[i].interp_perspective_pixel = grf;
- grf += 2 * reg_scale;
- }
- if (sh->in.barycentric_interpolation_mode &
- (GEN6_INTERP_PERSPECTIVE_CENTROID)) {
- fcc->payloads[i].interp_perspective_centroid = grf;
- grf += 2 * reg_scale;
- }
- if (sh->in.barycentric_interpolation_mode &
- (GEN6_INTERP_PERSPECTIVE_SAMPLE)) {
- fcc->payloads[i].interp_perspective_sample = grf;
- grf += 2 * reg_scale;
- }
- if (sh->in.barycentric_interpolation_mode &
- (GEN6_INTERP_NONPERSPECTIVE_PIXEL)) {
- fcc->payloads[i].interp_nonperspective_pixel = grf;
- grf += 2 * reg_scale;
- }
- if (sh->in.barycentric_interpolation_mode &
- (GEN6_INTERP_NONPERSPECTIVE_CENTROID)) {
- fcc->payloads[i].interp_nonperspective_centroid = grf;
- grf += 2 * reg_scale;
- }
- if (sh->in.barycentric_interpolation_mode &
- (GEN6_INTERP_NONPERSPECTIVE_SAMPLE)) {
- fcc->payloads[i].interp_nonperspective_sample = grf;
- grf += 2 * reg_scale;
- }
-
- /* r27-r28 or r56-r57: interpoloated depth */
- if (sh->in.has_pos) {
- fcc->payloads[i].source_depth = grf;
- grf += 1 * reg_scale;
- }
-
- /* r29-r30 or r58-r59: interpoloated w */
- if (sh->in.has_pos) {
- fcc->payloads[i].source_w = grf;
- grf += 1 * reg_scale;
- }
-
- /* r31 or r60: position offset */
- if (false) {
- fcc->payloads[i].pos_offset = grf;
- grf++;
- }
-
- if (fcc->dispatch_mode != GEN6_PS_DISPATCH_32)
- break;
- }
-
- return grf;
-}
-
-/**
- * Translate the TGSI tokens.
- */
-static bool
-fs_setup_tgsi(struct toy_compiler *tc, const struct tgsi_token *tokens,
- struct toy_tgsi *tgsi)
-{
- if (ilo_debug & ILO_DEBUG_FS) {
- ilo_printf("dumping fragment shader\n");
- ilo_printf("\n");
-
- tgsi_dump(tokens, 0);
- ilo_printf("\n");
- }
-
- toy_compiler_translate_tgsi(tc, tokens, false, tgsi);
- if (tc->fail) {
- ilo_err("failed to translate FS TGSI tokens: %s\n", tc->reason);
- return false;
- }
-
- if (ilo_debug & ILO_DEBUG_FS) {
- ilo_printf("TGSI translator:\n");
- toy_tgsi_dump(tgsi);
- ilo_printf("\n");
- toy_compiler_dump(tc);
- ilo_printf("\n");
- }
-
- return true;
-}
-
-/**
- * Set up FS compile context. This includes translating the TGSI tokens.
- */
-static bool
-fs_setup(struct fs_compile_context *fcc,
- const struct ilo_shader_state *state,
- const struct ilo_shader_variant *variant)
-{
- int num_consts;
-
- memset(fcc, 0, sizeof(*fcc));
-
- fcc->shader = CALLOC_STRUCT(ilo_shader);
- if (!fcc->shader)
- return false;
-
- fcc->variant = variant;
-
- toy_compiler_init(&fcc->tc, state->info.dev);
-
- fcc->dispatch_mode = GEN6_PS_DISPATCH_8;
-
- fcc->tc.templ.access_mode = GEN6_ALIGN_1;
- if (fcc->dispatch_mode == GEN6_PS_DISPATCH_16) {
- fcc->tc.templ.qtr_ctrl = GEN6_QTRCTRL_1H;
- fcc->tc.templ.exec_size = GEN6_EXECSIZE_16;
- }
- else {
- fcc->tc.templ.qtr_ctrl = GEN6_QTRCTRL_1Q;
- fcc->tc.templ.exec_size = GEN6_EXECSIZE_8;
- }
-
- fcc->tc.rect_linear_width = 8;
-
- /*
- * The classic driver uses the sampler cache (gen6) or the data cache
- * (gen7). Why?
- */
- fcc->const_cache = GEN6_SFID_DP_CC;
-
- if (!fs_setup_tgsi(&fcc->tc, state->info.tokens, &fcc->tgsi)) {
- toy_compiler_cleanup(&fcc->tc);
- FREE(fcc->shader);
- return false;
- }
-
- fs_setup_shader_in(fcc->shader, &fcc->tgsi, fcc->variant->u.fs.flatshade);
- fs_setup_shader_out(fcc->shader, &fcc->tgsi);
-
- if (fcc->variant->use_pcb && !fcc->tgsi.const_indirect) {
- num_consts = (fcc->tgsi.const_count + 1) / 2;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 287:
- *
- * "The sum of all four read length fields (each incremented to
- * represent the actual read length) must be less than or equal to
- * 64"
- *
- * Since we are usually under a high register pressure, do not allow
- * for more than 8.
- */
- if (num_consts > 8)
- num_consts = 0;
- }
- else {
- num_consts = 0;
- }
-
- fcc->shader->skip_cbuf0_upload = (!fcc->tgsi.const_count || num_consts);
- fcc->shader->pcb.cbuf0_size = num_consts * (sizeof(float) * 8);
-
- fcc->first_const_grf = fs_setup_payloads(fcc);
- fcc->first_attr_grf = fcc->first_const_grf + num_consts;
- fcc->first_free_grf = fcc->first_attr_grf + fcc->shader->in.count * 2;
- fcc->last_free_grf = 127;
-
- /* m0 is reserved for system routines */
- fcc->first_free_mrf = 1;
- fcc->last_free_mrf = 15;
-
- /* instructions are compressed with GEN6_EXECSIZE_16 */
- fcc->num_grf_per_vrf =
- (fcc->dispatch_mode == GEN6_PS_DISPATCH_16) ? 2 : 1;
-
- if (ilo_dev_gen(fcc->tc.dev) >= ILO_GEN(7)) {
- fcc->last_free_grf -= 15;
- fcc->first_free_mrf = fcc->last_free_grf + 1;
- fcc->last_free_mrf = fcc->first_free_mrf + 14;
- }
-
- fcc->shader->in.start_grf = fcc->first_const_grf;
- fcc->shader->has_kill = fcc->tgsi.uses_kill;
- fcc->shader->dispatch_16 =
- (fcc->dispatch_mode == GEN6_PS_DISPATCH_16);
-
- fcc->shader->bt.rt_base = 0;
- fcc->shader->bt.rt_count = fcc->variant->u.fs.num_cbufs;
- /* to send EOT */
- if (!fcc->shader->bt.rt_count)
- fcc->shader->bt.rt_count = 1;
-
- fcc->shader->bt.tex_base = fcc->shader->bt.rt_base +
- fcc->shader->bt.rt_count;
- fcc->shader->bt.tex_count = fcc->variant->num_sampler_views;
-
- fcc->shader->bt.const_base = fcc->shader->bt.tex_base +
- fcc->shader->bt.tex_count;
- fcc->shader->bt.const_count = state->info.constant_buffer_count;
-
- fcc->shader->bt.total_count = fcc->shader->bt.const_base +
- fcc->shader->bt.const_count;
-
- return true;
-}
-
-/**
- * Compile the fragment shader.
- */
-struct ilo_shader *
-ilo_shader_compile_fs(const struct ilo_shader_state *state,
- const struct ilo_shader_variant *variant)
-{
- struct fs_compile_context fcc;
-
- if (!fs_setup(&fcc, state, variant))
- return NULL;
-
- fs_write_fb(&fcc);
-
- if (!fs_compile(&fcc)) {
- FREE(fcc.shader);
- fcc.shader = NULL;
- }
-
- toy_tgsi_cleanup(&fcc.tgsi);
- toy_compiler_cleanup(&fcc.tc);
-
- return fcc.shader;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "tgsi/tgsi_dump.h"
-#include "toy_compiler.h"
-#include "toy_tgsi.h"
-#include "toy_legalize.h"
-#include "toy_optimize.h"
-#include "toy_helpers.h"
-#include "ilo_shader_internal.h"
-
-/* XXX Below is proof-of-concept code. Skip this file! */
-
-/*
- * TODO
- * - primitive id is in r0.1. FS receives PID as a flat attribute.
- * - set VUE header m0.1 for layered rendering
- */
-struct gs_compile_context {
- struct ilo_shader *shader;
- const struct ilo_shader_variant *variant;
- const struct pipe_stream_output_info *so_info;
-
- struct toy_compiler tc;
- struct toy_tgsi tgsi;
- int output_map[PIPE_MAX_SHADER_OUTPUTS];
-
- bool write_so;
- bool write_vue;
-
- int in_vue_size;
- int in_vue_count;
-
- int out_vue_size;
- int out_vue_min_count;
-
- bool is_static;
-
- struct {
- struct toy_src header;
- struct toy_src svbi;
- struct toy_src vues[6];
- } payload;
-
- struct {
- struct toy_dst urb_write_header;
- bool prim_start;
- bool prim_end;
- int prim_type;
-
- struct toy_dst tmp;
-
- /* buffered tgsi_outs */
- struct toy_dst buffers[3];
- int buffer_needed, buffer_cur;
-
- struct toy_dst so_written;
- struct toy_dst so_index;
-
- struct toy_src tgsi_outs[PIPE_MAX_SHADER_OUTPUTS];
- } vars;
-
- struct {
- struct toy_dst total_vertices;
- struct toy_dst total_prims;
-
- struct toy_dst num_vertices;
- struct toy_dst num_vertices_in_prim;
- } dynamic_data;
-
- struct {
- int total_vertices;
- int total_prims;
- /* this limits the max vertice count to be 256 */
- uint32_t last_vertex[8];
-
- int num_vertices;
- int num_vertices_in_prim;
- } static_data;
-
- int first_free_grf;
- int last_free_grf;
- int first_free_mrf;
- int last_free_mrf;
-};
-
-static void
-gs_COPY8(struct toy_compiler *tc, struct toy_dst dst, struct toy_src src)
-{
- struct toy_inst *inst;
-
- inst = tc_MOV(tc, dst, src);
- inst->exec_size = GEN6_EXECSIZE_8;
- inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
-}
-
-static void
-gs_COPY4(struct toy_compiler *tc,
- struct toy_dst dst, int dst_ch,
- struct toy_src src, int src_ch)
-{
- struct toy_inst *inst;
-
- inst = tc_MOV(tc,
- tdst_offset(dst, 0, dst_ch),
- tsrc_offset(src, 0, src_ch));
- inst->exec_size = GEN6_EXECSIZE_4;
- inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
-}
-
-static void
-gs_COPY1(struct toy_compiler *tc,
- struct toy_dst dst, int dst_ch,
- struct toy_src src, int src_ch)
-{
- struct toy_inst *inst;
-
- inst = tc_MOV(tc,
- tdst_offset(dst, 0, dst_ch),
- tsrc_rect(tsrc_offset(src, 0, src_ch), TOY_RECT_010));
- inst->exec_size = GEN6_EXECSIZE_1;
- inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
-}
-
-static void
-gs_init_vars(struct gs_compile_context *gcc)
-{
- struct toy_compiler *tc = &gcc->tc;
- struct toy_dst dst;
-
- /* init URB_WRITE header */
- dst = gcc->vars.urb_write_header;
-
- gs_COPY8(tc, dst, gcc->payload.header);
-
- gcc->vars.prim_start = true;
- gcc->vars.prim_end = false;
- switch (gcc->out_vue_min_count) {
- case 1:
- gcc->vars.prim_type = GEN6_3DPRIM_POINTLIST;
- break;
- case 2:
- gcc->vars.prim_type = GEN6_3DPRIM_LINESTRIP;
- break;
- case 3:
- gcc->vars.prim_type = GEN6_3DPRIM_TRISTRIP;
- break;
- }
-
- if (gcc->write_so)
- tc_MOV(tc, gcc->vars.so_written, tsrc_imm_d(0));
-}
-
-static void
-gs_save_output(struct gs_compile_context *gcc, const struct toy_src *outs)
-{
- struct toy_compiler *tc = &gcc->tc;
- const struct toy_dst buf = gcc->vars.buffers[gcc->vars.buffer_cur];
- int i;
-
- for (i = 0; i < gcc->shader->out.count; i++)
- tc_MOV(tc, tdst_offset(buf, i, 0), outs[i]);
-
- /* advance the cursor */
- gcc->vars.buffer_cur++;
- gcc->vars.buffer_cur %= gcc->vars.buffer_needed;
-}
-
-static void
-gs_write_so(struct gs_compile_context *gcc,
- struct toy_dst dst,
- struct toy_src index, struct toy_src out,
- bool send_write_commit_message,
- int binding_table_index)
-{
- struct toy_compiler *tc = &gcc->tc;
- struct toy_dst mrf_header;
- struct toy_src desc;
-
- mrf_header = tdst_d(tdst(TOY_FILE_MRF, gcc->first_free_mrf, 0));
-
- /* m0.5: destination index */
- gs_COPY1(tc, mrf_header, 5, index, 0);
-
- /* m0.0 - m0.3: RGBA */
- gs_COPY4(tc, mrf_header, 0, tsrc_type(out, mrf_header.type), 0);
-
- desc = tsrc_imm_mdesc_data_port(tc, false,
- 1, send_write_commit_message,
- true, send_write_commit_message,
- GEN6_MSG_DP_SVB_WRITE, 0,
- binding_table_index);
-
- tc_SEND(tc, dst, tsrc_from(mrf_header), desc,
- GEN6_SFID_DP_RC);
-}
-
-static void
-gs_write_vue(struct gs_compile_context *gcc,
- struct toy_dst dst, struct toy_src msg_header,
- const struct toy_src *outs, int num_outs,
- bool eot)
-{
- struct toy_compiler *tc = &gcc->tc;
- struct toy_dst mrf_header;
- struct toy_src desc;
- int sent = 0;
-
- mrf_header = tdst_d(tdst(TOY_FILE_MRF, gcc->first_free_mrf, 0));
- gs_COPY8(tc, mrf_header, msg_header);
-
- while (sent < num_outs) {
- int mrf = gcc->first_free_mrf + 1;
- const int mrf_avail = gcc->last_free_mrf - mrf + 1;
- int msg_len, num_entries, i;
- bool complete;
-
- num_entries = (num_outs - sent + 1) / 2;
- complete = true;
- if (num_entries > mrf_avail) {
- num_entries = mrf_avail;
- complete = false;
- }
-
- for (i = 0; i < num_entries; i++) {
- gs_COPY4(tc, tdst(TOY_FILE_MRF, mrf + i / 2, 0), 0,
- outs[sent + 2 * i], 0);
- if (sent + i * 2 + 1 < gcc->shader->out.count) {
- gs_COPY4(tc, tdst(TOY_FILE_MRF, mrf + i / 2, 0), 4,
- outs[sent + 2 * i + 1], 0);
- }
- mrf++;
- }
-
- /* do not forget the header */
- msg_len = num_entries + 1;
-
- if (complete) {
- desc = tsrc_imm_mdesc_urb(tc,
- eot, msg_len, !eot, true, true, !eot,
- false, sent, 0);
- }
- else {
- desc = tsrc_imm_mdesc_urb(tc,
- false, msg_len, 0, false, true, false,
- false, sent, 0);
- }
-
- tc_add2(tc, TOY_OPCODE_URB_WRITE,
- (complete) ? dst : tdst_null(), tsrc_from(mrf_header), desc);
-
- sent += num_entries * 2;
- }
-}
-
-static void
-gs_ff_sync(struct gs_compile_context *gcc, struct toy_dst dst,
- struct toy_src num_prims)
-{
- struct toy_compiler *tc = &gcc->tc;
- struct toy_dst mrf_header =
- tdst_d(tdst(TOY_FILE_MRF, gcc->first_free_mrf, 0));
- struct toy_src desc;
- bool allocate;
-
- gs_COPY8(tc, mrf_header, gcc->payload.header);
-
- /* set NumSOVertsToWrite and NumSOPrimsNeeded */
- if (gcc->write_so) {
- if (num_prims.file == TOY_FILE_IMM) {
- const uint32_t v =
- (num_prims.val32 * gcc->in_vue_count) << 16 | num_prims.val32;
-
- gs_COPY1(tc, mrf_header, 0, tsrc_imm_d(v), 0);
- }
- else {
- struct toy_dst m0_0 = tdst_d(gcc->vars.tmp);
-
- tc_MUL(tc, m0_0, num_prims, tsrc_imm_d(gcc->in_vue_count << 16));
- tc_OR(tc, m0_0, tsrc_from(m0_0), num_prims);
-
- gs_COPY1(tc, mrf_header, 0, tsrc_from(m0_0), 0);
- }
- }
-
- /* set NumGSPrimsGenerated */
- if (gcc->write_vue)
- gs_COPY1(tc, mrf_header, 1, num_prims, 0);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 173:
- *
- * "Programming Note: If the GS stage is enabled, software must always
- * allocate at least one GS URB Entry. This is true even if the GS
- * thread never needs to output vertices to the pipeline, e.g., when
- * only performing stream output. This is an artifact of the need to
- * pass the GS thread an initial destination URB handle."
- */
- allocate = true;
- desc = tsrc_imm_mdesc_urb(tc, false, 1, 1,
- false, false, allocate,
- false, 0, 1);
-
- tc_SEND(tc, dst, tsrc_from(mrf_header), desc, GEN6_SFID_URB);
-}
-
-static void
-gs_discard(struct gs_compile_context *gcc)
-{
- struct toy_compiler *tc = &gcc->tc;
- struct toy_dst mrf_header;
- struct toy_src desc;
-
- mrf_header = tdst_d(tdst(TOY_FILE_MRF, gcc->first_free_mrf, 0));
-
- gs_COPY8(tc, mrf_header, tsrc_from(gcc->vars.urb_write_header));
-
- desc = tsrc_imm_mdesc_urb(tc,
- true, 1, 0, true, false, false,
- false, 0, 0);
-
- tc_add2(tc, TOY_OPCODE_URB_WRITE,
- tdst_null(), tsrc_from(mrf_header), desc);
-}
-
-static void
-gs_lower_opcode_endprim(struct gs_compile_context *gcc, struct toy_inst *inst)
-{
- /* if has control flow, set PrimEnd on the last vertex and URB_WRITE */
-}
-
-static void
-gs_lower_opcode_emit_vue_dynamic(struct gs_compile_context *gcc)
-{
- /* TODO similar to the static version */
-
- /*
- * When SO is enabled and the inputs are lines or triangles, vertices are
- * always buffered. we can defer the emission of the current vertex until
- * the next EMIT or ENDPRIM. Or, we can emit two URB_WRITEs with the later
- * patching the former.
- */
-}
-
-static void
-gs_lower_opcode_emit_so_dynamic(struct gs_compile_context *gcc)
-{
- struct toy_compiler *tc = &gcc->tc;
-
- tc_IF(tc, tdst_null(),
- tsrc_from(gcc->dynamic_data.num_vertices_in_prim),
- tsrc_imm_d(gcc->out_vue_min_count),
- GEN6_COND_GE);
-
- {
- tc_ADD(tc, gcc->vars.tmp, tsrc_from(gcc->vars.so_index), tsrc_imm_d(0x03020100));
-
- /* TODO same as static version */
- }
-
- tc_ENDIF(tc);
-
- tc_ADD(tc, gcc->vars.so_index,
- tsrc_from(gcc->vars.so_index), tsrc_imm_d(gcc->out_vue_min_count));
-}
-
-static void
-gs_lower_opcode_emit_vue_static(struct gs_compile_context *gcc)
-{
- struct toy_compiler *tc = &gcc->tc;
- struct toy_inst *inst2;
- bool eot;
-
- eot = (gcc->static_data.num_vertices == gcc->static_data.total_vertices);
-
- gcc->vars.prim_end =
- ((gcc->static_data.last_vertex[(gcc->static_data.num_vertices - 1) / 32] &
- 1 << ((gcc->static_data.num_vertices - 1) % 32)) != 0);
-
- if (eot && gcc->write_so) {
- inst2 = tc_OR(tc, tdst_offset(gcc->vars.urb_write_header, 0, 2),
- tsrc_from(gcc->vars.so_written),
- tsrc_imm_d(gcc->vars.prim_type << 2 |
- gcc->vars.prim_start << 1 |
- gcc->vars.prim_end));
- inst2->exec_size = GEN6_EXECSIZE_1;
- inst2->src[0] = tsrc_rect(inst2->src[0], TOY_RECT_010);
- inst2->src[1] = tsrc_rect(inst2->src[1], TOY_RECT_010);
- }
- else {
- gs_COPY1(tc, gcc->vars.urb_write_header, 2,
- tsrc_imm_d(gcc->vars.prim_type << 2 |
- gcc->vars.prim_start << 1 |
- gcc->vars.prim_end), 0);
- }
-
- gs_write_vue(gcc, tdst_d(gcc->vars.tmp),
- tsrc_from(gcc->vars.urb_write_header),
- gcc->vars.tgsi_outs,
- gcc->shader->out.count, eot);
-
- if (!eot) {
- gs_COPY1(tc, gcc->vars.urb_write_header, 0,
- tsrc_from(tdst_d(gcc->vars.tmp)), 0);
- }
-
- gcc->vars.prim_start = gcc->vars.prim_end;
- gcc->vars.prim_end = false;
-}
-
-static void
-gs_lower_opcode_emit_so_static(struct gs_compile_context *gcc)
-{
- struct toy_compiler *tc = &gcc->tc;
- struct toy_inst *inst;
- int i, j;
-
- if (gcc->static_data.num_vertices_in_prim < gcc->out_vue_min_count)
- return;
-
- inst = tc_MOV(tc, tdst_w(gcc->vars.tmp), tsrc_imm_v(0x03020100));
- inst->exec_size = GEN6_EXECSIZE_8;
- inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
-
- tc_ADD(tc, tdst_d(gcc->vars.tmp), tsrc_from(tdst_d(gcc->vars.tmp)),
- tsrc_rect(tsrc_from(gcc->vars.so_index), TOY_RECT_010));
-
- tc_IF(tc, tdst_null(),
- tsrc_rect(tsrc_offset(tsrc_from(tdst_d(gcc->vars.tmp)), 0, gcc->out_vue_min_count - 1), TOY_RECT_010),
- tsrc_rect(tsrc_offset(gcc->payload.svbi, 0, 4), TOY_RECT_010),
- GEN6_COND_LE);
- {
- for (i = 0; i < gcc->out_vue_min_count; i++) {
- for (j = 0; j < gcc->so_info->num_outputs; j++) {
- const int idx = gcc->so_info->output[j].register_index;
- struct toy_src index, out;
- int binding_table_index;
- bool write_commit;
-
- index = tsrc_d(tsrc_offset(tsrc_from(gcc->vars.tmp), 0, i));
-
- if (i == gcc->out_vue_min_count - 1) {
- out = gcc->vars.tgsi_outs[idx];
- }
- else {
- /* gcc->vars.buffer_cur also points to the first vertex */
- const int buf =
- (gcc->vars.buffer_cur + i) % gcc->vars.buffer_needed;
-
- out = tsrc_offset(tsrc_from(gcc->vars.buffers[buf]), idx, 0);
- }
-
- out = tsrc_offset(out, 0, gcc->so_info->output[j].start_component);
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 2, page 19:
- *
- * "The Kernel must do a write commit on the last write to DAP
- * prior to a URB_WRITE with End of Thread."
- */
- write_commit =
- (gcc->static_data.num_vertices == gcc->static_data.total_vertices &&
- i == gcc->out_vue_min_count - 1 &&
- j == gcc->so_info->num_outputs - 1);
-
-
- binding_table_index = gcc->shader->bt.gen6_so_base + j;
-
- gs_write_so(gcc, gcc->vars.tmp, index,
- out, write_commit, binding_table_index);
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 168:
- *
- * "The write commit does not modify the destination register, but
- * merely clears the dependency associated with the destination
- * register. Thus, a simple "mov" instruction using the register as a
- * source is sufficient to wait for the write commit to occur."
- */
- if (write_commit)
- tc_MOV(tc, gcc->vars.tmp, tsrc_from(gcc->vars.tmp));
- }
- }
-
- /* SONumPrimsWritten occupies the higher word of m0.2 of URB_WRITE */
- tc_ADD(tc, gcc->vars.so_written,
- tsrc_from(gcc->vars.so_written), tsrc_imm_d(1 << 16));
- tc_ADD(tc, gcc->vars.so_index,
- tsrc_from(gcc->vars.so_index), tsrc_imm_d(gcc->out_vue_min_count));
- }
- tc_ENDIF(tc);
-}
-
-static void
-gs_lower_opcode_emit_static(struct gs_compile_context *gcc,
- struct toy_inst *inst)
-{
- gcc->static_data.num_vertices++;
- gcc->static_data.num_vertices_in_prim++;
-
- if (gcc->write_so) {
- gs_lower_opcode_emit_so_static(gcc);
-
- if (gcc->out_vue_min_count > 1 &&
- gcc->static_data.num_vertices != gcc->static_data.total_vertices)
- gs_save_output(gcc, gcc->vars.tgsi_outs);
- }
-
- if (gcc->write_vue)
- gs_lower_opcode_emit_vue_static(gcc);
-}
-
-static void
-gs_lower_opcode_emit_dynamic(struct gs_compile_context *gcc,
- struct toy_inst *inst)
-{
- struct toy_compiler *tc = &gcc->tc;
-
- tc_ADD(tc, gcc->dynamic_data.num_vertices,
- tsrc_from(gcc->dynamic_data.num_vertices), tsrc_imm_d(1));
- tc_ADD(tc, gcc->dynamic_data.num_vertices_in_prim,
- tsrc_from(gcc->dynamic_data.num_vertices_in_prim), tsrc_imm_d(1));
-
- if (gcc->write_so) {
- gs_lower_opcode_emit_so_dynamic(gcc);
-
- if (gcc->out_vue_min_count > 1)
- gs_save_output(gcc, gcc->vars.tgsi_outs);
- }
-
- if (gcc->write_vue)
- gs_lower_opcode_emit_vue_dynamic(gcc);
-}
-
-static void
-gs_lower_opcode_emit(struct gs_compile_context *gcc, struct toy_inst *inst)
-{
- if (gcc->is_static)
- gs_lower_opcode_emit_static(gcc, inst);
- else
- gs_lower_opcode_emit_dynamic(gcc, inst);
-}
-
-static void
-gs_lower_opcode_tgsi_in(struct gs_compile_context *gcc,
- struct toy_dst dst, int dim, int idx)
-{
- struct toy_compiler *tc = &gcc->tc;
- struct toy_src attr;
- int slot, reg = -1, subreg;
-
- slot = toy_tgsi_find_input(&gcc->tgsi, idx);
- if (slot >= 0) {
- int i;
-
- for (i = 0; i < gcc->variant->u.gs.num_inputs; i++) {
- if (gcc->variant->u.gs.semantic_names[i] ==
- gcc->tgsi.inputs[slot].semantic_name &&
- gcc->variant->u.gs.semantic_indices[i] ==
- gcc->tgsi.inputs[slot].semantic_index) {
- reg = i / 2;
- subreg = (i % 2) * 4;
- break;
- }
- }
- }
-
- if (reg < 0) {
- tc_MOV(tc, dst, tsrc_imm_f(0.0f));
- return;
- }
-
- /* fix vertex ordering for GEN6_3DPRIM_TRISTRIP_REVERSE */
- if (gcc->in_vue_count == 3 && dim < 2) {
- struct toy_inst *inst;
-
- /* get PrimType */
- inst = tc_AND(tc, tdst_d(gcc->vars.tmp),
- tsrc_offset(gcc->payload.header, 0, 2), tsrc_imm_d(0x1f));
- inst->exec_size = GEN6_EXECSIZE_1;
- inst->src[0] = tsrc_rect(inst->src[0], TOY_RECT_010);
- inst->src[1] = tsrc_rect(inst->src[1], TOY_RECT_010);
-
- inst = tc_CMP(tc, tdst_null(), tsrc_from(tdst_d(gcc->vars.tmp)),
- tsrc_imm_d(GEN6_3DPRIM_TRISTRIP_REVERSE), GEN6_COND_NZ);
- inst->src[0] = tsrc_rect(inst->src[0], TOY_RECT_010);
-
- attr = tsrc_offset(gcc->payload.vues[dim], reg, subreg);
- inst = tc_MOV(tc, dst, attr);
- inst->pred_ctrl = GEN6_PREDCTRL_NORMAL;
-
- /* swap IN[0] and IN[1] for GEN6_3DPRIM_TRISTRIP_REVERSE */
- dim = !dim;
-
- attr = tsrc_offset(gcc->payload.vues[dim], reg, subreg);
- inst = tc_MOV(tc, dst, attr);
- inst->pred_ctrl = GEN6_PREDCTRL_NORMAL;
- inst->pred_inv = true;
- }
- else {
- attr = tsrc_offset(gcc->payload.vues[dim], reg, subreg);
- tc_MOV(tc, dst, attr);
- }
-
-
-}
-
-static void
-gs_lower_opcode_tgsi_imm(struct gs_compile_context *gcc,
- struct toy_dst dst, int idx)
-{
- const uint32_t *imm;
- int ch;
-
- imm = toy_tgsi_get_imm(&gcc->tgsi, idx, NULL);
-
- for (ch = 0; ch < 4; ch++) {
- struct toy_inst *inst;
-
- /* raw moves */
- inst = tc_MOV(&gcc->tc,
- tdst_writemask(tdst_ud(dst), 1 << ch),
- tsrc_imm_ud(imm[ch]));
- inst->access_mode = GEN6_ALIGN_16;
- }
-}
-
-static void
-gs_lower_opcode_tgsi_direct(struct gs_compile_context *gcc,
- struct toy_inst *inst)
-{
- struct toy_compiler *tc = &gcc->tc;
- int dim, idx;
-
- assert(inst->src[0].file == TOY_FILE_IMM);
- dim = inst->src[0].val32;
-
- assert(inst->src[1].file == TOY_FILE_IMM);
- idx = inst->src[1].val32;
-
- switch (inst->opcode) {
- case TOY_OPCODE_TGSI_IN:
- gs_lower_opcode_tgsi_in(gcc, inst->dst, dim, idx);
- /* fetch all dimensions */
- if (dim == 0) {
- int i;
-
- for (i = 1; i < gcc->in_vue_count; i++) {
- const int vrf = toy_tgsi_get_vrf(&gcc->tgsi, TGSI_FILE_INPUT, i, idx);
- struct toy_dst dst;
-
- if (vrf < 0)
- continue;
-
- dst = tdst(TOY_FILE_VRF, vrf, 0);
- gs_lower_opcode_tgsi_in(gcc, dst, i, idx);
- }
- }
- break;
- case TOY_OPCODE_TGSI_IMM:
- assert(!dim);
- gs_lower_opcode_tgsi_imm(gcc, inst->dst, idx);
- break;
- case TOY_OPCODE_TGSI_CONST:
- case TOY_OPCODE_TGSI_SV:
- default:
- tc_fail(tc, "unhandled TGSI fetch");
- break;
- }
-
- tc_discard_inst(tc, inst);
-}
-
-static void
-gs_lower_virtual_opcodes(struct gs_compile_context *gcc)
-{
- struct toy_compiler *tc = &gcc->tc;
- struct toy_inst *inst;
-
- tc_head(tc);
- while ((inst = tc_next(tc)) != NULL) {
- switch (inst->opcode) {
- case TOY_OPCODE_TGSI_IN:
- case TOY_OPCODE_TGSI_CONST:
- case TOY_OPCODE_TGSI_SV:
- case TOY_OPCODE_TGSI_IMM:
- gs_lower_opcode_tgsi_direct(gcc, inst);
- break;
- case TOY_OPCODE_TGSI_INDIRECT_FETCH:
- case TOY_OPCODE_TGSI_INDIRECT_STORE:
- /* TODO similar to VS */
- tc_fail(tc, "no indirection support");
- tc_discard_inst(tc, inst);
- break;
- case TOY_OPCODE_TGSI_TEX:
- case TOY_OPCODE_TGSI_TXB:
- case TOY_OPCODE_TGSI_TXD:
- case TOY_OPCODE_TGSI_TXL:
- case TOY_OPCODE_TGSI_TXP:
- case TOY_OPCODE_TGSI_TXF:
- case TOY_OPCODE_TGSI_TXQ:
- case TOY_OPCODE_TGSI_TXQ_LZ:
- case TOY_OPCODE_TGSI_TEX2:
- case TOY_OPCODE_TGSI_TXB2:
- case TOY_OPCODE_TGSI_TXL2:
- case TOY_OPCODE_TGSI_SAMPLE:
- case TOY_OPCODE_TGSI_SAMPLE_I:
- case TOY_OPCODE_TGSI_SAMPLE_I_MS:
- case TOY_OPCODE_TGSI_SAMPLE_B:
- case TOY_OPCODE_TGSI_SAMPLE_C:
- case TOY_OPCODE_TGSI_SAMPLE_C_LZ:
- case TOY_OPCODE_TGSI_SAMPLE_D:
- case TOY_OPCODE_TGSI_SAMPLE_L:
- case TOY_OPCODE_TGSI_GATHER4:
- case TOY_OPCODE_TGSI_SVIEWINFO:
- case TOY_OPCODE_TGSI_SAMPLE_POS:
- case TOY_OPCODE_TGSI_SAMPLE_INFO:
- /* TODO similar to VS */
- tc_fail(tc, "no sampling support");
- tc_discard_inst(tc, inst);
- break;
- case TOY_OPCODE_EMIT:
- gs_lower_opcode_emit(gcc, inst);
- tc_discard_inst(tc, inst);
- break;
- case TOY_OPCODE_ENDPRIM:
- gs_lower_opcode_endprim(gcc, inst);
- tc_discard_inst(tc, inst);
- break;
- default:
- break;
- }
- }
-
- tc_head(tc);
- while ((inst = tc_next(tc)) != NULL) {
- switch (inst->opcode) {
- case TOY_OPCODE_INV:
- case TOY_OPCODE_LOG:
- case TOY_OPCODE_EXP:
- case TOY_OPCODE_SQRT:
- case TOY_OPCODE_RSQ:
- case TOY_OPCODE_SIN:
- case TOY_OPCODE_COS:
- case TOY_OPCODE_FDIV:
- case TOY_OPCODE_POW:
- case TOY_OPCODE_INT_DIV_QUOTIENT:
- case TOY_OPCODE_INT_DIV_REMAINDER:
- toy_compiler_lower_math(tc, inst);
- break;
- case TOY_OPCODE_URB_WRITE:
- toy_compiler_lower_to_send(tc, inst, false, GEN6_SFID_URB);
- break;
- default:
- if (inst->opcode > 127)
- tc_fail(tc, "unhandled virtual opcode");
- break;
- }
- }
-}
-
-/**
- * Get the number of (tessellated) primitives generated by this shader.
- * Return false if that is unknown until runtime.
- */
-static void
-get_num_prims_static(struct gs_compile_context *gcc)
-{
- struct toy_compiler *tc = &gcc->tc;
- const struct toy_inst *inst;
- int num_vertices_in_prim = 0, if_depth = 0, do_depth = 0;
- bool is_static = true;
-
- tc_head(tc);
- while ((inst = tc_next_no_skip(tc)) != NULL) {
- switch (inst->opcode) {
- case GEN6_OPCODE_IF:
- if_depth++;
- break;
- case GEN6_OPCODE_ENDIF:
- if_depth--;
- break;
- case TOY_OPCODE_DO:
- do_depth++;
- break;
- case GEN6_OPCODE_WHILE:
- do_depth--;
- break;
- case TOY_OPCODE_EMIT:
- if (if_depth || do_depth) {
- is_static = false;
- }
- else {
- gcc->static_data.total_vertices++;
-
- num_vertices_in_prim++;
- if (num_vertices_in_prim >= gcc->out_vue_min_count)
- gcc->static_data.total_prims++;
- }
- break;
- case TOY_OPCODE_ENDPRIM:
- if (if_depth || do_depth) {
- is_static = false;
- }
- else {
- const int vertidx = gcc->static_data.total_vertices - 1;
- const int idx = vertidx / 32;
- const int subidx = vertidx % 32;
-
- gcc->static_data.last_vertex[idx] |= 1 << subidx;
- num_vertices_in_prim = 0;
- }
- break;
- default:
- break;
- }
-
- if (!is_static)
- break;
- }
-
- gcc->is_static = is_static;
-}
-
-/**
- * Compile the shader.
- */
-static bool
-gs_compile(struct gs_compile_context *gcc)
-{
- struct toy_compiler *tc = &gcc->tc;
- struct ilo_shader *sh = gcc->shader;
-
- get_num_prims_static(gcc);
-
- if (gcc->is_static) {
- tc_head(tc);
-
- gs_init_vars(gcc);
- gs_ff_sync(gcc, tdst_d(gcc->vars.tmp), tsrc_imm_d(gcc->static_data.total_prims));
- gs_COPY1(tc, gcc->vars.urb_write_header, 0, tsrc_from(tdst_d(gcc->vars.tmp)), 0);
- if (gcc->write_so)
- gs_COPY4(tc, gcc->vars.so_index, 0, tsrc_from(tdst_d(gcc->vars.tmp)), 1);
-
- tc_tail(tc);
- }
- else {
- tc_fail(tc, "no control flow support");
- return false;
- }
-
- if (!gcc->write_vue)
- gs_discard(gcc);
-
- gs_lower_virtual_opcodes(gcc);
- toy_compiler_legalize_for_ra(tc);
- toy_compiler_optimize(tc);
- toy_compiler_allocate_registers(tc,
- gcc->first_free_grf,
- gcc->last_free_grf,
- 1);
- toy_compiler_legalize_for_asm(tc);
-
- if (tc->fail) {
- ilo_err("failed to legalize GS instructions: %s\n", tc->reason);
- return false;
- }
-
- if (ilo_debug & ILO_DEBUG_GS) {
- ilo_printf("legalized instructions:\n");
- toy_compiler_dump(tc);
- ilo_printf("\n");
- }
-
- sh->kernel = toy_compiler_assemble(tc, &sh->kernel_size);
- if (!sh->kernel)
- return false;
-
- if (ilo_debug & ILO_DEBUG_GS) {
- ilo_printf("disassembly:\n");
- toy_compiler_disassemble(tc->dev, sh->kernel, sh->kernel_size, false);
- ilo_printf("\n");
- }
-
- return true;
-}
-
-static bool
-gs_compile_passthrough(struct gs_compile_context *gcc)
-{
- struct toy_compiler *tc = &gcc->tc;
- struct ilo_shader *sh = gcc->shader;
-
- gcc->is_static = true;
- gcc->static_data.total_vertices = gcc->in_vue_count;
- gcc->static_data.total_prims = 1;
- gcc->static_data.last_vertex[0] = 1 << (gcc->in_vue_count - 1);
-
- gs_init_vars(gcc);
- gs_ff_sync(gcc, tdst_d(gcc->vars.tmp), tsrc_imm_d(gcc->static_data.total_prims));
- gs_COPY1(tc, gcc->vars.urb_write_header, 0, tsrc_from(tdst_d(gcc->vars.tmp)), 0);
- if (gcc->write_so)
- gs_COPY4(tc, gcc->vars.so_index, 0, tsrc_from(tdst_d(gcc->vars.tmp)), 1);
-
- {
- int vert, attr;
-
- for (vert = 0; vert < gcc->out_vue_min_count; vert++) {
- for (attr = 0; attr < gcc->shader->out.count; attr++) {
- tc_MOV(tc, tdst_from(gcc->vars.tgsi_outs[attr]),
- tsrc_offset(gcc->payload.vues[vert], attr / 2, (attr % 2) * 4));
- }
-
- gs_lower_opcode_emit(gcc, NULL);
- }
-
- gs_lower_opcode_endprim(gcc, NULL);
- }
-
- if (!gcc->write_vue)
- gs_discard(gcc);
-
- gs_lower_virtual_opcodes(gcc);
-
- toy_compiler_legalize_for_ra(tc);
- toy_compiler_optimize(tc);
- toy_compiler_allocate_registers(tc,
- gcc->first_free_grf,
- gcc->last_free_grf,
- 1);
-
- toy_compiler_legalize_for_asm(tc);
-
- if (tc->fail) {
- ilo_err("failed to translate GS TGSI tokens: %s\n", tc->reason);
- return false;
- }
-
- if (ilo_debug & ILO_DEBUG_GS) {
- int i;
-
- ilo_printf("VUE count %d, VUE size %d\n",
- gcc->in_vue_count, gcc->in_vue_size);
- ilo_printf("%srasterizer discard\n",
- (gcc->variant->u.gs.rasterizer_discard) ? "" : "no ");
-
- for (i = 0; i < gcc->so_info->num_outputs; i++) {
- ilo_printf("SO[%d] = OUT[%d]\n", i,
- gcc->so_info->output[i].register_index);
- }
-
- ilo_printf("legalized instructions:\n");
- toy_compiler_dump(tc);
- ilo_printf("\n");
- }
-
- sh->kernel = toy_compiler_assemble(tc, &sh->kernel_size);
- if (!sh->kernel) {
- ilo_err("failed to compile GS: %s\n", tc->reason);
- return false;
- }
-
- if (ilo_debug & ILO_DEBUG_GS) {
- ilo_printf("disassembly:\n");
- toy_compiler_disassemble(tc->dev, sh->kernel, sh->kernel_size, false);
- ilo_printf("\n");
- }
-
- return true;
-}
-
-/**
- * Translate the TGSI tokens.
- */
-static bool
-gs_setup_tgsi(struct toy_compiler *tc, const struct tgsi_token *tokens,
- struct toy_tgsi *tgsi)
-{
- if (ilo_debug & ILO_DEBUG_GS) {
- ilo_printf("dumping geometry shader\n");
- ilo_printf("\n");
-
- tgsi_dump(tokens, 0);
- ilo_printf("\n");
- }
-
- toy_compiler_translate_tgsi(tc, tokens, true, tgsi);
- if (tc->fail)
- return false;
-
- if (ilo_debug & ILO_DEBUG_GS) {
- ilo_printf("TGSI translator:\n");
- toy_tgsi_dump(tgsi);
- ilo_printf("\n");
- toy_compiler_dump(tc);
- ilo_printf("\n");
- }
-
- return true;
-}
-
-/**
- * Set up shader inputs for fixed-function units.
- */
-static void
-gs_setup_shader_in(struct ilo_shader *sh,
- const struct ilo_shader_variant *variant)
-{
- int i;
-
- for (i = 0; i < variant->u.gs.num_inputs; i++) {
- sh->in.semantic_names[i] = variant->u.gs.semantic_names[i];
- sh->in.semantic_indices[i] = variant->u.gs.semantic_indices[i];
- sh->in.interp[i] = TGSI_INTERPOLATE_CONSTANT;
- sh->in.centroid[i] = false;
- }
-
- sh->in.count = variant->u.gs.num_inputs;
-
- sh->in.has_pos = false;
- sh->in.has_linear_interp = false;
- sh->in.barycentric_interpolation_mode = 0;
-}
-
-/**
- * Set up shader outputs for fixed-function units.
- *
- * XXX share the code with VS
- */
-static void
-gs_setup_shader_out(struct ilo_shader *sh, const struct toy_tgsi *tgsi,
- bool output_clipdist, int *output_map)
-{
- int psize_slot = -1, pos_slot = -1;
- int clipdist_slot[2] = { -1, -1 };
- int color_slot[4] = { -1, -1, -1, -1 };
- int num_outs, i;
-
- /* find out the slots of outputs that need special care */
- for (i = 0; i < tgsi->num_outputs; i++) {
- switch (tgsi->outputs[i].semantic_name) {
- case TGSI_SEMANTIC_PSIZE:
- psize_slot = i;
- break;
- case TGSI_SEMANTIC_POSITION:
- pos_slot = i;
- break;
- case TGSI_SEMANTIC_CLIPDIST:
- if (tgsi->outputs[i].semantic_index)
- clipdist_slot[1] = i;
- else
- clipdist_slot[0] = i;
- break;
- case TGSI_SEMANTIC_COLOR:
- if (tgsi->outputs[i].semantic_index)
- color_slot[2] = i;
- else
- color_slot[0] = i;
- break;
- case TGSI_SEMANTIC_BCOLOR:
- if (tgsi->outputs[i].semantic_index)
- color_slot[3] = i;
- else
- color_slot[1] = i;
- break;
- default:
- break;
- }
- }
-
- /* the first two VUEs are always PSIZE and POSITION */
- num_outs = 2;
- output_map[0] = psize_slot;
- output_map[1] = pos_slot;
-
- sh->out.register_indices[0] =
- (psize_slot >= 0) ? tgsi->outputs[psize_slot].index : -1;
- sh->out.semantic_names[0] = TGSI_SEMANTIC_PSIZE;
- sh->out.semantic_indices[0] = 0;
-
- sh->out.register_indices[1] =
- (pos_slot >= 0) ? tgsi->outputs[pos_slot].index : -1;
- sh->out.semantic_names[1] = TGSI_SEMANTIC_POSITION;
- sh->out.semantic_indices[1] = 0;
-
- sh->out.has_pos = true;
-
- /* followed by optional clip distances */
- if (output_clipdist) {
- sh->out.register_indices[num_outs] =
- (clipdist_slot[0] >= 0) ? tgsi->outputs[clipdist_slot[0]].index : -1;
- sh->out.semantic_names[num_outs] = TGSI_SEMANTIC_CLIPDIST;
- sh->out.semantic_indices[num_outs] = 0;
- output_map[num_outs++] = clipdist_slot[0];
-
- sh->out.register_indices[num_outs] =
- (clipdist_slot[1] >= 0) ? tgsi->outputs[clipdist_slot[1]].index : -1;
- sh->out.semantic_names[num_outs] = TGSI_SEMANTIC_CLIPDIST;
- sh->out.semantic_indices[num_outs] = 1;
- output_map[num_outs++] = clipdist_slot[1];
- }
-
- /*
- * make BCOLOR follow COLOR so that we can make use of
- * ATTRIBUTE_SWIZZLE_INPUTATTR_FACING in 3DSTATE_SF
- */
- for (i = 0; i < 4; i++) {
- const int slot = color_slot[i];
-
- if (slot < 0)
- continue;
-
- sh->out.register_indices[num_outs] = tgsi->outputs[slot].index;
- sh->out.semantic_names[num_outs] = tgsi->outputs[slot].semantic_name;
- sh->out.semantic_indices[num_outs] = tgsi->outputs[slot].semantic_index;
-
- output_map[num_outs++] = slot;
- }
-
- /* add the rest of the outputs */
- for (i = 0; i < tgsi->num_outputs; i++) {
- switch (tgsi->outputs[i].semantic_name) {
- case TGSI_SEMANTIC_PSIZE:
- case TGSI_SEMANTIC_POSITION:
- case TGSI_SEMANTIC_CLIPDIST:
- case TGSI_SEMANTIC_COLOR:
- case TGSI_SEMANTIC_BCOLOR:
- break;
- default:
- sh->out.register_indices[num_outs] = tgsi->outputs[i].index;
- sh->out.semantic_names[num_outs] = tgsi->outputs[i].semantic_name;
- sh->out.semantic_indices[num_outs] = tgsi->outputs[i].semantic_index;
- output_map[num_outs++] = i;
- break;
- }
- }
-
- sh->out.count = num_outs;
-}
-
-static void
-gs_setup_vars(struct gs_compile_context *gcc)
-{
- int grf = gcc->first_free_grf;
- int i;
-
- gcc->vars.urb_write_header = tdst_d(tdst(TOY_FILE_GRF, grf, 0));
- grf++;
-
- gcc->vars.tmp = tdst(TOY_FILE_GRF, grf, 0);
- grf++;
-
- if (gcc->write_so) {
- gcc->vars.buffer_needed = gcc->out_vue_min_count - 1;
- for (i = 0; i < gcc->vars.buffer_needed; i++) {
- gcc->vars.buffers[i] = tdst(TOY_FILE_GRF, grf, 0);
- grf += gcc->shader->out.count;
- }
-
- gcc->vars.so_written = tdst_d(tdst(TOY_FILE_GRF, grf, 0));
- grf++;
-
- gcc->vars.so_index = tdst_d(tdst(TOY_FILE_GRF, grf, 0));
- grf++;
- }
-
- gcc->first_free_grf = grf;
-
- if (!gcc->tgsi.reg_mapping) {
- for (i = 0; i < gcc->shader->out.count; i++)
- gcc->vars.tgsi_outs[i] = tsrc(TOY_FILE_GRF, grf++, 0);
-
- gcc->first_free_grf = grf;
- return;
- }
-
- for (i = 0; i < gcc->shader->out.count; i++) {
- const int slot = gcc->output_map[i];
- const int vrf = (slot >= 0) ? toy_tgsi_get_vrf(&gcc->tgsi,
- TGSI_FILE_OUTPUT, 0, gcc->tgsi.outputs[slot].index) : -1;
-
- if (vrf >= 0)
- gcc->vars.tgsi_outs[i] = tsrc(TOY_FILE_VRF, vrf, 0);
- else
- gcc->vars.tgsi_outs[i] = (i == 0) ? tsrc_imm_d(0) : tsrc_imm_f(0.0f);
- }
-}
-
-static void
-gs_setup_payload(struct gs_compile_context *gcc)
-{
- int grf, i;
-
- grf = 0;
-
- /* r0: payload header */
- gcc->payload.header = tsrc_d(tsrc(TOY_FILE_GRF, grf, 0));
- grf++;
-
- /* r1: SVBI */
- if (gcc->write_so) {
- gcc->payload.svbi = tsrc_ud(tsrc(TOY_FILE_GRF, grf, 0));
- grf++;
- }
-
- /* URB data */
- gcc->shader->in.start_grf = grf;
-
- /* no pull constants */
-
- /* VUEs */
- for (i = 0; i < gcc->in_vue_count; i++) {
- gcc->payload.vues[i] = tsrc(TOY_FILE_GRF, grf, 0);
- grf += gcc->in_vue_size;
- }
-
- gcc->first_free_grf = grf;
- gcc->last_free_grf = 127;
-}
-
-/**
- * Set up GS compile context. This includes translating the TGSI tokens.
- */
-static bool
-gs_setup(struct gs_compile_context *gcc,
- const struct ilo_shader_state *state,
- const struct ilo_shader_variant *variant,
- int num_verts)
-{
- memset(gcc, 0, sizeof(*gcc));
-
- gcc->shader = CALLOC_STRUCT(ilo_shader);
- if (!gcc->shader)
- return false;
-
- gcc->variant = variant;
- gcc->so_info = &state->info.stream_output;
-
- toy_compiler_init(&gcc->tc, state->info.dev);
-
- gcc->write_so = (state->info.stream_output.num_outputs > 0);
- gcc->write_vue = !gcc->variant->u.gs.rasterizer_discard;
-
- gcc->tc.templ.access_mode = GEN6_ALIGN_16;
- gcc->tc.templ.exec_size = GEN6_EXECSIZE_4;
- gcc->tc.rect_linear_width = 4;
-
- if (state->info.tokens) {
- if (!gs_setup_tgsi(&gcc->tc, state->info.tokens, &gcc->tgsi)) {
- toy_compiler_cleanup(&gcc->tc);
- FREE(gcc->shader);
- return false;
- }
-
- switch (gcc->tgsi.props.gs_input_prim) {
- case PIPE_PRIM_POINTS:
- gcc->in_vue_count = 1;
- break;
- case PIPE_PRIM_LINES:
- gcc->in_vue_count = 2;
- gcc->shader->in.discard_adj = true;
- break;
- case PIPE_PRIM_TRIANGLES:
- gcc->in_vue_count = 3;
- gcc->shader->in.discard_adj = true;
- break;
- case PIPE_PRIM_LINES_ADJACENCY:
- gcc->in_vue_count = 4;
- break;
- case PIPE_PRIM_TRIANGLES_ADJACENCY:
- gcc->in_vue_count = 6;
- break;
- default:
- tc_fail(&gcc->tc, "unsupported GS input type");
- gcc->in_vue_count = 0;
- break;
- }
-
- switch (gcc->tgsi.props.gs_output_prim) {
- case PIPE_PRIM_POINTS:
- gcc->out_vue_min_count = 1;
- break;
- case PIPE_PRIM_LINE_STRIP:
- gcc->out_vue_min_count = 2;
- break;
- case PIPE_PRIM_TRIANGLE_STRIP:
- gcc->out_vue_min_count = 3;
- break;
- default:
- tc_fail(&gcc->tc, "unsupported GS output type");
- gcc->out_vue_min_count = 0;
- break;
- }
- }
- else {
- int i;
-
- gcc->in_vue_count = num_verts;
- gcc->out_vue_min_count = num_verts;
-
- gcc->tgsi.num_outputs = gcc->variant->u.gs.num_inputs;
- for (i = 0; i < gcc->variant->u.gs.num_inputs; i++) {
- gcc->tgsi.outputs[i].semantic_name =
- gcc->variant->u.gs.semantic_names[i];
- gcc->tgsi.outputs[i].semantic_index =
- gcc->variant->u.gs.semantic_indices[i];
- }
- }
-
- gcc->tc.templ.access_mode = GEN6_ALIGN_1;
-
- gs_setup_shader_in(gcc->shader, gcc->variant);
- gs_setup_shader_out(gcc->shader, &gcc->tgsi, false, gcc->output_map);
-
- gcc->in_vue_size = (gcc->shader->in.count + 1) / 2;
-
- gcc->out_vue_size = (gcc->shader->out.count + 1) / 2;
-
- gs_setup_payload(gcc);
- gs_setup_vars(gcc);
-
- /* m0 is reserved for system routines */
- gcc->first_free_mrf = 1;
- gcc->last_free_mrf = 15;
-
- gcc->shader->bt.gen6_so_base = 0;
- gcc->shader->bt.gen6_so_count = gcc->so_info->num_outputs;
-
- gcc->shader->bt.total_count = gcc->shader->bt.gen6_so_count;
-
- return true;
-}
-
-/**
- * Compile the geometry shader.
- */
-struct ilo_shader *
-ilo_shader_compile_gs(const struct ilo_shader_state *state,
- const struct ilo_shader_variant *variant)
-{
- struct gs_compile_context gcc;
-
- if (!gs_setup(&gcc, state, variant, 0))
- return NULL;
-
- if (!gs_compile(&gcc)) {
- FREE(gcc.shader);
- gcc.shader = NULL;
- }
-
- toy_tgsi_cleanup(&gcc.tgsi);
- toy_compiler_cleanup(&gcc.tc);
-
- return gcc.shader;
-}
-
-static bool
-append_gs_to_vs(struct ilo_shader *vs, struct ilo_shader *gs, int num_verts)
-{
- void *combined;
- int gs_offset;
-
- if (!gs)
- return false;
-
- /* kernels must be aligned to 64-byte */
- gs_offset = align(vs->kernel_size, 64);
- combined = REALLOC(vs->kernel, vs->kernel_size,
- gs_offset + gs->kernel_size);
- if (!combined)
- return false;
-
- memcpy(combined + gs_offset, gs->kernel, gs->kernel_size);
-
- vs->kernel = combined;
- vs->kernel_size = gs_offset + gs->kernel_size;
-
- vs->stream_output = true;
- vs->gs_offsets[num_verts - 1] = gs_offset;
- vs->gs_start_grf = gs->in.start_grf;
- vs->gs_bt_so_count = gs->bt.gen6_so_count;
-
- ilo_shader_destroy_kernel(gs);
-
- return true;
-}
-
-bool
-ilo_shader_compile_gs_passthrough(const struct ilo_shader_state *vs_state,
- const struct ilo_shader_variant *vs_variant,
- const int *so_mapping,
- struct ilo_shader *vs)
-{
- struct gs_compile_context gcc;
- struct ilo_shader_state state;
- struct ilo_shader_variant variant;
- const int num_verts = 3;
- int i;
-
- /* init GS state and variant */
- state = *vs_state;
- state.info.tokens = NULL;
- for (i = 0; i < state.info.stream_output.num_outputs; i++) {
- const int reg = state.info.stream_output.output[i].register_index;
-
- state.info.stream_output.output[i].register_index = so_mapping[reg];
- }
-
- variant = *vs_variant;
- variant.u.gs.rasterizer_discard = vs_variant->u.vs.rasterizer_discard;
- variant.u.gs.num_inputs = vs->out.count;
- for (i = 0; i < vs->out.count; i++) {
- variant.u.gs.semantic_names[i] =
- vs->out.semantic_names[i];
- variant.u.gs.semantic_indices[i] =
- vs->out.semantic_indices[i];
- }
-
- if (!gs_setup(&gcc, &state, &variant, num_verts))
- return false;
-
- if (!gs_compile_passthrough(&gcc)) {
- FREE(gcc.shader);
- gcc.shader = NULL;
- }
-
- /* no need to call toy_tgsi_cleanup() */
- toy_compiler_cleanup(&gcc.tc);
-
- return append_gs_to_vs(vs, gcc.shader, num_verts);
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_SHADER_INTERNAL_H
-#define ILO_SHADER_INTERNAL_H
-
-#include "core/ilo_state_sbe.h"
-#include "core/ilo_state_sol.h"
-
-#include "ilo_common.h"
-#include "ilo_state.h"
-#include "ilo_shader.h"
-
-/* XXX The interface needs to be reworked */
-
-/**
- * A shader variant. It consists of non-orthogonal states of the pipe context
- * affecting the compilation of a shader.
- */
-struct ilo_shader_variant {
- union {
- struct {
- bool rasterizer_discard;
- int num_ucps;
- } vs;
-
- struct {
- bool rasterizer_discard;
- int num_inputs;
- int semantic_names[PIPE_MAX_SHADER_INPUTS];
- int semantic_indices[PIPE_MAX_SHADER_INPUTS];
- } gs;
-
- struct {
- bool flatshade;
- int fb_height;
- int num_cbufs;
- } fs;
- } u;
-
- bool use_pcb;
-
- int num_sampler_views;
- struct {
- unsigned r:3;
- unsigned g:3;
- unsigned b:3;
- unsigned a:3;
- } sampler_view_swizzles[ILO_MAX_SAMPLER_VIEWS];
-
- uint32_t saturate_tex_coords[3];
-};
-
-struct ilo_kernel_routing {
- bool initialized;
-
- bool is_point;
- bool light_twoside;
- uint32_t sprite_coord_enable;
- int sprite_coord_mode;
- int src_len;
- int src_semantics[PIPE_MAX_SHADER_OUTPUTS];
- int src_indices[PIPE_MAX_SHADER_OUTPUTS];
-
- struct ilo_state_sbe sbe;
-};
-
-/**
- * A compiled shader.
- */
-struct ilo_shader {
- struct ilo_shader_variant variant;
-
- union ilo_shader_cso cso;
-
- struct {
- int semantic_names[PIPE_MAX_SHADER_INPUTS];
- int semantic_indices[PIPE_MAX_SHADER_INPUTS];
- int interp[PIPE_MAX_SHADER_INPUTS];
- bool centroid[PIPE_MAX_SHADER_INPUTS];
- int count;
-
- int start_grf;
- bool has_pos;
- bool has_linear_interp;
- int barycentric_interpolation_mode;
- uint32_t const_interp_enable;
- bool discard_adj;
- } in;
-
- struct {
- int register_indices[PIPE_MAX_SHADER_OUTPUTS];
- int semantic_names[PIPE_MAX_SHADER_OUTPUTS];
- int semantic_indices[PIPE_MAX_SHADER_OUTPUTS];
- int count;
-
- bool has_pos;
- } out;
-
- bool skip_cbuf0_upload;
-
- bool has_kill;
- bool dispatch_16;
-
- bool stream_output;
- int svbi_post_inc;
-
- uint32_t sol_data[PIPE_MAX_SO_OUTPUTS][2];
- struct ilo_state_sol sol;
-
- /* for VS stream output / rasterizer discard */
- int gs_offsets[3];
- int gs_start_grf;
- int gs_bt_so_count;
-
- void *kernel;
- int kernel_size;
- int per_thread_scratch_size;
-
- struct ilo_kernel_routing routing;
- struct ilo_state_ps_params_info ps_params;
-
- /* what does the push constant buffer consist of? */
- struct {
- int cbuf0_size;
- int clip_state_size;
- } pcb;
-
- /* binding table */
- struct {
- int rt_base, rt_count;
- int tex_base, tex_count;
- int const_base, const_count;
- int res_base, res_count;
-
- int gen6_so_base, gen6_so_count;
-
- int global_base, global_count;
-
- int total_count;
- } bt;
-
- struct list_head list;
-
- /* managed by shader cache */
- bool uploaded;
- uint32_t cache_offset;
-};
-
-/**
- * Information about a shader state.
- */
-struct ilo_shader_info {
- const struct ilo_dev *dev;
- int type;
-
- const struct tgsi_token *tokens;
-
- struct pipe_stream_output_info stream_output;
- struct {
- unsigned req_local_mem;
- unsigned req_private_mem;
- unsigned req_input_mem;
- } compute;
-
- uint32_t non_orthogonal_states;
-
- bool has_color_interp;
- bool has_pos;
- bool has_vertexid;
- bool has_instanceid;
- bool fs_color0_writes_all_cbufs;
-
- int edgeflag_in;
- int edgeflag_out;
-
- uint32_t shadow_samplers;
- int num_samplers;
-
- int constant_buffer_count;
-};
-
-/**
- * A shader state.
- */
-struct ilo_shader_state {
- struct ilo_shader_info info;
-
- struct list_head variants;
- int num_variants, total_size;
-
- struct ilo_shader *shader;
-
- /* managed by shader cache */
- struct ilo_shader_cache *cache;
- struct list_head list;
-};
-
-void
-ilo_shader_variant_init(struct ilo_shader_variant *variant,
- const struct ilo_shader_info *info,
- const struct ilo_state_vector *vec);
-
-bool
-ilo_shader_state_use_variant(struct ilo_shader_state *state,
- const struct ilo_shader_variant *variant);
-
-struct ilo_shader *
-ilo_shader_compile_vs(const struct ilo_shader_state *state,
- const struct ilo_shader_variant *variant);
-
-struct ilo_shader *
-ilo_shader_compile_gs(const struct ilo_shader_state *state,
- const struct ilo_shader_variant *variant);
-
-bool
-ilo_shader_compile_gs_passthrough(const struct ilo_shader_state *vs_state,
- const struct ilo_shader_variant *vs_variant,
- const int *so_mapping,
- struct ilo_shader *vs);
-
-struct ilo_shader *
-ilo_shader_compile_fs(const struct ilo_shader_state *state,
- const struct ilo_shader_variant *variant);
-
-struct ilo_shader *
-ilo_shader_compile_cs(const struct ilo_shader_state *state,
- const struct ilo_shader_variant *variant);
-
-static inline void
-ilo_shader_destroy_kernel(struct ilo_shader *sh)
-{
- FREE(sh->kernel);
- FREE(sh);
-}
-
-#endif /* ILO_SHADER_INTERNAL_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "tgsi/tgsi_dump.h"
-#include "tgsi/tgsi_util.h"
-#include "toy_compiler.h"
-#include "toy_tgsi.h"
-#include "toy_legalize.h"
-#include "toy_optimize.h"
-#include "toy_helpers.h"
-#include "ilo_shader_internal.h"
-
-struct vs_compile_context {
- struct ilo_shader *shader;
- const struct ilo_shader_variant *variant;
-
- struct toy_compiler tc;
- struct toy_tgsi tgsi;
- int const_cache;
-
- int output_map[PIPE_MAX_SHADER_OUTPUTS];
-
- int num_grf_per_vrf;
- int first_const_grf;
- int first_ucp_grf;
- int first_vue_grf;
- int first_free_grf;
- int last_free_grf;
-
- int first_free_mrf;
- int last_free_mrf;
-};
-
-static void
-vs_lower_opcode_tgsi_in(struct vs_compile_context *vcc,
- struct toy_dst dst, int dim, int idx)
-{
- struct toy_compiler *tc = &vcc->tc;
- int slot;
-
- assert(!dim);
-
- slot = toy_tgsi_find_input(&vcc->tgsi, idx);
- if (slot >= 0) {
- const int first_in_grf = vcc->first_vue_grf +
- (vcc->shader->in.count - vcc->tgsi.num_inputs);
- const int grf = first_in_grf + vcc->tgsi.inputs[slot].semantic_index;
- const struct toy_src src = tsrc(TOY_FILE_GRF, grf, 0);
-
- tc_MOV(tc, dst, src);
- }
- else {
- /* undeclared input */
- tc_MOV(tc, dst, tsrc_imm_f(0.0f));
- }
-}
-
-static bool
-vs_lower_opcode_tgsi_const_pcb(struct vs_compile_context *vcc,
- struct toy_dst dst, int dim,
- struct toy_src idx)
-{
- const int i = idx.val32;
- const int grf = vcc->first_const_grf + i / 2;
- const int grf_subreg = (i & 1) * 16;
- struct toy_src src;
-
- if (!vcc->variant->use_pcb || dim != 0 || idx.file != TOY_FILE_IMM ||
- grf >= vcc->first_ucp_grf)
- return false;
-
-
- src = tsrc_rect(tsrc(TOY_FILE_GRF, grf, grf_subreg), TOY_RECT_041);
- tc_MOV(&vcc->tc, dst, src);
-
- return true;
-}
-
-static void
-vs_lower_opcode_tgsi_const_gen6(struct vs_compile_context *vcc,
- struct toy_dst dst, int dim,
- struct toy_src idx)
-{
- const struct toy_dst header =
- tdst_ud(tdst(TOY_FILE_MRF, vcc->first_free_mrf, 0));
- const struct toy_dst block_offsets =
- tdst_ud(tdst(TOY_FILE_MRF, vcc->first_free_mrf + 1, 0));
- const struct toy_src r0 = tsrc_ud(tsrc(TOY_FILE_GRF, 0, 0));
- struct toy_compiler *tc = &vcc->tc;
- unsigned msg_type, msg_ctrl, msg_len;
- struct toy_inst *inst;
- struct toy_src desc;
-
- if (vs_lower_opcode_tgsi_const_pcb(vcc, dst, dim, idx))
- return;
-
- /* set message header */
- inst = tc_MOV(tc, header, r0);
- inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
-
- /* set block offsets */
- tc_MOV(tc, block_offsets, idx);
-
- msg_type = GEN6_MSG_DP_OWORD_DUAL_BLOCK_READ;
- msg_ctrl = GEN6_MSG_DP_OWORD_DUAL_BLOCK_SIZE_1;
- msg_len = 2;
-
- desc = tsrc_imm_mdesc_data_port(tc, false, msg_len, 1, true, false,
- msg_type, msg_ctrl, vcc->shader->bt.const_base + dim);
-
- tc_SEND(tc, dst, tsrc_from(header), desc, vcc->const_cache);
-}
-
-static void
-vs_lower_opcode_tgsi_const_gen7(struct vs_compile_context *vcc,
- struct toy_dst dst, int dim,
- struct toy_src idx)
-{
- struct toy_compiler *tc = &vcc->tc;
- const struct toy_dst offset =
- tdst_ud(tdst(TOY_FILE_MRF, vcc->first_free_mrf, 0));
- struct toy_src desc;
-
- if (vs_lower_opcode_tgsi_const_pcb(vcc, dst, dim, idx))
- return;
-
- /*
- * In 259b65e2e7938de4aab323033cfe2b33369ddb07, pull constant load was
- * changed from OWord Dual Block Read to ld to increase performance in the
- * classic driver. Since we use the constant cache instead of the data
- * cache, I wonder if we still want to follow the classic driver.
- */
-
- /* set offset */
- tc_MOV(tc, offset, idx);
-
- desc = tsrc_imm_mdesc_sampler(tc, 1, 1, false,
- GEN6_MSG_SAMPLER_SIMD4X2,
- GEN6_MSG_SAMPLER_LD,
- 0,
- vcc->shader->bt.const_base + dim);
-
- tc_SEND(tc, dst, tsrc_from(offset), desc, GEN6_SFID_SAMPLER);
-}
-
-static void
-vs_lower_opcode_tgsi_imm(struct vs_compile_context *vcc,
- struct toy_dst dst, int idx)
-{
- const uint32_t *imm;
- int ch;
-
- imm = toy_tgsi_get_imm(&vcc->tgsi, idx, NULL);
-
- for (ch = 0; ch < 4; ch++) {
- /* raw moves */
- tc_MOV(&vcc->tc,
- tdst_writemask(tdst_ud(dst), 1 << ch),
- tsrc_imm_ud(imm[ch]));
- }
-}
-
-
-static void
-vs_lower_opcode_tgsi_sv(struct vs_compile_context *vcc,
- struct toy_dst dst, int dim, int idx)
-{
- struct toy_compiler *tc = &vcc->tc;
- const struct toy_tgsi *tgsi = &vcc->tgsi;
- int slot;
-
- assert(!dim);
-
- slot = toy_tgsi_find_system_value(tgsi, idx);
- if (slot < 0)
- return;
-
- switch (tgsi->system_values[slot].semantic_name) {
- case TGSI_SEMANTIC_INSTANCEID:
- case TGSI_SEMANTIC_VERTEXID:
- /*
- * In 3DSTATE_VERTEX_ELEMENTS, we prepend an extra vertex element for
- * the generated IDs, with VID in the X channel and IID in the Y
- * channel.
- */
- {
- const int grf = vcc->first_vue_grf;
- const struct toy_src src = tsrc(TOY_FILE_GRF, grf, 0);
- const enum toy_swizzle swizzle =
- (tgsi->system_values[slot].semantic_name ==
- TGSI_SEMANTIC_INSTANCEID) ? TOY_SWIZZLE_Y : TOY_SWIZZLE_X;
-
- tc_MOV(tc, tdst_d(dst), tsrc_d(tsrc_swizzle1(src, swizzle)));
- }
- break;
- case TGSI_SEMANTIC_PRIMID:
- default:
- tc_fail(tc, "unhandled system value");
- tc_MOV(tc, dst, tsrc_imm_d(0));
- break;
- }
-}
-
-static void
-vs_lower_opcode_tgsi_direct(struct vs_compile_context *vcc,
- struct toy_inst *inst)
-{
- struct toy_compiler *tc = &vcc->tc;
- int dim, idx;
-
- assert(inst->src[0].file == TOY_FILE_IMM);
- dim = inst->src[0].val32;
-
- assert(inst->src[1].file == TOY_FILE_IMM);
- idx = inst->src[1].val32;
-
- switch (inst->opcode) {
- case TOY_OPCODE_TGSI_IN:
- vs_lower_opcode_tgsi_in(vcc, inst->dst, dim, idx);
- break;
- case TOY_OPCODE_TGSI_CONST:
- if (ilo_dev_gen(tc->dev) >= ILO_GEN(7))
- vs_lower_opcode_tgsi_const_gen7(vcc, inst->dst, dim, inst->src[1]);
- else
- vs_lower_opcode_tgsi_const_gen6(vcc, inst->dst, dim, inst->src[1]);
- break;
- case TOY_OPCODE_TGSI_SV:
- vs_lower_opcode_tgsi_sv(vcc, inst->dst, dim, idx);
- break;
- case TOY_OPCODE_TGSI_IMM:
- assert(!dim);
- vs_lower_opcode_tgsi_imm(vcc, inst->dst, idx);
- break;
- default:
- tc_fail(tc, "unhandled TGSI fetch");
- break;
- }
-
- tc_discard_inst(tc, inst);
-}
-
-static void
-vs_lower_opcode_tgsi_indirect(struct vs_compile_context *vcc,
- struct toy_inst *inst)
-{
- struct toy_compiler *tc = &vcc->tc;
- enum tgsi_file_type file;
- int dim, idx;
- struct toy_src indirect_dim, indirect_idx;
-
- assert(inst->src[0].file == TOY_FILE_IMM);
- file = inst->src[0].val32;
-
- assert(inst->src[1].file == TOY_FILE_IMM);
- dim = inst->src[1].val32;
- indirect_dim = inst->src[2];
-
- assert(inst->src[3].file == TOY_FILE_IMM);
- idx = inst->src[3].val32;
- indirect_idx = inst->src[4];
-
- /* no dimension indirection */
- assert(indirect_dim.file == TOY_FILE_IMM);
- dim += indirect_dim.val32;
-
- switch (inst->opcode) {
- case TOY_OPCODE_TGSI_INDIRECT_FETCH:
- if (file == TGSI_FILE_CONSTANT) {
- if (idx) {
- struct toy_dst tmp = tc_alloc_tmp(tc);
-
- tc_ADD(tc, tmp, indirect_idx, tsrc_imm_d(idx));
- indirect_idx = tsrc_from(tmp);
- }
-
- if (ilo_dev_gen(tc->dev) >= ILO_GEN(7))
- vs_lower_opcode_tgsi_const_gen7(vcc, inst->dst, dim, indirect_idx);
- else
- vs_lower_opcode_tgsi_const_gen6(vcc, inst->dst, dim, indirect_idx);
- break;
- }
- /* fall through */
- case TOY_OPCODE_TGSI_INDIRECT_STORE:
- default:
- tc_fail(tc, "unhandled TGSI indirection");
- break;
- }
-
- tc_discard_inst(tc, inst);
-}
-
-/**
- * Emit instructions to move sampling parameters to the message registers.
- */
-static int
-vs_add_sampler_params(struct toy_compiler *tc, int msg_type, int base_mrf,
- struct toy_src coords, int num_coords,
- struct toy_src bias_or_lod, struct toy_src ref_or_si,
- struct toy_src ddx, struct toy_src ddy, int num_derivs)
-{
- const unsigned coords_writemask = (1 << num_coords) - 1;
- struct toy_dst m[3];
- int num_params, i;
-
- assert(num_coords <= 4);
- assert(num_derivs <= 3 && num_derivs <= num_coords);
-
- for (i = 0; i < ARRAY_SIZE(m); i++)
- m[i] = tdst(TOY_FILE_MRF, base_mrf + i, 0);
-
- switch (msg_type) {
- case GEN6_MSG_SAMPLER_SAMPLE_L:
- tc_MOV(tc, tdst_writemask(m[0], coords_writemask), coords);
- tc_MOV(tc, tdst_writemask(m[1], TOY_WRITEMASK_X), bias_or_lod);
- num_params = 5;
- break;
- case GEN6_MSG_SAMPLER_SAMPLE_D:
- tc_MOV(tc, tdst_writemask(m[0], coords_writemask), coords);
- tc_MOV(tc, tdst_writemask(m[1], TOY_WRITEMASK_XZ),
- tsrc_swizzle(ddx, 0, 0, 1, 1));
- tc_MOV(tc, tdst_writemask(m[1], TOY_WRITEMASK_YW),
- tsrc_swizzle(ddy, 0, 0, 1, 1));
- if (num_derivs > 2) {
- tc_MOV(tc, tdst_writemask(m[2], TOY_WRITEMASK_X),
- tsrc_swizzle1(ddx, 2));
- tc_MOV(tc, tdst_writemask(m[2], TOY_WRITEMASK_Y),
- tsrc_swizzle1(ddy, 2));
- }
- num_params = 4 + num_derivs * 2;
- break;
- case GEN6_MSG_SAMPLER_SAMPLE_L_C:
- tc_MOV(tc, tdst_writemask(m[0], coords_writemask), coords);
- tc_MOV(tc, tdst_writemask(m[1], TOY_WRITEMASK_X), ref_or_si);
- tc_MOV(tc, tdst_writemask(m[1], TOY_WRITEMASK_Y), bias_or_lod);
- num_params = 6;
- break;
- case GEN6_MSG_SAMPLER_LD:
- assert(num_coords <= 3);
- tc_MOV(tc, tdst_writemask(tdst_d(m[0]), coords_writemask), coords);
- tc_MOV(tc, tdst_writemask(tdst_d(m[0]), TOY_WRITEMASK_W), bias_or_lod);
- if (ilo_dev_gen(tc->dev) >= ILO_GEN(7)) {
- num_params = 4;
- }
- else {
- tc_MOV(tc, tdst_writemask(tdst_d(m[1]), TOY_WRITEMASK_X), ref_or_si);
- num_params = 5;
- }
- break;
- case GEN6_MSG_SAMPLER_RESINFO:
- tc_MOV(tc, tdst_writemask(tdst_d(m[0]), TOY_WRITEMASK_X), bias_or_lod);
- num_params = 1;
- break;
- default:
- tc_fail(tc, "unknown sampler opcode");
- num_params = 0;
- break;
- }
-
- return (num_params + 3) / 4;
-}
-
-/**
- * Set up message registers and return the message descriptor for sampling.
- */
-static struct toy_src
-vs_prepare_tgsi_sampling(struct vs_compile_context *vcc,
- const struct toy_inst *inst,
- int base_mrf, unsigned *ret_sampler_index)
-{
- struct toy_compiler *tc = &vcc->tc;
- unsigned simd_mode, msg_type, msg_len, sampler_index, binding_table_index;
- struct toy_src coords, ddx, ddy, bias_or_lod, ref_or_si;
- int num_coords, ref_pos, num_derivs;
- int sampler_src;
-
- simd_mode = GEN6_MSG_SAMPLER_SIMD4X2;
-
- coords = inst->src[0];
- ddx = tsrc_null();
- ddy = tsrc_null();
- bias_or_lod = tsrc_null();
- ref_or_si = tsrc_null();
- num_derivs = 0;
- sampler_src = 1;
-
- num_coords = tgsi_util_get_texture_coord_dim(inst->tex.target);
- ref_pos = tgsi_util_get_shadow_ref_src_index(inst->tex.target);
-
- /* extract the parameters */
- switch (inst->opcode) {
- case TOY_OPCODE_TGSI_TXD:
- if (ref_pos >= 0) {
- assert(ref_pos < 4);
-
- msg_type = GEN7_MSG_SAMPLER_SAMPLE_D_C;
- ref_or_si = tsrc_swizzle1(coords, ref_pos);
-
- if (ilo_dev_gen(tc->dev) < ILO_GEN(7.5))
- tc_fail(tc, "TXD with shadow sampler not supported");
- }
- else {
- msg_type = GEN6_MSG_SAMPLER_SAMPLE_D;
- }
-
- ddx = inst->src[1];
- ddy = inst->src[2];
- num_derivs = num_coords;
- sampler_src = 3;
- break;
- case TOY_OPCODE_TGSI_TXL:
- if (ref_pos >= 0) {
- assert(ref_pos < 3);
-
- msg_type = GEN6_MSG_SAMPLER_SAMPLE_L_C;
- ref_or_si = tsrc_swizzle1(coords, ref_pos);
- }
- else {
- msg_type = GEN6_MSG_SAMPLER_SAMPLE_L;
- }
-
- bias_or_lod = tsrc_swizzle1(coords, TOY_SWIZZLE_W);
- break;
- case TOY_OPCODE_TGSI_TXF:
- msg_type = GEN6_MSG_SAMPLER_LD;
-
- switch (inst->tex.target) {
- case TGSI_TEXTURE_2D_MSAA:
- case TGSI_TEXTURE_2D_ARRAY_MSAA:
- assert(ref_pos >= 0 && ref_pos < 4);
- /* lod is always 0 */
- bias_or_lod = tsrc_imm_d(0);
- ref_or_si = tsrc_swizzle1(coords, ref_pos);
- break;
- default:
- bias_or_lod = tsrc_swizzle1(coords, TOY_SWIZZLE_W);
- break;
- }
-
- /* offset the coordinates */
- if (!tsrc_is_null(inst->tex.offsets[0])) {
- struct toy_dst tmp;
-
- tmp = tc_alloc_tmp(tc);
- tc_ADD(tc, tmp, coords, inst->tex.offsets[0]);
- coords = tsrc_from(tmp);
- }
-
- sampler_src = 1;
- break;
- case TOY_OPCODE_TGSI_TXQ:
- msg_type = GEN6_MSG_SAMPLER_RESINFO;
- num_coords = 0;
- bias_or_lod = tsrc_swizzle1(coords, TOY_SWIZZLE_X);
- break;
- case TOY_OPCODE_TGSI_TXQ_LZ:
- msg_type = GEN6_MSG_SAMPLER_RESINFO;
- num_coords = 0;
- sampler_src = 0;
- break;
- case TOY_OPCODE_TGSI_TXL2:
- if (ref_pos >= 0) {
- assert(ref_pos < 4);
-
- msg_type = GEN6_MSG_SAMPLER_SAMPLE_L_C;
- ref_or_si = tsrc_swizzle1(coords, ref_pos);
- }
- else {
- msg_type = GEN6_MSG_SAMPLER_SAMPLE_L;
- }
-
- bias_or_lod = tsrc_swizzle1(inst->src[1], TOY_SWIZZLE_X);
- sampler_src = 2;
- break;
- default:
- assert(!"unhandled sampling opcode");
- if (ret_sampler_index)
- *ret_sampler_index = 0;
- return tsrc_null();
- break;
- }
-
- assert(inst->src[sampler_src].file == TOY_FILE_IMM);
- sampler_index = inst->src[sampler_src].val32;
- binding_table_index = vcc->shader->bt.tex_base + sampler_index;
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 18:
- *
- * "Note that the (cube map) coordinates delivered to the sampling
- * engine must already have been divided by the component with the
- * largest absolute value."
- */
- switch (inst->tex.target) {
- case TGSI_TEXTURE_CUBE:
- case TGSI_TEXTURE_SHADOWCUBE:
- case TGSI_TEXTURE_CUBE_ARRAY:
- case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
- /* TXQ does not need coordinates */
- if (num_coords >= 3) {
- struct toy_dst tmp, max;
- struct toy_src abs_coords[3];
- unsigned i;
-
- tmp = tc_alloc_tmp(tc);
- max = tdst_writemask(tmp, TOY_WRITEMASK_W);
-
- for (i = 0; i < 3; i++)
- abs_coords[i] = tsrc_absolute(tsrc_swizzle1(coords, i));
-
- tc_SEL(tc, max, abs_coords[0], abs_coords[0], GEN6_COND_GE);
- tc_SEL(tc, max, tsrc_from(max), abs_coords[0], GEN6_COND_GE);
- tc_INV(tc, max, tsrc_from(max));
-
- for (i = 0; i < 3; i++)
- tc_MUL(tc, tdst_writemask(tmp, 1 << i), coords, tsrc_from(max));
-
- coords = tsrc_from(tmp);
- }
- break;
- }
-
- /* set up sampler parameters */
- msg_len = vs_add_sampler_params(tc, msg_type, base_mrf,
- coords, num_coords, bias_or_lod, ref_or_si, ddx, ddy, num_derivs);
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 136:
- *
- * "The maximum message length allowed to the sampler is 11. This would
- * disallow sample_d, sample_b_c, and sample_l_c with a SIMD Mode of
- * SIMD16."
- */
- if (msg_len > 11)
- tc_fail(tc, "maximum length for messages to the sampler is 11");
-
- if (ret_sampler_index)
- *ret_sampler_index = sampler_index;
-
- return tsrc_imm_mdesc_sampler(tc, msg_len, 1,
- false, simd_mode, msg_type, sampler_index, binding_table_index);
-}
-
-static void
-vs_lower_opcode_tgsi_sampling(struct vs_compile_context *vcc,
- struct toy_inst *inst)
-{
- struct toy_compiler *tc = &vcc->tc;
- struct toy_src desc;
- struct toy_dst dst, tmp;
- unsigned sampler_index;
- int swizzles[4], i;
- unsigned swizzle_zero_mask, swizzle_one_mask, swizzle_normal_mask;
- bool need_filter;
-
- desc = vs_prepare_tgsi_sampling(vcc, inst,
- vcc->first_free_mrf, &sampler_index);
-
- switch (inst->opcode) {
- case TOY_OPCODE_TGSI_TXF:
- case TOY_OPCODE_TGSI_TXQ:
- case TOY_OPCODE_TGSI_TXQ_LZ:
- need_filter = false;
- break;
- default:
- need_filter = true;
- break;
- }
-
- toy_compiler_lower_to_send(tc, inst, false, GEN6_SFID_SAMPLER);
- inst->src[0] = tsrc(TOY_FILE_MRF, vcc->first_free_mrf, 0);
- inst->src[1] = desc;
-
- /* write to a temp first */
- tmp = tc_alloc_tmp(tc);
- tmp.type = inst->dst.type;
- dst = inst->dst;
- inst->dst = tmp;
-
- tc_move_inst(tc, inst);
-
- if (need_filter) {
- assert(sampler_index < vcc->variant->num_sampler_views);
- swizzles[0] = vcc->variant->sampler_view_swizzles[sampler_index].r;
- swizzles[1] = vcc->variant->sampler_view_swizzles[sampler_index].g;
- swizzles[2] = vcc->variant->sampler_view_swizzles[sampler_index].b;
- swizzles[3] = vcc->variant->sampler_view_swizzles[sampler_index].a;
- }
- else {
- swizzles[0] = PIPE_SWIZZLE_X;
- swizzles[1] = PIPE_SWIZZLE_Y;
- swizzles[2] = PIPE_SWIZZLE_Z;
- swizzles[3] = PIPE_SWIZZLE_W;
- }
-
- swizzle_zero_mask = 0;
- swizzle_one_mask = 0;
- swizzle_normal_mask = 0;
- for (i = 0; i < 4; i++) {
- switch (swizzles[i]) {
- case PIPE_SWIZZLE_0:
- swizzle_zero_mask |= 1 << i;
- swizzles[i] = i;
- break;
- case PIPE_SWIZZLE_1:
- swizzle_one_mask |= 1 << i;
- swizzles[i] = i;
- break;
- default:
- swizzle_normal_mask |= 1 << i;
- break;
- }
- }
-
- /* swizzle the results */
- if (swizzle_normal_mask) {
- tc_MOV(tc, tdst_writemask(dst, swizzle_normal_mask),
- tsrc_swizzle(tsrc_from(tmp), swizzles[0],
- swizzles[1], swizzles[2], swizzles[3]));
- }
- if (swizzle_zero_mask)
- tc_MOV(tc, tdst_writemask(dst, swizzle_zero_mask), tsrc_imm_f(0.0f));
- if (swizzle_one_mask)
- tc_MOV(tc, tdst_writemask(dst, swizzle_one_mask), tsrc_imm_f(1.0f));
-}
-
-static void
-vs_lower_opcode_urb_write(struct toy_compiler *tc, struct toy_inst *inst)
-{
- /* vs_write_vue() has set up the message registers */
- toy_compiler_lower_to_send(tc, inst, false, GEN6_SFID_URB);
-}
-
-static void
-vs_lower_virtual_opcodes(struct vs_compile_context *vcc)
-{
- struct toy_compiler *tc = &vcc->tc;
- struct toy_inst *inst;
-
- tc_head(tc);
- while ((inst = tc_next(tc)) != NULL) {
- switch (inst->opcode) {
- case TOY_OPCODE_TGSI_IN:
- case TOY_OPCODE_TGSI_CONST:
- case TOY_OPCODE_TGSI_SV:
- case TOY_OPCODE_TGSI_IMM:
- vs_lower_opcode_tgsi_direct(vcc, inst);
- break;
- case TOY_OPCODE_TGSI_INDIRECT_FETCH:
- case TOY_OPCODE_TGSI_INDIRECT_STORE:
- vs_lower_opcode_tgsi_indirect(vcc, inst);
- break;
- case TOY_OPCODE_TGSI_TEX:
- case TOY_OPCODE_TGSI_TXB:
- case TOY_OPCODE_TGSI_TXD:
- case TOY_OPCODE_TGSI_TXL:
- case TOY_OPCODE_TGSI_TXP:
- case TOY_OPCODE_TGSI_TXF:
- case TOY_OPCODE_TGSI_TXQ:
- case TOY_OPCODE_TGSI_TXQ_LZ:
- case TOY_OPCODE_TGSI_TEX2:
- case TOY_OPCODE_TGSI_TXB2:
- case TOY_OPCODE_TGSI_TXL2:
- case TOY_OPCODE_TGSI_SAMPLE:
- case TOY_OPCODE_TGSI_SAMPLE_I:
- case TOY_OPCODE_TGSI_SAMPLE_I_MS:
- case TOY_OPCODE_TGSI_SAMPLE_B:
- case TOY_OPCODE_TGSI_SAMPLE_C:
- case TOY_OPCODE_TGSI_SAMPLE_C_LZ:
- case TOY_OPCODE_TGSI_SAMPLE_D:
- case TOY_OPCODE_TGSI_SAMPLE_L:
- case TOY_OPCODE_TGSI_GATHER4:
- case TOY_OPCODE_TGSI_SVIEWINFO:
- case TOY_OPCODE_TGSI_SAMPLE_POS:
- case TOY_OPCODE_TGSI_SAMPLE_INFO:
- vs_lower_opcode_tgsi_sampling(vcc, inst);
- break;
- case TOY_OPCODE_INV:
- case TOY_OPCODE_LOG:
- case TOY_OPCODE_EXP:
- case TOY_OPCODE_SQRT:
- case TOY_OPCODE_RSQ:
- case TOY_OPCODE_SIN:
- case TOY_OPCODE_COS:
- case TOY_OPCODE_FDIV:
- case TOY_OPCODE_POW:
- case TOY_OPCODE_INT_DIV_QUOTIENT:
- case TOY_OPCODE_INT_DIV_REMAINDER:
- toy_compiler_lower_math(tc, inst);
- break;
- case TOY_OPCODE_URB_WRITE:
- vs_lower_opcode_urb_write(tc, inst);
- break;
- default:
- if (inst->opcode > 127)
- tc_fail(tc, "unhandled virtual opcode");
- break;
- }
- }
-}
-
-/**
- * Compile the shader.
- */
-static bool
-vs_compile(struct vs_compile_context *vcc)
-{
- struct toy_compiler *tc = &vcc->tc;
- struct ilo_shader *sh = vcc->shader;
-
- vs_lower_virtual_opcodes(vcc);
- toy_compiler_legalize_for_ra(tc);
- toy_compiler_optimize(tc);
- toy_compiler_allocate_registers(tc,
- vcc->first_free_grf,
- vcc->last_free_grf,
- vcc->num_grf_per_vrf);
- toy_compiler_legalize_for_asm(tc);
-
- if (tc->fail) {
- ilo_err("failed to legalize VS instructions: %s\n", tc->reason);
- return false;
- }
-
- if (ilo_debug & ILO_DEBUG_VS) {
- ilo_printf("legalized instructions:\n");
- toy_compiler_dump(tc);
- ilo_printf("\n");
- }
-
- if (true) {
- sh->kernel = toy_compiler_assemble(tc, &sh->kernel_size);
- }
- else {
- static const uint32_t microcode[] = {
- /* fill in the microcode here */
- 0x0, 0x0, 0x0, 0x0,
- };
- const bool swap = true;
-
- sh->kernel_size = sizeof(microcode);
- sh->kernel = MALLOC(sh->kernel_size);
-
- if (sh->kernel) {
- const int num_dwords = sizeof(microcode) / 4;
- const uint32_t *src = microcode;
- uint32_t *dst = (uint32_t *) sh->kernel;
- int i;
-
- for (i = 0; i < num_dwords; i += 4) {
- if (swap) {
- dst[i + 0] = src[i + 3];
- dst[i + 1] = src[i + 2];
- dst[i + 2] = src[i + 1];
- dst[i + 3] = src[i + 0];
- }
- else {
- memcpy(dst, src, 16);
- }
- }
- }
- }
-
- if (!sh->kernel) {
- ilo_err("failed to compile VS: %s\n", tc->reason);
- return false;
- }
-
- if (ilo_debug & ILO_DEBUG_VS) {
- ilo_printf("disassembly:\n");
- toy_compiler_disassemble(tc->dev, sh->kernel, sh->kernel_size, false);
- ilo_printf("\n");
- }
-
- return true;
-}
-
-/**
- * Collect the toy registers to be written to the VUE.
- */
-static int
-vs_collect_outputs(struct vs_compile_context *vcc, struct toy_src *outs)
-{
- const struct toy_tgsi *tgsi = &vcc->tgsi;
- unsigned i;
-
- for (i = 0; i < vcc->shader->out.count; i++) {
- const int slot = vcc->output_map[i];
- const int vrf = (slot >= 0) ? toy_tgsi_get_vrf(tgsi,
- TGSI_FILE_OUTPUT, 0, tgsi->outputs[slot].index) : -1;
- struct toy_src src;
-
- if (vrf >= 0) {
- struct toy_dst dst;
-
- dst = tdst(TOY_FILE_VRF, vrf, 0);
- src = tsrc_from(dst);
-
- if (i == 0) {
- /* PSIZE is at channel W */
- tc_MOV(&vcc->tc, tdst_writemask(dst, TOY_WRITEMASK_W),
- tsrc_swizzle1(src, TOY_SWIZZLE_X));
-
- /* the other channels are for the header */
- dst = tdst_d(dst);
- tc_MOV(&vcc->tc, tdst_writemask(dst, TOY_WRITEMASK_XYZ),
- tsrc_imm_d(0));
- }
- else {
- /* initialize unused channels to 0.0f */
- if (tgsi->outputs[slot].undefined_mask) {
- dst = tdst_writemask(dst, tgsi->outputs[slot].undefined_mask);
- tc_MOV(&vcc->tc, dst, tsrc_imm_f(0.0f));
- }
- }
- }
- else {
- /* XXX this is too ugly */
- if (vcc->shader->out.semantic_names[i] == TGSI_SEMANTIC_CLIPDIST &&
- slot < 0) {
- /* ok, we need to compute clip distance */
- int clipvert_slot = -1, clipvert_vrf, j;
-
- for (j = 0; j < tgsi->num_outputs; j++) {
- if (tgsi->outputs[j].semantic_name ==
- TGSI_SEMANTIC_CLIPVERTEX) {
- clipvert_slot = j;
- break;
- }
- else if (tgsi->outputs[j].semantic_name ==
- TGSI_SEMANTIC_POSITION) {
- /* remember pos, but keep looking */
- clipvert_slot = j;
- }
- }
-
- clipvert_vrf = (clipvert_slot >= 0) ? toy_tgsi_get_vrf(tgsi,
- TGSI_FILE_OUTPUT, 0, tgsi->outputs[clipvert_slot].index) : -1;
- if (clipvert_vrf >= 0) {
- struct toy_dst tmp = tc_alloc_tmp(&vcc->tc);
- struct toy_src clipvert = tsrc(TOY_FILE_VRF, clipvert_vrf, 0);
- int first_ucp, last_ucp;
-
- if (vcc->shader->out.semantic_indices[i]) {
- first_ucp = 4;
- last_ucp = MIN2(7, vcc->variant->u.vs.num_ucps - 1);
- }
- else {
- first_ucp = 0;
- last_ucp = MIN2(3, vcc->variant->u.vs.num_ucps - 1);
- }
-
- for (j = first_ucp; j <= last_ucp; j++) {
- const int plane_grf = vcc->first_ucp_grf + j / 2;
- const int plane_subreg = (j & 1) * 16;
- const struct toy_src plane = tsrc_rect(tsrc(TOY_FILE_GRF,
- plane_grf, plane_subreg), TOY_RECT_041);
- const unsigned writemask = 1 << ((j >= 4) ? j - 4 : j);
-
- tc_DP4(&vcc->tc, tdst_writemask(tmp, writemask),
- clipvert, plane);
- }
-
- src = tsrc_from(tmp);
- }
- else {
- src = tsrc_imm_f(0.0f);
- }
- }
- else {
- src = (i == 0) ? tsrc_imm_d(0) : tsrc_imm_f(0.0f);
- }
- }
-
- outs[i] = src;
- }
-
- return i;
-}
-
-/**
- * Emit instructions to write the VUE.
- */
-static void
-vs_write_vue(struct vs_compile_context *vcc)
-{
- struct toy_compiler *tc = &vcc->tc;
- struct toy_src outs[PIPE_MAX_SHADER_OUTPUTS];
- struct toy_dst header;
- struct toy_src r0;
- struct toy_inst *inst;
- int sent_attrs, total_attrs;
-
- header = tdst_ud(tdst(TOY_FILE_MRF, vcc->first_free_mrf, 0));
- r0 = tsrc_ud(tsrc(TOY_FILE_GRF, 0, 0));
- inst = tc_MOV(tc, header, r0);
- inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
-
- if (ilo_dev_gen(tc->dev) >= ILO_GEN(7)) {
- inst = tc_OR(tc, tdst_offset(header, 0, 5),
- tsrc_rect(tsrc_offset(r0, 0, 5), TOY_RECT_010),
- tsrc_rect(tsrc_imm_ud(0xff00), TOY_RECT_010));
- inst->exec_size = GEN6_EXECSIZE_1;
- inst->access_mode = GEN6_ALIGN_1;
- inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
- }
-
- total_attrs = vs_collect_outputs(vcc, outs);
- sent_attrs = 0;
- while (sent_attrs < total_attrs) {
- struct toy_src desc;
- int mrf = vcc->first_free_mrf + 1, avail_mrf_for_attrs;
- int num_attrs, msg_len, i;
- bool eot;
-
- num_attrs = total_attrs - sent_attrs;
- eot = true;
-
- /* see if we need another message */
- avail_mrf_for_attrs = vcc->last_free_mrf - mrf + 1;
- if (num_attrs > avail_mrf_for_attrs) {
- /*
- * From the Sandy Bridge PRM, volume 4 part 2, page 22:
- *
- * "Offset. This field specifies a destination offset (in 256-bit
- * units) from the start of the URB entry(s), as referenced by
- * URB Return Handle n, at which the data (if any) will be
- * written."
- *
- * As we need to offset the following messages, we must make sure
- * this one writes an even number of attributes.
- */
- num_attrs = avail_mrf_for_attrs & ~1;
- eot = false;
- }
-
- if (ilo_dev_gen(tc->dev) >= ILO_GEN(7)) {
- /* do not forget about the header */
- msg_len = 1 + num_attrs;
- }
- else {
- /*
- * From the Sandy Bridge PRM, volume 4 part 2, page 26:
- *
- * "At least 256 bits per vertex (512 bits total, M1 & M2) must
- * be written. Writing only 128 bits per vertex (256 bits
- * total, M1 only) results in UNDEFINED operation."
- *
- * "[DevSNB] Interleave writes must be in multiples of 256 per
- * vertex."
- *
- * That is, we must write or appear to write an even number of
- * attributes, starting from two.
- */
- if (num_attrs % 2 && num_attrs == avail_mrf_for_attrs) {
- num_attrs--;
- eot = false;
- }
-
- msg_len = 1 + align(num_attrs, 2);
- }
-
- for (i = 0; i < num_attrs; i++)
- tc_MOV(tc, tdst(TOY_FILE_MRF, mrf++, 0), outs[sent_attrs + i]);
-
- assert(sent_attrs % 2 == 0);
- desc = tsrc_imm_mdesc_urb(tc, eot, msg_len, 0,
- eot, true, false, true, sent_attrs / 2, 0);
-
- tc_add2(tc, TOY_OPCODE_URB_WRITE, tdst_null(), tsrc_from(header), desc);
-
- sent_attrs += num_attrs;
- }
-}
-
-/**
- * Set up shader inputs for fixed-function units.
- */
-static void
-vs_setup_shader_in(struct ilo_shader *sh, const struct toy_tgsi *tgsi)
-{
- int num_attrs, i;
-
- /* vertex/instance id is the first VE if exists */
- for (i = 0; i < tgsi->num_system_values; i++) {
- bool found = false;
-
- switch (tgsi->system_values[i].semantic_name) {
- case TGSI_SEMANTIC_INSTANCEID:
- case TGSI_SEMANTIC_VERTEXID:
- found = true;
- break;
- default:
- break;
- }
-
- if (found) {
- sh->in.semantic_names[sh->in.count] =
- tgsi->system_values[i].semantic_name;
- sh->in.semantic_indices[sh->in.count] =
- tgsi->system_values[i].semantic_index;
- sh->in.interp[sh->in.count] = TGSI_INTERPOLATE_CONSTANT;
- sh->in.centroid[sh->in.count] = false;
-
- sh->in.count++;
- break;
- }
- }
-
- num_attrs = 0;
- for (i = 0; i < tgsi->num_inputs; i++) {
- assert(tgsi->inputs[i].semantic_name == TGSI_SEMANTIC_GENERIC);
- if (tgsi->inputs[i].semantic_index >= num_attrs)
- num_attrs = tgsi->inputs[i].semantic_index + 1;
- }
- assert(num_attrs <= PIPE_MAX_ATTRIBS);
-
- /* VF cannot remap VEs. VE[i] must be used as GENERIC[i]. */
- for (i = 0; i < num_attrs; i++) {
- sh->in.semantic_names[sh->in.count + i] = TGSI_SEMANTIC_GENERIC;
- sh->in.semantic_indices[sh->in.count + i] = i;
- sh->in.interp[sh->in.count + i] = TGSI_INTERPOLATE_CONSTANT;
- sh->in.centroid[sh->in.count + i] = false;
- }
-
- sh->in.count += num_attrs;
-
- sh->in.has_pos = false;
- sh->in.has_linear_interp = false;
- sh->in.barycentric_interpolation_mode = 0;
-}
-
-/**
- * Set up shader outputs for fixed-function units.
- */
-static void
-vs_setup_shader_out(struct ilo_shader *sh, const struct toy_tgsi *tgsi,
- bool output_clipdist, int *output_map)
-{
- int psize_slot = -1, pos_slot = -1;
- int clipdist_slot[2] = { -1, -1 };
- int color_slot[4] = { -1, -1, -1, -1 };
- int num_outs, i;
-
- /* find out the slots of outputs that need special care */
- for (i = 0; i < tgsi->num_outputs; i++) {
- switch (tgsi->outputs[i].semantic_name) {
- case TGSI_SEMANTIC_PSIZE:
- psize_slot = i;
- break;
- case TGSI_SEMANTIC_POSITION:
- pos_slot = i;
- break;
- case TGSI_SEMANTIC_CLIPDIST:
- if (tgsi->outputs[i].semantic_index)
- clipdist_slot[1] = i;
- else
- clipdist_slot[0] = i;
- break;
- case TGSI_SEMANTIC_COLOR:
- if (tgsi->outputs[i].semantic_index)
- color_slot[2] = i;
- else
- color_slot[0] = i;
- break;
- case TGSI_SEMANTIC_BCOLOR:
- if (tgsi->outputs[i].semantic_index)
- color_slot[3] = i;
- else
- color_slot[1] = i;
- break;
- default:
- break;
- }
- }
-
- /* the first two VUEs are always PSIZE and POSITION */
- num_outs = 2;
- output_map[0] = psize_slot;
- output_map[1] = pos_slot;
-
- sh->out.register_indices[0] =
- (psize_slot >= 0) ? tgsi->outputs[psize_slot].index : -1;
- sh->out.semantic_names[0] = TGSI_SEMANTIC_PSIZE;
- sh->out.semantic_indices[0] = 0;
-
- sh->out.register_indices[1] =
- (pos_slot >= 0) ? tgsi->outputs[pos_slot].index : -1;
- sh->out.semantic_names[1] = TGSI_SEMANTIC_POSITION;
- sh->out.semantic_indices[1] = 0;
-
- sh->out.has_pos = true;
-
- /* followed by optional clip distances */
- if (output_clipdist) {
- sh->out.register_indices[num_outs] =
- (clipdist_slot[0] >= 0) ? tgsi->outputs[clipdist_slot[0]].index : -1;
- sh->out.semantic_names[num_outs] = TGSI_SEMANTIC_CLIPDIST;
- sh->out.semantic_indices[num_outs] = 0;
- output_map[num_outs++] = clipdist_slot[0];
-
- sh->out.register_indices[num_outs] =
- (clipdist_slot[1] >= 0) ? tgsi->outputs[clipdist_slot[1]].index : -1;
- sh->out.semantic_names[num_outs] = TGSI_SEMANTIC_CLIPDIST;
- sh->out.semantic_indices[num_outs] = 1;
- output_map[num_outs++] = clipdist_slot[1];
- }
-
- /*
- * make BCOLOR follow COLOR so that we can make use of
- * ATTRIBUTE_SWIZZLE_INPUTATTR_FACING in 3DSTATE_SF
- */
- for (i = 0; i < 4; i++) {
- const int slot = color_slot[i];
-
- if (slot < 0)
- continue;
-
- sh->out.register_indices[num_outs] = tgsi->outputs[slot].index;
- sh->out.semantic_names[num_outs] = tgsi->outputs[slot].semantic_name;
- sh->out.semantic_indices[num_outs] = tgsi->outputs[slot].semantic_index;
-
- output_map[num_outs++] = slot;
- }
-
- /* add the rest of the outputs */
- for (i = 0; i < tgsi->num_outputs; i++) {
- switch (tgsi->outputs[i].semantic_name) {
- case TGSI_SEMANTIC_PSIZE:
- case TGSI_SEMANTIC_POSITION:
- case TGSI_SEMANTIC_CLIPDIST:
- case TGSI_SEMANTIC_COLOR:
- case TGSI_SEMANTIC_BCOLOR:
- break;
- default:
- sh->out.register_indices[num_outs] = tgsi->outputs[i].index;
- sh->out.semantic_names[num_outs] = tgsi->outputs[i].semantic_name;
- sh->out.semantic_indices[num_outs] = tgsi->outputs[i].semantic_index;
- output_map[num_outs++] = i;
- break;
- }
- }
-
- sh->out.count = num_outs;
-}
-
-/**
- * Translate the TGSI tokens.
- */
-static bool
-vs_setup_tgsi(struct toy_compiler *tc, const struct tgsi_token *tokens,
- struct toy_tgsi *tgsi)
-{
- if (ilo_debug & ILO_DEBUG_VS) {
- ilo_printf("dumping vertex shader\n");
- ilo_printf("\n");
-
- tgsi_dump(tokens, 0);
- ilo_printf("\n");
- }
-
- toy_compiler_translate_tgsi(tc, tokens, true, tgsi);
- if (tc->fail) {
- ilo_err("failed to translate VS TGSI tokens: %s\n", tc->reason);
- return false;
- }
-
- if (ilo_debug & ILO_DEBUG_VS) {
- ilo_printf("TGSI translator:\n");
- toy_tgsi_dump(tgsi);
- ilo_printf("\n");
- toy_compiler_dump(tc);
- ilo_printf("\n");
- }
-
- return true;
-}
-
-/**
- * Set up VS compile context. This includes translating the TGSI tokens.
- */
-static bool
-vs_setup(struct vs_compile_context *vcc,
- const struct ilo_shader_state *state,
- const struct ilo_shader_variant *variant)
-{
- int num_consts;
-
- memset(vcc, 0, sizeof(*vcc));
-
- vcc->shader = CALLOC_STRUCT(ilo_shader);
- if (!vcc->shader)
- return false;
-
- vcc->variant = variant;
-
- toy_compiler_init(&vcc->tc, state->info.dev);
- vcc->tc.templ.access_mode = GEN6_ALIGN_16;
- vcc->tc.templ.exec_size = GEN6_EXECSIZE_8;
- vcc->tc.rect_linear_width = 4;
-
- /*
- * The classic driver uses the sampler cache (gen6) or the data cache
- * (gen7). Why?
- */
- vcc->const_cache = GEN6_SFID_DP_CC;
-
- if (!vs_setup_tgsi(&vcc->tc, state->info.tokens, &vcc->tgsi)) {
- toy_compiler_cleanup(&vcc->tc);
- FREE(vcc->shader);
- return false;
- }
-
- vs_setup_shader_in(vcc->shader, &vcc->tgsi);
- vs_setup_shader_out(vcc->shader, &vcc->tgsi,
- (vcc->variant->u.vs.num_ucps > 0), vcc->output_map);
-
- if (vcc->variant->use_pcb && !vcc->tgsi.const_indirect) {
- num_consts = (vcc->tgsi.const_count + 1) / 2;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 138:
- *
- * "The sum of all four read length fields (each incremented to
- * represent the actual read length) must be less than or equal to
- * 32"
- */
- if (num_consts > 32)
- num_consts = 0;
- }
- else {
- num_consts = 0;
- }
-
- vcc->shader->skip_cbuf0_upload = (!vcc->tgsi.const_count || num_consts);
- vcc->shader->pcb.cbuf0_size = num_consts * (sizeof(float) * 8);
-
- /* r0 is reserved for payload header */
- vcc->first_const_grf = 1;
- vcc->first_ucp_grf = vcc->first_const_grf + num_consts;
-
- /* fit each pair of user clip planes into a register */
- vcc->first_vue_grf = vcc->first_ucp_grf +
- (vcc->variant->u.vs.num_ucps + 1) / 2;
-
- vcc->first_free_grf = vcc->first_vue_grf + vcc->shader->in.count;
- vcc->last_free_grf = 127;
-
- /* m0 is reserved for system routines */
- vcc->first_free_mrf = 1;
- vcc->last_free_mrf = 15;
-
- vcc->num_grf_per_vrf = 1;
-
- if (ilo_dev_gen(vcc->tc.dev) >= ILO_GEN(7)) {
- vcc->last_free_grf -= 15;
- vcc->first_free_mrf = vcc->last_free_grf + 1;
- vcc->last_free_mrf = vcc->first_free_mrf + 14;
- }
-
- vcc->shader->in.start_grf = vcc->first_const_grf;
- vcc->shader->pcb.clip_state_size =
- vcc->variant->u.vs.num_ucps * (sizeof(float) * 4);
-
- vcc->shader->bt.tex_base = 0;
- vcc->shader->bt.tex_count = vcc->variant->num_sampler_views;
-
- vcc->shader->bt.const_base = vcc->shader->bt.tex_base +
- vcc->shader->bt.tex_count;
- vcc->shader->bt.const_count = state->info.constant_buffer_count;
-
- vcc->shader->bt.total_count = vcc->shader->bt.const_base +
- vcc->shader->bt.const_count;
-
- return true;
-}
-
-/**
- * Compile the vertex shader.
- */
-struct ilo_shader *
-ilo_shader_compile_vs(const struct ilo_shader_state *state,
- const struct ilo_shader_variant *variant)
-{
- struct vs_compile_context vcc;
- bool need_gs;
-
- if (!vs_setup(&vcc, state, variant))
- return NULL;
-
- if (ilo_dev_gen(vcc.tc.dev) >= ILO_GEN(7)) {
- need_gs = false;
- }
- else {
- need_gs = variant->u.vs.rasterizer_discard ||
- state->info.stream_output.num_outputs;
- }
-
- vs_write_vue(&vcc);
-
- if (!vs_compile(&vcc)) {
- FREE(vcc.shader);
- vcc.shader = NULL;
- }
-
- toy_tgsi_cleanup(&vcc.tgsi);
- toy_compiler_cleanup(&vcc.tc);
-
- if (need_gs) {
- int so_mapping[PIPE_MAX_SHADER_OUTPUTS];
- int i, j;
-
- for (i = 0; i < vcc.tgsi.num_outputs; i++) {
- int attr = 0;
-
- for (j = 0; j < vcc.shader->out.count; j++) {
- if (vcc.tgsi.outputs[i].semantic_name ==
- vcc.shader->out.semantic_names[j] &&
- vcc.tgsi.outputs[i].semantic_index ==
- vcc.shader->out.semantic_indices[j]) {
- attr = j;
- break;
- }
- }
-
- so_mapping[i] = attr;
- }
-
- if (!ilo_shader_compile_gs_passthrough(state, variant,
- so_mapping, vcc.shader)) {
- ilo_shader_destroy_kernel(vcc.shader);
- vcc.shader = NULL;
- }
- }
-
- return vcc.shader;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "toy_compiler.h"
-
-/**
- * Dump an operand.
- */
-static void
-tc_dump_operand(struct toy_compiler *tc,
- enum toy_file file, enum toy_type type, enum toy_rect rect,
- bool indirect, unsigned indirect_subreg, uint32_t val32,
- bool is_dst)
-{
- static const char *toy_file_names[TOY_FILE_COUNT] = {
- [TOY_FILE_VRF] = "v",
- [TOY_FILE_ARF] = "NOT USED",
- [TOY_FILE_GRF] = "r",
- [TOY_FILE_MRF] = "m",
- [TOY_FILE_IMM] = "NOT USED",
- };
- const char *name = toy_file_names[file];
- int reg, subreg;
-
- if (file != TOY_FILE_IMM) {
- reg = val32 / TOY_REG_WIDTH;
- subreg = (val32 % TOY_REG_WIDTH) / toy_type_size(type);
- }
-
- switch (file) {
- case TOY_FILE_GRF:
- if (indirect) {
- const int addr_subreg = indirect_subreg / toy_type_size(TOY_TYPE_UW);
-
- ilo_printf("%s[a0.%d", name, addr_subreg);
- if (val32)
- ilo_printf("%+d", (int) val32);
- ilo_printf("]");
- break;
- }
- /* fall through */
- case TOY_FILE_VRF:
- case TOY_FILE_MRF:
- ilo_printf("%s%d", name, reg);
- if (subreg)
- ilo_printf(".%d", subreg);
- break;
- case TOY_FILE_ARF:
- switch (reg) {
- case GEN6_ARF_NULL:
- ilo_printf("null");
- break;
- case GEN6_ARF_A0:
- ilo_printf("a0.%d", subreg);
- break;
- case GEN6_ARF_ACC0:
- case GEN6_ARF_ACC0 + 1:
- ilo_printf("acc%d.%d", (reg & 1), subreg);
- break;
- case GEN6_ARF_F0:
- ilo_printf("f0.%d", subreg);
- break;
- case GEN6_ARF_SR0:
- ilo_printf("sr0.%d", subreg);
- break;
- case GEN6_ARF_CR0:
- ilo_printf("cr0.%d", subreg);
- break;
- case GEN6_ARF_N0:
- case GEN6_ARF_N0 + 1:
- ilo_printf("n%d.%d", (reg & 1), subreg);
- break;
- case GEN6_ARF_IP:
- ilo_printf("ip");
- break;
- }
- break;
- case TOY_FILE_IMM:
- switch (type) {
- case TOY_TYPE_F:
- {
- union fi fi = { .ui = val32 };
- ilo_printf("%f", fi.f);
- }
- break;
- case TOY_TYPE_D:
- ilo_printf("%d", (int32_t) val32);
- break;
- case TOY_TYPE_UD:
- ilo_printf("%u", val32);
- break;
- case TOY_TYPE_W:
- ilo_printf("%d", (int16_t) (val32 & 0xffff));
- break;
- case TOY_TYPE_UW:
- ilo_printf("%u", val32 & 0xffff);
- break;
- case TOY_TYPE_V:
- ilo_printf("0x%08x", val32);
- break;
- default:
- assert(!"unknown imm type");
- break;
- }
- break;
- default:
- assert(!"unexpected file");
- break;
- }
-
- /* dump the region parameter */
- if (file != TOY_FILE_IMM) {
- int vert_stride, width, horz_stride;
-
- switch (rect) {
- case TOY_RECT_LINEAR:
- vert_stride = tc->rect_linear_width;
- width = tc->rect_linear_width;
- horz_stride = 1;
- break;
- case TOY_RECT_041:
- vert_stride = 0;
- width = 4;
- horz_stride = 1;
- break;
- case TOY_RECT_010:
- vert_stride = 0;
- width = 1;
- horz_stride = 0;
- break;
- case TOY_RECT_220:
- vert_stride = 2;
- width = 2;
- horz_stride = 0;
- break;
- case TOY_RECT_440:
- vert_stride = 4;
- width = 4;
- horz_stride = 0;
- break;
- case TOY_RECT_240:
- vert_stride = 2;
- width = 4;
- horz_stride = 0;
- break;
- default:
- assert(!"unknown rect parameter");
- vert_stride = 0;
- width = 0;
- horz_stride = 0;
- break;
- }
-
- if (is_dst)
- ilo_printf("<%d>", horz_stride);
- else
- ilo_printf("<%d;%d,%d>", vert_stride, width, horz_stride);
- }
-
- switch (type) {
- case TOY_TYPE_F:
- ilo_printf(":f");
- break;
- case TOY_TYPE_D:
- ilo_printf(":d");
- break;
- case TOY_TYPE_UD:
- ilo_printf(":ud");
- break;
- case TOY_TYPE_W:
- ilo_printf(":w");
- break;
- case TOY_TYPE_UW:
- ilo_printf(":uw");
- break;
- case TOY_TYPE_V:
- ilo_printf(":v");
- break;
- default:
- assert(!"unexpected type");
- break;
- }
-}
-
-/**
- * Dump a source operand.
- */
-static void
-tc_dump_src(struct toy_compiler *tc, struct toy_src src)
-{
- if (src.negate)
- ilo_printf("-");
- if (src.absolute)
- ilo_printf("|");
-
- tc_dump_operand(tc, src.file, src.type, src.rect,
- src.indirect, src.indirect_subreg, src.val32, false);
-
- if (tsrc_is_swizzled(src)) {
- const char xyzw[] = "xyzw";
- ilo_printf(".%c%c%c%c",
- xyzw[src.swizzle_x],
- xyzw[src.swizzle_y],
- xyzw[src.swizzle_z],
- xyzw[src.swizzle_w]);
- }
-
- if (src.absolute)
- ilo_printf("|");
-}
-
-/**
- * Dump a destination operand.
- */
-static void
-tc_dump_dst(struct toy_compiler *tc, struct toy_dst dst)
-{
- tc_dump_operand(tc, dst.file, dst.type, dst.rect,
- dst.indirect, dst.indirect_subreg, dst.val32, true);
-
- if (dst.writemask != TOY_WRITEMASK_XYZW) {
- ilo_printf(".");
- if (dst.writemask & TOY_WRITEMASK_X)
- ilo_printf("x");
- if (dst.writemask & TOY_WRITEMASK_Y)
- ilo_printf("y");
- if (dst.writemask & TOY_WRITEMASK_Z)
- ilo_printf("z");
- if (dst.writemask & TOY_WRITEMASK_W)
- ilo_printf("w");
- }
-}
-
-static const char *
-get_opcode_name(unsigned opcode)
-{
- switch (opcode) {
- case GEN6_OPCODE_MOV: return "mov";
- case GEN6_OPCODE_SEL: return "sel";
- case GEN6_OPCODE_NOT: return "not";
- case GEN6_OPCODE_AND: return "and";
- case GEN6_OPCODE_OR: return "or";
- case GEN6_OPCODE_XOR: return "xor";
- case GEN6_OPCODE_SHR: return "shr";
- case GEN6_OPCODE_SHL: return "shl";
- case 0xa: return "rsr";
- case 0xb: return "rsl";
- case GEN6_OPCODE_ASR: return "asr";
- case GEN6_OPCODE_CMP: return "cmp";
- case GEN6_OPCODE_CMPN: return "cmpn";
- case GEN6_OPCODE_JMPI: return "jmpi";
- case GEN6_OPCODE_IF: return "if";
- case 0x23: return "iff";
- case GEN6_OPCODE_ELSE: return "else";
- case GEN6_OPCODE_ENDIF: return "endif";
- case 0x26: return "do";
- case GEN6_OPCODE_WHILE: return "while";
- case GEN6_OPCODE_BREAK: return "break";
- case GEN6_OPCODE_CONT: return "continue";
- case GEN6_OPCODE_HALT: return "halt";
- case 0x2c: return "msave";
- case 0x2d: return "mrestore";
- case 0x2e: return "push";
- case 0x2f: return "pop";
- case GEN6_OPCODE_WAIT: return "wait";
- case GEN6_OPCODE_SEND: return "send";
- case GEN6_OPCODE_SENDC: return "sendc";
- case GEN6_OPCODE_MATH: return "math";
- case GEN6_OPCODE_ADD: return "add";
- case GEN6_OPCODE_MUL: return "mul";
- case GEN6_OPCODE_AVG: return "avg";
- case GEN6_OPCODE_FRC: return "frc";
- case GEN6_OPCODE_RNDU: return "rndu";
- case GEN6_OPCODE_RNDD: return "rndd";
- case GEN6_OPCODE_RNDE: return "rnde";
- case GEN6_OPCODE_RNDZ: return "rndz";
- case GEN6_OPCODE_MAC: return "mac";
- case GEN6_OPCODE_MACH: return "mach";
- case GEN6_OPCODE_LZD: return "lzd";
- case GEN6_OPCODE_SAD2: return "sad2";
- case GEN6_OPCODE_SADA2: return "sada2";
- case GEN6_OPCODE_DP4: return "dp4";
- case GEN6_OPCODE_DPH: return "dph";
- case GEN6_OPCODE_DP3: return "dp3";
- case GEN6_OPCODE_DP2: return "dp2";
- case 0x58: return "dpa2";
- case GEN6_OPCODE_LINE: return "line";
- case GEN6_OPCODE_PLN: return "pln";
- case GEN6_OPCODE_MAD: return "mad";
- case GEN6_OPCODE_NOP: return "nop";
- case TOY_OPCODE_DO: return "do";
- /* TGSI */
- case TOY_OPCODE_TGSI_IN: return "tgsi.in";
- case TOY_OPCODE_TGSI_CONST: return "tgsi.const";
- case TOY_OPCODE_TGSI_SV: return "tgsi.sv";
- case TOY_OPCODE_TGSI_IMM: return "tgsi.imm";
- case TOY_OPCODE_TGSI_INDIRECT_FETCH: return "tgsi.indirect_fetch";
- case TOY_OPCODE_TGSI_INDIRECT_STORE: return "tgsi.indirect_store";
- case TOY_OPCODE_TGSI_TEX: return "tgsi.tex";
- case TOY_OPCODE_TGSI_TXB: return "tgsi.txb";
- case TOY_OPCODE_TGSI_TXD: return "tgsi.txd";
- case TOY_OPCODE_TGSI_TXL: return "tgsi.txl";
- case TOY_OPCODE_TGSI_TXP: return "tgsi.txp";
- case TOY_OPCODE_TGSI_TXF: return "tgsi.txf";
- case TOY_OPCODE_TGSI_TXQ: return "tgsi.txq";
- case TOY_OPCODE_TGSI_TXQ_LZ: return "tgsi.txq_lz";
- case TOY_OPCODE_TGSI_TEX2: return "tgsi.tex2";
- case TOY_OPCODE_TGSI_TXB2: return "tgsi.txb2";
- case TOY_OPCODE_TGSI_TXL2: return "tgsi.txl2";
- case TOY_OPCODE_TGSI_SAMPLE: return "tgsi.sample";
- case TOY_OPCODE_TGSI_SAMPLE_I: return "tgsi.sample_i";
- case TOY_OPCODE_TGSI_SAMPLE_I_MS: return "tgsi.sample_i_ms";
- case TOY_OPCODE_TGSI_SAMPLE_B: return "tgsi.sample_b";
- case TOY_OPCODE_TGSI_SAMPLE_C: return "tgsi.sample_c";
- case TOY_OPCODE_TGSI_SAMPLE_C_LZ: return "tgsi.sample_c_lz";
- case TOY_OPCODE_TGSI_SAMPLE_D: return "tgsi.sample_d";
- case TOY_OPCODE_TGSI_SAMPLE_L: return "tgsi.sample_l";
- case TOY_OPCODE_TGSI_GATHER4: return "tgsi.gather4";
- case TOY_OPCODE_TGSI_SVIEWINFO: return "tgsi.sviewinfo";
- case TOY_OPCODE_TGSI_SAMPLE_POS: return "tgsi.sample_pos";
- case TOY_OPCODE_TGSI_SAMPLE_INFO: return "tgsi.sample_info";
- /* math */
- case TOY_OPCODE_INV: return "math.inv";
- case TOY_OPCODE_LOG: return "math.log";
- case TOY_OPCODE_EXP: return "math.exp";
- case TOY_OPCODE_SQRT: return "math.sqrt";
- case TOY_OPCODE_RSQ: return "math.rsq";
- case TOY_OPCODE_SIN: return "math.sin";
- case TOY_OPCODE_COS: return "math.cos";
- case TOY_OPCODE_FDIV: return "math.fdiv";
- case TOY_OPCODE_POW: return "math.pow";
- case TOY_OPCODE_INT_DIV_QUOTIENT: return "math.int_div_quotient";
- case TOY_OPCODE_INT_DIV_REMAINDER: return "math.int_div_remainer";
- /* urb */
- case TOY_OPCODE_URB_WRITE: return "urb.urb_write";
- /* gs */
- case TOY_OPCODE_EMIT: return "gs.emit";
- case TOY_OPCODE_ENDPRIM: return "gs.endprim";
- /* fs */
- case TOY_OPCODE_DDX: return "fs.ddx";
- case TOY_OPCODE_DDY: return "fs.ddy";
- case TOY_OPCODE_FB_WRITE: return "fs.fb_write";
- case TOY_OPCODE_KIL: return "fs.kil";
- default: return "unk";
- }
-}
-
-static const char *
-get_cond_modifier_name(unsigned opcode, unsigned cond_modifier)
-{
- switch (opcode) {
- case GEN6_OPCODE_SEND:
- case GEN6_OPCODE_SENDC:
- /* SFID */
- switch (cond_modifier) {
- case GEN6_SFID_NULL: return "Null";
- case GEN6_SFID_SAMPLER: return "Sampling Engine";
- case GEN6_SFID_GATEWAY: return "Message Gateway";
- case GEN6_SFID_DP_SAMPLER: return "Data Port Sampler Cache";
- case GEN6_SFID_DP_RC: return "Data Port Render Cache";
- case GEN6_SFID_URB: return "URB";
- case GEN6_SFID_SPAWNER: return "Thread Spawner";
- case GEN6_SFID_DP_CC: return "Constant Cache";
- default: return "Unknown";
- }
- break;
- case GEN6_OPCODE_MATH:
- /* FC */
- switch (cond_modifier) {
- case GEN6_MATH_INV: return "INV";
- case GEN6_MATH_LOG: return "LOG";
- case GEN6_MATH_EXP: return "EXP";
- case GEN6_MATH_SQRT: return "SQRT";
- case GEN6_MATH_RSQ: return "RSQ";
- case GEN6_MATH_SIN: return "SIN";
- case GEN6_MATH_COS: return "COS";
- case GEN6_MATH_FDIV: return "FDIV";
- case GEN6_MATH_POW: return "POW";
- case GEN6_MATH_INT_DIV_QUOTIENT: return "INT DIV (quotient)";
- case GEN6_MATH_INT_DIV_REMAINDER: return "INT DIV (remainder)";
- default: return "UNK";
- }
- break;
- default:
- switch (cond_modifier) {
- case GEN6_COND_NONE: return NULL;
- case GEN6_COND_Z: return "z";
- case GEN6_COND_NZ: return "nz";
- case GEN6_COND_G: return "g";
- case GEN6_COND_GE: return "ge";
- case GEN6_COND_L: return "l";
- case GEN6_COND_LE: return "le";
- default: return "unk";
- }
- break;
- }
-}
-
-/**
- * Dump an instruction.
- */
-static void
-tc_dump_inst(struct toy_compiler *tc, const struct toy_inst *inst)
-{
- const char *name;
- int i;
-
- name = get_opcode_name(inst->opcode);
-
- ilo_printf(" %s", name);
-
- if (inst->opcode == GEN6_OPCODE_NOP) {
- ilo_printf("\n");
- return;
- }
-
- if (inst->saturate)
- ilo_printf(".sat");
-
- name = get_cond_modifier_name(inst->opcode, inst->cond_modifier);
- if (name)
- ilo_printf(".%s", name);
-
- ilo_printf(" ");
-
- tc_dump_dst(tc, inst->dst);
-
- for (i = 0; i < ARRAY_SIZE(inst->src); i++) {
- if (tsrc_is_null(inst->src[i]))
- break;
-
- ilo_printf(", ");
- tc_dump_src(tc, inst->src[i]);
- }
-
- ilo_printf("\n");
-}
-
-/**
- * Dump the instructions added to the compiler.
- */
-void
-toy_compiler_dump(struct toy_compiler *tc)
-{
- struct toy_inst *inst;
- int pc;
-
- pc = 0;
- tc_head(tc);
- while ((inst = tc_next_no_skip(tc)) != NULL) {
- /* we do not generate code for markers */
- if (inst->marker)
- ilo_printf("marker:");
- else
- ilo_printf("%6d:", pc++);
-
- tc_dump_inst(tc, inst);
- }
-}
-
-/**
- * Clean up the toy compiler.
- */
-void
-toy_compiler_cleanup(struct toy_compiler *tc)
-{
- struct toy_inst *inst, *next;
-
- LIST_FOR_EACH_ENTRY_SAFE(inst, next, &tc->instructions, list)
- slab_free_st(&tc->mempool, inst);
-
- slab_destroy(&tc->mempool);
-}
-
-/**
- * Initialize the instruction template, from which tc_add() initializes the
- * newly added instructions.
- */
-static void
-tc_init_inst_templ(struct toy_compiler *tc)
-{
- struct toy_inst *templ = &tc->templ;
- int i;
-
- templ->opcode = GEN6_OPCODE_NOP;
- templ->access_mode = GEN6_ALIGN_1;
- templ->mask_ctrl = GEN6_MASKCTRL_NORMAL;
- templ->dep_ctrl = GEN6_DEPCTRL_NORMAL;
- templ->qtr_ctrl = GEN6_QTRCTRL_1Q;
- templ->thread_ctrl = GEN6_THREADCTRL_NORMAL;
- templ->pred_ctrl = GEN6_PREDCTRL_NONE;
- templ->pred_inv = false;
- templ->exec_size = GEN6_EXECSIZE_1;
- templ->cond_modifier = GEN6_COND_NONE;
- templ->acc_wr_ctrl = false;
- templ->saturate = false;
-
- templ->marker = false;
-
- templ->dst = tdst_null();
- for (i = 0; i < ARRAY_SIZE(templ->src); i++)
- templ->src[i] = tsrc_null();
-
- for (i = 0; i < ARRAY_SIZE(templ->tex.offsets); i++)
- templ->tex.offsets[i] = tsrc_null();
-
- list_inithead(&templ->list);
-}
-
-/**
- * Initialize the toy compiler.
- */
-void
-toy_compiler_init(struct toy_compiler *tc, const struct ilo_dev *dev)
-{
- memset(tc, 0, sizeof(*tc));
-
- tc->dev = dev;
-
- tc_init_inst_templ(tc);
-
- slab_create(&tc->mempool, sizeof(struct toy_inst),
- 64);
-
- list_inithead(&tc->instructions);
- /* instructions are added to the tail */
- tc_tail(tc);
-
- tc->rect_linear_width = 1;
-
- /* skip 0 so that util_hash_table_get() never returns NULL */
- tc->next_vrf = 1;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef TOY_COMPILER_H
-#define TOY_COMPILER_H
-
-#include "genhw/genhw.h"
-#include "util/slab.h"
-
-#include "ilo_common.h"
-#include "toy_compiler_reg.h"
-
-/**
- * Toy opcodes.
- */
-enum toy_opcode {
- /* 0..127 are reserved for GEN6_OPCODE_x */
- TOY_OPCODE_LAST_HW = 127,
-
- TOY_OPCODE_DO,
-
- /* TGSI register functions */
- TOY_OPCODE_TGSI_IN,
- TOY_OPCODE_TGSI_CONST,
- TOY_OPCODE_TGSI_SV,
- TOY_OPCODE_TGSI_IMM,
- TOY_OPCODE_TGSI_INDIRECT_FETCH,
- TOY_OPCODE_TGSI_INDIRECT_STORE,
-
- /* TGSI sampling functions */
- TOY_OPCODE_TGSI_TEX,
- TOY_OPCODE_TGSI_TXB,
- TOY_OPCODE_TGSI_TXD,
- TOY_OPCODE_TGSI_TXL,
- TOY_OPCODE_TGSI_TXP,
- TOY_OPCODE_TGSI_TXF,
- TOY_OPCODE_TGSI_TXQ,
- TOY_OPCODE_TGSI_TXQ_LZ,
- TOY_OPCODE_TGSI_TEX2,
- TOY_OPCODE_TGSI_TXB2,
- TOY_OPCODE_TGSI_TXL2,
- TOY_OPCODE_TGSI_SAMPLE,
- TOY_OPCODE_TGSI_SAMPLE_I,
- TOY_OPCODE_TGSI_SAMPLE_I_MS,
- TOY_OPCODE_TGSI_SAMPLE_B,
- TOY_OPCODE_TGSI_SAMPLE_C,
- TOY_OPCODE_TGSI_SAMPLE_C_LZ,
- TOY_OPCODE_TGSI_SAMPLE_D,
- TOY_OPCODE_TGSI_SAMPLE_L,
- TOY_OPCODE_TGSI_GATHER4,
- TOY_OPCODE_TGSI_SVIEWINFO,
- TOY_OPCODE_TGSI_SAMPLE_POS,
- TOY_OPCODE_TGSI_SAMPLE_INFO,
-
- /* math functions */
- TOY_OPCODE_INV,
- TOY_OPCODE_LOG,
- TOY_OPCODE_EXP,
- TOY_OPCODE_SQRT,
- TOY_OPCODE_RSQ,
- TOY_OPCODE_SIN,
- TOY_OPCODE_COS,
- TOY_OPCODE_FDIV,
- TOY_OPCODE_POW,
- TOY_OPCODE_INT_DIV_QUOTIENT,
- TOY_OPCODE_INT_DIV_REMAINDER,
-
- /* URB functions */
- TOY_OPCODE_URB_WRITE,
-
- /* GS-specific functions */
- TOY_OPCODE_EMIT,
- TOY_OPCODE_ENDPRIM,
-
- /* FS-specific functions */
- TOY_OPCODE_DDX,
- TOY_OPCODE_DDY,
- TOY_OPCODE_FB_WRITE,
- TOY_OPCODE_KIL,
-};
-
-/**
- * Toy instruction.
- */
-struct toy_inst {
- unsigned opcode:8; /* enum toy_opcode */
- unsigned access_mode:1; /* GEN6_ALIGN_x */
- unsigned mask_ctrl:1; /* GEN6_MASKCTRL_x */
- unsigned dep_ctrl:2; /* GEN6_DEPCTRL_x */
- unsigned qtr_ctrl:2; /* GEN6_QTRCTRL_x */
- unsigned thread_ctrl:2; /* GEN6_THREADCTRL_x */
- unsigned pred_ctrl:4; /* GEN6_PREDCTRL_x */
- unsigned pred_inv:1; /* true or false */
- unsigned exec_size:3; /* GEN6_EXECSIZE_x */
- unsigned cond_modifier:4; /* GEN6_COND_x */
- unsigned acc_wr_ctrl:1; /* true or false */
- unsigned saturate:1; /* true or false */
-
- /* true if the instruction should be ignored for instruction iteration */
- unsigned marker:1;
-
- unsigned pad:1;
-
- struct toy_dst dst;
- struct toy_src src[5]; /* match TGSI_FULL_MAX_SRC_REGISTERS */
-
- struct {
- int target; /* TGSI_TEXTURE_x */
- struct toy_src offsets[1]; /* need to be 4 when GATHER4 is supported */
- } tex;
-
- struct list_head list;
-};
-
-struct toy_compaction_table {
- uint32_t control[32];
- uint32_t datatype[32];
- uint32_t subreg[32];
- uint32_t src[32];
-
- uint32_t control_3src[4];
- uint64_t source_3src[4];
-};
-
-/**
- * Toy compiler.
- */
-struct toy_compiler {
- const struct ilo_dev *dev;
-
- struct toy_inst templ;
- struct slab_mempool mempool;
- struct list_head instructions;
- struct list_head *iter, *iter_next;
-
- /* this is not set until toy_compiler_legalize_for_asm() */
- int num_instructions;
-
- int rect_linear_width;
- int next_vrf;
-
- bool fail;
- const char *reason;
-};
-
-/**
- * Allocate the given number of VRF registers.
- */
-static inline int
-tc_alloc_vrf(struct toy_compiler *tc, int count)
-{
- const int vrf = tc->next_vrf;
-
- tc->next_vrf += count;
-
- return vrf;
-}
-
-/**
- * Allocate a temporary register.
- */
-static inline struct toy_dst
-tc_alloc_tmp(struct toy_compiler *tc)
-{
- return tdst(TOY_FILE_VRF, tc_alloc_vrf(tc, 1), 0);
-}
-
-/**
- * Allocate four temporary registers.
- */
-static inline void
-tc_alloc_tmp4(struct toy_compiler *tc, struct toy_dst *tmp)
-{
- tmp[0] = tc_alloc_tmp(tc);
- tmp[1] = tc_alloc_tmp(tc);
- tmp[2] = tc_alloc_tmp(tc);
- tmp[3] = tc_alloc_tmp(tc);
-}
-
-/**
- * Duplicate an instruction at the current location.
- */
-static inline struct toy_inst *
-tc_duplicate_inst(struct toy_compiler *tc, const struct toy_inst *inst)
-{
- struct toy_inst *new_inst;
-
- new_inst = slab_alloc_st(&tc->mempool);
- if (!new_inst)
- return NULL;
-
- *new_inst = *inst;
- list_addtail(&new_inst->list, tc->iter_next);
-
- return new_inst;
-}
-
-/**
- * Move an instruction to the current location.
- */
-static inline void
-tc_move_inst(struct toy_compiler *tc, struct toy_inst *inst)
-{
- list_del(&inst->list);
- list_addtail(&inst->list, tc->iter_next);
-}
-
-/**
- * Discard an instruction.
- */
-static inline void
-tc_discard_inst(struct toy_compiler *tc, struct toy_inst *inst)
-{
- list_del(&inst->list);
- slab_free_st(&tc->mempool, inst);
-}
-
-/**
- * Add a new instruction at the current location, using tc->templ as the
- * template.
- */
-static inline struct toy_inst *
-tc_add(struct toy_compiler *tc)
-{
- return tc_duplicate_inst(tc, &tc->templ);
-}
-
-/**
- * A convenient version of tc_add() for instructions with 3 source operands.
- */
-static inline struct toy_inst *
-tc_add3(struct toy_compiler *tc, unsigned opcode,
- struct toy_dst dst,
- struct toy_src src0,
- struct toy_src src1,
- struct toy_src src2)
-{
- struct toy_inst *inst;
-
- inst = tc_add(tc);
- if (!inst)
- return NULL;
-
- inst->opcode = opcode;
- inst->dst = dst;
- inst->src[0] = src0;
- inst->src[1] = src1;
- inst->src[2] = src2;
-
- return inst;
-}
-
-/**
- * A convenient version of tc_add() for instructions with 2 source operands.
- */
-static inline struct toy_inst *
-tc_add2(struct toy_compiler *tc, int opcode,
- struct toy_dst dst,
- struct toy_src src0,
- struct toy_src src1)
-{
- return tc_add3(tc, opcode, dst, src0, src1, tsrc_null());
-}
-
-/**
- * A convenient version of tc_add() for instructions with 1 source operand.
- */
-static inline struct toy_inst *
-tc_add1(struct toy_compiler *tc, unsigned opcode,
- struct toy_dst dst,
- struct toy_src src0)
-{
- return tc_add2(tc, opcode, dst, src0, tsrc_null());
-}
-
-/**
- * A convenient version of tc_add() for instructions without source or
- * destination operands.
- */
-static inline struct toy_inst *
-tc_add0(struct toy_compiler *tc, unsigned opcode)
-{
- return tc_add1(tc, opcode, tdst_null(), tsrc_null());
-}
-
-#define TC_ALU0(func, opcode) \
-static inline struct toy_inst * \
-func(struct toy_compiler *tc) \
-{ \
- return tc_add0(tc, opcode); \
-}
-
-#define TC_ALU1(func, opcode) \
-static inline struct toy_inst * \
-func(struct toy_compiler *tc, \
- struct toy_dst dst, \
- struct toy_src src) \
-{ \
- return tc_add1(tc, opcode, dst, src); \
-}
-
-#define TC_ALU2(func, opcode) \
-static inline struct toy_inst * \
-func(struct toy_compiler *tc, \
- struct toy_dst dst, \
- struct toy_src src0, \
- struct toy_src src1) \
-{ \
- return tc_add2(tc, opcode, \
- dst, src0, src1); \
-}
-
-#define TC_ALU3(func, opcode) \
-static inline struct toy_inst * \
-func(struct toy_compiler *tc, \
- struct toy_dst dst, \
- struct toy_src src0, \
- struct toy_src src1, \
- struct toy_src src2) \
-{ \
- return tc_add3(tc, opcode, \
- dst, src0, src1, src2); \
-}
-
-#define TC_CND2(func, opcode) \
-static inline struct toy_inst * \
-func(struct toy_compiler *tc, \
- struct toy_dst dst, \
- struct toy_src src0, \
- struct toy_src src1, \
- unsigned cond_modifier) \
-{ \
- struct toy_inst *inst; \
- inst = tc_add2(tc, opcode, \
- dst, src0, src1); \
- inst->cond_modifier = cond_modifier; \
- return inst; \
-}
-
-TC_ALU0(tc_NOP, GEN6_OPCODE_NOP)
-TC_ALU0(tc_ELSE, GEN6_OPCODE_ELSE)
-TC_ALU0(tc_ENDIF, GEN6_OPCODE_ENDIF)
-TC_ALU1(tc_MOV, GEN6_OPCODE_MOV)
-TC_ALU1(tc_RNDD, GEN6_OPCODE_RNDD)
-TC_ALU1(tc_INV, TOY_OPCODE_INV)
-TC_ALU1(tc_FRC, GEN6_OPCODE_FRC)
-TC_ALU1(tc_EXP, TOY_OPCODE_EXP)
-TC_ALU1(tc_LOG, TOY_OPCODE_LOG)
-TC_ALU2(tc_ADD, GEN6_OPCODE_ADD)
-TC_ALU2(tc_MUL, GEN6_OPCODE_MUL)
-TC_ALU2(tc_AND, GEN6_OPCODE_AND)
-TC_ALU2(tc_OR, GEN6_OPCODE_OR)
-TC_ALU2(tc_DP2, GEN6_OPCODE_DP2)
-TC_ALU2(tc_DP3, GEN6_OPCODE_DP3)
-TC_ALU2(tc_DP4, GEN6_OPCODE_DP4)
-TC_ALU2(tc_SHL, GEN6_OPCODE_SHL)
-TC_ALU2(tc_SHR, GEN6_OPCODE_SHR)
-TC_ALU2(tc_POW, TOY_OPCODE_POW)
-TC_ALU3(tc_MAC, GEN6_OPCODE_MAC)
-TC_CND2(tc_SEL, GEN6_OPCODE_SEL)
-TC_CND2(tc_CMP, GEN6_OPCODE_CMP)
-TC_CND2(tc_IF, GEN6_OPCODE_IF)
-TC_CND2(tc_SEND, GEN6_OPCODE_SEND)
-
-/**
- * Upcast a list_head to an instruction.
- */
-static inline struct toy_inst *
-tc_list_to_inst(struct toy_compiler *tc, struct list_head *item)
-{
- return container_of(item, (struct toy_inst *) NULL, list);
-}
-
-/**
- * Return the instruction at the current location.
- */
-static inline struct toy_inst *
-tc_current(struct toy_compiler *tc)
-{
- return (tc->iter != &tc->instructions) ?
- tc_list_to_inst(tc, tc->iter) : NULL;
-}
-
-/**
- * Set the current location to the head.
- */
-static inline void
-tc_head(struct toy_compiler *tc)
-{
- tc->iter = &tc->instructions;
- tc->iter_next = tc->iter->next;
-}
-
-/**
- * Set the current location to the tail.
- */
-static inline void
-tc_tail(struct toy_compiler *tc)
-{
- tc->iter = &tc->instructions;
- tc->iter_next = tc->iter;
-}
-
-/**
- * Advance the current location.
- */
-static inline struct toy_inst *
-tc_next_no_skip(struct toy_compiler *tc)
-{
- /* stay at the tail so that new instructions are added there */
- if (tc->iter_next == &tc->instructions) {
- tc_tail(tc);
- return NULL;
- }
-
- tc->iter = tc->iter_next;
- tc->iter_next = tc->iter_next->next;
-
- return tc_list_to_inst(tc, tc->iter);
-}
-
-/**
- * Advance the current location, skipping markers.
- */
-static inline struct toy_inst *
-tc_next(struct toy_compiler *tc)
-{
- struct toy_inst *inst;
-
- do {
- inst = tc_next_no_skip(tc);
- } while (inst && inst->marker);
-
- return inst;
-}
-
-static inline void
-tc_fail(struct toy_compiler *tc, const char *reason)
-{
- if (!tc->fail) {
- tc->fail = true;
- tc->reason = reason;
- }
-}
-
-void
-toy_compiler_init(struct toy_compiler *tc, const struct ilo_dev *dev);
-
-void
-toy_compiler_cleanup(struct toy_compiler *tc);
-
-void
-toy_compiler_dump(struct toy_compiler *tc);
-
-void *
-toy_compiler_assemble(struct toy_compiler *tc, int *size);
-
-const struct toy_compaction_table *
-toy_compiler_get_compaction_table(const struct ilo_dev *dev);
-
-void
-toy_compiler_disassemble(const struct ilo_dev *dev,
- const void *kernel, int size,
- bool dump_hex);
-
-#endif /* TOY_COMPILER_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "toy_compiler.h"
-
-#define CG_REG_SHIFT 5
-#define CG_REG_NUM(origin) ((origin) >> CG_REG_SHIFT)
-
-struct codegen {
- const struct ilo_dev *dev;
- const struct toy_inst *inst;
- int pc;
-
- unsigned flag_reg_num;
- unsigned flag_sub_reg_num;
-
- struct codegen_dst {
- unsigned file;
- unsigned type;
- bool indirect;
- unsigned indirect_subreg;
- unsigned origin; /* (RegNum << 5 | SubRegNumInBytes) */
-
- unsigned horz_stride;
-
- unsigned writemask;
- } dst;
-
- struct codegen_src {
- unsigned file;
- unsigned type;
- bool indirect;
- unsigned indirect_subreg;
- unsigned origin; /* (RegNum << 5 | SubRegNumInBytes) */
-
- unsigned vert_stride;
- unsigned width;
- unsigned horz_stride;
-
- unsigned swizzle[4];
- bool absolute;
- bool negate;
- } src[3];
-};
-
-/*
- * From the Sandy Bridge PRM, volume 4 part 2, page 107-108:
- *
- * "(Src0Index) The 5-bit index for source 0. The 12-bit table-look-up
- * result forms bits [88:77], the source 0 register region fields, of the
- * 128-bit instruction word."
- *
- * "(SubRegIndex) The 5-bit index for sub-register fields. The 15-bit
- * table-look-up result forms bits [100:96], [68,64] and [52,48] of the
- * 128-bit instruction word."
- *
- * "(DataTypeIndex) The 5-bit index for data type fields. The 18-bit
- * table-look-up result forms bits [63:61] and [46, 32] of the 128-bit
- * instruction word."
- *
- * "(ControlIndex) The 5-bit index for data type fields. The 17-bit
- * table-look-up result forms bits[31], and [23, 8] of the 128-bit
- * instruction word."
- */
-static const struct toy_compaction_table toy_compaction_table_gen6 = {
- .control = {
- [0] = 0x00000, /* 00000000000000000 */
- [1] = 0x08000, /* 01000000000000000 */
- [2] = 0x06000, /* 00110000000000000 */
- [3] = 0x00100, /* 00000000100000000 */
- [4] = 0x02000, /* 00010000000000000 */
- [5] = 0x01100, /* 00001000100000000 */
- [6] = 0x00102, /* 00000000100000010 */
- [7] = 0x00002, /* 00000000000000010 */
- [8] = 0x08100, /* 01000000100000000 */
- [9] = 0x0a000, /* 01010000000000000 */
- [10] = 0x16000, /* 10110000000000000 */
- [11] = 0x04000, /* 00100000000000000 */
- [12] = 0x1a000, /* 11010000000000000 */
- [13] = 0x18000, /* 11000000000000000 */
- [14] = 0x09100, /* 01001000100000000 */
- [15] = 0x08008, /* 01000000000001000 */
- [16] = 0x08004, /* 01000000000000100 */
- [17] = 0x00008, /* 00000000000001000 */
- [18] = 0x00004, /* 00000000000000100 */
- [19] = 0x01100, /* 00111000100000000 */
- [20] = 0x01102, /* 00001000100000010 */
- [21] = 0x06100, /* 00110000100000000 */
- [22] = 0x06001, /* 00110000000000001 */
- [23] = 0x04001, /* 00100000000000001 */
- [24] = 0x06002, /* 00110000000000010 */
- [25] = 0x06005, /* 00110000000000101 */
- [26] = 0x06009, /* 00110000000001001 */
- [27] = 0x06010, /* 00110000000010000 */
- [28] = 0x06003, /* 00110000000000011 */
- [29] = 0x06004, /* 00110000000000100 */
- [30] = 0x06108, /* 00110000100001000 */
- [31] = 0x04009, /* 00100000000001001 */
- },
- .datatype = {
- [0] = 0x09c00, /* 001001110000000000 */
- [1] = 0x08c20, /* 001000110000100000 */
- [2] = 0x09c01, /* 001001110000000001 */
- [3] = 0x08060, /* 001000000001100000 */
- [4] = 0x0ad29, /* 001010110100101001 */
- [5] = 0x081ad, /* 001000000110101101 */
- [6] = 0x0c62c, /* 001100011000101100 */
- [7] = 0x0bdad, /* 001011110110101101 */
- [8] = 0x081ec, /* 001000000111101100 */
- [9] = 0x08061, /* 001000000001100001 */
- [10] = 0x08ca5, /* 001000110010100101 */
- [11] = 0x08041, /* 001000000001000001 */
- [12] = 0x08231, /* 001000001000110001 */
- [13] = 0x08229, /* 001000001000101001 */
- [14] = 0x08020, /* 001000000000100000 */
- [15] = 0x08232, /* 001000001000110010 */
- [16] = 0x0a529, /* 001010010100101001 */
- [17] = 0x0b4a5, /* 001011010010100101 */
- [18] = 0x081a5, /* 001000000110100101 */
- [19] = 0x0c629, /* 001100011000101001 */
- [20] = 0x0b62c, /* 001011011000101100 */
- [21] = 0x0b5a5, /* 001011010110100101 */
- [22] = 0x0bda5, /* 001011110110100101 */
- [23] = 0x0f1bd, /* 001111011110111101 */
- [24] = 0x0f1bc, /* 001111011110111100 */
- [25] = 0x0f1bd, /* 001111011110111101 */
- [26] = 0x0f19d, /* 001111011110011101 */
- [27] = 0x0f1be, /* 001111011110111110 */
- [28] = 0x08021, /* 001000000000100001 */
- [29] = 0x08022, /* 001000000000100010 */
- [30] = 0x09fdd, /* 001001111111011101 */
- [31] = 0x083be, /* 001000001110111110 */
- },
- .subreg = {
- [0] = 0x0000, /* 000000000000000 */
- [1] = 0x0004, /* 000000000000100 */
- [2] = 0x0180, /* 000000110000000 */
- [3] = 0x1000, /* 111000000000000 */
- [4] = 0x3c08, /* 011110000001000 */
- [5] = 0x0400, /* 000010000000000 */
- [6] = 0x0010, /* 000000000010000 */
- [7] = 0x0c0c, /* 000110000001100 */
- [8] = 0x1000, /* 001000000000000 */
- [9] = 0x0200, /* 000001000000000 */
- [10] = 0x0294, /* 000001010010100 */
- [11] = 0x0056, /* 000000001010110 */
- [12] = 0x2000, /* 010000000000000 */
- [13] = 0x6000, /* 110000000000000 */
- [14] = 0x0800, /* 000100000000000 */
- [15] = 0x0080, /* 000000010000000 */
- [16] = 0x0008, /* 000000000001000 */
- [17] = 0x4000, /* 100000000000000 */
- [18] = 0x0280, /* 000001010000000 */
- [19] = 0x1400, /* 001010000000000 */
- [20] = 0x1800, /* 001100000000000 */
- [21] = 0x0054, /* 000000001010100 */
- [22] = 0x5a94, /* 101101010010100 */
- [23] = 0x2800, /* 010100000000000 */
- [24] = 0x008f, /* 000000010001111 */
- [25] = 0x3000, /* 011000000000000 */
- [26] = 0x1c00, /* 111110000000000 */
- [27] = 0x5000, /* 101000000000000 */
- [28] = 0x000f, /* 000000000001111 */
- [29] = 0x088f, /* 000100010001111 */
- [30] = 0x108f, /* 001000010001111 */
- [31] = 0x0c00, /* 000110000000000 */
- },
- .src = {
- [0] = 0x000, /* 000000000000 */
- [1] = 0x588, /* 010110001000 */
- [2] = 0x468, /* 010001101000 */
- [3] = 0x228, /* 001000101000 */
- [4] = 0x690, /* 011010010000 */
- [5] = 0x120, /* 000100100000 */
- [6] = 0x46c, /* 010001101100 */
- [7] = 0x510, /* 010101110000 */
- [8] = 0x618, /* 011001111000 */
- [9] = 0x328, /* 001100101000 */
- [10] = 0x58c, /* 010110001100 */
- [11] = 0x220, /* 001000100000 */
- [12] = 0x58a, /* 010110001010 */
- [13] = 0x002, /* 000000000010 */
- [14] = 0x550, /* 010101010000 */
- [15] = 0x568, /* 010101101000 */
- [16] = 0xf4c, /* 111101001100 */
- [17] = 0xf2c, /* 111100101100 */
- [18] = 0x610, /* 011001110000 */
- [19] = 0x589, /* 010110001001 */
- [20] = 0x558, /* 010101011000 */
- [21] = 0x348, /* 001101001000 */
- [22] = 0x42c, /* 010000101100 */
- [23] = 0x400, /* 010000000000 */
- [24] = 0x310, /* 001101110000 */
- [25] = 0x310, /* 001100010000 */
- [26] = 0x300, /* 001100000000 */
- [27] = 0x46a, /* 010001101010 */
- [28] = 0x318, /* 001101111000 */
- [29] = 0x010, /* 000001110000 */
- [30] = 0x320, /* 001100100000 */
- [31] = 0x350, /* 001101010000 */
- },
-};
-
-/*
- * From the Ivy Bridge PRM, volume 4 part 3, page 128:
- *
- * "(Src0Index) Lookup one of 32 12-bit values. That value is used (from
- * MSB to LSB) for the Src0.AddrMode, Src0.ChanSel[7:4], Src0.HorzStride,
- * Src0.SrcMod, Src0.VertStride, and Src0.Width bit fields."
- *
- * "(SubRegIndex) Lookup one of 32 15-bit values. That value is used (from
- * MSB to LSB) for various fields for Src1, Src0, and Dst, including
- * ChanEn/ChanSel, SubRegNum, and AddrImm[4] or AddrImm[4:0], depending
- * on AddrMode and AccessMode.
- *
- * "(DataTypeIndex) Lookup one of 32 18-bit values. That value is used
- * (from MSB to LSB) for the Dst.AddrMode, Dst.HorzStride, Dst.DstType,
- * Dst.RegFile, Src0.SrcType, Src0.RegFile, Src1.SrcType, and
- * Src1.RegType bit fields."
- *
- * "(ControlIndex) Lookup one of 32 19-bit values. That value is used
- * (from MSB to LSB) for the FlagRegNum, FlagSubRegNum, Saturate,
- * ExecSize, PredInv, PredCtrl, ThreadCtrl, QtrCtrl, DepCtrl, MaskCtrl,
- * and AccessMode bit fields."
- */
-static const struct toy_compaction_table toy_compaction_table_gen7 = {
- .control = {
- [0] = 0x00002, /* 0000000000000000010 */
- [1] = 0x04000, /* 0000100000000000000 */
- [2] = 0x04001, /* 0000100000000000001 */
- [3] = 0x04002, /* 0000100000000000010 */
- [4] = 0x04003, /* 0000100000000000011 */
- [5] = 0x04004, /* 0000100000000000100 */
- [6] = 0x04005, /* 0000100000000000101 */
- [7] = 0x04007, /* 0000100000000000111 */
- [8] = 0x04008, /* 0000100000000001000 */
- [9] = 0x04009, /* 0000100000000001001 */
- [10] = 0x0400d, /* 0000100000000001101 */
- [11] = 0x06000, /* 0000110000000000000 */
- [12] = 0x06001, /* 0000110000000000001 */
- [13] = 0x06002, /* 0000110000000000010 */
- [14] = 0x06003, /* 0000110000000000011 */
- [15] = 0x06004, /* 0000110000000000100 */
- [16] = 0x06005, /* 0000110000000000101 */
- [17] = 0x06007, /* 0000110000000000111 */
- [18] = 0x06009, /* 0000110000000001001 */
- [19] = 0x0600d, /* 0000110000000001101 */
- [20] = 0x06010, /* 0000110000000010000 */
- [21] = 0x06100, /* 0000110000100000000 */
- [22] = 0x08000, /* 0001000000000000000 */
- [23] = 0x08002, /* 0001000000000000010 */
- [24] = 0x08004, /* 0001000000000000100 */
- [25] = 0x08100, /* 0001000000100000000 */
- [26] = 0x16000, /* 0010110000000000000 */
- [27] = 0x16010, /* 0010110000000010000 */
- [28] = 0x18000, /* 0011000000000000000 */
- [29] = 0x18100, /* 0011000000100000000 */
- [30] = 0x28000, /* 0101000000000000000 */
- [31] = 0x28100, /* 0101000000100000000 */
- },
- .datatype = {
- [0] = 0x08001, /* 001000000000000001 */
- [1] = 0x08020, /* 001000000000100000 */
- [2] = 0x08021, /* 001000000000100001 */
- [3] = 0x08061, /* 001000000001100001 */
- [4] = 0x080bd, /* 001000000010111101 */
- [5] = 0x082fd, /* 001000001011111101 */
- [6] = 0x083a1, /* 001000001110100001 */
- [7] = 0x083a5, /* 001000001110100101 */
- [8] = 0x083bd, /* 001000001110111101 */
- [9] = 0x08421, /* 001000010000100001 */
- [10] = 0x08c20, /* 001000110000100000 */
- [11] = 0x08c21, /* 001000110000100001 */
- [12] = 0x094a5, /* 001001010010100101 */
- [13] = 0x09ca4, /* 001001110010100100 */
- [14] = 0x09ca5, /* 001001110010100101 */
- [15] = 0x0f3bd, /* 001111001110111101 */
- [16] = 0x0f79d, /* 001111011110011101 */
- [17] = 0x0f7bc, /* 001111011110111100 */
- [18] = 0x0f7bd, /* 001111011110111101 */
- [19] = 0x0ffbc, /* 001111111110111100 */
- [20] = 0x0020c, /* 000000001000001100 */
- [21] = 0x0803d, /* 001000000000111101 */
- [22] = 0x080a5, /* 001000000010100101 */
- [23] = 0x08420, /* 001000010000100000 */
- [24] = 0x094a4, /* 001001010010100100 */
- [25] = 0x09c84, /* 001001110010000100 */
- [26] = 0x0a509, /* 001010010100001001 */
- [27] = 0x0dfbd, /* 001101111110111101 */
- [28] = 0x0ffbd, /* 001111111110111101 */
- [29] = 0x0bdac, /* 001011110110101100 */
- [30] = 0x0a528, /* 001010010100101000 */
- [31] = 0x0ad28, /* 001010110100101000 */
- },
- .subreg = {
- [0] = 0x0000, /* 000000000000000 */
- [1] = 0x0001, /* 000000000000001 */
- [2] = 0x0008, /* 000000000001000 */
- [3] = 0x000f, /* 000000000001111 */
- [4] = 0x0010, /* 000000000010000 */
- [5] = 0x0080, /* 000000010000000 */
- [6] = 0x0100, /* 000000100000000 */
- [7] = 0x0180, /* 000000110000000 */
- [8] = 0x0200, /* 000001000000000 */
- [9] = 0x0210, /* 000001000010000 */
- [10] = 0x0280, /* 000001010000000 */
- [11] = 0x1000, /* 001000000000000 */
- [12] = 0x1001, /* 001000000000001 */
- [13] = 0x1081, /* 001000010000001 */
- [14] = 0x1082, /* 001000010000010 */
- [15] = 0x1083, /* 001000010000011 */
- [16] = 0x1084, /* 001000010000100 */
- [17] = 0x1087, /* 001000010000111 */
- [18] = 0x1088, /* 001000010001000 */
- [19] = 0x108e, /* 001000010001110 */
- [20] = 0x108f, /* 001000010001111 */
- [21] = 0x1180, /* 001000110000000 */
- [22] = 0x11e8, /* 001000111101000 */
- [23] = 0x2000, /* 010000000000000 */
- [24] = 0x2180, /* 010000110000000 */
- [25] = 0x3000, /* 011000000000000 */
- [26] = 0x3c87, /* 011110010000111 */
- [27] = 0x4000, /* 100000000000000 */
- [28] = 0x5000, /* 101000000000000 */
- [29] = 0x6000, /* 110000000000000 */
- [30] = 0x7000, /* 111000000000000 */
- [31] = 0x701c, /* 111000000011100 */
- },
- .src = {
- [0] = 0x000, /* 000000000000 */
- [1] = 0x002, /* 000000000010 */
- [2] = 0x010, /* 000000010000 */
- [3] = 0x012, /* 000000010010 */
- [4] = 0x018, /* 000000011000 */
- [5] = 0x020, /* 000000100000 */
- [6] = 0x028, /* 000000101000 */
- [7] = 0x048, /* 000001001000 */
- [8] = 0x050, /* 000001010000 */
- [9] = 0x070, /* 000001110000 */
- [10] = 0x078, /* 000001111000 */
- [11] = 0x300, /* 001100000000 */
- [12] = 0x302, /* 001100000010 */
- [13] = 0x308, /* 001100001000 */
- [14] = 0x310, /* 001100010000 */
- [15] = 0x312, /* 001100010010 */
- [16] = 0x320, /* 001100100000 */
- [17] = 0x328, /* 001100101000 */
- [18] = 0x338, /* 001100111000 */
- [19] = 0x340, /* 001101000000 */
- [20] = 0x342, /* 001101000010 */
- [21] = 0x348, /* 001101001000 */
- [22] = 0x350, /* 001101010000 */
- [23] = 0x360, /* 001101100000 */
- [24] = 0x368, /* 001101101000 */
- [25] = 0x370, /* 001101110000 */
- [26] = 0x371, /* 001101110001 */
- [27] = 0x378, /* 001101111000 */
- [28] = 0x468, /* 010001101000 */
- [29] = 0x469, /* 010001101001 */
- [30] = 0x46a, /* 010001101010 */
- [31] = 0x588, /* 010110001000 */
- },
-};
-
-static const struct toy_compaction_table toy_compaction_table_gen8 = {
- .control = {
- },
- .datatype = {
- },
- .subreg = {
- },
- .src = {
- },
- .control_3src = {
- },
- .source_3src = {
- },
-};
-
-const struct toy_compaction_table *
-toy_compiler_get_compaction_table(const struct ilo_dev *dev)
-{
- switch (ilo_dev_gen(dev)) {
- case ILO_GEN(8):
- return &toy_compaction_table_gen8;
- case ILO_GEN(7.5):
- case ILO_GEN(7):
- return &toy_compaction_table_gen7;
- case ILO_GEN(6):
- return &toy_compaction_table_gen6;
- default:
- assert(!"unsupported gen");
- return NULL;
- }
-}
-
-/**
- * Return true if the source operand is null.
- */
-static bool
-src_is_null(const struct codegen *cg, int idx)
-{
- const struct codegen_src *src = &cg->src[idx];
-
- return (src->file == GEN6_FILE_ARF &&
- src->origin == GEN6_ARF_NULL << CG_REG_SHIFT);
-}
-
-/**
- * Translate a source operand to DW2 or DW3 of the 1-src/2-src format.
- */
-static uint32_t
-translate_src_gen6(const struct codegen *cg, int idx)
-{
- const struct codegen_src *src = &cg->src[idx];
- uint32_t dw;
-
- ILO_DEV_ASSERT(cg->dev, 6, 8);
-
- /* special treatment may be needed if any of the operand is immediate */
- if (cg->src[0].file == GEN6_FILE_IMM) {
- assert(!cg->src[0].absolute && !cg->src[0].negate);
-
- /* only the last src operand can be an immediate unless it is Gen8+ */
- assert(ilo_dev_gen(cg->dev) >= ILO_GEN(8) || src_is_null(cg, 1));
-
- if (!src_is_null(cg, 1))
- return cg->src[idx].origin;
-
- if (idx == 0) {
- if (ilo_dev_gen(cg->dev) >= ILO_GEN(8)) {
- return cg->src[1].type << 27 |
- cg->src[1].file << 25;
- } else {
- return cg->flag_sub_reg_num << 25;
- }
- } else {
- return cg->src[0].origin;
- }
- }
- else if (idx && cg->src[1].file == GEN6_FILE_IMM) {
- assert(!cg->src[1].absolute && !cg->src[1].negate);
- return cg->src[1].origin;
- }
-
- assert(src->file != GEN6_FILE_IMM);
-
- if (src->indirect) {
- const int offset = (int) src->origin;
-
- assert(src->file == GEN6_FILE_GRF);
- assert(offset < 512 && offset >= -512);
-
- if (cg->inst->access_mode == GEN6_ALIGN_16) {
- assert(src->width == GEN6_WIDTH_4);
- assert(src->horz_stride == GEN6_HORZSTRIDE_1);
-
- /* the lower 4 bits are reserved for the swizzle_[xy] */
- assert(!(src->origin & 0xf));
-
- dw = src->vert_stride << 21 |
- src->swizzle[3] << 18 |
- src->swizzle[2] << 16 |
- GEN6_ADDRMODE_INDIRECT << 15 |
- src->negate << 14 |
- src->absolute << 13 |
- src->swizzle[1] << 2 |
- src->swizzle[0];
- if (ilo_dev_gen(cg->dev) >= ILO_GEN(8)) {
- dw |= src->indirect_subreg << 9 |
- (src->origin & 0x1f0);
- } else {
- dw |= src->indirect_subreg << 10 |
- (src->origin & 0x3f0);
- }
- }
- else {
- assert(src->swizzle[0] == TOY_SWIZZLE_X &&
- src->swizzle[1] == TOY_SWIZZLE_Y &&
- src->swizzle[2] == TOY_SWIZZLE_Z &&
- src->swizzle[3] == TOY_SWIZZLE_W);
-
- dw = src->vert_stride << 21 |
- src->width << 18 |
- src->horz_stride << 16 |
- GEN6_ADDRMODE_INDIRECT << 15 |
- src->negate << 14 |
- src->absolute << 13;
- if (ilo_dev_gen(cg->dev) >= ILO_GEN(8)) {
- dw |= src->indirect_subreg << 9 |
- (src->origin & 0x1ff);
- } else {
- dw |= src->indirect_subreg << 10 |
- (src->origin & 0x3ff);
- }
- }
- }
- else {
- switch (src->file) {
- case GEN6_FILE_ARF:
- break;
- case GEN6_FILE_GRF:
- assert(CG_REG_NUM(src->origin) < 128);
- break;
- case GEN6_FILE_MRF:
- assert(cg->inst->opcode == GEN6_OPCODE_SEND ||
- cg->inst->opcode == GEN6_OPCODE_SENDC);
- assert(CG_REG_NUM(src->origin) < 16);
- break;
- case GEN6_FILE_IMM:
- default:
- assert(!"invalid src file");
- break;
- }
-
- if (cg->inst->access_mode == GEN6_ALIGN_16) {
- assert(src->width == GEN6_WIDTH_4);
- assert(src->horz_stride == GEN6_HORZSTRIDE_1);
-
- /* the lower 4 bits are reserved for the swizzle_[xy] */
- assert(!(src->origin & 0xf));
-
- dw = src->vert_stride << 21 |
- src->swizzle[3] << 18 |
- src->swizzle[2] << 16 |
- GEN6_ADDRMODE_DIRECT << 15 |
- src->negate << 14 |
- src->absolute << 13 |
- src->origin |
- src->swizzle[1] << 2 |
- src->swizzle[0];
- }
- else {
- assert(src->swizzle[0] == TOY_SWIZZLE_X &&
- src->swizzle[1] == TOY_SWIZZLE_Y &&
- src->swizzle[2] == TOY_SWIZZLE_Z &&
- src->swizzle[3] == TOY_SWIZZLE_W);
-
- dw = src->vert_stride << 21 |
- src->width << 18 |
- src->horz_stride << 16 |
- GEN6_ADDRMODE_DIRECT << 15 |
- src->negate << 14 |
- src->absolute << 13 |
- src->origin;
- }
- }
-
- if (ilo_dev_gen(cg->dev) >= ILO_GEN(8)) {
- const bool indirect_origin_bit9 = (cg->dst.indirect) ?
- (src->origin & 0x200) : 0;
-
- if (idx == 0) {
- dw |= indirect_origin_bit9 << 31 |
- cg->src[1].type << 27 |
- cg->src[1].file << 25;
- } else {
- dw |= indirect_origin_bit9 << 25;
- }
- } else {
- if (idx == 0)
- dw |= cg->flag_sub_reg_num << 25;
- }
-
- return dw;
-}
-
-/**
- * Translate the destination operand to the higher 16 bits of DW1 of the
- * 1-src/2-src format.
- */
-static uint16_t
-translate_dst_region_gen6(const struct codegen *cg)
-{
- const struct codegen_dst *dst = &cg->dst;
- uint16_t dw1_region;
-
- ILO_DEV_ASSERT(cg->dev, 6, 8);
-
- if (dst->file == GEN6_FILE_IMM) {
- /* dst is immediate (JIP) when the opcode is a conditional branch */
- switch (cg->inst->opcode) {
- case GEN6_OPCODE_IF:
- case GEN6_OPCODE_ELSE:
- case GEN6_OPCODE_ENDIF:
- case GEN6_OPCODE_WHILE:
- assert(dst->type == GEN6_TYPE_W);
- dw1_region = (dst->origin & 0xffff);
- break;
- default:
- assert(!"dst cannot be immediate");
- dw1_region = 0;
- break;
- }
-
- return dw1_region;
- }
-
- if (dst->indirect) {
- const int offset = (int) dst->origin;
-
- assert(dst->file == GEN6_FILE_GRF);
- assert(offset < 512 && offset >= -512);
-
- if (cg->inst->access_mode == GEN6_ALIGN_16) {
- /*
- * From the Sandy Bridge PRM, volume 4 part 2, page 144:
- *
- * "Allthough Dst.HorzStride is a don't care for Align16, HW
- * needs this to be programmed as 01."
- */
- assert(dst->horz_stride == GEN6_HORZSTRIDE_1);
- /* the lower 4 bits are reserved for the writemask */
- assert(!(dst->origin & 0xf));
-
- dw1_region = GEN6_ADDRMODE_INDIRECT << 15 |
- dst->horz_stride << 13 |
- dst->writemask;
- if (ilo_dev_gen(cg->dev) >= ILO_GEN(8)) {
- dw1_region |= dst->indirect_subreg << 9 |
- (dst->origin & 0x1f0);
- } else {
- dw1_region |= dst->indirect_subreg << 10 |
- (dst->origin & 0x3f0);
- }
- }
- else {
- assert(dst->writemask == TOY_WRITEMASK_XYZW);
-
- dw1_region = GEN6_ADDRMODE_INDIRECT << 15 |
- dst->horz_stride << 13;
- if (ilo_dev_gen(cg->dev) >= ILO_GEN(8)) {
- dw1_region |= dst->indirect_subreg << 9 |
- (dst->origin & 0x1ff);
- } else {
- dw1_region |= dst->indirect_subreg << 10 |
- (dst->origin & 0x3ff);
- }
- }
- }
- else {
- assert((dst->file == GEN6_FILE_GRF &&
- CG_REG_NUM(dst->origin) < 128) ||
- (dst->file == GEN6_FILE_MRF &&
- CG_REG_NUM(dst->origin) < 16) ||
- (dst->file == GEN6_FILE_ARF));
-
- if (cg->inst->access_mode == GEN6_ALIGN_16) {
- /* similar to the indirect case */
- assert(dst->horz_stride == GEN6_HORZSTRIDE_1);
- assert(!(dst->origin & 0xf));
-
- dw1_region = GEN6_ADDRMODE_DIRECT << 15 |
- dst->horz_stride << 13 |
- dst->origin |
- dst->writemask;
- }
- else {
- assert(dst->writemask == TOY_WRITEMASK_XYZW);
-
- dw1_region = GEN6_ADDRMODE_DIRECT << 15 |
- dst->horz_stride << 13 |
- dst->origin;
- }
- }
-
- return dw1_region;
-}
-
-/**
- * Translate the destination operand to DW1 of the 1-src/2-src format.
- */
-static uint32_t
-translate_dst_gen6(const struct codegen *cg)
-{
- ILO_DEV_ASSERT(cg->dev, 6, 7.5);
-
- return translate_dst_region_gen6(cg) << 16 |
- cg->src[1].type << 12 |
- cg->src[1].file << 10 |
- cg->src[0].type << 7 |
- cg->src[0].file << 5 |
- cg->dst.type << 2 |
- cg->dst.file;
-}
-
-static uint32_t
-translate_dst_gen8(const struct codegen *cg)
-{
- const bool indirect_origin_bit9 = (cg->dst.indirect) ?
- (cg->dst.origin & 0x200) : 0;
-
- ILO_DEV_ASSERT(cg->dev, 8, 8);
-
- return translate_dst_region_gen6(cg) << 16 |
- indirect_origin_bit9 << 15 |
- cg->src[0].type << 11 |
- cg->src[0].file << 9 |
- cg->dst.type << 5 |
- cg->dst.file << 3 |
- cg->inst->mask_ctrl << 2 |
- cg->flag_reg_num << 1 |
- cg->flag_sub_reg_num;
-}
-
-/**
- * Translate the instruction to DW0 of the 1-src/2-src format.
- */
-static uint32_t
-translate_inst_gen6(const struct codegen *cg)
-{
- const bool debug_ctrl = false;
- const bool cmpt_ctrl = false;
-
- ILO_DEV_ASSERT(cg->dev, 6, 7.5);
-
- assert(cg->inst->opcode < 128);
-
- return cg->inst->saturate << 31 |
- debug_ctrl << 30 |
- cmpt_ctrl << 29 |
- cg->inst->acc_wr_ctrl << 28 |
- cg->inst->cond_modifier << 24 |
- cg->inst->exec_size << 21 |
- cg->inst->pred_inv << 20 |
- cg->inst->pred_ctrl << 16 |
- cg->inst->thread_ctrl << 14 |
- cg->inst->qtr_ctrl << 12 |
- cg->inst->dep_ctrl << 10 |
- cg->inst->mask_ctrl << 9 |
- cg->inst->access_mode << 8 |
- cg->inst->opcode;
-}
-
-static uint32_t
-translate_inst_gen8(const struct codegen *cg)
-{
- const bool debug_ctrl = false;
- const bool cmpt_ctrl = false;
-
- ILO_DEV_ASSERT(cg->dev, 8, 8);
-
- assert(cg->inst->opcode < 128);
-
- return cg->inst->saturate << 31 |
- debug_ctrl << 30 |
- cmpt_ctrl << 29 |
- cg->inst->acc_wr_ctrl << 28 |
- cg->inst->cond_modifier << 24 |
- cg->inst->exec_size << 21 |
- cg->inst->pred_inv << 20 |
- cg->inst->pred_ctrl << 16 |
- cg->inst->thread_ctrl << 14 |
- cg->inst->qtr_ctrl << 12 |
- cg->inst->dep_ctrl << 9 |
- cg->inst->access_mode << 8 |
- cg->inst->opcode;
-}
-
-/**
- * Codegen an instruction in 1-src/2-src format.
- */
-static void
-codegen_inst_gen6(const struct codegen *cg, uint32_t *code)
-{
- ILO_DEV_ASSERT(cg->dev, 6, 8);
-
- if (ilo_dev_gen(cg->dev) >= ILO_GEN(8)) {
- code[0] = translate_inst_gen8(cg);
- code[1] = translate_dst_gen8(cg);
- } else {
- code[0] = translate_inst_gen6(cg);
- code[1] = translate_dst_gen6(cg);
- }
-
- code[2] = translate_src_gen6(cg, 0);
- code[3] = translate_src_gen6(cg, 1);
- assert(src_is_null(cg, 2));
-}
-
-/**
- * Codegen an instruction in 3-src format.
- */
-static void
-codegen_inst_3src_gen6(const struct codegen *cg, uint32_t *code)
-{
- const struct codegen_dst *dst = &cg->dst;
- uint32_t dw0, dw1, dw_src[3];
- int i;
-
- ILO_DEV_ASSERT(cg->dev, 6, 8);
-
- if (ilo_dev_gen(cg->dev) >= ILO_GEN(8))
- dw0 = translate_inst_gen8(cg);
- else
- dw0 = translate_inst_gen6(cg);
-
- /*
- * 3-src instruction restrictions
- *
- * - align16 with direct addressing
- * - GRF or MRF dst
- * - GRF src
- * - sub_reg_num is DWORD aligned
- * - no regioning except replication control
- * (vert_stride == 0 && horz_stride == 0)
- */
- assert(cg->inst->access_mode == GEN6_ALIGN_16);
-
- assert(!dst->indirect);
- assert((dst->file == GEN6_FILE_GRF && CG_REG_NUM(dst->origin) < 128) ||
- (dst->file == GEN6_FILE_MRF && CG_REG_NUM(dst->origin) < 16));
- assert(!(dst->origin & 0x3));
- assert(dst->horz_stride == GEN6_HORZSTRIDE_1);
-
- if (ilo_dev_gen(cg->dev) >= ILO_GEN(8)) {
- dw1 = dst->origin << 19 |
- dst->writemask << 17 |
- cg->src[2].negate << 10 |
- cg->src[2].negate << 10 |
- cg->src[2].absolute << 9 |
- cg->src[1].negate << 8 |
- cg->src[1].absolute << 7 |
- cg->src[0].negate << 6 |
- cg->src[0].absolute << 5 |
- cg->inst->mask_ctrl << 2 |
- cg->flag_reg_num << 1 |
- cg->flag_sub_reg_num;
- } else {
- dw1 = dst->origin << 19 |
- dst->writemask << 17 |
- cg->src[2].negate << 9 |
- cg->src[2].absolute << 8 |
- cg->src[1].negate << 7 |
- cg->src[1].absolute << 6 |
- cg->src[0].negate << 5 |
- cg->src[0].absolute << 4 |
- cg->flag_sub_reg_num << 1 |
- (dst->file == GEN6_FILE_MRF);
- }
-
- for (i = 0; i < 3; i++) {
- const struct codegen_src *src = &cg->src[i];
-
- assert(!src->indirect);
- assert(src->file == GEN6_FILE_GRF && CG_REG_NUM(src->origin) < 128);
- assert(!(src->origin & 0x3));
-
- assert((src->vert_stride == GEN6_VERTSTRIDE_4 &&
- src->horz_stride == GEN6_HORZSTRIDE_1) ||
- (src->vert_stride == GEN6_VERTSTRIDE_0 &&
- src->horz_stride == GEN6_HORZSTRIDE_0));
- assert(src->width == GEN6_WIDTH_4);
-
- dw_src[i] = src->origin << 7 |
- src->swizzle[3] << 7 |
- src->swizzle[2] << 5 |
- src->swizzle[1] << 3 |
- src->swizzle[0] << 1 |
- (src->vert_stride == GEN6_VERTSTRIDE_0 &&
- src->horz_stride == GEN6_HORZSTRIDE_0);
-
- /* only the lower 20 bits are used */
- assert((dw_src[i] & 0xfffff) == dw_src[i]);
- }
-
- code[0] = dw0;
- code[1] = dw1;
- /* concatenate the bits of dw_src */
- code[2] = (dw_src[1] & 0x7ff ) << 21 | dw_src[0];
- code[3] = dw_src[2] << 10 | (dw_src[1] >> 11);
-}
-
-/**
- * Sanity check the region parameters of the operands.
- */
-static void
-codegen_validate_region_restrictions(const struct codegen *cg)
-{
- const int exec_size_map[] = {
- [GEN6_EXECSIZE_1] = 1,
- [GEN6_EXECSIZE_2] = 2,
- [GEN6_EXECSIZE_4] = 4,
- [GEN6_EXECSIZE_8] = 8,
- [GEN6_EXECSIZE_16] = 16,
- [GEN6_EXECSIZE_32] = 32,
- };
- const int width_map[] = {
- [GEN6_WIDTH_1] = 1,
- [GEN6_WIDTH_2] = 2,
- [GEN6_WIDTH_4] = 4,
- [GEN6_WIDTH_8] = 8,
- [GEN6_WIDTH_16] = 16,
- };
- const int horz_stride_map[] = {
- [GEN6_HORZSTRIDE_0] = 0,
- [GEN6_HORZSTRIDE_1] = 1,
- [GEN6_HORZSTRIDE_2] = 2,
- [GEN6_HORZSTRIDE_4] = 4,
- };
- const int vert_stride_map[] = {
- [GEN6_VERTSTRIDE_0] = 0,
- [GEN6_VERTSTRIDE_1] = 1,
- [GEN6_VERTSTRIDE_2] = 2,
- [GEN6_VERTSTRIDE_4] = 4,
- [GEN6_VERTSTRIDE_8] = 8,
- [GEN6_VERTSTRIDE_16] = 16,
- [GEN6_VERTSTRIDE_32] = 32,
- [7] = 64,
- [8] = 128,
- [9] = 256,
- [GEN6_VERTSTRIDE_VXH] = 0,
- };
- const int exec_size = exec_size_map[cg->inst->exec_size];
- int i;
-
- /* Sandy Bridge PRM, volume 4 part 2, page 94 */
-
- /* 1. (we don't do 32 anyway) */
- assert(exec_size <= 16);
-
- for (i = 0; i < ARRAY_SIZE(cg->src); i++) {
- const int width = width_map[cg->src[i].width];
- const int horz_stride = horz_stride_map[cg->src[i].horz_stride];
- const int vert_stride = vert_stride_map[cg->src[i].vert_stride];
-
- if (src_is_null(cg, i))
- break;
-
- /* 3. */
- assert(exec_size >= width);
-
- if (exec_size == width) {
- /* 4. & 5. */
- if (horz_stride)
- assert(vert_stride == width * horz_stride);
- }
-
- if (width == 1) {
- /* 6. */
- assert(horz_stride == 0);
-
- /* 7. */
- if (exec_size == 1)
- assert(vert_stride == 0);
- }
-
- /* 8. */
- if (!vert_stride && !horz_stride)
- assert(width == 1);
- }
-
- /* derived from 10.1.2. & 10.2. */
- assert(cg->dst.horz_stride != GEN6_HORZSTRIDE_0);
-}
-
-static unsigned
-translate_vfile(enum toy_file file)
-{
- switch (file) {
- case TOY_FILE_ARF: return GEN6_FILE_ARF;
- case TOY_FILE_GRF: return GEN6_FILE_GRF;
- case TOY_FILE_MRF: return GEN6_FILE_MRF;
- case TOY_FILE_IMM: return GEN6_FILE_IMM;
- default:
- assert(!"unhandled toy file");
- return GEN6_FILE_GRF;
- }
-}
-
-static unsigned
-translate_vtype(enum toy_type type)
-{
- switch (type) {
- case TOY_TYPE_F: return GEN6_TYPE_F;
- case TOY_TYPE_D: return GEN6_TYPE_D;
- case TOY_TYPE_UD: return GEN6_TYPE_UD;
- case TOY_TYPE_W: return GEN6_TYPE_W;
- case TOY_TYPE_UW: return GEN6_TYPE_UW;
- case TOY_TYPE_V: return GEN6_TYPE_V_IMM;
- default:
- assert(!"unhandled toy type");
- return GEN6_TYPE_F;
- }
-}
-
-static unsigned
-translate_writemask(enum toy_writemask writemask)
-{
- /* TOY_WRITEMASK_* are compatible with the hardware definitions */
- assert(writemask <= 0xf);
- return writemask;
-}
-
-static unsigned
-translate_swizzle(enum toy_swizzle swizzle)
-{
- /* TOY_SWIZZLE_* are compatible with the hardware definitions */
- assert(swizzle <= 3);
- return swizzle;
-}
-
-/**
- * Prepare for generating an instruction.
- */
-static void
-codegen_prepare(struct codegen *cg, const struct ilo_dev *dev,
- const struct toy_inst *inst, int pc, int rect_linear_width)
-{
- int i;
-
- cg->dev = dev;
- cg->inst = inst;
- cg->pc = pc;
-
- cg->flag_reg_num = 0;
- cg->flag_sub_reg_num = 0;
-
- cg->dst.file = translate_vfile(inst->dst.file);
- cg->dst.type = translate_vtype(inst->dst.type);
- cg->dst.indirect = inst->dst.indirect;
- cg->dst.indirect_subreg = inst->dst.indirect_subreg;
- cg->dst.origin = inst->dst.val32;
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 2, page 81:
- *
- * "For a word or an unsigned word immediate data, software must
- * replicate the same 16-bit immediate value to both the lower word
- * and the high word of the 32-bit immediate field in an instruction."
- */
- if (inst->dst.file == TOY_FILE_IMM) {
- switch (inst->dst.type) {
- case TOY_TYPE_W:
- case TOY_TYPE_UW:
- cg->dst.origin &= 0xffff;
- cg->dst.origin |= cg->dst.origin << 16;
- break;
- default:
- break;
- }
- }
-
- cg->dst.writemask = translate_writemask(inst->dst.writemask);
-
- switch (inst->dst.rect) {
- case TOY_RECT_LINEAR:
- cg->dst.horz_stride = GEN6_HORZSTRIDE_1;
- break;
- default:
- assert(!"unsupported dst region");
- cg->dst.horz_stride = GEN6_HORZSTRIDE_1;
- break;
- }
-
- for (i = 0; i < ARRAY_SIZE(cg->src); i++) {
- struct codegen_src *src = &cg->src[i];
-
- src->file = translate_vfile(inst->src[i].file);
- src->type = translate_vtype(inst->src[i].type);
- src->indirect = inst->src[i].indirect;
- src->indirect_subreg = inst->src[i].indirect_subreg;
- src->origin = inst->src[i].val32;
-
- /* do the same for src */
- if (inst->dst.file == TOY_FILE_IMM) {
- switch (inst->src[i].type) {
- case TOY_TYPE_W:
- case TOY_TYPE_UW:
- src->origin &= 0xffff;
- src->origin |= src->origin << 16;
- break;
- default:
- break;
- }
- }
-
- src->swizzle[0] = translate_swizzle(inst->src[i].swizzle_x);
- src->swizzle[1] = translate_swizzle(inst->src[i].swizzle_y);
- src->swizzle[2] = translate_swizzle(inst->src[i].swizzle_z);
- src->swizzle[3] = translate_swizzle(inst->src[i].swizzle_w);
- src->absolute = inst->src[i].absolute;
- src->negate = inst->src[i].negate;
-
- switch (inst->src[i].rect) {
- case TOY_RECT_LINEAR:
- switch (rect_linear_width) {
- case 1:
- src->vert_stride = GEN6_VERTSTRIDE_1;
- src->width = GEN6_WIDTH_1;
- break;
- case 2:
- src->vert_stride = GEN6_VERTSTRIDE_2;
- src->width = GEN6_WIDTH_2;
- break;
- case 4:
- src->vert_stride = GEN6_VERTSTRIDE_4;
- src->width = GEN6_WIDTH_4;
- break;
- case 8:
- src->vert_stride = GEN6_VERTSTRIDE_8;
- src->width = GEN6_WIDTH_8;
- break;
- case 16:
- src->vert_stride = GEN6_VERTSTRIDE_16;
- src->width = GEN6_WIDTH_16;
- break;
- default:
- assert(!"unsupported TOY_RECT_LINEAR width");
- src->vert_stride = GEN6_VERTSTRIDE_1;
- src->width = GEN6_WIDTH_1;
- break;
- }
- src->horz_stride = GEN6_HORZSTRIDE_1;
- break;
- case TOY_RECT_041:
- src->vert_stride = GEN6_VERTSTRIDE_0;
- src->width = GEN6_WIDTH_4;
- src->horz_stride = GEN6_HORZSTRIDE_1;
- break;
- case TOY_RECT_010:
- src->vert_stride = GEN6_VERTSTRIDE_0;
- src->width = GEN6_WIDTH_1;
- src->horz_stride = GEN6_HORZSTRIDE_0;
- break;
- case TOY_RECT_220:
- src->vert_stride = GEN6_VERTSTRIDE_2;
- src->width = GEN6_WIDTH_2;
- src->horz_stride = GEN6_HORZSTRIDE_0;
- break;
- case TOY_RECT_440:
- src->vert_stride = GEN6_VERTSTRIDE_4;
- src->width = GEN6_WIDTH_4;
- src->horz_stride = GEN6_HORZSTRIDE_0;
- break;
- case TOY_RECT_240:
- src->vert_stride = GEN6_VERTSTRIDE_2;
- src->width = GEN6_WIDTH_4;
- src->horz_stride = GEN6_HORZSTRIDE_0;
- break;
- default:
- assert(!"unsupported src region");
- src->vert_stride = GEN6_VERTSTRIDE_1;
- src->width = GEN6_WIDTH_1;
- src->horz_stride = GEN6_HORZSTRIDE_1;
- break;
- }
- }
-}
-
-/**
- * Generate HW shader code. The instructions should have been legalized.
- */
-void *
-toy_compiler_assemble(struct toy_compiler *tc, int *size)
-{
- const struct toy_inst *inst;
- uint32_t *code;
- int pc;
-
- code = MALLOC(tc->num_instructions * 4 * sizeof(uint32_t));
- if (!code)
- return NULL;
-
- pc = 0;
- tc_head(tc);
- while ((inst = tc_next(tc)) != NULL) {
- uint32_t *dw = &code[pc * 4];
- struct codegen cg;
-
- if (pc >= tc->num_instructions) {
- tc_fail(tc, "wrong instructoun count");
- break;
- }
-
- codegen_prepare(&cg, tc->dev, inst, pc, tc->rect_linear_width);
- codegen_validate_region_restrictions(&cg);
-
- switch (inst->opcode) {
- case GEN6_OPCODE_MAD:
- codegen_inst_3src_gen6(&cg, dw);
- break;
- default:
- codegen_inst_gen6(&cg, dw);
- break;
- }
-
- pc++;
- }
-
- /* never return an invalid kernel */
- if (tc->fail) {
- FREE(code);
- return NULL;
- }
-
- if (size)
- *size = pc * 4 * sizeof(uint32_t);
-
- return code;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include <stdio.h>
-#include "genhw/genhw.h"
-#include "toy_compiler.h"
-
-#define DISASM_PRINTER_BUFFER_SIZE 256
-#define DISASM_PRINTER_COLUMN_WIDTH 16
-
-struct disasm_printer {
- char buf[DISASM_PRINTER_BUFFER_SIZE];
- int len;
-};
-
-struct disasm_operand {
- unsigned file:2;
- unsigned type:4;
-
- unsigned addr_mode:1;
- unsigned reg:8;
- unsigned subreg:5;
- unsigned addr_subreg:3;
- unsigned addr_imm:10;
-};
-
-struct disasm_dst_operand {
- struct disasm_operand base;
-
- unsigned horz_stride:2;
- unsigned writemask:4;
-};
-
-struct disasm_src_operand {
- struct disasm_operand base;
-
- unsigned vert_stride:4;
- unsigned width:3;
- unsigned horz_stride:2;
- unsigned swizzle_x:2;
- unsigned swizzle_y:2;
- unsigned swizzle_z:2;
- unsigned swizzle_w:2;
- unsigned negate:1;
- unsigned absolute:1;
-};
-
-struct disasm_inst {
- const struct ilo_dev *dev;
-
- unsigned has_jip:1;
- unsigned has_uip:1;
-
- unsigned opcode:7;
- unsigned access_mode:1;
- unsigned mask_ctrl:1;
- unsigned dep_ctrl:2;
- unsigned qtr_ctrl:2;
- unsigned thread_ctrl:2;
- unsigned pred_ctrl:4;
- unsigned pred_inv:1;
- unsigned exec_size:3;
-
- unsigned cond_modifier:4;
- unsigned sfid:4;
- unsigned fc:4;
-
- unsigned acc_wr_ctrl:1;
- unsigned branch_ctrl:1;
-
- unsigned cmpt_ctrl:1;
- unsigned debug_ctrl:1;
- unsigned saturate:1;
-
- unsigned nib_ctrl:1;
-
- unsigned flag_reg:1;
- unsigned flag_subreg:1;
-
- struct disasm_dst_operand dst;
- struct disasm_src_operand src0;
- struct disasm_src_operand src1;
- union {
- struct disasm_src_operand src2;
- uint64_t imm64;
-
- uint32_t ud;
- int32_t d;
- uint16_t uw;
- int16_t w;
- float f;
-
- struct {
- int16_t jip;
- int16_t uip;
- } ip16;
-
- struct {
- int32_t jip;
- int32_t uip;
- } ip32;
- } u;
-};
-
-static const struct {
- const char *name;
- int src_count;
-} disasm_opcode_table[128] = {
- [GEN6_OPCODE_ILLEGAL] = { "illegal", 0 },
- [GEN6_OPCODE_MOV] = { "mov", 1 },
- [GEN6_OPCODE_SEL] = { "sel", 2 },
- [GEN6_OPCODE_MOVI] = { "movi", 1 },
- [GEN6_OPCODE_NOT] = { "not", 1 },
- [GEN6_OPCODE_AND] = { "and", 2 },
- [GEN6_OPCODE_OR] = { "or", 2 },
- [GEN6_OPCODE_XOR] = { "xor", 2 },
- [GEN6_OPCODE_SHR] = { "shr", 2 },
- [GEN6_OPCODE_SHL] = { "shl", 2 },
- [GEN6_OPCODE_DIM] = { "dim", 1 },
- [GEN6_OPCODE_ASR] = { "asr", 2 },
- [GEN6_OPCODE_CMP] = { "cmp", 2 },
- [GEN6_OPCODE_CMPN] = { "cmpn", 2 },
- [GEN7_OPCODE_CSEL] = { "csel", 3 },
- [GEN7_OPCODE_F32TO16] = { "f32to16", 1 },
- [GEN7_OPCODE_F16TO32] = { "f16to32", 1 },
- [GEN7_OPCODE_BFREV] = { "bfrev", 1 },
- [GEN7_OPCODE_BFE] = { "bfe", 3 },
- [GEN7_OPCODE_BFI1] = { "bfi1", 2 },
- [GEN7_OPCODE_BFI2] = { "bfi2", 3 },
- [GEN6_OPCODE_JMPI] = { "jmpi", 1 },
- [GEN7_OPCODE_BRD] = { "brd", 1 },
- [GEN6_OPCODE_IF] = { "if", 2 },
- [GEN7_OPCODE_BRC] = { "brc", 1 },
- [GEN6_OPCODE_ELSE] = { "else", 1 },
- [GEN6_OPCODE_ENDIF] = { "endif", 0 },
- [GEN6_OPCODE_CASE] = { "case", 2 },
- [GEN6_OPCODE_WHILE] = { "while", 1 },
- [GEN6_OPCODE_BREAK] = { "break", 1 },
- [GEN6_OPCODE_CONT] = { "cont", 1 },
- [GEN6_OPCODE_HALT] = { "halt", 1 },
- [GEN75_OPCODE_CALLA] = { "calla", 1 },
- [GEN6_OPCODE_CALL] = { "call", 1 },
- [GEN6_OPCODE_RETURN] = { "return", 1 },
- [GEN8_OPCODE_GOTO] = { "goto", 1 },
- [GEN6_OPCODE_WAIT] = { "wait", 1 },
- [GEN6_OPCODE_SEND] = { "send", 1 },
- [GEN6_OPCODE_SENDC] = { "sendc", 1 },
- [GEN6_OPCODE_MATH] = { "math", 2 },
- [GEN6_OPCODE_ADD] = { "add", 2 },
- [GEN6_OPCODE_MUL] = { "mul", 2 },
- [GEN6_OPCODE_AVG] = { "avg", 2 },
- [GEN6_OPCODE_FRC] = { "frc", 1 },
- [GEN6_OPCODE_RNDU] = { "rndu", 1 },
- [GEN6_OPCODE_RNDD] = { "rndd", 1 },
- [GEN6_OPCODE_RNDE] = { "rnde", 1 },
- [GEN6_OPCODE_RNDZ] = { "rndz", 1 },
- [GEN6_OPCODE_MAC] = { "mac", 2 },
- [GEN6_OPCODE_MACH] = { "mach", 2 },
- [GEN6_OPCODE_LZD] = { "lzd", 1 },
- [GEN7_OPCODE_FBH] = { "fbh", 1 },
- [GEN7_OPCODE_FBL] = { "fbl", 1 },
- [GEN7_OPCODE_CBIT] = { "cbit", 1 },
- [GEN7_OPCODE_ADDC] = { "addc", 2 },
- [GEN7_OPCODE_SUBB] = { "subb", 2 },
- [GEN6_OPCODE_SAD2] = { "sad2", 2 },
- [GEN6_OPCODE_SADA2] = { "sada2", 2 },
- [GEN6_OPCODE_DP4] = { "dp4", 2 },
- [GEN6_OPCODE_DPH] = { "dph", 2 },
- [GEN6_OPCODE_DP3] = { "dp3", 2 },
- [GEN6_OPCODE_DP2] = { "dp2", 2 },
- [GEN6_OPCODE_LINE] = { "line", 2 },
- [GEN6_OPCODE_PLN] = { "pln", 2 },
- [GEN6_OPCODE_MAD] = { "mad", 3 },
- [GEN6_OPCODE_LRP] = { "lrp", 3 },
- [GEN6_OPCODE_NOP] = { "nop", 0 },
-};
-
-static void
-disasm_inst_decode_dw0_opcode_gen6(struct disasm_inst *inst, uint32_t dw0)
-{
- ILO_DEV_ASSERT(inst->dev, 6, 8);
-
- inst->opcode = GEN_EXTRACT(dw0, GEN6_INST_OPCODE);
-
- switch (inst->opcode) {
- case GEN6_OPCODE_IF:
- inst->has_jip = true;
- inst->has_uip = (ilo_dev_gen(inst->dev) >= ILO_GEN(7));
- break;
- case GEN6_OPCODE_ELSE:
- inst->has_jip = true;
- inst->has_uip = (ilo_dev_gen(inst->dev) >= ILO_GEN(8));
- break;
- case GEN6_OPCODE_BREAK:
- case GEN6_OPCODE_CONT:
- case GEN6_OPCODE_HALT:
- inst->has_uip = true;
- /* fall through */
- case GEN6_OPCODE_JMPI:
- case GEN7_OPCODE_BRD:
- case GEN7_OPCODE_BRC:
- case GEN6_OPCODE_ENDIF:
- case GEN6_OPCODE_CASE:
- case GEN6_OPCODE_WHILE:
- case GEN75_OPCODE_CALLA:
- case GEN6_OPCODE_CALL:
- case GEN6_OPCODE_RETURN:
- inst->has_jip = true;
- break;
- default:
- break;
- }
-}
-
-static void
-disasm_inst_decode_dw0_gen6(struct disasm_inst *inst, uint32_t dw0)
-{
- ILO_DEV_ASSERT(inst->dev, 6, 8);
-
- disasm_inst_decode_dw0_opcode_gen6(inst, dw0);
-
- inst->access_mode = GEN_EXTRACT(dw0, GEN6_INST_ACCESSMODE);
-
- if (ilo_dev_gen(inst->dev) >= ILO_GEN(8)) {
- inst->dep_ctrl = GEN_EXTRACT(dw0, GEN8_INST_DEPCTRL);
- inst->nib_ctrl = (bool) (dw0 & GEN8_INST_NIBCTRL);
- } else {
- inst->mask_ctrl = GEN_EXTRACT(dw0, GEN6_INST_MASKCTRL);
- inst->dep_ctrl = GEN_EXTRACT(dw0, GEN6_INST_DEPCTRL);
- }
-
- inst->qtr_ctrl = GEN_EXTRACT(dw0, GEN6_INST_QTRCTRL);
- inst->thread_ctrl = GEN_EXTRACT(dw0, GEN6_INST_THREADCTRL);
- inst->pred_ctrl = GEN_EXTRACT(dw0, GEN6_INST_PREDCTRL);
-
- inst->pred_inv = (bool) (dw0 & GEN6_INST_PREDINV);
-
- inst->exec_size = GEN_EXTRACT(dw0, GEN6_INST_EXECSIZE);
-
- switch (inst->opcode) {
- case GEN6_OPCODE_SEND:
- case GEN6_OPCODE_SENDC:
- inst->sfid = GEN_EXTRACT(dw0, GEN6_INST_SFID);
- break;
- case GEN6_OPCODE_MATH:
- inst->fc = GEN_EXTRACT(dw0, GEN6_INST_FC);
- break;
- default:
- inst->cond_modifier = GEN_EXTRACT(dw0, GEN6_INST_CONDMODIFIER);
- break;
- }
-
- switch (inst->opcode) {
- case GEN6_OPCODE_IF:
- case GEN6_OPCODE_ELSE:
- case GEN8_OPCODE_GOTO:
- if (ilo_dev_gen(inst->dev) >= ILO_GEN(8)) {
- inst->branch_ctrl = (bool) (dw0 & GEN8_INST_BRANCHCTRL);
- break;
- }
- default:
- inst->acc_wr_ctrl = (bool) (dw0 & GEN6_INST_ACCWRCTRL);
- break;
- }
-
- inst->cmpt_ctrl = (bool) (dw0 & GEN6_INST_CMPTCTRL);
- inst->debug_ctrl = (bool) (dw0 & GEN6_INST_DEBUGCTRL);
- inst->saturate = (bool) (dw0 & GEN6_INST_SATURATE);
-}
-
-static void
-disasm_inst_decode_dw1_low_gen6(struct disasm_inst *inst, uint32_t dw1)
-{
- ILO_DEV_ASSERT(inst->dev, 6, 7.5);
-
- inst->dst.base.file = GEN_EXTRACT(dw1, GEN6_INST_DST_FILE);
- inst->dst.base.type = GEN_EXTRACT(dw1, GEN6_INST_DST_TYPE);
- inst->src0.base.file = GEN_EXTRACT(dw1, GEN6_INST_SRC0_FILE);
- inst->src0.base.type = GEN_EXTRACT(dw1, GEN6_INST_SRC0_TYPE);
- inst->src1.base.file = GEN_EXTRACT(dw1, GEN6_INST_SRC1_FILE);
- inst->src1.base.type = GEN_EXTRACT(dw1, GEN6_INST_SRC1_TYPE);
-
- if (ilo_dev_gen(inst->dev) >= ILO_GEN(7))
- inst->nib_ctrl = (bool) (dw1 & GEN7_INST_NIBCTRL);
-}
-
-static void
-disasm_inst_decode_dw1_low_gen8(struct disasm_inst *inst, uint32_t dw1)
-{
- ILO_DEV_ASSERT(inst->dev, 8, 8);
-
- inst->flag_subreg = GEN_EXTRACT(dw1, GEN8_INST_FLAG_SUBREG);
- inst->flag_reg = GEN_EXTRACT(dw1, GEN8_INST_FLAG_REG);
- inst->mask_ctrl = GEN_EXTRACT(dw1, GEN8_INST_MASKCTRL);
-
- inst->dst.base.file = GEN_EXTRACT(dw1, GEN8_INST_DST_FILE);
- inst->dst.base.type = GEN_EXTRACT(dw1, GEN8_INST_DST_TYPE);
- inst->src0.base.file = GEN_EXTRACT(dw1, GEN8_INST_SRC0_FILE);
- inst->src0.base.type = GEN_EXTRACT(dw1, GEN8_INST_SRC0_TYPE);
-
- inst->dst.base.addr_imm = GEN_EXTRACT(dw1, GEN8_INST_DST_ADDR_IMM_BIT9) <<
- GEN8_INST_DST_ADDR_IMM_BIT9__SHR;
-}
-
-static void
-disasm_inst_decode_dw1_high_gen6(struct disasm_inst *inst, uint32_t dw1)
-{
- ILO_DEV_ASSERT(inst->dev, 6, 8);
-
- inst->dst.base.addr_mode = GEN_EXTRACT(dw1, GEN6_INST_DST_ADDRMODE);
-
- if (inst->dst.base.addr_mode == GEN6_ADDRMODE_DIRECT) {
- inst->dst.base.reg = GEN_EXTRACT(dw1, GEN6_INST_DST_REG);
-
- if (inst->access_mode == GEN6_ALIGN_1) {
- inst->dst.base.subreg = GEN_EXTRACT(dw1, GEN6_INST_DST_SUBREG);
- } else {
- inst->dst.base.subreg =
- GEN_EXTRACT(dw1, GEN6_INST_DST_SUBREG_ALIGN16) <<
- GEN6_INST_DST_SUBREG_ALIGN16__SHR;
- }
- } else {
- if (ilo_dev_gen(inst->dev) >= ILO_GEN(8)) {
- inst->dst.base.addr_subreg =
- GEN_EXTRACT(dw1, GEN8_INST_DST_ADDR_SUBREG);
-
- /* bit 9 is already set in disasm_inst_decode_dw1_low_gen8() */
- if (inst->access_mode == GEN6_ALIGN_1) {
- inst->dst.base.addr_imm |=
- GEN_EXTRACT(dw1, GEN8_INST_DST_ADDR_IMM);
- } else {
- inst->dst.base.addr_imm |=
- GEN_EXTRACT(dw1, GEN8_INST_DST_ADDR_IMM_ALIGN16) <<
- GEN8_INST_DST_ADDR_IMM_ALIGN16__SHR;
- }
- } else {
- inst->dst.base.addr_subreg =
- GEN_EXTRACT(dw1, GEN6_INST_DST_ADDR_SUBREG);
-
- if (inst->access_mode == GEN6_ALIGN_1) {
- inst->dst.base.addr_imm =
- GEN_EXTRACT(dw1, GEN6_INST_DST_ADDR_IMM);
- } else {
- inst->dst.base.addr_imm =
- GEN_EXTRACT(dw1, GEN6_INST_DST_ADDR_IMM_ALIGN16) <<
- GEN6_INST_DST_ADDR_IMM_ALIGN16__SHR;
- }
- }
- }
-
- inst->dst.horz_stride = GEN_EXTRACT(dw1, GEN6_INST_DST_HORZSTRIDE);
-
- if (inst->access_mode == GEN6_ALIGN_1)
- inst->dst.writemask = 0xf;
- else
- inst->dst.writemask = GEN_EXTRACT(dw1, GEN6_INST_DST_WRITEMASK);
-}
-
-static void
-disasm_inst_decode_dw1_gen6(struct disasm_inst *inst, uint32_t dw1)
-{
- ILO_DEV_ASSERT(inst->dev, 6, 8);
-
- if (ilo_dev_gen(inst->dev) >= ILO_GEN(8))
- disasm_inst_decode_dw1_low_gen8(inst, dw1);
- else
- disasm_inst_decode_dw1_low_gen6(inst, dw1);
-
- if (ilo_dev_gen(inst->dev) == ILO_GEN(6) &&
- inst->has_jip && !inst->has_uip)
- inst->u.imm64 = dw1 >> 16;
- else
- disasm_inst_decode_dw1_high_gen6(inst, dw1);
-}
-
-static void
-disasm_inst_decode_dw2_dw3_gen6(struct disasm_inst *inst,
- uint32_t dw2, uint32_t dw3)
-{
- int imm_bits = 0, count, i;
-
- ILO_DEV_ASSERT(inst->dev, 6, 8);
-
- if (ilo_dev_gen(inst->dev) >= ILO_GEN(8)) {
- /* how about real 64-bit immediates? */
- if (inst->has_uip) {
- imm_bits = 64;
- inst->src1.base.file = GEN6_FILE_IMM;
- inst->src1.base.type = GEN6_TYPE_D;
- } else {
- inst->src1.base.file = GEN_EXTRACT(dw2, GEN8_INST_SRC1_FILE);
- inst->src1.base.type = GEN_EXTRACT(dw2, GEN8_INST_SRC1_TYPE);
-
- if (inst->src0.base.file == GEN6_FILE_IMM ||
- inst->src1.base.file == GEN6_FILE_IMM)
- imm_bits = 32;
- }
- } else {
- if (ilo_dev_gen(inst->dev) >= ILO_GEN(7))
- inst->flag_reg = GEN_EXTRACT(dw2, GEN7_INST_FLAG_REG);
- inst->flag_subreg = GEN_EXTRACT(dw2, GEN6_INST_FLAG_SUBREG);
-
- if (inst->src0.base.file == GEN6_FILE_IMM ||
- inst->src1.base.file == GEN6_FILE_IMM)
- imm_bits = 32;
- }
-
- switch (imm_bits) {
- case 32:
- inst->u.imm64 = dw3;
- count = 1;
- break;
- case 64:
- inst->u.imm64 = (uint64_t) dw2 << 32 | dw3;
- count = 0;
- break;
- default:
- count = 2;
- break;
- }
-
- for (i = 0; i < count; i++) {
- struct disasm_src_operand *src = (i == 0) ? &inst->src0 : &inst->src1;
- const uint32_t dw = (i == 0) ? dw2 : dw3;
-
- src->base.addr_mode = GEN_EXTRACT(dw, GEN6_INST_SRC_ADDRMODE);
-
- if (src->base.addr_mode == GEN6_ADDRMODE_DIRECT) {
- src->base.reg = GEN_EXTRACT(dw, GEN6_INST_SRC_REG);
-
- if (inst->access_mode == GEN6_ALIGN_1) {
- src->base.subreg = GEN_EXTRACT(dw, GEN6_INST_SRC_SUBREG);
- } else {
- src->base.subreg = GEN_EXTRACT(dw, GEN6_INST_SRC_SUBREG_ALIGN16) <<
- GEN6_INST_SRC_SUBREG_ALIGN16__SHR;
- }
- } else {
- if (ilo_dev_gen(inst->dev) >= ILO_GEN(8)) {
- src->base.addr_subreg =
- GEN_EXTRACT(dw, GEN8_INST_SRC_ADDR_SUBREG);
-
- if (inst->access_mode == GEN6_ALIGN_1) {
- src->base.addr_imm = GEN_EXTRACT(dw, GEN8_INST_SRC_ADDR_IMM);
- } else {
- src->base.addr_imm =
- GEN_EXTRACT(dw, GEN8_INST_SRC_ADDR_IMM_ALIGN16) <<
- GEN8_INST_SRC_ADDR_IMM_ALIGN16__SHR;
- }
-
- if (i == 0) {
- inst->dst.base.addr_imm |= GEN_EXTRACT(dw,
- GEN8_INST_SRC0_ADDR_IMM_BIT9) <<
- GEN8_INST_SRC0_ADDR_IMM_BIT9__SHR;
- } else {
- inst->dst.base.addr_imm |= GEN_EXTRACT(dw,
- GEN8_INST_SRC1_ADDR_IMM_BIT9) <<
- GEN8_INST_SRC1_ADDR_IMM_BIT9__SHR;
- }
- } else {
- src->base.addr_subreg =
- GEN_EXTRACT(dw, GEN6_INST_SRC_ADDR_SUBREG);
-
- if (inst->access_mode == GEN6_ALIGN_1) {
- src->base.addr_imm = GEN_EXTRACT(dw, GEN6_INST_SRC_ADDR_IMM);
- } else {
- src->base.addr_imm =
- GEN_EXTRACT(dw, GEN6_INST_SRC_ADDR_IMM_ALIGN16) <<
- GEN6_INST_SRC_ADDR_IMM_ALIGN16__SHR;
- }
- }
- }
-
- src->vert_stride = GEN_EXTRACT(dw, GEN6_INST_SRC_VERTSTRIDE);
-
- if (inst->access_mode == GEN6_ALIGN_1) {
- src->width = GEN_EXTRACT(dw, GEN6_INST_SRC_WIDTH);
- src->horz_stride = GEN_EXTRACT(dw, GEN6_INST_SRC_HORZSTRIDE);
-
- src->swizzle_x = GEN6_SWIZZLE_X;
- src->swizzle_y = GEN6_SWIZZLE_Y;
- src->swizzle_z = GEN6_SWIZZLE_Z;
- src->swizzle_w = GEN6_SWIZZLE_W;
- } else {
- src->width = GEN6_WIDTH_4;
- src->horz_stride = GEN6_HORZSTRIDE_1;
-
- src->swizzle_x = GEN_EXTRACT(dw, GEN6_INST_SRC_SWIZZLE_X);
- src->swizzle_y = GEN_EXTRACT(dw, GEN6_INST_SRC_SWIZZLE_Y);
- src->swizzle_z = GEN_EXTRACT(dw, GEN6_INST_SRC_SWIZZLE_Z);
- src->swizzle_w = GEN_EXTRACT(dw, GEN6_INST_SRC_SWIZZLE_W);
- }
-
- src->negate = (bool) (dw & GEN6_INST_SRC_NEGATE);
- src->absolute = (bool) (dw & GEN6_INST_SRC_ABSOLUTE);
- }
-}
-
-static void
-disasm_inst_decode_3src_dw1_gen6(struct disasm_inst *inst, uint32_t dw1)
-{
- static const unsigned type_mapping[4] = {
- [GEN7_TYPE_F_3SRC] = GEN6_TYPE_F,
- [GEN7_TYPE_D_3SRC] = GEN6_TYPE_D,
- [GEN7_TYPE_UD_3SRC] = GEN6_TYPE_UD,
- [GEN7_TYPE_DF_3SRC] = GEN7_TYPE_DF,
- };
-
- ILO_DEV_ASSERT(inst->dev, 6, 7.5);
-
- inst->flag_subreg = GEN_EXTRACT(dw1, GEN6_3SRC_FLAG_SUBREG);
-
- if (ilo_dev_gen(inst->dev) >= ILO_GEN(7)) {
- inst->nib_ctrl = (bool) (dw1 & GEN7_3SRC_NIBCTRL);
- inst->flag_reg = GEN_EXTRACT(dw1, GEN7_3SRC_FLAG_REG);
-
- inst->dst.base.file = GEN6_FILE_GRF;
- inst->dst.base.type = GEN_EXTRACT(dw1, GEN7_3SRC_DST_TYPE);
- inst->dst.base.type = type_mapping[inst->dst.base.type];
-
- inst->src0.base.type = GEN_EXTRACT(dw1, GEN7_3SRC_SRC_TYPE);
- inst->src0.base.type = type_mapping[inst->src0.base.type];
-
- inst->src1.base.type = inst->src0.base.type;
- inst->u.src2.base.type = inst->src0.base.type;
- } else {
- inst->dst.base.file = (dw1 & GEN6_3SRC_DST_FILE_MRF) ?
- GEN6_FILE_MRF: GEN6_FILE_GRF;
- inst->dst.base.type = GEN6_TYPE_F;
-
- inst->src0.base.type = GEN6_TYPE_F;
- inst->src1.base.type = GEN6_TYPE_F;
- inst->u.src2.base.type = GEN6_TYPE_F;
- }
-
- inst->dst.base.addr_mode = GEN6_ADDRMODE_DIRECT;
- inst->dst.base.reg = GEN_EXTRACT(dw1, GEN6_3SRC_DST_REG);
- inst->dst.base.subreg = GEN_EXTRACT(dw1, GEN6_3SRC_DST_SUBREG) <<
- GEN6_3SRC_DST_SUBREG__SHR;
-
- inst->dst.horz_stride = GEN6_HORZSTRIDE_1;
- inst->dst.writemask = GEN_EXTRACT(dw1, GEN6_3SRC_DST_WRITEMASK);
-
- inst->src0.base.file = GEN6_FILE_GRF;
- inst->src0.negate = (bool) (dw1 & GEN6_3SRC_SRC0_NEGATE);
- inst->src0.absolute = (bool) (dw1 & GEN6_3SRC_SRC0_ABSOLUTE);
- inst->src1.base.file = GEN6_FILE_GRF;
- inst->src1.negate = (bool) (dw1 & GEN6_3SRC_SRC1_NEGATE);
- inst->src1.absolute = (bool) (dw1 & GEN6_3SRC_SRC1_ABSOLUTE);
- inst->u.src2.base.file = GEN6_FILE_GRF;
- inst->u.src2.negate = (bool) (dw1 & GEN6_3SRC_SRC2_NEGATE);
- inst->u.src2.absolute = (bool) (dw1 & GEN6_3SRC_SRC2_ABSOLUTE);
-}
-
-static void
-disasm_inst_decode_3src_dw1_gen8(struct disasm_inst *inst, uint32_t dw1)
-{
- static const unsigned type_mapping[8] = {
- [GEN7_TYPE_F_3SRC] = GEN6_TYPE_F,
- [GEN7_TYPE_D_3SRC] = GEN6_TYPE_D,
- [GEN7_TYPE_UD_3SRC] = GEN6_TYPE_UD,
- [GEN7_TYPE_DF_3SRC] = GEN7_TYPE_DF,
- /* map unknown types to unknown types */
- [0x4] = 0xf,
- [0x5] = 0xf,
- [0x6] = 0xf,
- [0x7] = 0xf,
- };
-
- ILO_DEV_ASSERT(inst->dev, 8, 8);
-
- inst->flag_subreg = GEN_EXTRACT(dw1, GEN8_3SRC_FLAG_SUBREG);
- inst->flag_reg = GEN_EXTRACT(dw1, GEN8_3SRC_FLAG_REG);
- inst->mask_ctrl = GEN_EXTRACT(dw1, GEN8_3SRC_MASKCTRL);
- inst->src0.absolute = (bool) (dw1 & GEN8_3SRC_SRC0_ABSOLUTE);
- inst->src0.negate = (bool) (dw1 & GEN8_3SRC_SRC0_NEGATE);
- inst->src1.negate = (bool) (dw1 & GEN8_3SRC_SRC1_NEGATE);
- inst->src1.absolute = (bool) (dw1 & GEN8_3SRC_SRC1_ABSOLUTE);
- inst->u.src2.negate = (bool) (dw1 & GEN8_3SRC_SRC2_NEGATE);
- inst->u.src2.absolute = (bool) (dw1 & GEN8_3SRC_SRC2_ABSOLUTE);
-
- inst->src0.base.file = GEN6_FILE_GRF;
- inst->src0.base.type = GEN_EXTRACT(dw1, GEN8_3SRC_SRC_TYPE);
- inst->src0.base.type = type_mapping[inst->src0.base.type];
-
- inst->src1.base.file = GEN6_FILE_GRF;
- inst->src1.base.type = inst->src0.base.type;
-
- inst->u.src2.base.file = GEN6_FILE_GRF;
- inst->u.src2.base.type = inst->src0.base.type;
-
- inst->dst.base.file = GEN6_FILE_GRF;
- inst->dst.base.type = GEN_EXTRACT(dw1, GEN8_3SRC_DST_TYPE);
- inst->dst.base.type = type_mapping[inst->dst.base.type];
- inst->dst.base.addr_mode = GEN6_ADDRMODE_DIRECT;
- inst->dst.horz_stride = GEN6_HORZSTRIDE_1;
-
- inst->dst.writemask = GEN_EXTRACT(dw1, GEN6_3SRC_DST_WRITEMASK);
- inst->dst.base.subreg = GEN_EXTRACT(dw1, GEN6_3SRC_DST_SUBREG) <<
- GEN6_3SRC_DST_SUBREG__SHR;
- inst->dst.base.reg = GEN_EXTRACT(dw1, GEN6_3SRC_DST_REG);
-}
-
-static void
-disasm_inst_decode_3src_dw2_dw3_gen6(struct disasm_inst *inst,
- uint32_t dw2, uint32_t dw3)
-{
- const uint64_t qw = (uint64_t) dw3 << 32 | dw2;
- int i;
-
- ILO_DEV_ASSERT(inst->dev, 6, 8);
-
- for (i = 0; i < 3; i++) {
- struct disasm_src_operand *src = (i == 0) ? &inst->src0 :
- (i == 1) ? &inst->src1 :
- &inst->u.src2;
- const uint32_t dw = (i == 0) ? GEN_EXTRACT(qw, GEN6_3SRC_SRC_0) :
- (i == 1) ? GEN_EXTRACT(qw, GEN6_3SRC_SRC_1) :
- GEN_EXTRACT(qw, GEN6_3SRC_SRC_2);
-
- src->base.addr_mode = GEN6_ADDRMODE_DIRECT;
- src->base.reg = GEN_EXTRACT(dw, GEN6_3SRC_SRC_REG);
- src->base.subreg = GEN_EXTRACT(dw, GEN6_3SRC_SRC_SUBREG) <<
- GEN6_3SRC_SRC_SUBREG__SHR;
-
- if (dw & GEN6_3SRC_SRC_REPCTRL) {
- src->vert_stride = GEN6_VERTSTRIDE_0;
- src->width = GEN6_WIDTH_1;
- src->horz_stride = GEN6_HORZSTRIDE_0;
- } else {
- src->vert_stride = GEN6_VERTSTRIDE_4;
- src->width = GEN6_WIDTH_4;
- src->horz_stride = GEN6_HORZSTRIDE_1;
- }
-
- src->swizzle_x = GEN_EXTRACT(dw, GEN6_3SRC_SRC_SWIZZLE_X);
- src->swizzle_y = GEN_EXTRACT(dw, GEN6_3SRC_SRC_SWIZZLE_Y);
- src->swizzle_z = GEN_EXTRACT(dw, GEN6_3SRC_SRC_SWIZZLE_Z);
- src->swizzle_w = GEN_EXTRACT(dw, GEN6_3SRC_SRC_SWIZZLE_W);
- }
-}
-
-/*
- * When GEN6_INST_CMPTCTRL of DW0 is set, the instruction has 64 bits and is
- * in EU_INSTRUCTION_COMPACT_TWO_SRC form. We should have expanded it to its
- * original form.
- *
- * Depending on the opcode, the 128-bits instruction is in one of the
- * following forms
- *
- * - EU_INSTRUCTION_BASIC_ONE_SRC
- * - EU_INSTRUCTION_BASIC_TWO_SRC
- * - EU_INSTRUCTION_BASIC_THREE_SRC
- * - EU_INSTRUCTION_BRANCH_CONDITIONAL
- * - EU_INSTRUCTION_BRANCH_ONE_SRC
- * - EU_INSTRUCTION_BRANCH_TWO_SRC
- * - EU_INSTRUCTION_ILLEGAL
- * - EU_INSTRUCTION_MATH
- * - EU_INSTRUCTION_NOP
- * - EU_INSTRUCTION_SEND
- *
- * In EU_INSTRUCTION_BASIC_ONE_SRC form,
- *
- * - DW0 is EU_INSTRUCTION_HEADER
- * - DW1 is EU_INSTRUCTION_OPERAND_CONTROLS
- * - DW2 is Source 0 and EU_INSTRUCTION_FLAGS
- * - DW3 is reserved unless Source 0 is an immediate
- *
- * All other forms except EU_INSTRUCTION_BASIC_THREE_SRC are quite compatible
- * with EU_INSTRUCTION_BASIC_ONE_SRC.
- */
-static void
-disasm_inst_decode(struct disasm_inst *inst,
- const uint32_t *dw)
-{
- assert(!(dw[0] & GEN6_INST_CMPTCTRL));
-
- disasm_inst_decode_dw0_gen6(inst, dw[0]);
-
- if (disasm_opcode_table[inst->opcode].src_count == 3) {
- if (ilo_dev_gen(inst->dev) >= ILO_GEN(8))
- disasm_inst_decode_3src_dw1_gen8(inst, dw[1]);
- else
- disasm_inst_decode_3src_dw1_gen6(inst, dw[1]);
- disasm_inst_decode_3src_dw2_dw3_gen6(inst, dw[2], dw[3]);
- } else {
- disasm_inst_decode_dw1_gen6(inst, dw[1]);
- disasm_inst_decode_dw2_dw3_gen6(inst, dw[2], dw[3]);
- }
-}
-
-static const char *
-disasm_inst_opcode(const struct disasm_inst *inst)
-{
- return (disasm_opcode_table[inst->opcode].name) ?
- disasm_opcode_table[inst->opcode].name : "BAD";
-}
-
-static const char *
-disasm_inst_pred_ctrl(const struct disasm_inst *inst)
-{
- if (inst->access_mode == GEN6_ALIGN_1) {
- switch (inst->pred_ctrl) {
- case GEN6_PREDCTRL_NORMAL: return "";
- case GEN6_PREDCTRL_ANYV: return ".anyv";
- case GEN6_PREDCTRL_ALLV: return ".allv";
- case GEN6_PREDCTRL_ANY2H: return ".any2h";
- case GEN6_PREDCTRL_ALL2H: return ".all2h";
- case GEN6_PREDCTRL_ANY4H: return ".any4h";
- case GEN6_PREDCTRL_ALL4H: return ".all4h";
- case GEN6_PREDCTRL_ANY8H: return ".any8h";
- case GEN6_PREDCTRL_ALL8H: return ".all8h";
- case GEN6_PREDCTRL_ANY16H: return ".any16h";
- case GEN6_PREDCTRL_ALL16H: return ".all16h";
- case GEN7_PREDCTRL_ANY32H: return ".any32h";
- case GEN7_PREDCTRL_ALL32H: return ".all32h";
- default: return ".BAD";
- }
- } else {
- switch (inst->pred_ctrl) {
- case GEN6_PREDCTRL_NORMAL: return "";
- case GEN6_PREDCTRL_X: return ".x";
- case GEN6_PREDCTRL_Y: return ".y";
- case GEN6_PREDCTRL_Z: return ".z";
- case GEN6_PREDCTRL_W: return ".w";
- default: return ".BAD";
- }
- }
-}
-
-static char
-disasm_inst_pred_inv(const struct disasm_inst *inst)
-{
- return (inst->pred_inv) ? '-' : '+';
-}
-
-static const char *
-disasm_inst_exec_size(const struct disasm_inst *inst)
-{
- switch (inst->exec_size) {
- case GEN6_EXECSIZE_1: return "1";
- case GEN6_EXECSIZE_2: return "2";
- case GEN6_EXECSIZE_4: return "4";
- case GEN6_EXECSIZE_8: return "8";
- case GEN6_EXECSIZE_16: return "16";
- case GEN6_EXECSIZE_32: return "32";
- default: return "BAD";
- }
-}
-
-static const char *
-disasm_inst_fc(const struct disasm_inst *inst)
-{
- assert(inst->opcode == GEN6_OPCODE_MATH);
-
- switch (inst->fc) {
- case GEN6_MATH_INV: return "inv";
- case GEN6_MATH_LOG: return "log";
- case GEN6_MATH_EXP: return "exp";
- case GEN6_MATH_SQRT: return "sqrt";
- case GEN6_MATH_RSQ: return "rsq";
- case GEN6_MATH_SIN: return "sin";
- case GEN6_MATH_COS: return "cos";
- case GEN6_MATH_FDIV: return "fdiv";
- case GEN6_MATH_POW: return "pow";
- case GEN6_MATH_INT_DIV: return "int_div";
- case GEN6_MATH_INT_DIV_QUOTIENT: return "int_div_quotient";
- case GEN6_MATH_INT_DIV_REMAINDER: return "int_div_remainder";
- case GEN8_MATH_INVM: return "invm";
- case GEN8_MATH_RSQRTM: return "rsqrtm";
- default: return "BAD";
- }
-}
-
-static const char *
-disasm_inst_sfid(const struct disasm_inst *inst)
-{
- assert(inst->opcode == GEN6_OPCODE_SEND ||
- inst->opcode == GEN6_OPCODE_SENDC);
-
- switch (inst->sfid) {
- case GEN6_SFID_NULL: return "null";
- case GEN6_SFID_SAMPLER: return "sampler";
- case GEN6_SFID_GATEWAY: return "gateway";
- case GEN6_SFID_DP_SAMPLER: return "dp sampler";
- case GEN6_SFID_DP_RC: return "dp render";
- case GEN6_SFID_URB: return "urb";
- case GEN6_SFID_SPAWNER: return "spawner";
- case GEN6_SFID_VME: return "vme";
- case GEN6_SFID_DP_CC: return "dp const";
- case GEN7_SFID_DP_DC0: return "dp data 0";
- case GEN7_SFID_PI: return "pixel interp";
- case GEN75_SFID_DP_DC1: return "dp data 1";
- default: return "BAD";
- }
-}
-
-static const char *
-disasm_inst_cond_modifier(const struct disasm_inst *inst)
-{
- switch (inst->cond_modifier) {
- case GEN6_COND_NONE: return "";
- case GEN6_COND_Z: return ".z";
- case GEN6_COND_NZ: return ".nz";
- case GEN6_COND_G: return ".g";
- case GEN6_COND_GE: return ".ge";
- case GEN6_COND_L: return ".l";
- case GEN6_COND_LE: return ".le";
- case GEN6_COND_O: return ".o";
- case GEN6_COND_U: return ".u";
- default: return ".BAD";
- }
-}
-
-static const char *
-disasm_inst_debug_ctrl(const struct disasm_inst *inst)
-{
- return (inst->debug_ctrl) ? ".breakpoint" : "";
-}
-
-static const char *
-disasm_inst_saturate(const struct disasm_inst *inst)
-{
- return (inst->saturate) ? ".sat" : "";
-}
-
-static const char *
-disasm_inst_flag_reg(const struct disasm_inst *inst)
-{
- static const char *flag_names[2][2] = {
- { "f0", "f0.1" },
- { "f1.0", "f1.1" },
- };
-
- return (inst->flag_reg <= 1 && inst->flag_subreg <= 1) ?
- flag_names[inst->flag_reg][inst->flag_subreg] : "fBAD";
-}
-
-static const char *
-disasm_inst_access_mode(const struct disasm_inst *inst)
-{
- switch (inst->access_mode) {
- case GEN6_ALIGN_1: return " align1";
- case GEN6_ALIGN_16: return " align16";
- default: return " alignBAD";
- }
-}
-
-static const char *
-disasm_inst_mask_ctrl(const struct disasm_inst *inst)
-{
- switch (inst->mask_ctrl) {
- case GEN6_MASKCTRL_NORMAL: return "";
- case GEN6_MASKCTRL_NOMASK: return " WE_all";
- default: return " WE_BAD";
- }
-}
-
-static const char *
-disasm_inst_dep_ctrl(const struct disasm_inst *inst)
-{
- switch (inst->dep_ctrl) {
- case GEN6_DEPCTRL_NORMAL: return "";
- case GEN6_DEPCTRL_NODDCLR: return " NoDDClr";
- case GEN6_DEPCTRL_NODDCHK: return " NoDDChk";
- case GEN6_DEPCTRL_NEITHER: return " NoDDClr,NoDDChk";
- default: return " NoDDBAD";
- }
-}
-
-static const char *
-disasm_inst_qtr_ctrl(const struct disasm_inst *inst)
-{
- switch (inst->exec_size) {
- case GEN6_EXECSIZE_8:
- switch (inst->qtr_ctrl) {
- case GEN6_QTRCTRL_1Q: return " 1Q";
- case GEN6_QTRCTRL_2Q: return " 2Q";
- case GEN6_QTRCTRL_3Q: return " 3Q";
- case GEN6_QTRCTRL_4Q: return " 4Q";
- default: return " BADQ";
- }
- break;
- case GEN6_EXECSIZE_16:
- switch (inst->qtr_ctrl) {
- case GEN6_QTRCTRL_1H: return " 1H";
- case GEN6_QTRCTRL_2H: return " 2H";
- default: return " BADH";
- }
- break;
- default:
- return "";
- }
-
-}
-
-static const char *
-disasm_inst_thread_ctrl(const struct disasm_inst *inst)
-{
- switch (inst->thread_ctrl) {
- case GEN6_THREADCTRL_NORMAL: return "";
- case GEN6_THREADCTRL_ATOMIC: return " atomic";
- case GEN6_THREADCTRL_SWITCH: return " switch";
- default: return " BAD";
- }
-}
-
-static const char *
-disasm_inst_acc_wr_ctrl(const struct disasm_inst *inst)
-{
- return (inst->acc_wr_ctrl) ? " AccWrEnable" : "";
-}
-
-static const char *
-disasm_inst_cmpt_ctrl(const struct disasm_inst *inst)
-{
- return (inst->cmpt_ctrl) ? " compacted" : "";
-}
-
-static const char *
-disasm_inst_eot(const struct disasm_inst *inst)
-{
- const uint32_t mdesc = inst->u.ud;
-
- if (inst->opcode == GEN6_OPCODE_SEND ||
- inst->opcode == GEN6_OPCODE_SENDC)
- return (mdesc & GEN6_MSG_EOT) ? " EOT" : "";
- else
- return "";
-}
-
-static const char *
-disasm_inst_file(const struct disasm_inst *inst,
- const struct disasm_operand *operand,
- bool *multi_regs)
-{
- switch (operand->file) {
- case GEN6_FILE_ARF:
- switch (operand->reg & 0xf0) {
- case GEN6_ARF_NULL: *multi_regs = false; return "null";
- case GEN6_ARF_A0: *multi_regs = true; return "a";
- case GEN6_ARF_ACC0: *multi_regs = true; return "acc";
- case GEN6_ARF_F0: *multi_regs = true; return "f";
- case GEN6_ARF_SR0: *multi_regs = true; return "sr";
- case GEN6_ARF_CR0: *multi_regs = true; return "cr";
- case GEN6_ARF_N0: *multi_regs = true; return "n";
- case GEN6_ARF_IP: *multi_regs = false; return "ip";
- case GEN6_ARF_TDR: *multi_regs = false; return "tdr";
- case GEN7_ARF_TM0: *multi_regs = true; return "tm";
- default: *multi_regs = false; return "BAD";
- }
- break;
- case GEN6_FILE_GRF: *multi_regs = true; return "g";
- case GEN6_FILE_MRF: *multi_regs = true; return "m";
- case GEN6_FILE_IMM: *multi_regs = true; return "";
- default: *multi_regs = false; return "BAD";
- }
-}
-
-static const char *
-disasm_inst_type(const struct disasm_inst *inst,
- const struct disasm_operand *operand)
-{
- if (operand->file == GEN6_FILE_IMM) {
- switch (operand->type) {
- case GEN6_TYPE_UD: return "UD";
- case GEN6_TYPE_D: return "D";
- case GEN6_TYPE_UW: return "UW";
- case GEN6_TYPE_W: return "W";
- case GEN6_TYPE_UV_IMM: return "UV";
- case GEN6_TYPE_VF_IMM: return "VF";
- case GEN6_TYPE_V_IMM: return "V";
- case GEN6_TYPE_F: return "F";
- case GEN8_TYPE_DF_IMM: return "DF";
- case GEN8_TYPE_HF_IMM: return "HF";
- default: return "BAD";
- }
- } else {
- switch (operand->type) {
- case GEN6_TYPE_UD: return "UD";
- case GEN6_TYPE_D: return "D";
- case GEN6_TYPE_UW: return "UW";
- case GEN6_TYPE_W: return "W";
- case GEN6_TYPE_UB: return "UB";
- case GEN6_TYPE_B: return "B";
- case GEN7_TYPE_DF: return "DF";
- case GEN6_TYPE_F: return "F";
- case GEN8_TYPE_UQ: return "UQ";
- case GEN8_TYPE_Q: return "Q";
- case GEN8_TYPE_HF: return "HF";
- default: return "BAD";
- }
- }
-}
-
-static const char *
-disasm_inst_vert_stride(const struct disasm_inst *inst, unsigned vert_stride)
-{
- switch (vert_stride) {
- case GEN6_VERTSTRIDE_0: return "0";
- case GEN6_VERTSTRIDE_1: return "1";
- case GEN6_VERTSTRIDE_2: return "2";
- case GEN6_VERTSTRIDE_4: return "4";
- case GEN6_VERTSTRIDE_8: return "8";
- case GEN6_VERTSTRIDE_16: return "16";
- case GEN6_VERTSTRIDE_32: return "32";
- case GEN6_VERTSTRIDE_VXH: return "VxH";
- default: return "BAD";
- }
-}
-
-static const char *
-disasm_inst_width(const struct disasm_inst *inst, unsigned width)
-{
- switch (width) {
- case GEN6_WIDTH_1: return "1";
- case GEN6_WIDTH_2: return "2";
- case GEN6_WIDTH_4: return "4";
- case GEN6_WIDTH_8: return "8";
- case GEN6_WIDTH_16: return "16";
- default: return "BAD";
- }
-}
-
-static const char *
-disasm_inst_horz_stride(const struct disasm_inst *inst, unsigned horz_stride)
-{
- switch (horz_stride) {
- case GEN6_HORZSTRIDE_0: return "0";
- case GEN6_HORZSTRIDE_1: return "1";
- case GEN6_HORZSTRIDE_2: return "2";
- case GEN6_HORZSTRIDE_4: return "4";
- default: return "BAD";
- }
-}
-
-static const char *
-disasm_inst_writemask(const struct disasm_inst *inst, unsigned writemask)
-{
- switch (writemask) {
- case 0x0: return ".";
- case 0x1: return ".x";
- case 0x2: return ".y";
- case 0x3: return ".xy";
- case 0x4: return ".z";
- case 0x5: return ".xz";
- case 0x6: return ".yz";
- case 0x7: return ".xyz";
- case 0x8: return ".w";
- case 0x9: return ".xw";
- case 0xa: return ".yw";
- case 0xb: return ".xyw";
- case 0xc: return ".zw";
- case 0xd: return ".xzw";
- case 0xe: return ".yzw";
- case 0xf: return "";
- default: return ".BAD";
- }
-}
-
-static const char *
-disasm_inst_negate(const struct disasm_inst *inst, bool negate)
-{
- if (ilo_dev_gen(inst->dev) >= ILO_GEN(8)) {
- switch (inst->opcode) {
- case GEN6_OPCODE_AND:
- case GEN6_OPCODE_NOT:
- case GEN6_OPCODE_OR:
- case GEN6_OPCODE_XOR:
- return (negate) ? "~" : "";
- break;
- default:
- break;
- }
- }
-
- return (negate) ? "-" : "";
-}
-
-static const char *
-disasm_inst_absolute(const struct disasm_inst *inst, bool absolute)
-{
- return (absolute) ? "(abs)" : "";
-}
-
-static const char *
-disasm_inst_mdesc_sampler_op(const struct disasm_inst *inst, int op)
-{
- switch (op) {
- case GEN6_MSG_SAMPLER_SAMPLE: return "sample";
- case GEN6_MSG_SAMPLER_SAMPLE_B: return "sample_b";
- case GEN6_MSG_SAMPLER_SAMPLE_L: return "sample_l";
- case GEN6_MSG_SAMPLER_SAMPLE_C: return "sample_c";
- case GEN6_MSG_SAMPLER_SAMPLE_D: return "sample_d";
- case GEN6_MSG_SAMPLER_SAMPLE_B_C: return "sample_b_c";
- case GEN6_MSG_SAMPLER_SAMPLE_L_C: return "sample_l_c";
- case GEN6_MSG_SAMPLER_LD: return "ld";
- case GEN6_MSG_SAMPLER_GATHER4: return "gather4";
- case GEN6_MSG_SAMPLER_LOD: return "lod";
- case GEN6_MSG_SAMPLER_RESINFO: return "resinfo";
- case GEN6_MSG_SAMPLER_SAMPLEINFO: return "sampleinfo";
- case GEN7_MSG_SAMPLER_GATHER4_C: return "gather4_c";
- case GEN7_MSG_SAMPLER_GATHER4_PO: return "gather4_po";
- case GEN7_MSG_SAMPLER_GATHER4_PO_C: return "gather4_po_c";
- case GEN7_MSG_SAMPLER_SAMPLE_D_C: return "sample_d_c";
- case GEN7_MSG_SAMPLER_SAMPLE_LZ: return "sample_lz";
- case GEN7_MSG_SAMPLER_SAMPLE_C_LC: return "sample_c_lc";
- case GEN7_MSG_SAMPLER_LD_LZ: return "ld_lz";
- case GEN7_MSG_SAMPLER_LD_MCS: return "ld_mcs";
- case GEN7_MSG_SAMPLER_LD2DMS: return "ld2dms";
- case GEN7_MSG_SAMPLER_LD2DSS: return "ld2dss";
- default: return "BAD";
- }
-}
-
-static const char *
-disasm_inst_mdesc_sampler_simd(const struct disasm_inst *inst, int simd)
-{
- switch (simd) {
- case GEN6_MSG_SAMPLER_SIMD4X2: return "SIMD4x2";
- case GEN6_MSG_SAMPLER_SIMD8: return "SIMD8";
- case GEN6_MSG_SAMPLER_SIMD16: return "SIMD16";
- case GEN6_MSG_SAMPLER_SIMD32_64: return "SIMD32";
- default: return "BAD";
- }
-}
-
-static const char *
-disasm_inst_mdesc_urb_op(const struct disasm_inst *inst, int op)
-{
- if (ilo_dev_gen(inst->dev) >= ILO_GEN(7)) {
- switch (op) {
- case GEN7_MSG_URB_WRITE_HWORD: return "write HWord";
- case GEN7_MSG_URB_WRITE_OWORD: return "write OWord";
- case GEN7_MSG_URB_READ_HWORD: return "read HWord";
- case GEN7_MSG_URB_READ_OWORD: return "read OWord";
- case GEN7_MSG_URB_ATOMIC_MOV: return "atomic mov";
- case GEN7_MSG_URB_ATOMIC_INC: return "atomic inc";
- default: return "BAD";
- }
- } else {
- switch (op) {
- case GEN6_MSG_URB_WRITE: return "urb_write";
- case GEN6_MSG_URB_FF_SYNC: return "ff_sync";
- default: return "BAD";
- }
- }
-}
-
-static const char *
-disasm_inst_mdesc_dp_op_gen6(const struct disasm_inst *inst,
- int sfid, int op)
-{
- ILO_DEV_ASSERT(inst->dev, 6, 6);
-
- switch (op) {
- case GEN6_MSG_DP_OWORD_BLOCK_READ: return "OWORD block read";
- case GEN6_MSG_DP_RT_UNORM_READ: return "RT UNORM read";
- case GEN6_MSG_DP_OWORD_DUAL_BLOCK_READ: return "OWORD dual block read";
- case GEN6_MSG_DP_MEDIA_BLOCK_READ: return "media block read";
- case GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_READ: return "unaligned OWORD block read";
- case GEN6_MSG_DP_DWORD_SCATTERED_READ: return "DWORD scattered read";
- case GEN6_MSG_DP_DWORD_ATOMIC_WRITE: return "DWORD atomic write";
- case GEN6_MSG_DP_OWORD_BLOCK_WRITE: return "OWORD block write";
- case GEN6_MSG_DP_OWORD_DUAL_BLOCK_WRITE: return "OWORD dual block_write";
- case GEN6_MSG_DP_MEDIA_BLOCK_WRITE: return "media block write";
- case GEN6_MSG_DP_DWORD_SCATTERED_WRITE: return "DWORD scattered write";
- case GEN6_MSG_DP_RT_WRITE: return "RT write";
- case GEN6_MSG_DP_SVB_WRITE: return "SVB write";
- case GEN6_MSG_DP_RT_UNORM_WRITE: return "RT UNORM write";
- default: return "BAD";
- }
-}
-
-static const char *
-disasm_inst_mdesc_dp_op_gen7(const struct disasm_inst *inst,
- int sfid, int op)
-{
- ILO_DEV_ASSERT(inst->dev, 7, 7);
-
- switch (sfid) {
- case GEN6_SFID_DP_SAMPLER:
- switch (op) {
- case GEN7_MSG_DP_SAMPLER_UNALIGNED_OWORD_BLOCK_READ: return "OWORD block read";
- case GEN7_MSG_DP_SAMPLER_MEDIA_BLOCK_READ: return "media block read";
- default: return "BAD";
- }
- case GEN6_SFID_DP_RC:
- switch (op) {
- case GEN7_MSG_DP_RC_MEDIA_BLOCK_READ: return "media block read";
- case GEN7_MSG_DP_RC_TYPED_SURFACE_READ: return "typed surface read";
- case GEN7_MSG_DP_RC_TYPED_ATOMIC_OP: return "typed atomic op";
- case GEN7_MSG_DP_RC_MEMORY_FENCE: return "memory fence";
- case GEN7_MSG_DP_RC_MEDIA_BLOCK_WRITE: return "media block write";
- case GEN7_MSG_DP_RC_RT_WRITE: return "RT write";
- case GEN7_MSG_DP_RC_TYPED_SURFACE_WRITE: return "typed surface write";
- default: return "BAD";
- }
- case GEN6_SFID_DP_CC:
- switch (op) {
- case GEN7_MSG_DP_CC_OWORD_BLOCK_READ: return "OWROD block read";
- case GEN7_MSG_DP_CC_UNALIGNED_OWORD_BLOCK_READ: return "unaligned OWORD block read";
- case GEN7_MSG_DP_CC_OWORD_DUAL_BLOCK_READ: return "OWORD dual block read";
- case GEN7_MSG_DP_CC_DWORD_SCATTERED_READ: return "DWORD scattered read";
- default: return "BAD";
- }
- case GEN7_SFID_DP_DC0:
- switch (op) {
- case GEN7_MSG_DP_DC0_OWORD_BLOCK_READ: return "OWORD block read";
- case GEN7_MSG_DP_DC0_UNALIGNED_OWORD_BLOCK_READ: return "unaligned OWORD block read";
- case GEN7_MSG_DP_DC0_OWORD_DUAL_BLOCK_READ: return "OWORD dual block read";
- case GEN7_MSG_DP_DC0_DWORD_SCATTERED_READ: return "DWORD scattered read";
- case GEN7_MSG_DP_DC0_BYTE_SCATTERED_READ: return "BYTE scattered read";
- case GEN7_MSG_DP_DC0_UNTYPED_SURFACE_READ: return "untyped surface read";
- case GEN7_MSG_DP_DC0_UNTYPED_ATOMIC_OP: return "untyped atomic op";
- case GEN7_MSG_DP_DC0_MEMORY_FENCE: return "memory fence";
- case GEN7_MSG_DP_DC0_OWORD_BLOCK_WRITE: return "OWORD block write";
- case GEN7_MSG_DP_DC0_OWORD_DUAL_BLOCK_WRITE: return "OWORD dual block write";
- case GEN7_MSG_DP_DC0_DWORD_SCATTERED_WRITE: return "OWORD scattered write";
- case GEN7_MSG_DP_DC0_BYTE_SCATTERED_WRITE: return "BYTE scattered write";
- case GEN7_MSG_DP_DC0_UNTYPED_SURFACE_WRITE: return "untyped surface write";
- default: return "BAD";
- }
- default: return "BAD";
- }
-}
-
-static const char *
-disasm_inst_mdesc_dp_op_gen75(const struct disasm_inst *inst,
- int sfid, int op)
-{
- ILO_DEV_ASSERT(inst->dev, 7.5, 8);
-
- switch (sfid) {
- case GEN6_SFID_DP_SAMPLER:
- switch (op) {
- case GEN75_MSG_DP_SAMPLER_READ_SURFACE_INFO: return "read surface info";
- case GEN75_MSG_DP_SAMPLER_UNALIGNED_OWORD_BLOCK_READ: return "unaligned OWORD block read";
- case GEN75_MSG_DP_SAMPLER_MEDIA_BLOCK_READ: return "media block read";
- default: return "BAD";
- }
-
- case GEN6_SFID_DP_RC:
- switch (op) {
- case GEN75_MSG_DP_RC_MEDIA_BLOCK_READ: return "media block read";
- case GEN75_MSG_DP_RC_MEMORY_FENCE: return "memory fence";
- case GEN75_MSG_DP_RC_MEDIA_BLOCK_WRITE: return "media block write";
- case GEN75_MSG_DP_RC_RT_WRITE: return "RT write";
- default: return "BAD";
- }
- case GEN6_SFID_DP_CC:
- switch (op) {
- case GEN75_MSG_DP_CC_OWORD_BLOCK_READ: return "OWROD block read";
- case GEN75_MSG_DP_CC_UNALIGNED_OWORD_BLOCK_READ: return "unaligned OWORD block read";
- case GEN75_MSG_DP_CC_OWORD_DUAL_BLOCK_READ: return "OWORD dual block read";
- case GEN75_MSG_DP_CC_DWORD_SCATTERED_READ: return "DWORD scattered read";
- default: return "BAD";
- }
- case GEN7_SFID_DP_DC0:
- switch (op) {
- case GEN75_MSG_DP_DC0_OWORD_BLOCK_READ: return "OWORD block read";
- case GEN75_MSG_DP_DC0_UNALIGNED_OWORD_BLOCK_READ: return "unaligned OWORD block read";
- case GEN75_MSG_DP_DC0_OWORD_DUAL_BLOCK_READ: return "OWORD dual block read";
- case GEN75_MSG_DP_DC0_DWORD_SCATTERED_READ: return "DWORD scattered read";
- case GEN75_MSG_DP_DC0_BYTE_SCATTERED_READ: return "BYTE scattered read";
- case GEN75_MSG_DP_DC0_MEMORY_FENCE: return "memory fence";
- case GEN75_MSG_DP_DC0_OWORD_BLOCK_WRITE: return "OWORD block write";
- case GEN75_MSG_DP_DC0_OWORD_DUAL_BLOCK_WRITE: return "OWORD dual block write";
- case GEN75_MSG_DP_DC0_DWORD_SCATTERED_WRITE: return "OWORD scattered write";
- case GEN75_MSG_DP_DC0_BYTE_SCATTERED_WRITE: return "BYTE scattered write";
- default: return "BAD";
- }
- case GEN75_SFID_DP_DC1:
- switch (op) {
- case GEN75_MSG_DP_DC1_UNTYPED_SURFACE_READ: return "untyped surface read";
- case GEN75_MSG_DP_DC1_UNTYPED_ATOMIC_OP: return "DC untyped atomic op";
- case GEN75_MSG_DP_DC1_UNTYPED_ATOMIC_OP_SIMD4X2: return "DC untyped 4x2 atomic op";
- case GEN75_MSG_DP_DC1_MEDIA_BLOCK_READ: return "DC media block read";
- case GEN75_MSG_DP_DC1_TYPED_SURFACE_READ: return "DC typed surface read";
- case GEN75_MSG_DP_DC1_TYPED_ATOMIC_OP: return "DC typed atomic";
- case GEN75_MSG_DP_DC1_TYPED_ATOMIC_OP_SIMD4X2: return "DC typed 4x2 atomic op";
- case GEN75_MSG_DP_DC1_UNTYPED_SURFACE_WRITE: return "DC untyped surface write";
- case GEN75_MSG_DP_DC1_MEDIA_BLOCK_WRITE: return "DC media block write";
- case GEN75_MSG_DP_DC1_ATOMIC_COUNTER_OP: return "DC atomic counter op";
- case GEN75_MSG_DP_DC1_ATOMIC_COUNTER_OP_SIMD4X2: return "DC 4x2 atomic counter op";
- case GEN75_MSG_DP_DC1_TYPED_SURFACE_WRITE: return "DC typed surface write";
- default: return "BAD";
- }
- default: return "BAD";
- }
-}
-
-static const char *
-disasm_inst_mdesc_dp_op(const struct disasm_inst *inst, int sfid, int op)
-{
- switch (ilo_dev_gen(inst->dev)) {
- case ILO_GEN(8):
- case ILO_GEN(7.5): return disasm_inst_mdesc_dp_op_gen75(inst, sfid, op);
- case ILO_GEN(7): return disasm_inst_mdesc_dp_op_gen7(inst, sfid, op);
- case ILO_GEN(6): return disasm_inst_mdesc_dp_op_gen6(inst, sfid, op);
- default: return "BAD";
- }
-}
-
-static const char *
-disasm_inst_mdesc_dp_untyped_surface_simd_mode(const struct disasm_inst *inst,
- uint32_t mdesc)
-{
- switch (mdesc & GEN7_MSG_DP_UNTYPED_MODE__MASK) {
- case GEN7_MSG_DP_UNTYPED_MODE_SIMD4X2: return "SIMD4x2";
- case GEN7_MSG_DP_UNTYPED_MODE_SIMD16: return "SIMD16";
- case GEN7_MSG_DP_UNTYPED_MODE_SIMD8: return "SIMD8";
- default: return "BAD";
- }
-}
-
-static const char *
-disasm_inst_mdesc_dp_rt_write_simd_mode(const struct disasm_inst *inst,
- uint32_t mdesc)
-{
- switch (mdesc & GEN6_MSG_DP_RT_MODE__MASK) {
- case GEN6_MSG_DP_RT_MODE_SIMD16: return "SIMD16";
- case GEN6_MSG_DP_RT_MODE_SIMD16_REPDATA: return "SIMD16/RepData";
- case GEN6_MSG_DP_RT_MODE_SIMD8_DUALSRC_LO: return "SIMD8/DualSrcLow";
- case GEN6_MSG_DP_RT_MODE_SIMD8_DUALSRC_HI: return "SIMD8/DualSrcHigh";
- case GEN6_MSG_DP_RT_MODE_SIMD8_LO: return "SIMD8";
- case GEN6_MSG_DP_RT_MODE_SIMD8_IMAGE_WR: return "SIMD8/ImageWrite";
- default: return "BAD";
- }
-}
-
-static bool
-disasm_inst_is_null(const struct disasm_inst *inst,
- const struct disasm_operand *operand)
-{
- return (operand->file == GEN6_FILE_ARF && operand->reg == GEN6_ARF_NULL);
-}
-
-static int
-disasm_inst_type_size(const struct disasm_inst *inst,
- const struct disasm_operand *operand)
-{
- assert(operand->file != GEN6_FILE_IMM);
-
- switch (operand->type) {
- case GEN6_TYPE_UD: return 4;
- case GEN6_TYPE_D: return 4;
- case GEN6_TYPE_UW: return 2;
- case GEN6_TYPE_W: return 2;
- case GEN6_TYPE_UB: return 1;
- case GEN6_TYPE_B: return 1;
- case GEN7_TYPE_DF: return 8;
- case GEN6_TYPE_F: return 4;
- default: return 1;
- }
-}
-
-static void
-disasm_printer_reset(struct disasm_printer *printer)
-{
- printer->buf[0] = '\0';
- printer->len = 0;
-}
-
-static const char *
-disasm_printer_get_string(struct disasm_printer *printer)
-{
- return printer->buf;
-}
-
-static void _util_printf_format(2, 3)
-disasm_printer_add(struct disasm_printer *printer, const char *format, ...)
-{
- const size_t avail = sizeof(printer->buf) - printer->len;
- va_list ap;
- int written;
-
- va_start(ap, format);
- written = vsnprintf(printer->buf + printer->len, avail, format, ap);
- va_end(ap);
-
- /* truncated */
- if (written < 0 || written >= avail) {
- memcpy(printer->buf + sizeof(printer->buf) - 4, "...", 4);
- printer->len = sizeof(printer->buf) - 1;
- } else {
- printer->len += written;
- }
-}
-
-/**
- * Pad to the specified column.
- */
-static void
-disasm_printer_column(struct disasm_printer *printer, int col)
-{
- int len = DISASM_PRINTER_COLUMN_WIDTH * col;
-
- if (len <= printer->len) {
- if (!printer->len)
- return;
-
- /* at least one space */
- len = printer->len + 1;
- }
-
- if (len >= sizeof(printer->buf)) {
- len = sizeof(printer->buf) - 1;
-
- if (len <= printer->len)
- return;
- }
-
- memset(printer->buf + printer->len, ' ', len - printer->len);
- printer->len = len;
- printer->buf[printer->len] = '\0';
-}
-
-static void
-disasm_printer_add_op(struct disasm_printer *printer,
- const struct disasm_inst *inst)
-{
- if (inst->pred_ctrl != GEN6_PREDCTRL_NONE) {
- disasm_printer_add(printer, "(%c%s%s) ",
- disasm_inst_pred_inv(inst),
- disasm_inst_flag_reg(inst),
- disasm_inst_pred_ctrl(inst));
- }
-
- disasm_printer_add(printer, "%s%s%s%s",
- disasm_inst_opcode(inst),
- disasm_inst_saturate(inst),
- disasm_inst_debug_ctrl(inst),
- disasm_inst_cond_modifier(inst));
-
- if (inst->cond_modifier != GEN6_COND_NONE) {
- switch (inst->opcode) {
- case GEN6_OPCODE_SEL:
- case GEN6_OPCODE_IF:
- case GEN6_OPCODE_WHILE:
- /* these do not update flag registers */
- break;
- default:
- disasm_printer_add(printer, ".%s", disasm_inst_flag_reg(inst));
- break;
- }
- }
-
- if (inst->opcode == GEN6_OPCODE_MATH)
- disasm_printer_add(printer, " %s", disasm_inst_fc(inst));
- if (inst->opcode != GEN6_OPCODE_NOP)
- disasm_printer_add(printer, "(%s)", disasm_inst_exec_size(inst));
-}
-
-static void
-disasm_printer_add_operand(struct disasm_printer *printer,
- const struct disasm_inst *inst,
- const struct disasm_operand *operand)
-{
- const char *name;
- bool multi_regs;
-
- name = disasm_inst_file(inst, operand, &multi_regs);
- if (!multi_regs) {
- disasm_printer_add(printer, "%s", name);
- return;
- }
-
- if (operand->file == GEN6_FILE_IMM) {
- switch (operand->type) {
- case GEN6_TYPE_UD:
- disasm_printer_add(printer, "0x%08xUD", inst->u.ud);
- break;
- case GEN6_TYPE_D:
- disasm_printer_add(printer, "%dD", inst->u.d);
- break;
- case GEN6_TYPE_UW:
- disasm_printer_add(printer, "0x%04xUW", inst->u.uw);
- break;
- case GEN6_TYPE_W:
- disasm_printer_add(printer, "%dW", inst->u.w);
- break;
- case GEN6_TYPE_UV_IMM:
- disasm_printer_add(printer, "0x%08xUV", inst->u.ud);
- break;
- case GEN6_TYPE_VF_IMM:
- disasm_printer_add(printer, "Vector Float");
- break;
- case GEN6_TYPE_V_IMM:
- disasm_printer_add(printer, "0x%08xV", inst->u.ud);
- break;
- case GEN6_TYPE_F:
- disasm_printer_add(printer, "%-gF", uif(inst->u.f));
- break;
- default:
- disasm_printer_add(printer, "BAD");
- break;
- }
-
- return;
- }
-
- if (operand->addr_mode == GEN6_ADDRMODE_DIRECT) {
- unsigned reg, subreg;
-
- reg = operand->reg;
- if (operand->file == GEN6_FILE_ARF)
- reg &= 0xf;
-
- subreg = operand->subreg / disasm_inst_type_size(inst, operand);
-
- if (subreg)
- disasm_printer_add(printer, "%s%d.%d", name, reg, subreg);
- else
- disasm_printer_add(printer, "%s%d", name, reg);
- } else {
- disasm_printer_add(printer, "%s[a0.%d %d]",
- name, operand->addr_subreg, operand->addr_imm);
- }
-}
-
-static void
-disasm_printer_add_dst(struct disasm_printer *printer,
- const struct disasm_inst *inst,
- const struct disasm_dst_operand *dst)
-{
- disasm_printer_add_operand(printer, inst, &dst->base);
-
- /* dst is an immediate when in EU_INSTRUCTION_BRANCH_CONDITIONAL form */
- if (disasm_inst_is_null(inst, &dst->base) ||
- dst->base.file == GEN6_FILE_IMM)
- return;
-
- disasm_printer_add(printer, "<%s>%s%s",
- disasm_inst_horz_stride(inst, dst->horz_stride),
- disasm_inst_writemask(inst, dst->writemask),
- disasm_inst_type(inst, &dst->base));
-}
-
-static void
-disasm_printer_add_src(struct disasm_printer *printer,
- const struct disasm_inst *inst,
- const struct disasm_src_operand *src)
-{
- static const char swizzle_chars[4] = { 'x', 'y', 'z', 'w' };
- char swizzle[5];
-
- disasm_printer_add(printer, "%s%s",
- disasm_inst_negate(inst, src->negate),
- disasm_inst_absolute(inst, src->absolute));
-
- disasm_printer_add_operand(printer, inst, &src->base);
-
- if (disasm_inst_is_null(inst, &src->base) ||
- src->base.file == GEN6_FILE_IMM)
- return;
-
- if (src->swizzle_x == 0 && src->swizzle_y == 1 &&
- src->swizzle_z == 2 && src->swizzle_w == 3) {
- swizzle[0] = '\0';
- } else if (src->swizzle_x == src->swizzle_y &&
- src->swizzle_x == src->swizzle_z &&
- src->swizzle_x == src->swizzle_w) {
- swizzle[0] = swizzle_chars[src->swizzle_x];
- swizzle[1] = '\0';
- } else {
- swizzle[0] = swizzle_chars[src->swizzle_x];
- swizzle[1] = swizzle_chars[src->swizzle_y];
- swizzle[2] = swizzle_chars[src->swizzle_z];
- swizzle[3] = swizzle_chars[src->swizzle_w];
- swizzle[4] = '\0';
- }
-
- disasm_printer_add(printer, "<%s,%s,%s>%s%s",
- disasm_inst_vert_stride(inst, src->vert_stride),
- disasm_inst_width(inst, src->width),
- disasm_inst_horz_stride(inst, src->horz_stride),
- swizzle,
- disasm_inst_type(inst, &src->base));
-}
-
-static void
-disasm_printer_add_ctrl(struct disasm_printer *printer,
- const struct disasm_inst *inst)
-{
- if (inst->opcode == GEN6_OPCODE_NOP) {
- disasm_printer_add(printer, ";");
- return;
- }
-
- disasm_printer_add(printer, "{%s%s%s%s%s%s%s%s };",
- disasm_inst_access_mode(inst),
- disasm_inst_mask_ctrl(inst),
- disasm_inst_dep_ctrl(inst),
- disasm_inst_qtr_ctrl(inst),
- disasm_inst_cmpt_ctrl(inst),
- disasm_inst_thread_ctrl(inst),
- disasm_inst_acc_wr_ctrl(inst),
- disasm_inst_eot(inst));
-}
-
-static void
-disasm_printer_add_mdesc_sampler(struct disasm_printer *printer,
- const struct disasm_inst *inst,
- uint32_t mdesc)
-{
- int op, simd;
-
- if (ilo_dev_gen(inst->dev) >= ILO_GEN(7)) {
- op = GEN_EXTRACT(mdesc, GEN7_MSG_SAMPLER_OP);
- simd = GEN_EXTRACT(mdesc, GEN7_MSG_SAMPLER_SIMD);
- } else {
- op = GEN_EXTRACT(mdesc, GEN6_MSG_SAMPLER_OP);
- simd = GEN_EXTRACT(mdesc, GEN6_MSG_SAMPLER_SIMD);
- }
-
- disasm_printer_add(printer,
- "%s %s samp %d surf %d",
- disasm_inst_mdesc_sampler_op(inst, op),
- disasm_inst_mdesc_sampler_simd(inst, simd),
- GEN_EXTRACT(mdesc, GEN6_MSG_SAMPLER_INDEX),
- GEN_EXTRACT(mdesc, GEN6_MSG_SAMPLER_SURFACE));
-}
-
-static void
-disasm_printer_add_mdesc_urb(struct disasm_printer *printer,
- const struct disasm_inst *inst,
- uint32_t mdesc)
-{
- int op, offset;
- bool interleaved, complete, allocate, used;
-
- if (ilo_dev_gen(inst->dev) >= ILO_GEN(7)) {
- op = GEN_EXTRACT(mdesc, GEN7_MSG_URB_OP);
- offset = GEN_EXTRACT(mdesc, GEN7_MSG_URB_GLOBAL_OFFSET);
- interleaved = mdesc & GEN7_MSG_URB_INTERLEAVED;
-
- complete = (ilo_dev_gen(inst->dev) >= ILO_GEN(8)) ?
- false : (mdesc & GEN7_MSG_URB_COMPLETE);
-
- allocate = false;
- used = false;
- } else {
- op = GEN_EXTRACT(mdesc, GEN6_MSG_URB_OP);
- offset = GEN_EXTRACT(mdesc, GEN6_MSG_URB_OFFSET);
- interleaved = mdesc & GEN6_MSG_URB_INTERLEAVED;
- complete = mdesc & GEN6_MSG_URB_COMPLETE;
-
- allocate = mdesc & GEN6_MSG_URB_ALLOCATE;
- used = mdesc & GEN6_MSG_URB_USED;
- }
-
- disasm_printer_add(printer, "%s offset %d%s%s%s%s",
- disasm_inst_mdesc_urb_op(inst, op),
- offset,
- (interleaved) ? " interleave" : "",
- (allocate) ? " allocate" : "",
- (used) ? " used" : "",
- (complete) ? " complete" : "");
-}
-
-static void
-disasm_printer_add_mdesc_spawner(struct disasm_printer *printer,
- const struct disasm_inst *inst,
- uint32_t mdesc)
-{
- const char *requester, *op;
-
- switch (mdesc & GEN6_MSG_TS_REQUESTER_TYPE__MASK) {
- case GEN6_MSG_TS_REQUESTER_TYPE_ROOT: requester = "root"; break;
- case GEN6_MSG_TS_REQUESTER_TYPE_CHILD: requester = "child"; break;
- default: requester = "BAD"; break;
- }
-
- switch (mdesc & GEN6_MSG_TS_OPCODE__MASK) {
- case GEN6_MSG_TS_OPCODE_DEREF:
- op = (mdesc & GEN6_MSG_TS_RESOURCE_SELECT_NO_DEREF) ?
- "no deref" : "deref";
- break;
- case GEN6_MSG_TS_OPCODE_SPAWN:
- op = (mdesc & GEN6_MSG_TS_RESOURCE_SELECT_ROOT) ?
- "spawn root" : "spawn child";
- break;
- default:
- op = "BAD";
- break;
- }
-
- disasm_printer_add(printer, "%s thread %s", requester, op);
-}
-
-static void
-disasm_printer_add_mdesc_dp_sampler(struct disasm_printer *printer,
- const struct disasm_inst *inst,
- uint32_t mdesc)
-{
- const int op = (ilo_dev_gen(inst->dev) >= ILO_GEN(7)) ?
- GEN_EXTRACT(mdesc, GEN7_MSG_DP_OP) : GEN_EXTRACT(mdesc, GEN6_MSG_DP_OP);
- const bool write_commit = (ilo_dev_gen(inst->dev) == ILO_GEN(6)) ?
- (mdesc & GEN6_MSG_DP_SEND_WRITE_COMMIT) : 0;
-
- disasm_printer_add(printer, "%s block size %d commit %d surf %d",
- disasm_inst_mdesc_dp_op(inst, GEN6_SFID_DP_SAMPLER, op),
- GEN_EXTRACT(mdesc, GEN6_MSG_DP_OWORD_BLOCK_SIZE),
- write_commit,
- GEN_EXTRACT(mdesc, GEN6_MSG_DP_SURFACE));
-}
-
-static void
-disasm_printer_add_mdesc_dp_dc0(struct disasm_printer *printer,
- const struct disasm_inst *inst,
- uint32_t mdesc)
-{
- const int op = GEN_EXTRACT(mdesc, GEN7_MSG_DP_OP);
-
- ILO_DEV_ASSERT(inst->dev, 7, 7.5);
-
- if (ilo_dev_gen(inst->dev) >= ILO_GEN(7.5)) {
- disasm_printer_add(printer, "%s ctrl 0x%x surf %d",
- disasm_inst_mdesc_dp_op(inst, GEN7_SFID_DP_DC0, op),
- GEN_EXTRACT(mdesc, GEN6_MSG_DP_CTRL),
- GEN_EXTRACT(mdesc, GEN6_MSG_DP_SURFACE));
- } else {
- switch (op) {
- case GEN7_MSG_DP_DC0_UNTYPED_SURFACE_READ:
- case GEN7_MSG_DP_DC0_UNTYPED_SURFACE_WRITE:
- disasm_printer_add(printer, "%s %s mask 0x%x surf %d",
- disasm_inst_mdesc_dp_op(inst, GEN7_SFID_DP_DC0, op),
- disasm_inst_mdesc_dp_untyped_surface_simd_mode(inst, mdesc),
- GEN_EXTRACT(mdesc, GEN7_MSG_DP_UNTYPED_MASK),
- GEN_EXTRACT(mdesc, GEN6_MSG_DP_SURFACE));
- break;
- default:
- disasm_printer_add(printer, "%s ctrl 0x%x surf %d",
- disasm_inst_mdesc_dp_op(inst, GEN7_SFID_DP_DC0, op),
- GEN_EXTRACT(mdesc, GEN6_MSG_DP_CTRL),
- GEN_EXTRACT(mdesc, GEN6_MSG_DP_SURFACE));
- break;
- }
- }
-}
-
-static void
-disasm_printer_add_mdesc_dp_dc1(struct disasm_printer *printer,
- const struct disasm_inst *inst,
- uint32_t mdesc)
-{
- const int op = GEN_EXTRACT(mdesc, GEN7_MSG_DP_OP);
-
- ILO_DEV_ASSERT(inst->dev, 7.5, 7.5);
-
- switch (op) {
- case GEN75_MSG_DP_DC1_UNTYPED_SURFACE_READ:
- case GEN75_MSG_DP_DC1_UNTYPED_SURFACE_WRITE:
- disasm_printer_add(printer, "%s %s mask 0x%x surf %d",
- disasm_inst_mdesc_dp_op(inst, GEN75_SFID_DP_DC1, op),
- disasm_inst_mdesc_dp_untyped_surface_simd_mode(inst, mdesc),
- GEN_EXTRACT(mdesc, GEN7_MSG_DP_UNTYPED_MASK),
- GEN_EXTRACT(mdesc, GEN6_MSG_DP_SURFACE));
- break;
- default:
- disasm_printer_add(printer, "%s ctrl 0x%x surf %d",
- disasm_inst_mdesc_dp_op(inst, GEN75_SFID_DP_DC1, op),
- GEN_EXTRACT(mdesc, GEN6_MSG_DP_CTRL),
- GEN_EXTRACT(mdesc, GEN6_MSG_DP_SURFACE));
- break;
- }
-}
-
-static void
-disasm_printer_add_mdesc_dp_rc(struct disasm_printer *printer,
- const struct disasm_inst *inst,
- uint32_t mdesc)
-{
- const int op = (ilo_dev_gen(inst->dev) >= ILO_GEN(7)) ?
- GEN_EXTRACT(mdesc, GEN7_MSG_DP_OP) : GEN_EXTRACT(mdesc, GEN6_MSG_DP_OP);
- bool is_rt_write;
-
- if (ilo_dev_gen(inst->dev) >= ILO_GEN(7.5))
- is_rt_write = (op == GEN75_MSG_DP_RC_RT_WRITE);
- else if (ilo_dev_gen(inst->dev) >= ILO_GEN(7))
- is_rt_write = (op == GEN7_MSG_DP_RC_RT_WRITE);
- else
- is_rt_write = (op == GEN6_MSG_DP_RT_WRITE);
-
- disasm_printer_add(printer, "%s",
- disasm_inst_mdesc_dp_op(inst, GEN6_SFID_DP_RC, op));
-
- if (is_rt_write) {
- disasm_printer_add(printer, " %s%s%s%s",
- disasm_inst_mdesc_dp_rt_write_simd_mode(inst, mdesc),
- (mdesc & GEN6_MSG_DP_RT_SLOTGRP_HI) ? " Hi" : "",
- (mdesc & GEN6_MSG_DP_RT_LAST) ? " LastRT" : "",
- (ilo_dev_gen(inst->dev) == ILO_GEN(6) &&
- (mdesc & GEN6_MSG_DP_SEND_WRITE_COMMIT)) ? " WriteCommit" : "");
- }
-
- disasm_printer_add(printer, " surf %d",
- GEN_EXTRACT(mdesc, GEN6_MSG_DP_SURFACE));
-}
-
-static void
-disasm_printer_add_mdesc(struct disasm_printer *printer,
- const struct disasm_inst *inst)
-{
- const uint32_t mdesc = inst->u.ud;
-
- assert(inst->opcode == GEN6_OPCODE_SEND ||
- inst->opcode == GEN6_OPCODE_SENDC);
- assert(inst->src1.base.file == GEN6_FILE_IMM);
-
- disasm_printer_add(printer, " %s (", disasm_inst_sfid(inst));
-
- switch (inst->sfid) {
- case GEN6_SFID_SAMPLER:
- disasm_printer_add_mdesc_sampler(printer, inst, mdesc);
- break;
- case GEN6_SFID_DP_SAMPLER:
- disasm_printer_add_mdesc_dp_sampler(printer, inst, mdesc);
- break;
- case GEN6_SFID_DP_RC:
- disasm_printer_add_mdesc_dp_rc(printer, inst, mdesc);
- break;
- case GEN6_SFID_URB:
- disasm_printer_add_mdesc_urb(printer, inst, mdesc);
- break;
- case GEN6_SFID_SPAWNER:
- disasm_printer_add_mdesc_spawner(printer, inst, mdesc);
- break;
- case GEN7_SFID_DP_DC0:
- disasm_printer_add_mdesc_dp_dc0(printer, inst, mdesc);
- break;
- case GEN75_SFID_DP_DC1:
- disasm_printer_add_mdesc_dp_dc1(printer, inst, mdesc);
- break;
- case GEN6_SFID_DP_CC:
- case GEN7_SFID_PI:
- default:
- break;
- }
-
- disasm_printer_add(printer, ") mlen %d rlen %d",
- GEN_EXTRACT(mdesc, GEN6_MSG_MLEN),
- GEN_EXTRACT(mdesc, GEN6_MSG_RLEN));
-}
-
-static void
-disasm_printer_print_inst(struct disasm_printer *printer,
- const struct disasm_inst *inst)
-{
- int col = 0;
-
- disasm_printer_reset(printer);
-
- disasm_printer_column(printer, col++);
- disasm_printer_add_op(printer, inst);
-
- if (inst->has_jip || inst->has_uip) {
- if (inst->has_jip) {
- const int32_t jip = (ilo_dev_gen(inst->dev) >= ILO_GEN(8)) ?
- inst->u.ip32.jip : inst->u.ip16.jip;
-
- disasm_printer_column(printer, col++);
- disasm_printer_add(printer, "JIP: %d", jip);
- }
-
- if (inst->has_uip) {
- const int32_t uip = (ilo_dev_gen(inst->dev) >= ILO_GEN(8)) ?
- inst->u.ip32.uip : inst->u.ip16.uip;
-
- disasm_printer_column(printer, col++);
- disasm_printer_add(printer, "UIP: %d", uip);
- }
- } else {
- const int src_count = disasm_opcode_table[inst->opcode].src_count;
-
- if (src_count) {
- const struct disasm_src_operand *src[3] = {
- &inst->src0, &inst->src1, &inst->u.src2
- };
- int i;
-
- disasm_printer_column(printer, col++);
- disasm_printer_add_dst(printer, inst, &inst->dst);
-
- for (i = 0; i < src_count; i++) {
- disasm_printer_column(printer, col++);
- disasm_printer_add_src(printer, inst, src[i]);
- }
- }
- }
-
- if (inst->opcode == GEN6_OPCODE_SEND ||
- inst->opcode == GEN6_OPCODE_SENDC) {
- /* start a new line */
- ilo_printf("%s\n", disasm_printer_get_string(printer));
- disasm_printer_reset(printer);
- col = 0;
-
- disasm_printer_column(printer, col++);
-
- disasm_printer_column(printer, col++);
- disasm_printer_add_mdesc(printer, inst);
- }
-
- if (col < 4)
- col = 4;
-
- disasm_printer_column(printer, col++);
- disasm_printer_add_ctrl(printer, inst);
-
- ilo_printf("%s\n", disasm_printer_get_string(printer));
-}
-
-static void
-disasm_uncompact_3src(const struct ilo_dev *dev,
- uint64_t compact, uint32_t *dw)
-{
- const struct toy_compaction_table *tbl =
- toy_compiler_get_compaction_table(dev);
- uint32_t src[3], tmp;
- uint64_t tmp64;
-
- ILO_DEV_ASSERT(dev, 8, 8);
-
- tmp = GEN_EXTRACT(compact, GEN8_COMPACT_3SRC_OPCODE);
- dw[0] = GEN_SHIFT32(tmp, GEN6_INST_OPCODE);
-
- /* ControlIndex */
- tmp = GEN_EXTRACT(compact, GEN8_COMPACT_3SRC_CONTROL_INDEX);
- tmp = tbl->control_3src[tmp];
-
- dw[0] |= (tmp & 0x1fffff) << GEN6_INST_ACCESSMODE__SHIFT;
- dw[1] = (tmp >> 21) & ((ilo_dev_gen(dev) >= ILO_GEN(9)) ? 0x1f : 0x7);
-
- /* SourceIndex */
- tmp = GEN_EXTRACT(compact, GEN8_COMPACT_3SRC_SOURCE_INDEX);
- tmp64 = tbl->source_3src[tmp];
-
- dw[1] |= (tmp64 & 0x7ffff) << 5;
- src[0] = ((tmp64 >> 19) & 0xff) << 1;
- src[1] = ((tmp64 >> 27) & 0xff) << 1;
- src[2] = ((tmp64 >> 35) & 0xff) << 1;
- if (ilo_dev_gen(dev) >= ILO_GEN(9)) {
- src[0] |= ((tmp64 >> 43) & 0x3) << 19;
- src[1] |= ((tmp64 >> 45) & 0x3) << 19;
- src[2] |= ((tmp64 >> 47) & 0x3) << 19;
- } else {
- src[0] |= ((tmp64 >> 43) & 0x1) << 19;
- src[1] |= ((tmp64 >> 44) & 0x1) << 19;
- src[2] |= ((tmp64 >> 45) & 0x1) << 19;
- }
-
- tmp = GEN_EXTRACT(compact, GEN8_COMPACT_3SRC_DST_REG);
- dw[1] |= GEN_SHIFT32(tmp, GEN6_3SRC_DST_REG);
-
- if (compact & GEN8_COMPACT_3SRC_SRC0_REPCTRL)
- src[0] |= GEN6_3SRC_SRC_REPCTRL;
-
- assert(compact & GEN8_COMPACT_3SRC_CMPTCTRL);
-
- if (compact & GEN8_COMPACT_3SRC_DEBUGCTRL)
- dw[0] |= GEN6_INST_DEBUGCTRL;
- if (compact & GEN8_COMPACT_3SRC_SATURATE)
- dw[0] |= GEN6_INST_SATURATE;
-
- if (compact & GEN8_COMPACT_3SRC_SRC1_REPCTRL)
- src[1] |= GEN6_3SRC_SRC_REPCTRL;
- if (compact & GEN8_COMPACT_3SRC_SRC2_REPCTRL)
- src[2] |= GEN6_3SRC_SRC_REPCTRL;
-
- tmp = GEN_EXTRACT(compact, GEN8_COMPACT_3SRC_SRC0_SUBREG);
- src[0] |= GEN_SHIFT32(tmp, GEN6_3SRC_SRC_SUBREG);
- tmp = GEN_EXTRACT(compact, GEN8_COMPACT_3SRC_SRC1_SUBREG);
- src[1] |= GEN_SHIFT32(tmp, GEN6_3SRC_SRC_SUBREG);
- tmp = GEN_EXTRACT(compact, GEN8_COMPACT_3SRC_SRC2_SUBREG);
- src[2] |= GEN_SHIFT32(tmp, GEN6_3SRC_SRC_SUBREG);
-
- tmp = GEN_EXTRACT(compact, GEN8_COMPACT_3SRC_SRC0_REG);
- src[0] |= GEN_SHIFT32(tmp, GEN6_3SRC_SRC_REG);
- tmp = GEN_EXTRACT(compact, GEN8_COMPACT_3SRC_SRC1_REG);
- src[1] |= GEN_SHIFT32(tmp, GEN6_3SRC_SRC_REG);
- tmp = GEN_EXTRACT(compact, GEN8_COMPACT_3SRC_SRC2_REG);
- src[2] |= GEN_SHIFT32(tmp, GEN6_3SRC_SRC_REG);
-
- tmp64 = (uint64_t) src[2] << 42 |
- (uint64_t) src[1] << 21 |
- (uint64_t) src[0];
- dw[2] = (uint32_t) tmp64;
- dw[3] = (uint32_t) (tmp64 >> 32);
-}
-
-static void
-disasm_uncompact(const struct ilo_dev *dev,
- uint64_t compact, uint32_t *dw)
-{
- const struct toy_compaction_table *tbl =
- toy_compiler_get_compaction_table(dev);
- bool src_is_imm;
- uint32_t tmp;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- tmp = GEN_EXTRACT(compact, GEN6_COMPACT_OPCODE);
- if (disasm_opcode_table[tmp].src_count == 3) {
- disasm_uncompact_3src(dev, compact, dw);
- return;
- }
-
- memset(dw, 0, sizeof(*dw) * 4);
-
- dw[0] |= GEN_SHIFT32(tmp, GEN6_INST_OPCODE);
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7) && (compact & GEN6_COMPACT_DEBUGCTRL))
- dw[0] |= GEN6_INST_DEBUGCTRL;
-
- /* ControlIndex */
- tmp = GEN_EXTRACT(compact, GEN6_COMPACT_CONTROL_INDEX);
- tmp = tbl->control[tmp];
-
- dw[0] |= (tmp & 0xffff) << GEN6_INST_ACCESSMODE__SHIFT;
- if (tmp & 0x10000)
- dw[0] |= GEN6_INST_SATURATE;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- dw[2] |= (tmp >> 17) << GEN6_INST_FLAG_SUBREG__SHIFT;
-
- /* DataTypeIndex */
- tmp = GEN_EXTRACT(compact, GEN6_COMPACT_DATATYPE_INDEX);
- tmp = tbl->datatype[tmp];
-
- dw[1] |= (tmp & 0x7fff) << GEN6_INST_DST_FILE__SHIFT;
- dw[1] |= (tmp >> 15) << GEN6_INST_DST_HORZSTRIDE__SHIFT;
-
- /* SubRegIndex */
- tmp = GEN_EXTRACT(compact, GEN6_COMPACT_SUBREG_INDEX);
- tmp = tbl->subreg[tmp];
-
- dw[1] |= (tmp & 0x1f) << 16;
- dw[2] |= ((tmp >> 5) & 0x1f);
- dw[3] |= ((tmp >> 10) & 0x1f);
-
- if (compact & GEN6_COMPACT_ACCWRCTRL)
- dw[0] |= GEN6_INST_ACCWRCTRL;
-
- tmp = GEN_EXTRACT(compact, GEN6_COMPACT_CONDMODIFIER);
- dw[0] |= GEN_SHIFT32(tmp, GEN6_INST_CONDMODIFIER);
-
- if (ilo_dev_gen(dev) == ILO_GEN(6)) {
- tmp = GEN_EXTRACT(compact, GEN6_COMPACT_FLAG_SUBREG);
- dw[2] |= GEN_SHIFT32(compact, GEN6_INST_FLAG_SUBREG);
- }
-
- assert(compact & GEN6_COMPACT_CMPTCTRL);
-
- /* Src0Index */
- tmp = GEN_EXTRACT(compact, GEN6_COMPACT_SRC0_INDEX);
- tmp = tbl->src[tmp];
- dw[2] |= tmp << 13;
-
- src_is_imm = (GEN_EXTRACT(dw[1], GEN6_INST_SRC0_FILE) == GEN6_FILE_IMM) ||
- (GEN_EXTRACT(dw[1], GEN6_INST_SRC1_FILE) == GEN6_FILE_IMM);
-
- /* Src1Index */
- tmp = GEN_EXTRACT(compact, GEN6_COMPACT_SRC1_INDEX);
- if (src_is_imm) {
- if (tmp & 0x10)
- tmp |= 0xfffff0;
- dw[3] |= tmp << 8;
- } else {
- tmp = tbl->src[tmp];
- dw[3] |= tmp << 13;
- }
-
- tmp = GEN_EXTRACT(compact, GEN6_COMPACT_DST_REG);
- dw[1] |= GEN_SHIFT32(tmp, GEN6_INST_DST_REG);
-
- tmp = GEN_EXTRACT(compact, GEN6_COMPACT_SRC0_REG);
- dw[2] |= GEN_SHIFT32(tmp, GEN6_INST_SRC_REG);
-
- tmp = GEN_EXTRACT(compact, GEN6_COMPACT_SRC1_REG);
- if (src_is_imm)
- dw[3] |= tmp;
- else
- dw[3] |= GEN_SHIFT32(tmp, GEN6_INST_SRC_REG);
-}
-
-void
-toy_compiler_disassemble(const struct ilo_dev *dev,
- const void *kernel, int size,
- bool dump_hex)
-{
- const uint32_t *cur = (const uint32_t *) kernel;
- const uint32_t *end = cur + size / sizeof(*cur);
- struct disasm_printer printer;
-
- disasm_printer_reset(&printer);
-
- while (cur < end) {
- struct disasm_inst inst;
- const bool compacted = (cur[0] & GEN6_INST_CMPTCTRL);
- const uint32_t *dw = cur;
- uint32_t temp[4];
-
- cur += (compacted) ? 2 : 4;
- /* incomplete instruction */
- if (cur > end)
- break;
-
- if (compacted) {
- const uint64_t compact = (uint64_t) dw[1] << 32 | dw[0];
- disasm_uncompact(dev, compact, temp);
- dw = temp;
- }
-
- if (dump_hex) {
- ilo_printf("0x%08x 0x%08x 0x%08x 0x%08x ",
- dw[0], dw[1], dw[2], dw[3]);
- }
-
- memset(&inst, 0, sizeof(inst));
- inst.dev = dev;
- disasm_inst_decode(&inst, dw);
- inst.cmpt_ctrl = compacted;
-
- disasm_printer_print_inst(&printer, &inst);
- }
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef TOY_REG_H
-#define TOY_REG_H
-
-#include "pipe/p_compiler.h"
-#include "util/u_debug.h" /* for assert() */
-#include "util/u_math.h" /* for union fi */
-
-/* a toy reg is 256-bit wide */
-#define TOY_REG_WIDTH 32
-
-/**
- * Register files.
- */
-enum toy_file {
- /* virtual register file */
- TOY_FILE_VRF,
-
- TOY_FILE_ARF,
- TOY_FILE_GRF,
- TOY_FILE_MRF,
- TOY_FILE_IMM,
-
- TOY_FILE_COUNT,
-};
-
-/**
- * Register types.
- */
-enum toy_type {
- TOY_TYPE_F,
- TOY_TYPE_D,
- TOY_TYPE_UD,
- TOY_TYPE_W,
- TOY_TYPE_UW,
- TOY_TYPE_V, /* only valid for immediates */
-
- TOY_TYPE_COUNT,
-};
-
-/**
- * Register rectangles. The three numbers stand for vertical stride, width,
- * and horizontal stride respectively.
- */
-enum toy_rect {
- TOY_RECT_LINEAR,
- TOY_RECT_041,
- TOY_RECT_010,
- TOY_RECT_220,
- TOY_RECT_440,
- TOY_RECT_240,
-
- TOY_RECT_COUNT,
-};
-
-/**
- * Source swizzles. They are compatible with TGSI_SWIZZLE_x and hardware
- * values.
- */
-enum toy_swizzle {
- TOY_SWIZZLE_X = 0,
- TOY_SWIZZLE_Y = 1,
- TOY_SWIZZLE_Z = 2,
- TOY_SWIZZLE_W = 3,
-};
-
-/**
- * Destination writemasks. They are compatible with TGSI_WRITEMASK_x and
- * hardware values.
- */
-enum toy_writemask {
- TOY_WRITEMASK_X = (1 << TOY_SWIZZLE_X),
- TOY_WRITEMASK_Y = (1 << TOY_SWIZZLE_Y),
- TOY_WRITEMASK_Z = (1 << TOY_SWIZZLE_Z),
- TOY_WRITEMASK_W = (1 << TOY_SWIZZLE_W),
- TOY_WRITEMASK_XY = (TOY_WRITEMASK_X | TOY_WRITEMASK_Y),
- TOY_WRITEMASK_XZ = (TOY_WRITEMASK_X | TOY_WRITEMASK_Z),
- TOY_WRITEMASK_XW = (TOY_WRITEMASK_X | TOY_WRITEMASK_W),
- TOY_WRITEMASK_YZ = (TOY_WRITEMASK_Y | TOY_WRITEMASK_Z),
- TOY_WRITEMASK_YW = (TOY_WRITEMASK_Y | TOY_WRITEMASK_W),
- TOY_WRITEMASK_ZW = (TOY_WRITEMASK_Z | TOY_WRITEMASK_W),
- TOY_WRITEMASK_XYZ = (TOY_WRITEMASK_X | TOY_WRITEMASK_Y | TOY_WRITEMASK_Z),
- TOY_WRITEMASK_XYW = (TOY_WRITEMASK_X | TOY_WRITEMASK_Y | TOY_WRITEMASK_W),
- TOY_WRITEMASK_XZW = (TOY_WRITEMASK_X | TOY_WRITEMASK_Z | TOY_WRITEMASK_W),
- TOY_WRITEMASK_YZW = (TOY_WRITEMASK_Y | TOY_WRITEMASK_Z | TOY_WRITEMASK_W),
- TOY_WRITEMASK_XYZW = (TOY_WRITEMASK_X | TOY_WRITEMASK_Y |
- TOY_WRITEMASK_Z | TOY_WRITEMASK_W),
-};
-
-/**
- * Destination operand.
- */
-struct toy_dst {
- unsigned file:3; /* TOY_FILE_x */
- unsigned type:4; /* TOY_TYPE_x */
- unsigned rect:3; /* TOY_RECT_x */
- unsigned indirect:1; /* true or false */
- unsigned indirect_subreg:6; /* which subreg of a0? */
-
- unsigned writemask:4; /* TOY_WRITEMASK_x */
- unsigned pad:11;
-
- uint32_t val32;
-};
-
-/**
- * Source operand.
- */
-struct toy_src {
- unsigned file:3; /* TOY_FILE_x */
- unsigned type:4; /* TOY_TYPE_x */
- unsigned rect:3; /* TOY_RECT_x */
- unsigned indirect:1; /* true or false */
- unsigned indirect_subreg:6; /* which subreg of a0? */
-
- unsigned swizzle_x:2; /* TOY_SWIZZLE_x */
- unsigned swizzle_y:2; /* TOY_SWIZZLE_x */
- unsigned swizzle_z:2; /* TOY_SWIZZLE_x */
- unsigned swizzle_w:2; /* TOY_SWIZZLE_x */
- unsigned absolute:1; /* true or false */
- unsigned negate:1; /* true or false */
- unsigned pad:5;
-
- uint32_t val32;
-};
-
-/**
- * Return true if the file is virtual.
- */
-static inline bool
-toy_file_is_virtual(enum toy_file file)
-{
- return (file == TOY_FILE_VRF);
-}
-
-/**
- * Return true if the file is a hardware one.
- */
-static inline bool
-toy_file_is_hw(enum toy_file file)
-{
- return !toy_file_is_virtual(file);
-}
-
-/**
- * Return the size of the file.
- */
-static inline uint32_t
-toy_file_size(enum toy_file file)
-{
- switch (file) {
- case TOY_FILE_GRF:
- return 256 * TOY_REG_WIDTH;
- case TOY_FILE_MRF:
- /* there is no MRF on GEN7+ */
- return 256 * TOY_REG_WIDTH;
- default:
- assert(!"invalid toy file");
- return 0;
- }
-}
-
-/**
- * Return the size of the type.
- */
-static inline int
-toy_type_size(enum toy_type type)
-{
- switch (type) {
- case TOY_TYPE_F:
- case TOY_TYPE_D:
- case TOY_TYPE_UD:
- return 4;
- case TOY_TYPE_W:
- case TOY_TYPE_UW:
- return 2;
- case TOY_TYPE_V:
- default:
- assert(!"invalid toy type");
- return 0;
- }
-}
-
-/**
- * Return true if the destination operand is null.
- */
-static inline bool
-tdst_is_null(struct toy_dst dst)
-{
- /* GEN6_ARF_NULL happens to be 0 */
- return (dst.file == TOY_FILE_ARF && dst.val32 == 0);
-}
-
-/**
- * Validate the destination operand.
- */
-static inline struct toy_dst
-tdst_validate(struct toy_dst dst)
-{
- switch (dst.file) {
- case TOY_FILE_VRF:
- case TOY_FILE_ARF:
- case TOY_FILE_MRF:
- assert(!dst.indirect);
- if (dst.file == TOY_FILE_MRF)
- assert(dst.val32 < toy_file_size(dst.file));
- break;
- case TOY_FILE_GRF:
- if (!dst.indirect)
- assert(dst.val32 < toy_file_size(dst.file));
- break;
- case TOY_FILE_IMM:
- /* yes, dst can be IMM of type W (for IF/ELSE/ENDIF/WHILE) */
- assert(!dst.indirect);
- assert(dst.type == TOY_TYPE_W);
- break;
- default:
- assert(!"invalid dst file");
- break;
- }
-
- switch (dst.type) {
- case TOY_TYPE_V:
- assert(!"invalid dst type");
- break;
- default:
- break;
- }
-
- assert(dst.rect == TOY_RECT_LINEAR);
- if (dst.file != TOY_FILE_IMM)
- assert(dst.val32 % toy_type_size(dst.type) == 0);
-
- assert(dst.writemask <= TOY_WRITEMASK_XYZW);
-
- return dst;
-}
-
-/**
- * Change the type of the destination operand.
- */
-static inline struct toy_dst
-tdst_type(struct toy_dst dst, enum toy_type type)
-{
- dst.type = type;
- return tdst_validate(dst);
-}
-
-/**
- * Change the type of the destination operand to TOY_TYPE_D.
- */
-static inline struct toy_dst
-tdst_d(struct toy_dst dst)
-{
- return tdst_type(dst, TOY_TYPE_D);
-}
-
-/**
- * Change the type of the destination operand to TOY_TYPE_UD.
- */
-static inline struct toy_dst
-tdst_ud(struct toy_dst dst)
-{
- return tdst_type(dst, TOY_TYPE_UD);
-}
-
-/**
- * Change the type of the destination operand to TOY_TYPE_W.
- */
-static inline struct toy_dst
-tdst_w(struct toy_dst dst)
-{
- return tdst_type(dst, TOY_TYPE_W);
-}
-
-/**
- * Change the type of the destination operand to TOY_TYPE_UW.
- */
-static inline struct toy_dst
-tdst_uw(struct toy_dst dst)
-{
- return tdst_type(dst, TOY_TYPE_UW);
-}
-
-/**
- * Change the rectangle of the destination operand.
- */
-static inline struct toy_dst
-tdst_rect(struct toy_dst dst, enum toy_rect rect)
-{
- dst.rect = rect;
- return tdst_validate(dst);
-}
-
-/**
- * Apply writemask to the destination operand. Note that the current
- * writemask is honored.
- */
-static inline struct toy_dst
-tdst_writemask(struct toy_dst dst, enum toy_writemask writemask)
-{
- dst.writemask &= writemask;
- return tdst_validate(dst);
-}
-
-/**
- * Offset the destination operand.
- */
-static inline struct toy_dst
-tdst_offset(struct toy_dst dst, int reg, int subreg)
-{
- dst.val32 += reg * TOY_REG_WIDTH + subreg * toy_type_size(dst.type);
- return tdst_validate(dst);
-}
-
-/**
- * Construct a destination operand.
- */
-static inline struct toy_dst
-tdst_full(enum toy_file file, enum toy_type type, enum toy_rect rect,
- bool indirect, unsigned indirect_subreg,
- enum toy_writemask writemask, uint32_t val32)
-{
- struct toy_dst dst;
-
- dst.file = file;
- dst.type = type;
- dst.rect = rect;
- dst.indirect = indirect;
- dst.indirect_subreg = indirect_subreg;
- dst.writemask = writemask;
- dst.pad = 0;
-
- dst.val32 = val32;
-
- return tdst_validate(dst);
-}
-
-/**
- * Construct a null destination operand.
- */
-static inline struct toy_dst
-tdst_null(void)
-{
- static const struct toy_dst null_dst = {
- .file = TOY_FILE_ARF,
- .type = TOY_TYPE_F,
- .rect = TOY_RECT_LINEAR,
- .indirect = false,
- .indirect_subreg = 0,
- .writemask = TOY_WRITEMASK_XYZW,
- .pad = 0,
- .val32 = 0,
- };
-
- return null_dst;
-}
-
-/**
- * Construct a destination operand from a source operand.
- */
-static inline struct toy_dst
-tdst_from(struct toy_src src)
-{
- const enum toy_writemask writemask =
- (1 << src.swizzle_x) |
- (1 << src.swizzle_y) |
- (1 << src.swizzle_z) |
- (1 << src.swizzle_w);
-
- return tdst_full(src.file, src.type, src.rect,
- src.indirect, src.indirect_subreg, writemask, src.val32);
-}
-
-/**
- * Construct a destination operand, assuming the type is TOY_TYPE_F, the
- * rectangle is TOY_RECT_LINEAR, and the writemask is TOY_WRITEMASK_XYZW.
- */
-static inline struct toy_dst
-tdst(enum toy_file file, unsigned reg, unsigned subreg_in_bytes)
-{
- const enum toy_type type = TOY_TYPE_F;
- const enum toy_rect rect = TOY_RECT_LINEAR;
- const uint32_t val32 = reg * TOY_REG_WIDTH + subreg_in_bytes;
-
- return tdst_full(file, type, rect,
- false, 0, TOY_WRITEMASK_XYZW, val32);
-}
-
-/**
- * Construct an immediate destination operand of type TOY_TYPE_W.
- */
-static inline struct toy_dst
-tdst_imm_w(int16_t w)
-{
- const union fi fi = { .i = w };
-
- return tdst_full(TOY_FILE_IMM, TOY_TYPE_W, TOY_RECT_LINEAR,
- false, 0, TOY_WRITEMASK_XYZW, fi.ui);
-}
-
-/**
- * Return true if the source operand is null.
- */
-static inline bool
-tsrc_is_null(struct toy_src src)
-{
- /* GEN6_ARF_NULL happens to be 0 */
- return (src.file == TOY_FILE_ARF && src.val32 == 0);
-}
-
-/**
- * Return true if the source operand is swizzled.
- */
-static inline bool
-tsrc_is_swizzled(struct toy_src src)
-{
- return (src.swizzle_x != TOY_SWIZZLE_X ||
- src.swizzle_y != TOY_SWIZZLE_Y ||
- src.swizzle_z != TOY_SWIZZLE_Z ||
- src.swizzle_w != TOY_SWIZZLE_W);
-}
-
-/**
- * Return true if the source operand is swizzled to the same channel.
- */
-static inline bool
-tsrc_is_swizzle1(struct toy_src src)
-{
- return (src.swizzle_x == src.swizzle_y &&
- src.swizzle_x == src.swizzle_z &&
- src.swizzle_x == src.swizzle_w);
-}
-
-/**
- * Validate the source operand.
- */
-static inline struct toy_src
-tsrc_validate(struct toy_src src)
-{
- switch (src.file) {
- case TOY_FILE_VRF:
- case TOY_FILE_ARF:
- case TOY_FILE_MRF:
- assert(!src.indirect);
- if (src.file == TOY_FILE_MRF)
- assert(src.val32 < toy_file_size(src.file));
- break;
- case TOY_FILE_GRF:
- if (!src.indirect)
- assert(src.val32 < toy_file_size(src.file));
- break;
- case TOY_FILE_IMM:
- assert(!src.indirect);
- break;
- default:
- assert(!"invalid src file");
- break;
- }
-
- switch (src.type) {
- case TOY_TYPE_V:
- assert(src.file == TOY_FILE_IMM);
- break;
- default:
- break;
- }
-
- if (src.file != TOY_FILE_IMM)
- assert(src.val32 % toy_type_size(src.type) == 0);
-
- assert(src.swizzle_x < 4 && src.swizzle_y < 4 &&
- src.swizzle_z < 4 && src.swizzle_w < 4);
-
- return src;
-}
-
-/**
- * Change the type of the source operand.
- */
-static inline struct toy_src
-tsrc_type(struct toy_src src, enum toy_type type)
-{
- src.type = type;
- return tsrc_validate(src);
-}
-
-/**
- * Change the type of the source operand to TOY_TYPE_D.
- */
-static inline struct toy_src
-tsrc_d(struct toy_src src)
-{
- return tsrc_type(src, TOY_TYPE_D);
-}
-
-/**
- * Change the type of the source operand to TOY_TYPE_UD.
- */
-static inline struct toy_src
-tsrc_ud(struct toy_src src)
-{
- return tsrc_type(src, TOY_TYPE_UD);
-}
-
-/**
- * Change the type of the source operand to TOY_TYPE_W.
- */
-static inline struct toy_src
-tsrc_w(struct toy_src src)
-{
- return tsrc_type(src, TOY_TYPE_W);
-}
-
-/**
- * Change the type of the source operand to TOY_TYPE_UW.
- */
-static inline struct toy_src
-tsrc_uw(struct toy_src src)
-{
- return tsrc_type(src, TOY_TYPE_UW);
-}
-
-/**
- * Change the rectangle of the source operand.
- */
-static inline struct toy_src
-tsrc_rect(struct toy_src src, enum toy_rect rect)
-{
- src.rect = rect;
- return tsrc_validate(src);
-}
-
-/**
- * Swizzle the source operand. Note that the current swizzles are honored.
- */
-static inline struct toy_src
-tsrc_swizzle(struct toy_src src,
- enum toy_swizzle swizzle_x, enum toy_swizzle swizzle_y,
- enum toy_swizzle swizzle_z, enum toy_swizzle swizzle_w)
-{
- const enum toy_swizzle current[4] = {
- src.swizzle_x, src.swizzle_y,
- src.swizzle_z, src.swizzle_w,
- };
-
- src.swizzle_x = current[swizzle_x];
- src.swizzle_y = current[swizzle_y];
- src.swizzle_z = current[swizzle_z];
- src.swizzle_w = current[swizzle_w];
-
- return tsrc_validate(src);
-}
-
-/**
- * Swizzle the source operand to the same channel. Note that the current
- * swizzles are honored.
- */
-static inline struct toy_src
-tsrc_swizzle1(struct toy_src src, enum toy_swizzle swizzle)
-{
- return tsrc_swizzle(src, swizzle, swizzle, swizzle, swizzle);
-}
-
-/**
- * Set absolute and unset negate of the source operand.
- */
-static inline struct toy_src
-tsrc_absolute(struct toy_src src)
-{
- src.absolute = true;
- src.negate = false;
- return tsrc_validate(src);
-}
-
-/**
- * Negate the source operand.
- */
-static inline struct toy_src
-tsrc_negate(struct toy_src src)
-{
- src.negate = !src.negate;
- return tsrc_validate(src);
-}
-
-/**
- * Offset the source operand.
- */
-static inline struct toy_src
-tsrc_offset(struct toy_src src, int reg, int subreg)
-{
- src.val32 += reg * TOY_REG_WIDTH + subreg * toy_type_size(src.type);
- return tsrc_validate(src);
-}
-
-/**
- * Construct a source operand.
- */
-static inline struct toy_src
-tsrc_full(enum toy_file file, enum toy_type type,
- enum toy_rect rect, bool indirect, unsigned indirect_subreg,
- enum toy_swizzle swizzle_x, enum toy_swizzle swizzle_y,
- enum toy_swizzle swizzle_z, enum toy_swizzle swizzle_w,
- bool absolute, bool negate,
- uint32_t val32)
-{
- struct toy_src src;
-
- src.file = file;
- src.type = type;
- src.rect = rect;
- src.indirect = indirect;
- src.indirect_subreg = indirect_subreg;
- src.swizzle_x = swizzle_x;
- src.swizzle_y = swizzle_y;
- src.swizzle_z = swizzle_z;
- src.swizzle_w = swizzle_w;
- src.absolute = absolute;
- src.negate = negate;
- src.pad = 0;
-
- src.val32 = val32;
-
- return tsrc_validate(src);
-}
-
-/**
- * Construct a null source operand.
- */
-static inline struct toy_src
-tsrc_null(void)
-{
- static const struct toy_src null_src = {
- .file = TOY_FILE_ARF,
- .type = TOY_TYPE_F,
- .rect = TOY_RECT_LINEAR,
- .indirect = false,
- .indirect_subreg = 0,
- .swizzle_x = TOY_SWIZZLE_X,
- .swizzle_y = TOY_SWIZZLE_Y,
- .swizzle_z = TOY_SWIZZLE_Z,
- .swizzle_w = TOY_SWIZZLE_W,
- .absolute = false,
- .negate = false,
- .pad = 0,
- .val32 = 0,
- };
-
- return null_src;
-}
-
-/**
- * Construct a source operand from a destination operand.
- */
-static inline struct toy_src
-tsrc_from(struct toy_dst dst)
-{
- enum toy_swizzle swizzle[4];
-
- if (dst.writemask == TOY_WRITEMASK_XYZW) {
- swizzle[0] = TOY_SWIZZLE_X;
- swizzle[1] = TOY_SWIZZLE_Y;
- swizzle[2] = TOY_SWIZZLE_Z;
- swizzle[3] = TOY_SWIZZLE_W;
- }
- else {
- const enum toy_swizzle first =
- (dst.writemask & TOY_WRITEMASK_X) ? TOY_SWIZZLE_X :
- (dst.writemask & TOY_WRITEMASK_Y) ? TOY_SWIZZLE_Y :
- (dst.writemask & TOY_WRITEMASK_Z) ? TOY_SWIZZLE_Z :
- (dst.writemask & TOY_WRITEMASK_W) ? TOY_SWIZZLE_W :
- TOY_SWIZZLE_X;
-
- swizzle[0] = (dst.writemask & TOY_WRITEMASK_X) ? TOY_SWIZZLE_X : first;
- swizzle[1] = (dst.writemask & TOY_WRITEMASK_Y) ? TOY_SWIZZLE_Y : first;
- swizzle[2] = (dst.writemask & TOY_WRITEMASK_Z) ? TOY_SWIZZLE_Z : first;
- swizzle[3] = (dst.writemask & TOY_WRITEMASK_W) ? TOY_SWIZZLE_W : first;
- }
-
- return tsrc_full(dst.file, dst.type, dst.rect,
- dst.indirect, dst.indirect_subreg,
- swizzle[0], swizzle[1], swizzle[2], swizzle[3],
- false, false, dst.val32);
-}
-
-/**
- * Construct a source operand, assuming the type is TOY_TYPE_F, the
- * rectangle is TOY_RECT_LINEAR, and no swizzles/absolute/negate.
- */
-static inline struct toy_src
-tsrc(enum toy_file file, unsigned reg, unsigned subreg_in_bytes)
-{
- const enum toy_type type = TOY_TYPE_F;
- const enum toy_rect rect = TOY_RECT_LINEAR;
- const uint32_t val32 = reg * TOY_REG_WIDTH + subreg_in_bytes;
-
- return tsrc_full(file, type, rect, false, 0,
- TOY_SWIZZLE_X, TOY_SWIZZLE_Y,
- TOY_SWIZZLE_Z, TOY_SWIZZLE_W,
- false, false, val32);
-}
-
-/**
- * Construct an immediate source operand.
- */
-static inline struct toy_src
-tsrc_imm(enum toy_type type, uint32_t val32)
-{
- return tsrc_full(TOY_FILE_IMM, type, TOY_RECT_LINEAR, false, 0,
- TOY_SWIZZLE_X, TOY_SWIZZLE_Y,
- TOY_SWIZZLE_Z, TOY_SWIZZLE_W,
- false, false, val32);
-}
-
-/**
- * Construct an immediate source operand of type TOY_TYPE_F.
- */
-static inline struct toy_src
-tsrc_imm_f(float f)
-{
- const union fi fi = { .f = f };
- return tsrc_imm(TOY_TYPE_F, fi.ui);
-}
-
-/**
- * Construct an immediate source operand of type TOY_TYPE_D.
- */
-static inline struct toy_src
-tsrc_imm_d(int32_t d)
-{
- const union fi fi = { .i = d };
- return tsrc_imm(TOY_TYPE_D, fi.ui);
-}
-
-/**
- * Construct an immediate source operand of type TOY_TYPE_UD.
- */
-static inline struct toy_src
-tsrc_imm_ud(uint32_t ud)
-{
- const union fi fi = { .ui = ud };
- return tsrc_imm(TOY_TYPE_UD, fi.ui);
-}
-
-/**
- * Construct an immediate source operand of type TOY_TYPE_W.
- */
-static inline struct toy_src
-tsrc_imm_w(int16_t w)
-{
- const union fi fi = { .i = w };
- return tsrc_imm(TOY_TYPE_W, fi.ui);
-}
-
-/**
- * Construct an immediate source operand of type TOY_TYPE_UW.
- */
-static inline struct toy_src
-tsrc_imm_uw(uint16_t uw)
-{
- const union fi fi = { .ui = uw };
- return tsrc_imm(TOY_TYPE_UW, fi.ui);
-}
-
-/**
- * Construct an immediate source operand of type TOY_TYPE_V.
- */
-static inline struct toy_src
-tsrc_imm_v(uint32_t v)
-{
- return tsrc_imm(TOY_TYPE_V, v);
-}
-
-#endif /* TOY_REG_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef TOY_HELPERS_H
-#define TOY_HELPERS_H
-
-#include "toy_compiler.h"
-
-/**
- * Transpose a dst operand.
- *
- * Instead of processing a single vertex with each of its attributes in one
- * register, such as
- *
- * r0 = [x0, y0, z0, w0]
- *
- * we want to process four vertices at a time
- *
- * r0 = [x0, y0, z0, w0]
- * r1 = [x1, y1, z1, w1]
- * r2 = [x2, y2, z2, w2]
- * r3 = [x3, y3, z3, w3]
- *
- * but with the attribute data "transposed"
- *
- * r0 = [x0, x1, x2, x3]
- * r1 = [y0, y1, y2, y3]
- * r2 = [z0, z1, z2, z3]
- * r3 = [w0, w1, w2, w3]
- *
- * This is also known as the SoA form.
- */
-static inline void
-tdst_transpose(struct toy_dst dst, struct toy_dst *trans)
-{
- int i;
-
- switch (dst.file) {
- case TOY_FILE_VRF:
- assert(!dst.indirect);
- for (i = 0; i < 4; i++) {
- if (dst.writemask & (1 << i)) {
- trans[i] = tdst_offset(dst, i, 0);
- trans[i].writemask = TOY_WRITEMASK_XYZW;
- }
- else {
- trans[i] = tdst_null();
- }
- }
- break;
- case TOY_FILE_ARF:
- assert(tdst_is_null(dst));
- for (i = 0; i < 4; i++)
- trans[i] = dst;
- break;
- case TOY_FILE_GRF:
- case TOY_FILE_MRF:
- case TOY_FILE_IMM:
- default:
- assert(!"unexpected file in dst transposition");
- for (i = 0; i < 4; i++)
- trans[i] = tdst_null();
- break;
- }
-}
-
-/**
- * Transpose a src operand.
- */
-static inline void
-tsrc_transpose(struct toy_src src, struct toy_src *trans)
-{
- const enum toy_swizzle swizzle[4] = {
- src.swizzle_x, src.swizzle_y,
- src.swizzle_z, src.swizzle_w,
- };
- int i;
-
- switch (src.file) {
- case TOY_FILE_VRF:
- assert(!src.indirect);
- for (i = 0; i < 4; i++) {
- trans[i] = tsrc_offset(src, swizzle[i], 0);
- trans[i].swizzle_x = TOY_SWIZZLE_X;
- trans[i].swizzle_y = TOY_SWIZZLE_Y;
- trans[i].swizzle_z = TOY_SWIZZLE_Z;
- trans[i].swizzle_w = TOY_SWIZZLE_W;
- }
- break;
- case TOY_FILE_ARF:
- assert(tsrc_is_null(src));
- /* fall through */
- case TOY_FILE_IMM:
- for (i = 0; i < 4; i++)
- trans[i] = src;
- break;
- case TOY_FILE_GRF:
- case TOY_FILE_MRF:
- default:
- assert(!"unexpected file in src transposition");
- for (i = 0; i < 4; i++)
- trans[i] = tsrc_null();
- break;
- }
-}
-
-static inline struct toy_src
-tsrc_imm_mdesc(const struct toy_compiler *tc,
- bool eot,
- unsigned message_length,
- unsigned response_length,
- bool header_present,
- uint32_t function_control)
-{
- uint32_t desc;
-
- assert(message_length >= 1 && message_length <= 15);
- assert(response_length >= 0 && response_length <= 16);
- assert(function_control < 1 << 19);
-
- desc = eot << 31 |
- message_length << 25 |
- response_length << 20 |
- header_present << 19 |
- function_control;
-
- return tsrc_imm_ud(desc);
-}
-
-static inline struct toy_src
-tsrc_imm_mdesc_sampler(const struct toy_compiler *tc,
- unsigned message_length,
- unsigned response_length,
- bool header_present,
- unsigned simd_mode,
- unsigned message_type,
- unsigned sampler_index,
- unsigned binding_table_index)
-{
- const bool eot = false;
- uint32_t ctrl;
-
- assert(simd_mode < 4);
- assert(sampler_index < 16);
- assert(binding_table_index < 256);
-
- if (ilo_dev_gen(tc->dev) >= ILO_GEN(7)) {
- ctrl = simd_mode << 17 |
- message_type << 12 |
- sampler_index << 8 |
- binding_table_index;
- }
- else {
- ctrl = simd_mode << 16 |
- message_type << 12 |
- sampler_index << 8 |
- binding_table_index;
- }
-
- return tsrc_imm_mdesc(tc, eot, message_length,
- response_length, header_present, ctrl);
-}
-
-static inline struct toy_src
-tsrc_imm_mdesc_data_port(const struct toy_compiler *tc,
- bool eot,
- unsigned message_length,
- unsigned response_length,
- bool header_present,
- bool send_write_commit_message,
- unsigned message_type,
- unsigned message_specific_control,
- unsigned binding_table_index)
-{
- uint32_t ctrl;
-
- if (ilo_dev_gen(tc->dev) >= ILO_GEN(7)) {
- assert(!send_write_commit_message);
- assert((message_specific_control & 0x3f00) == message_specific_control);
-
- ctrl = message_type << 14 |
- (message_specific_control & 0x3f00) |
- binding_table_index;
- }
- else {
- assert(!send_write_commit_message ||
- message_type == GEN6_MSG_DP_SVB_WRITE);
- assert((message_specific_control & 0x1f00) == message_specific_control);
-
- ctrl = send_write_commit_message << 17 |
- message_type << 13 |
- (message_specific_control & 0x1f00) |
- binding_table_index;
- }
-
- return tsrc_imm_mdesc(tc, eot, message_length,
- response_length, header_present, ctrl);
-}
-
-static inline struct toy_src
-tsrc_imm_mdesc_data_port_scratch(const struct toy_compiler *tc,
- unsigned message_length,
- unsigned response_length,
- bool write_type,
- bool dword_mode,
- bool invalidate_after_read,
- int num_registers,
- int hword_offset)
-{
- const bool eot = false;
- const bool header_present = true;
- uint32_t ctrl;
-
- assert(ilo_dev_gen(tc->dev) >= ILO_GEN(7));
- assert(num_registers == 1 || num_registers == 2 || num_registers == 4);
-
- ctrl = 1 << 18 |
- write_type << 17 |
- dword_mode << 16 |
- invalidate_after_read << 15 |
- (num_registers - 1) << 12 |
- hword_offset;
-
- return tsrc_imm_mdesc(tc, eot, message_length,
- response_length, header_present, ctrl);
-}
-
-static inline struct toy_src
-tsrc_imm_mdesc_urb(const struct toy_compiler *tc,
- bool eot,
- unsigned message_length,
- unsigned response_length,
- bool complete,
- bool used,
- bool allocate,
- unsigned swizzle_control,
- unsigned global_offset,
- unsigned urb_opcode)
-{
- const bool header_present = true;
- uint32_t ctrl;
-
- if (ilo_dev_gen(tc->dev) >= ILO_GEN(8)) {
- const bool per_slot_offset = false;
-
- ctrl = per_slot_offset << 17 |
- swizzle_control << 15 |
- global_offset << 4 |
- urb_opcode;
- } else if (ilo_dev_gen(tc->dev) >= ILO_GEN(7)) {
- const bool per_slot_offset = false;
-
- ctrl = per_slot_offset << 16 |
- complete << 15 |
- swizzle_control << 14 |
- global_offset << 3 |
- urb_opcode;
- } else {
- ctrl = complete << 15 |
- used << 14 |
- allocate << 13 |
- swizzle_control << 10 |
- global_offset << 4 |
- urb_opcode;
- }
-
- return tsrc_imm_mdesc(tc, eot, message_length,
- response_length, header_present, ctrl);
-}
-
-#endif /* TOY_HELPERS_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "pipe/p_shader_tokens.h"
-#include "toy_compiler.h"
-#include "toy_tgsi.h"
-#include "toy_helpers.h"
-#include "toy_legalize.h"
-
-/**
- * Lower an instruction to GEN6_OPCODE_SEND(C).
- */
-void
-toy_compiler_lower_to_send(struct toy_compiler *tc, struct toy_inst *inst,
- bool sendc, unsigned sfid)
-{
- assert(inst->opcode >= 128);
-
- inst->opcode = (sendc) ? GEN6_OPCODE_SENDC : GEN6_OPCODE_SEND;
-
- /* thread control is reserved */
- assert(inst->thread_ctrl == 0);
-
- assert(inst->cond_modifier == GEN6_COND_NONE);
- inst->cond_modifier = sfid;
-}
-
-static int
-math_op_to_func(unsigned opcode)
-{
- switch (opcode) {
- case TOY_OPCODE_INV: return GEN6_MATH_INV;
- case TOY_OPCODE_LOG: return GEN6_MATH_LOG;
- case TOY_OPCODE_EXP: return GEN6_MATH_EXP;
- case TOY_OPCODE_SQRT: return GEN6_MATH_SQRT;
- case TOY_OPCODE_RSQ: return GEN6_MATH_RSQ;
- case TOY_OPCODE_SIN: return GEN6_MATH_SIN;
- case TOY_OPCODE_COS: return GEN6_MATH_COS;
- case TOY_OPCODE_FDIV: return GEN6_MATH_FDIV;
- case TOY_OPCODE_POW: return GEN6_MATH_POW;
- case TOY_OPCODE_INT_DIV_QUOTIENT: return GEN6_MATH_INT_DIV_QUOTIENT;
- case TOY_OPCODE_INT_DIV_REMAINDER: return GEN6_MATH_INT_DIV_REMAINDER;
- default:
- assert(!"unknown math opcode");
- return -1;
- }
-}
-
-/**
- * Lower virtual math opcodes to GEN6_OPCODE_MATH.
- */
-void
-toy_compiler_lower_math(struct toy_compiler *tc, struct toy_inst *inst)
-{
- struct toy_dst tmp;
- int i;
-
- /* see commit 250770b74d33bb8625c780a74a89477af033d13a */
- for (i = 0; i < ARRAY_SIZE(inst->src); i++) {
- if (tsrc_is_null(inst->src[i]))
- break;
-
- /* no swizzling in align1 */
- /* XXX how about source modifiers? */
- if (toy_file_is_virtual(inst->src[i].file) &&
- !tsrc_is_swizzled(inst->src[i]) &&
- !inst->src[i].absolute &&
- !inst->src[i].negate)
- continue;
-
- tmp = tdst_type(tc_alloc_tmp(tc), inst->src[i].type);
- tc_MOV(tc, tmp, inst->src[i]);
- inst->src[i] = tsrc_from(tmp);
- }
-
- /* FC[0:3] */
- assert(inst->cond_modifier == GEN6_COND_NONE);
- inst->cond_modifier = math_op_to_func(inst->opcode);
- /* FC[4:5] */
- assert(inst->thread_ctrl == 0);
- inst->thread_ctrl = 0;
-
- inst->opcode = GEN6_OPCODE_MATH;
- tc_move_inst(tc, inst);
-
- /* no writemask in align1 */
- if (inst->dst.writemask != TOY_WRITEMASK_XYZW) {
- struct toy_dst dst = inst->dst;
- struct toy_inst *inst2;
-
- tmp = tc_alloc_tmp(tc);
- tmp.type = inst->dst.type;
- inst->dst = tmp;
-
- inst2 = tc_MOV(tc, dst, tsrc_from(tmp));
- inst2->pred_ctrl = inst->pred_ctrl;
- }
-}
-
-static uint32_t
-absolute_imm(uint32_t imm32, enum toy_type type)
-{
- union fi val = { .ui = imm32 };
-
- switch (type) {
- case TOY_TYPE_F:
- val.f = fabs(val.f);
- break;
- case TOY_TYPE_D:
- if (val.i < 0)
- val.i = -val.i;
- break;
- case TOY_TYPE_W:
- if ((int16_t) (val.ui & 0xffff) < 0)
- val.i = -((int16_t) (val.ui & 0xffff));
- break;
- case TOY_TYPE_V:
- assert(!"cannot take absoulte of immediates of type V");
- break;
- default:
- break;
- }
-
- return val.ui;
-}
-
-static uint32_t
-negate_imm(uint32_t imm32, enum toy_type type)
-{
- union fi val = { .ui = imm32 };
-
- switch (type) {
- case TOY_TYPE_F:
- val.f = -val.f;
- break;
- case TOY_TYPE_D:
- case TOY_TYPE_UD:
- val.i = -val.i;
- break;
- case TOY_TYPE_W:
- case TOY_TYPE_UW:
- val.i = -((int16_t) (val.ui & 0xffff));
- break;
- default:
- assert(!"negate immediate of unknown type");
- break;
- }
-
- return val.ui;
-}
-
-static void
-validate_imm(struct toy_compiler *tc, struct toy_inst *inst)
-{
- bool move_inst = false;
- int i;
-
- for (i = 0; i < ARRAY_SIZE(inst->src); i++) {
- struct toy_dst tmp;
-
- if (tsrc_is_null(inst->src[i]))
- break;
-
- if (inst->src[i].file != TOY_FILE_IMM)
- continue;
-
- if (inst->src[i].absolute) {
- inst->src[i].val32 =
- absolute_imm(inst->src[i].val32, inst->src[i].type);
- inst->src[i].absolute = false;
- }
-
- if (inst->src[i].negate) {
- inst->src[i].val32 =
- negate_imm(inst->src[i].val32, inst->src[i].type);
- inst->src[i].negate = false;
- }
-
- /* this is the last operand */
- if (i + 1 == ARRAY_SIZE(inst->src) || tsrc_is_null(inst->src[i + 1]))
- break;
-
- /* need to use a temp if this imm is not the last operand */
- /* TODO we should simply swap the operands if the op is commutative */
- tmp = tc_alloc_tmp(tc);
- tmp = tdst_type(tmp, inst->src[i].type);
- tc_MOV(tc, tmp, inst->src[i]);
- inst->src[i] = tsrc_from(tmp);
-
- move_inst = true;
- }
-
- if (move_inst)
- tc_move_inst(tc, inst);
-}
-
-static void
-lower_opcode_mul(struct toy_compiler *tc, struct toy_inst *inst)
-{
- const enum toy_type inst_type = inst->dst.type;
- const struct toy_dst acc0 =
- tdst_type(tdst(TOY_FILE_ARF, GEN6_ARF_ACC0, 0), inst_type);
- struct toy_inst *inst2;
-
- /* only need to take care of integer multiplications */
- if (inst_type != TOY_TYPE_UD && inst_type != TOY_TYPE_D)
- return;
-
- /* acc0 = (src0 & 0x0000ffff) * src1 */
- tc_MUL(tc, acc0, inst->src[0], inst->src[1]);
-
- /* acc0 = (src0 & 0xffff0000) * src1 + acc0 */
- inst2 = tc_add2(tc, GEN6_OPCODE_MACH, tdst_type(tdst_null(), inst_type),
- inst->src[0], inst->src[1]);
- inst2->acc_wr_ctrl = true;
-
- /* dst = acc0 & 0xffffffff */
- tc_MOV(tc, inst->dst, tsrc_from(acc0));
-
- tc_discard_inst(tc, inst);
-}
-
-static void
-lower_opcode_mac(struct toy_compiler *tc, struct toy_inst *inst)
-{
- const enum toy_type inst_type = inst->dst.type;
-
- if (inst_type != TOY_TYPE_UD && inst_type != TOY_TYPE_D) {
- const struct toy_dst acc0 = tdst(TOY_FILE_ARF, GEN6_ARF_ACC0, 0);
-
- tc_MOV(tc, acc0, inst->src[2]);
- inst->src[2] = tsrc_null();
- tc_move_inst(tc, inst);
- }
- else {
- struct toy_dst tmp = tdst_type(tc_alloc_tmp(tc), inst_type);
- struct toy_inst *inst2;
-
- inst2 = tc_MUL(tc, tmp, inst->src[0], inst->src[1]);
- lower_opcode_mul(tc, inst2);
-
- tc_ADD(tc, inst->dst, tsrc_from(tmp), inst->src[2]);
-
- tc_discard_inst(tc, inst);
- }
-}
-
-/**
- * Legalize the instructions for register allocation.
- */
-void
-toy_compiler_legalize_for_ra(struct toy_compiler *tc)
-{
- struct toy_inst *inst;
-
- tc_head(tc);
- while ((inst = tc_next(tc)) != NULL) {
- switch (inst->opcode) {
- case GEN6_OPCODE_MAC:
- lower_opcode_mac(tc, inst);
- break;
- case GEN6_OPCODE_MAD:
- /* TODO operands must be floats */
- break;
- case GEN6_OPCODE_MUL:
- lower_opcode_mul(tc, inst);
- break;
- default:
- if (inst->opcode > TOY_OPCODE_LAST_HW)
- tc_fail(tc, "internal opcodes not lowered");
- }
- }
-
- /* loop again as the previous pass may add new instructions */
- tc_head(tc);
- while ((inst = tc_next(tc)) != NULL) {
- validate_imm(tc, inst);
- }
-}
-
-static void
-patch_while_jip(struct toy_compiler *tc, struct toy_inst *inst)
-{
- struct toy_inst *inst2;
- int nest_level, dist;
-
- nest_level = 0;
- dist = -1;
-
- /* search backward */
- LIST_FOR_EACH_ENTRY_FROM_REV(inst2, inst->list.prev,
- &tc->instructions, list) {
- if (inst2->marker) {
- if (inst2->opcode == TOY_OPCODE_DO) {
- if (nest_level) {
- nest_level--;
- }
- else {
- /* the following instruction */
- dist++;
- break;
- }
- }
-
- continue;
- }
-
- if (inst2->opcode == GEN6_OPCODE_WHILE)
- nest_level++;
-
- dist--;
- }
-
- if (ilo_dev_gen(tc->dev) >= ILO_GEN(8))
- inst->src[1] = tsrc_imm_d(dist * 16);
- else if (ilo_dev_gen(tc->dev) >= ILO_GEN(7))
- inst->src[1] = tsrc_imm_w(dist * 2);
- else
- inst->dst = tdst_imm_w(dist * 2);
-}
-
-static void
-patch_if_else_jip(struct toy_compiler *tc, struct toy_inst *inst)
-{
- struct toy_inst *inst2;
- int nest_level, dist;
- int jip, uip;
-
- nest_level = 0;
- dist = 1;
- jip = 0;
- uip = 0;
-
- /* search forward */
- LIST_FOR_EACH_ENTRY_FROM(inst2, inst->list.next, &tc->instructions, list) {
- if (inst2->marker)
- continue;
-
- if (inst2->opcode == GEN6_OPCODE_ENDIF) {
- if (nest_level) {
- nest_level--;
- }
- else {
- uip = dist * 2;
- if (!jip)
- jip = uip;
- break;
- }
- }
- else if (inst2->opcode == GEN6_OPCODE_ELSE &&
- inst->opcode == GEN6_OPCODE_IF) {
- if (!nest_level) {
- /* the following instruction */
- jip = (dist + 1) * 2;
-
- if (ilo_dev_gen(tc->dev) == ILO_GEN(6)) {
- uip = jip;
- break;
- }
- }
- }
- else if (inst2->opcode == GEN6_OPCODE_IF) {
- nest_level++;
- }
-
- dist++;
- }
-
- if (ilo_dev_gen(tc->dev) >= ILO_GEN(8)) {
- inst->dst.type = TOY_TYPE_D;
- inst->src[0] = tsrc_imm_d(uip * 8);
- inst->src[1] = tsrc_imm_d(jip * 8);
- } else if (ilo_dev_gen(tc->dev) >= ILO_GEN(7)) {
- /* what should the type be? */
- inst->dst.type = TOY_TYPE_D;
- inst->src[0].type = TOY_TYPE_D;
- inst->src[1] = tsrc_imm_d(uip << 16 | jip);
- } else {
- inst->dst = tdst_imm_w(jip);
- }
-}
-
-static void
-patch_endif_jip(struct toy_compiler *tc, struct toy_inst *inst)
-{
- struct toy_inst *inst2;
- bool found = false;
- int dist = 1;
-
- /* search forward for instructions that may enable channels */
- LIST_FOR_EACH_ENTRY_FROM(inst2, inst->list.next, &tc->instructions, list) {
- if (inst2->marker)
- continue;
-
- switch (inst2->opcode) {
- case GEN6_OPCODE_ENDIF:
- case GEN6_OPCODE_ELSE:
- case GEN6_OPCODE_WHILE:
- found = true;
- break;
- default:
- break;
- }
-
- if (found)
- break;
-
- dist++;
- }
-
- /* should we set dist to (dist - 1) or 1? */
- if (!found)
- dist = 1;
-
- if (ilo_dev_gen(tc->dev) >= ILO_GEN(8))
- inst->src[1] = tsrc_imm_d(dist * 16);
- else if (ilo_dev_gen(tc->dev) >= ILO_GEN(7))
- inst->src[1] = tsrc_imm_w(dist * 2);
- else
- inst->dst = tdst_imm_w(dist * 2);
-}
-
-static void
-patch_break_continue_jip(struct toy_compiler *tc, struct toy_inst *inst)
-{
- struct toy_inst *inst2, *inst3;
- int nest_level, dist, jip, uip;
-
- nest_level = 0;
- dist = 1;
- jip = 1 * 2;
- uip = 1 * 2;
-
- /* search forward */
- LIST_FOR_EACH_ENTRY_FROM(inst2, inst->list.next, &tc->instructions, list) {
- if (inst2->marker) {
- if (inst2->opcode == TOY_OPCODE_DO)
- nest_level++;
- continue;
- }
-
- if (inst2->opcode == GEN6_OPCODE_ELSE ||
- inst2->opcode == GEN6_OPCODE_ENDIF ||
- inst2->opcode == GEN6_OPCODE_WHILE) {
- jip = dist * 2;
- break;
- }
-
- dist++;
- }
-
- /* go on to determine uip */
- inst3 = inst2;
- LIST_FOR_EACH_ENTRY_FROM(inst2, &inst3->list, &tc->instructions, list) {
- if (inst2->marker) {
- if (inst2->opcode == TOY_OPCODE_DO)
- nest_level++;
- continue;
- }
-
- if (inst2->opcode == GEN6_OPCODE_WHILE) {
- if (nest_level) {
- nest_level--;
- }
- else {
- /* the following instruction */
- if (ilo_dev_gen(tc->dev) == ILO_GEN(6) &&
- inst->opcode == GEN6_OPCODE_BREAK)
- dist++;
-
- uip = dist * 2;
- break;
- }
- }
-
- dist++;
- }
-
- /* should the type be D or W? */
- inst->dst.type = TOY_TYPE_D;
- if (ilo_dev_gen(tc->dev) >= ILO_GEN(8)) {
- inst->src[0] = tsrc_imm_d(uip * 8);
- inst->src[1] = tsrc_imm_d(jip * 8);
- } else {
- inst->src[0].type = TOY_TYPE_D;
- inst->src[1] = tsrc_imm_d(uip << 16 | jip);
- }
-}
-
-/**
- * Legalize the instructions for assembling.
- */
-void
-toy_compiler_legalize_for_asm(struct toy_compiler *tc)
-{
- struct toy_inst *inst;
- int pc = 0;
-
- tc_head(tc);
- while ((inst = tc_next(tc)) != NULL) {
- int i;
-
- pc++;
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 2, page 112:
- *
- * "Specifically, for instructions with a single source, it only
- * uses the first source operand <src0>. In this case, the second
- * source operand <src1> must be set to null and also with the same
- * type as the first source operand <src0>. It is a special case
- * when <src0> is an immediate, as an immediate <src0> uses DW3 of
- * the instruction word, which is normally used by <src1>. In this
- * case, <src1> must be programmed with register file ARF and the
- * same data type as <src0>."
- *
- * Since we already fill unused operands with null, we only need to take
- * care of the type.
- */
- if (tsrc_is_null(inst->src[1]))
- inst->src[1].type = inst->src[0].type;
-
- switch (inst->opcode) {
- case GEN6_OPCODE_MATH:
- /* math does not support align16 nor exec_size > 8 */
- inst->access_mode = GEN6_ALIGN_1;
-
- if (inst->exec_size == GEN6_EXECSIZE_16) {
- /*
- * From the Ivy Bridge PRM, volume 4 part 3, page 192:
- *
- * "INT DIV function does not support SIMD16."
- */
- if (ilo_dev_gen(tc->dev) < ILO_GEN(7) ||
- inst->cond_modifier == GEN6_MATH_INT_DIV_QUOTIENT ||
- inst->cond_modifier == GEN6_MATH_INT_DIV_REMAINDER) {
- struct toy_inst *inst2;
-
- inst->exec_size = GEN6_EXECSIZE_8;
- inst->qtr_ctrl = GEN6_QTRCTRL_1Q;
-
- inst2 = tc_duplicate_inst(tc, inst);
- inst2->qtr_ctrl = GEN6_QTRCTRL_2Q;
- inst2->dst = tdst_offset(inst2->dst, 1, 0);
- inst2->src[0] = tsrc_offset(inst2->src[0], 1, 0);
- if (!tsrc_is_null(inst2->src[1]))
- inst2->src[1] = tsrc_offset(inst2->src[1], 1, 0);
-
- pc++;
- }
- }
- break;
- case GEN6_OPCODE_IF:
- if (ilo_dev_gen(tc->dev) >= ILO_GEN(7) &&
- inst->cond_modifier != GEN6_COND_NONE) {
- struct toy_inst *inst2;
-
- inst2 = tc_duplicate_inst(tc, inst);
-
- /* replace the original IF by CMP */
- inst->opcode = GEN6_OPCODE_CMP;
-
- /* predicate control instead of condition modifier */
- inst2->dst = tdst_null();
- inst2->src[0] = tsrc_null();
- inst2->src[1] = tsrc_null();
- inst2->cond_modifier = GEN6_COND_NONE;
- inst2->pred_ctrl = GEN6_PREDCTRL_NORMAL;
-
- pc++;
- }
- break;
- default:
- break;
- }
-
- /* MRF to GRF */
- if (ilo_dev_gen(tc->dev) >= ILO_GEN(7)) {
- for (i = 0; i < ARRAY_SIZE(inst->src); i++) {
- if (inst->src[i].file != TOY_FILE_MRF)
- continue;
- else if (tsrc_is_null(inst->src[i]))
- break;
-
- inst->src[i].file = TOY_FILE_GRF;
- }
-
- if (inst->dst.file == TOY_FILE_MRF)
- inst->dst.file = TOY_FILE_GRF;
- }
- }
-
- tc->num_instructions = pc;
-
- /* set JIP/UIP */
- tc_head(tc);
- while ((inst = tc_next(tc)) != NULL) {
- switch (inst->opcode) {
- case GEN6_OPCODE_IF:
- case GEN6_OPCODE_ELSE:
- patch_if_else_jip(tc, inst);
- break;
- case GEN6_OPCODE_ENDIF:
- patch_endif_jip(tc, inst);
- break;
- case GEN6_OPCODE_WHILE:
- patch_while_jip(tc, inst);
- break;
- case GEN6_OPCODE_BREAK:
- case GEN6_OPCODE_CONT:
- patch_break_continue_jip(tc, inst);
- break;
- default:
- break;
- }
- }
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef TOY_LEGALIZE_H
-#define TOY_LEGALIZE_H
-
-#include "toy_compiler.h"
-#include "toy_tgsi.h"
-
-void
-toy_compiler_lower_to_send(struct toy_compiler *tc, struct toy_inst *inst,
- bool sendc, unsigned sfid);
-
-void
-toy_compiler_lower_math(struct toy_compiler *tc, struct toy_inst *inst);
-
-void
-toy_compiler_allocate_registers(struct toy_compiler *tc,
- int start_grf, int end_grf,
- int num_grf_per_vrf);
-
-void
-toy_compiler_legalize_for_ra(struct toy_compiler *tc);
-
-void
-toy_compiler_legalize_for_asm(struct toy_compiler *tc);
-
-#endif /* TOY_LEGALIZE_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include <stdlib.h> /* for qsort() */
-#include "toy_compiler.h"
-#include "toy_legalize.h"
-
-/**
- * Live interval of a VRF register.
- */
-struct linear_scan_live_interval {
- int vrf;
- int startpoint;
- int endpoint;
-
- /*
- * should this be assigned a consecutive register of the previous
- * interval's?
- */
- bool consecutive;
-
- int reg;
-
- struct list_head list;
-};
-
-/**
- * Linear scan.
- */
-struct linear_scan {
- struct linear_scan_live_interval *intervals;
- int max_vrf, num_vrfs;
-
- int num_regs;
-
- struct list_head active_list;
- int *free_regs;
- int num_free_regs;
-
- int *vrf_mapping;
-};
-
-/**
- * Return a chunk of registers to the free register pool.
- */
-static void
-linear_scan_free_regs(struct linear_scan *ls, int reg, int count)
-{
- unsigned i;
-
- for (i = 0; i < count; i++)
- ls->free_regs[ls->num_free_regs++] = reg + count - 1 - i;
-}
-
-static int
-linear_scan_compare_regs(const void *elem1, const void *elem2)
-{
- const int *reg1 = elem1;
- const int *reg2 = elem2;
-
- /* in reverse order */
- return (*reg2 - *reg1);
-}
-
-/**
- * Allocate a chunk of registers from the free register pool.
- */
-static int
-linear_scan_allocate_regs(struct linear_scan *ls, int count)
-{
- bool sorted = false;
- int reg;
-
- /* simple cases */
- if (count > ls->num_free_regs)
- return -1;
- else if (count == 1)
- return ls->free_regs[--ls->num_free_regs];
-
- /* TODO a free register pool */
- /* TODO reserve some regs for spilling */
- while (true) {
- bool found = false;
- int start;
-
- /*
- * find a chunk of registers that have consecutive register
- * numbers
- */
- for (start = ls->num_free_regs - 1; start >= count - 1; start--) {
- int i;
-
- for (i = 1; i < count; i++) {
- if (ls->free_regs[start - i] != ls->free_regs[start] + i)
- break;
- }
-
- if (i >= count) {
- found = true;
- break;
- }
- }
-
- if (found) {
- reg = ls->free_regs[start];
-
- if (start != ls->num_free_regs - 1) {
- start++;
- memmove(&ls->free_regs[start - count],
- &ls->free_regs[start],
- sizeof(*ls->free_regs) * (ls->num_free_regs - start));
- }
- ls->num_free_regs -= count;
- break;
- }
- else if (!sorted) {
- /* sort and retry */
- qsort(ls->free_regs, ls->num_free_regs, sizeof(*ls->free_regs),
- linear_scan_compare_regs);
- sorted = true;
- }
- else {
- /* failed */
- reg = -1;
- break;
- }
- }
-
- return reg;
-}
-
-/**
- * Add an interval to the active list.
- */
-static void
-linear_scan_add_active(struct linear_scan *ls,
- struct linear_scan_live_interval *interval)
-{
- struct linear_scan_live_interval *pos;
-
- /* keep the active list sorted by endpoints */
- LIST_FOR_EACH_ENTRY(pos, &ls->active_list, list) {
- if (pos->endpoint >= interval->endpoint)
- break;
- }
-
- list_addtail(&interval->list, &pos->list);
-}
-
-/**
- * Remove an interval from the active list.
- */
-static void
-linear_scan_remove_active(struct linear_scan *ls,
- struct linear_scan_live_interval *interval)
-{
- list_del(&interval->list);
-}
-
-/**
- * Remove intervals that are no longer active from the active list.
- */
-static void
-linear_scan_expire_active(struct linear_scan *ls, int pc)
-{
- struct linear_scan_live_interval *interval, *next;
-
- LIST_FOR_EACH_ENTRY_SAFE(interval, next, &ls->active_list, list) {
- /*
- * since we sort intervals on the active list by their endpoints, we
- * know that this and the rest of the intervals are still active.
- */
- if (interval->endpoint >= pc)
- break;
-
- linear_scan_remove_active(ls, interval);
-
- /* recycle the reg */
- linear_scan_free_regs(ls, interval->reg, 1);
- }
-}
-
-/**
- * Spill an interval.
- */
-static void
-linear_scan_spill(struct linear_scan *ls,
- struct linear_scan_live_interval *interval,
- bool is_active)
-{
- assert(!"no spilling support");
-}
-
-/**
- * Spill a range of intervals.
- */
-static void
-linear_scan_spill_range(struct linear_scan *ls, int first, int count)
-{
- unsigned i;
-
- for (i = 0; i < count; i++) {
- struct linear_scan_live_interval *interval = &ls->intervals[first + i];
-
- linear_scan_spill(ls, interval, false);
- }
-}
-
-/**
- * Perform linear scan to allocate registers for the intervals.
- */
-static bool
-linear_scan_run(struct linear_scan *ls)
-{
- int i;
-
- i = 0;
- while (i < ls->num_vrfs) {
- struct linear_scan_live_interval *first = &ls->intervals[i];
- int reg, count;
-
- /*
- * GEN6_OPCODE_SEND may write to multiple consecutive registers and we need to
- * support that
- */
- for (count = 1; i + count < ls->num_vrfs; count++) {
- const struct linear_scan_live_interval *interval =
- &ls->intervals[i + count];
-
- if (interval->startpoint != first->startpoint ||
- !interval->consecutive)
- break;
- }
-
- reg = linear_scan_allocate_regs(ls, count);
-
- /* expire intervals that are no longer active and try again */
- if (reg < 0) {
- linear_scan_expire_active(ls, first->startpoint);
- reg = linear_scan_allocate_regs(ls, count);
- }
-
- /* have to spill some intervals */
- if (reg < 0) {
- struct linear_scan_live_interval *last_active =
- container_of(ls->active_list.prev,
- (struct linear_scan_live_interval *) NULL, list);
-
- /* heuristically spill the interval that ends last */
- if (count > 1 || last_active->endpoint < first->endpoint) {
- linear_scan_spill_range(ls, i, count);
- i += count;
- continue;
- }
-
- /* make some room for the new interval */
- linear_scan_spill(ls, last_active, true);
- reg = linear_scan_allocate_regs(ls, count);
- if (reg < 0) {
- assert(!"failed to spill any register");
- return false;
- }
- }
-
- while (count--) {
- struct linear_scan_live_interval *interval = &ls->intervals[i++];
-
- interval->reg = reg++;
- linear_scan_add_active(ls, interval);
-
- ls->vrf_mapping[interval->vrf] = interval->reg;
-
- /*
- * this should and must be the case because of how we initialized the
- * intervals
- */
- assert(interval->vrf - first->vrf == interval->reg - first->reg);
- }
- }
-
- return true;
-}
-
-/**
- * Add a new interval.
- */
-static void
-linear_scan_add_live_interval(struct linear_scan *ls, int vrf, int pc)
-{
- if (ls->intervals[vrf].vrf)
- return;
-
- ls->intervals[vrf].vrf = vrf;
- ls->intervals[vrf].startpoint = pc;
-
- ls->num_vrfs++;
- if (vrf > ls->max_vrf)
- ls->max_vrf = vrf;
-}
-
-/**
- * Perform (oversimplified?) live variable analysis.
- */
-static void
-linear_scan_init_live_intervals(struct linear_scan *ls,
- struct toy_compiler *tc)
-{
- const struct toy_inst *inst;
- int pc, do_pc, while_pc;
-
- pc = 0;
- do_pc = -1;
- while_pc = -1;
-
- tc_head(tc);
- while ((inst = tc_next_no_skip(tc)) != NULL) {
- const int startpoint = (pc <= while_pc) ? do_pc : pc;
- const int endpoint = (pc <= while_pc) ? while_pc : pc;
- int vrf, i;
-
- /*
- * assume all registers used in this outermost loop are live through out
- * the whole loop
- */
- if (inst->marker) {
- if (pc > while_pc) {
- struct toy_inst *inst2;
- int loop_level = 1;
-
- assert(inst->opcode == TOY_OPCODE_DO);
- do_pc = pc;
- while_pc = pc + 1;
-
- /* find the matching GEN6_OPCODE_WHILE */
- LIST_FOR_EACH_ENTRY_FROM(inst2, tc->iter_next,
- &tc->instructions, list) {
- if (inst2->marker) {
- assert(inst->opcode == TOY_OPCODE_DO);
- loop_level++;
- continue;
- }
-
- if (inst2->opcode == GEN6_OPCODE_WHILE) {
- loop_level--;
- if (!loop_level)
- break;
- }
- while_pc++;
- }
- }
-
- continue;
- }
-
- if (inst->dst.file == TOY_FILE_VRF) {
- int num_dst;
-
- /* TODO this is a hack */
- if (inst->opcode == GEN6_OPCODE_SEND ||
- inst->opcode == GEN6_OPCODE_SENDC) {
- const uint32_t mdesc = inst->src[1].val32;
- int response_length = (mdesc >> 20) & 0x1f;
-
- num_dst = response_length;
- if (num_dst > 1 && inst->exec_size == GEN6_EXECSIZE_16)
- num_dst /= 2;
- }
- else {
- num_dst = 1;
- }
-
- vrf = inst->dst.val32 / TOY_REG_WIDTH;
-
- for (i = 0; i < num_dst; i++) {
- /* first use */
- if (!ls->intervals[vrf].vrf)
- linear_scan_add_live_interval(ls, vrf, startpoint);
-
- ls->intervals[vrf].endpoint = endpoint;
- ls->intervals[vrf].consecutive = (i > 0);
-
- vrf++;
- }
- }
-
- for (i = 0; i < ARRAY_SIZE(inst->src); i++) {
- if (inst->src[i].file != TOY_FILE_VRF)
- continue;
-
- vrf = inst->src[i].val32 / TOY_REG_WIDTH;
-
- /* first use */
- if (!ls->intervals[vrf].vrf)
- linear_scan_add_live_interval(ls, vrf, startpoint);
-
- ls->intervals[vrf].endpoint = endpoint;
- }
-
- pc++;
- }
-}
-
-/**
- * Clean up after performing linear scan.
- */
-static void
-linear_scan_cleanup(struct linear_scan *ls)
-{
- FREE(ls->vrf_mapping);
- FREE(ls->intervals);
- FREE(ls->free_regs);
-}
-
-static int
-linear_scan_compare_live_intervals(const void *elem1, const void *elem2)
-{
- const struct linear_scan_live_interval *interval1 = elem1;
- const struct linear_scan_live_interval *interval2 = elem2;
-
- /* make unused elements appear at the end */
- if (!interval1->vrf)
- return 1;
- else if (!interval2->vrf)
- return -1;
-
- /* sort by startpoints first, and then by vrf */
- if (interval1->startpoint != interval2->startpoint)
- return (interval1->startpoint - interval2->startpoint);
- else
- return (interval1->vrf - interval2->vrf);
-
-}
-
-/**
- * Prepare for linear scan.
- */
-static bool
-linear_scan_init(struct linear_scan *ls, int num_regs,
- struct toy_compiler *tc)
-{
- int num_intervals, i;
-
- memset(ls, 0, sizeof(*ls));
-
- /* this may be much larger than ls->num_vrfs... */
- num_intervals = tc->next_vrf;
- ls->intervals = CALLOC(num_intervals, sizeof(ls->intervals[0]));
- if (!ls->intervals)
- return false;
-
- linear_scan_init_live_intervals(ls, tc);
- /* sort intervals by startpoints */
- qsort(ls->intervals, num_intervals, sizeof(*ls->intervals),
- linear_scan_compare_live_intervals);
-
- ls->num_regs = num_regs;
- ls->num_free_regs = num_regs;
-
- ls->free_regs = MALLOC(ls->num_regs * sizeof(*ls->free_regs));
- if (!ls->free_regs) {
- FREE(ls->intervals);
- return false;
- }
-
- /* add in reverse order as we will allocate from the tail */
- for (i = 0; i < ls->num_regs; i++)
- ls->free_regs[i] = num_regs - i - 1;
-
- list_inithead(&ls->active_list);
-
- ls->vrf_mapping = CALLOC(ls->max_vrf + 1, sizeof(*ls->vrf_mapping));
- if (!ls->vrf_mapping) {
- FREE(ls->intervals);
- FREE(ls->free_regs);
- return false;
- }
-
- return true;
-}
-
-/**
- * Allocate registers with linear scan.
- */
-static void
-linear_scan_allocation(struct toy_compiler *tc,
- int start_grf, int end_grf,
- int num_grf_per_vrf)
-{
- const int num_grfs = end_grf - start_grf + 1;
- struct linear_scan ls;
- struct toy_inst *inst;
-
- if (!linear_scan_init(&ls, num_grfs / num_grf_per_vrf, tc))
- return;
-
- if (!linear_scan_run(&ls)) {
- tc_fail(tc, "failed to allocate registers");
- return;
- }
-
-
- tc_head(tc);
- while ((inst = tc_next(tc)) != NULL) {
- int i;
-
- if (inst->dst.file == TOY_FILE_VRF) {
- const uint32_t val32 = inst->dst.val32;
- int reg = val32 / TOY_REG_WIDTH;
- int subreg = val32 % TOY_REG_WIDTH;
-
- /* map to GRF */
- reg = ls.vrf_mapping[reg] * num_grf_per_vrf + start_grf;
-
- inst->dst.file = TOY_FILE_GRF;
- inst->dst.val32 = reg * TOY_REG_WIDTH + subreg;
- }
-
- for (i = 0; i < ARRAY_SIZE(inst->src); i++) {
- const uint32_t val32 = inst->src[i].val32;
- int reg, subreg;
-
- if (inst->src[i].file != TOY_FILE_VRF)
- continue;
-
- reg = val32 / TOY_REG_WIDTH;
- subreg = val32 % TOY_REG_WIDTH;
-
- /* map to GRF */
- reg = ls.vrf_mapping[reg] * num_grf_per_vrf + start_grf;
-
- inst->src[i].file = TOY_FILE_GRF;
- inst->src[i].val32 = reg * TOY_REG_WIDTH + subreg;
- }
- }
-
- linear_scan_cleanup(&ls);
-}
-
-/**
- * Trivially allocate registers.
- */
-static void
-trivial_allocation(struct toy_compiler *tc,
- int start_grf, int end_grf,
- int num_grf_per_vrf)
-{
- struct toy_inst *inst;
- int max_grf = -1;
-
- tc_head(tc);
- while ((inst = tc_next(tc)) != NULL) {
- int i;
-
- if (inst->dst.file == TOY_FILE_VRF) {
- const uint32_t val32 = inst->dst.val32;
- int reg = val32 / TOY_REG_WIDTH;
- int subreg = val32 % TOY_REG_WIDTH;
-
- reg = reg * num_grf_per_vrf + start_grf - 1;
-
- inst->dst.file = TOY_FILE_GRF;
- inst->dst.val32 = reg * TOY_REG_WIDTH + subreg;
-
- if (reg > max_grf)
- max_grf = reg;
- }
-
- for (i = 0; i < ARRAY_SIZE(inst->src); i++) {
- const uint32_t val32 = inst->src[i].val32;
- int reg, subreg;
-
- if (inst->src[i].file != TOY_FILE_VRF)
- continue;
-
- reg = val32 / TOY_REG_WIDTH;
- subreg = val32 % TOY_REG_WIDTH;
-
- reg = reg * num_grf_per_vrf + start_grf - 1;
-
- inst->src[i].file = TOY_FILE_GRF;
- inst->src[i].val32 = reg * TOY_REG_WIDTH + subreg;
-
- if (reg > max_grf)
- max_grf = reg;
- }
- }
-
- if (max_grf + num_grf_per_vrf - 1 > end_grf)
- tc_fail(tc, "failed to allocate registers");
-}
-
-/**
- * Allocate GRF registers to VRF registers.
- */
-void
-toy_compiler_allocate_registers(struct toy_compiler *tc,
- int start_grf, int end_grf,
- int num_grf_per_vrf)
-{
- if (true)
- linear_scan_allocation(tc, start_grf, end_grf, num_grf_per_vrf);
- else
- trivial_allocation(tc, start_grf, end_grf, num_grf_per_vrf);
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "toy_compiler.h"
-#include "toy_tgsi.h"
-#include "toy_optimize.h"
-
-/**
- * This just eliminates instructions with null dst so far.
- */
-static void
-eliminate_dead_code(struct toy_compiler *tc)
-{
- struct toy_inst *inst;
-
- tc_head(tc);
- while ((inst = tc_next(tc)) != NULL) {
- switch (inst->opcode) {
- case GEN6_OPCODE_IF:
- case GEN6_OPCODE_ELSE:
- case GEN6_OPCODE_ENDIF:
- case GEN6_OPCODE_WHILE:
- case GEN6_OPCODE_BREAK:
- case GEN6_OPCODE_CONT:
- case GEN6_OPCODE_SEND:
- case GEN6_OPCODE_SENDC:
- case GEN6_OPCODE_NOP:
- /* never eliminated */
- break;
- default:
- if (tdst_is_null(inst->dst) || !inst->dst.writemask) {
- /* math is always GEN6_COND_NORMAL */
- if ((inst->opcode == GEN6_OPCODE_MATH ||
- inst->cond_modifier == GEN6_COND_NONE) &&
- !inst->acc_wr_ctrl)
- tc_discard_inst(tc, inst);
- }
- break;
- }
- }
-}
-
-void
-toy_compiler_optimize(struct toy_compiler *tc)
-{
- eliminate_dead_code(tc);
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef TOY_OPTIMIZE_H
-#define TOY_OPTIMIZE_H
-
-#include "toy_compiler.h"
-
-void
-toy_compiler_optimize(struct toy_compiler *tc);
-
-#endif /* TOY_OPTIMIZE_H */
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "tgsi/tgsi_parse.h"
-#include "tgsi/tgsi_info.h"
-#include "tgsi/tgsi_strings.h"
-#include "util/u_hash_table.h"
-#include "toy_helpers.h"
-#include "toy_tgsi.h"
-
-/* map TGSI opcode to GEN opcode 1-to-1 */
-static const struct {
- int opcode;
- int num_dst;
- int num_src;
-} aos_simple_opcode_map[TGSI_OPCODE_LAST] = {
- [TGSI_OPCODE_ARL] = { GEN6_OPCODE_RNDD, 1, 1 },
- [TGSI_OPCODE_MOV] = { GEN6_OPCODE_MOV, 1, 1 },
- [TGSI_OPCODE_RCP] = { TOY_OPCODE_INV, 1, 1 },
- [TGSI_OPCODE_RSQ] = { TOY_OPCODE_RSQ, 1, 1 },
- [TGSI_OPCODE_MUL] = { GEN6_OPCODE_MUL, 1, 2 },
- [TGSI_OPCODE_ADD] = { GEN6_OPCODE_ADD, 1, 2 },
- [TGSI_OPCODE_DP3] = { GEN6_OPCODE_DP3, 1, 2 },
- [TGSI_OPCODE_DP4] = { GEN6_OPCODE_DP4, 1, 2 },
- [TGSI_OPCODE_MIN] = { GEN6_OPCODE_SEL, 1, 2 },
- [TGSI_OPCODE_MAX] = { GEN6_OPCODE_SEL, 1, 2 },
- /* a later pass will move src[2] to accumulator */
- [TGSI_OPCODE_MAD] = { GEN6_OPCODE_MAC, 1, 3 },
- [TGSI_OPCODE_SQRT] = { TOY_OPCODE_SQRT, 1, 1 },
- [TGSI_OPCODE_FRC] = { GEN6_OPCODE_FRC, 1, 1 },
- [TGSI_OPCODE_FLR] = { GEN6_OPCODE_RNDD, 1, 1 },
- [TGSI_OPCODE_ROUND] = { GEN6_OPCODE_RNDE, 1, 1 },
- [TGSI_OPCODE_EX2] = { TOY_OPCODE_EXP, 1, 1 },
- [TGSI_OPCODE_LG2] = { TOY_OPCODE_LOG, 1, 1 },
- [TGSI_OPCODE_POW] = { TOY_OPCODE_POW, 1, 2 },
- [TGSI_OPCODE_DPH] = { GEN6_OPCODE_DPH, 1, 2 },
- [TGSI_OPCODE_COS] = { TOY_OPCODE_COS, 1, 1 },
- [TGSI_OPCODE_KILL] = { TOY_OPCODE_KIL, 0, 0 },
- [TGSI_OPCODE_SIN] = { TOY_OPCODE_SIN, 1, 1 },
- [TGSI_OPCODE_ARR] = { GEN6_OPCODE_RNDZ, 1, 1 },
- [TGSI_OPCODE_DP2] = { GEN6_OPCODE_DP2, 1, 2 },
- [TGSI_OPCODE_IF] = { GEN6_OPCODE_IF, 0, 1 },
- [TGSI_OPCODE_UIF] = { GEN6_OPCODE_IF, 0, 1 },
- [TGSI_OPCODE_ELSE] = { GEN6_OPCODE_ELSE, 0, 0 },
- [TGSI_OPCODE_ENDIF] = { GEN6_OPCODE_ENDIF, 0, 0 },
- [TGSI_OPCODE_I2F] = { GEN6_OPCODE_MOV, 1, 1 },
- [TGSI_OPCODE_NOT] = { GEN6_OPCODE_NOT, 1, 1 },
- [TGSI_OPCODE_TRUNC] = { GEN6_OPCODE_RNDZ, 1, 1 },
- [TGSI_OPCODE_SHL] = { GEN6_OPCODE_SHL, 1, 2 },
- [TGSI_OPCODE_AND] = { GEN6_OPCODE_AND, 1, 2 },
- [TGSI_OPCODE_OR] = { GEN6_OPCODE_OR, 1, 2 },
- [TGSI_OPCODE_MOD] = { TOY_OPCODE_INT_DIV_REMAINDER, 1, 2 },
- [TGSI_OPCODE_XOR] = { GEN6_OPCODE_XOR, 1, 2 },
- [TGSI_OPCODE_EMIT] = { TOY_OPCODE_EMIT, 0, 0 },
- [TGSI_OPCODE_ENDPRIM] = { TOY_OPCODE_ENDPRIM, 0, 0 },
- [TGSI_OPCODE_NOP] = { GEN6_OPCODE_NOP, 0, 0 },
- [TGSI_OPCODE_KILL_IF] = { TOY_OPCODE_KIL, 0, 1 },
- [TGSI_OPCODE_END] = { GEN6_OPCODE_NOP, 0, 0 },
- [TGSI_OPCODE_F2I] = { GEN6_OPCODE_MOV, 1, 1 },
- [TGSI_OPCODE_IDIV] = { TOY_OPCODE_INT_DIV_QUOTIENT, 1, 2 },
- [TGSI_OPCODE_IMAX] = { GEN6_OPCODE_SEL, 1, 2 },
- [TGSI_OPCODE_IMIN] = { GEN6_OPCODE_SEL, 1, 2 },
- [TGSI_OPCODE_INEG] = { GEN6_OPCODE_MOV, 1, 1 },
- [TGSI_OPCODE_ISHR] = { GEN6_OPCODE_ASR, 1, 2 },
- [TGSI_OPCODE_F2U] = { GEN6_OPCODE_MOV, 1, 1 },
- [TGSI_OPCODE_U2F] = { GEN6_OPCODE_MOV, 1, 1 },
- [TGSI_OPCODE_UADD] = { GEN6_OPCODE_ADD, 1, 2 },
- [TGSI_OPCODE_UDIV] = { TOY_OPCODE_INT_DIV_QUOTIENT, 1, 2 },
- /* a later pass will move src[2] to accumulator */
- [TGSI_OPCODE_UMAD] = { GEN6_OPCODE_MAC, 1, 3 },
- [TGSI_OPCODE_UMAX] = { GEN6_OPCODE_SEL, 1, 2 },
- [TGSI_OPCODE_UMIN] = { GEN6_OPCODE_SEL, 1, 2 },
- [TGSI_OPCODE_UMOD] = { TOY_OPCODE_INT_DIV_REMAINDER, 1, 2 },
- [TGSI_OPCODE_UMUL] = { GEN6_OPCODE_MUL, 1, 2 },
- [TGSI_OPCODE_USHR] = { GEN6_OPCODE_SHR, 1, 2 },
- [TGSI_OPCODE_UARL] = { GEN6_OPCODE_MOV, 1, 1 },
- [TGSI_OPCODE_IABS] = { GEN6_OPCODE_MOV, 1, 1 },
-};
-
-static void
-aos_simple(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- struct toy_inst *inst;
- int opcode;
- int cond_modifier = GEN6_COND_NONE;
- int num_dst = tgsi_inst->Instruction.NumDstRegs;
- int num_src = tgsi_inst->Instruction.NumSrcRegs;
- int i;
-
- opcode = aos_simple_opcode_map[tgsi_inst->Instruction.Opcode].opcode;
- assert(num_dst == aos_simple_opcode_map[tgsi_inst->Instruction.Opcode].num_dst);
- assert(num_src == aos_simple_opcode_map[tgsi_inst->Instruction.Opcode].num_src);
- if (!opcode) {
- assert(!"invalid aos_simple() call");
- return;
- }
-
- /* no need to emit nop */
- if (opcode == GEN6_OPCODE_NOP)
- return;
-
- inst = tc_add(tc);
- if (!inst)
- return;
-
- inst->opcode = opcode;
-
- switch (tgsi_inst->Instruction.Opcode) {
- case TGSI_OPCODE_MIN:
- case TGSI_OPCODE_IMIN:
- case TGSI_OPCODE_UMIN:
- cond_modifier = GEN6_COND_L;
- break;
- case TGSI_OPCODE_MAX:
- case TGSI_OPCODE_IMAX:
- case TGSI_OPCODE_UMAX:
- cond_modifier = GEN6_COND_GE;
- break;
- case TGSI_OPCODE_IABS:
- src[0] = tsrc_absolute(src[0]);
- break;
- case TGSI_OPCODE_IF:
- cond_modifier = GEN6_COND_NZ;
- num_src = 2;
- assert(src[0].type == TOY_TYPE_F);
- src[0] = tsrc_swizzle1(src[0], TOY_SWIZZLE_X);
- src[1] = tsrc_imm_f(0.0f);
- break;
- case TGSI_OPCODE_UIF:
- cond_modifier = GEN6_COND_NZ;
- num_src = 2;
- assert(src[0].type == TOY_TYPE_UD);
- src[0] = tsrc_swizzle1(src[0], TOY_SWIZZLE_X);
- src[1] = tsrc_imm_d(0);
- break;
- case TGSI_OPCODE_INEG:
- src[0] = tsrc_negate(src[0]);
- break;
- case TGSI_OPCODE_RCP:
- case TGSI_OPCODE_RSQ:
- case TGSI_OPCODE_EX2:
- case TGSI_OPCODE_LG2:
- case TGSI_OPCODE_COS:
- case TGSI_OPCODE_SIN:
- src[0] = tsrc_swizzle1(src[0], TOY_SWIZZLE_X);
- break;
- case TGSI_OPCODE_POW:
- src[0] = tsrc_swizzle1(src[0], TOY_SWIZZLE_X);
- src[1] = tsrc_swizzle1(src[1], TOY_SWIZZLE_X);
- break;
- }
-
- inst->cond_modifier = cond_modifier;
-
- if (num_dst) {
- assert(num_dst == 1);
- inst->dst = dst[0];
- }
-
- assert(num_src <= ARRAY_SIZE(inst->src));
- for (i = 0; i < num_src; i++)
- inst->src[i] = src[i];
-}
-
-static void
-aos_set_on_cond(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- struct toy_inst *inst;
- int cond;
- struct toy_src zero, one;
-
- switch (tgsi_inst->Instruction.Opcode) {
- case TGSI_OPCODE_SLT:
- case TGSI_OPCODE_ISLT:
- case TGSI_OPCODE_USLT:
- case TGSI_OPCODE_FSLT:
- cond = GEN6_COND_L;
- break;
- case TGSI_OPCODE_SGE:
- case TGSI_OPCODE_ISGE:
- case TGSI_OPCODE_USGE:
- case TGSI_OPCODE_FSGE:
- cond = GEN6_COND_GE;
- break;
- case TGSI_OPCODE_SEQ:
- case TGSI_OPCODE_USEQ:
- case TGSI_OPCODE_FSEQ:
- cond = GEN6_COND_Z;
- break;
- case TGSI_OPCODE_SGT:
- cond = GEN6_COND_G;
- break;
- case TGSI_OPCODE_SLE:
- cond = GEN6_COND_LE;
- break;
- case TGSI_OPCODE_SNE:
- case TGSI_OPCODE_USNE:
- case TGSI_OPCODE_FSNE:
- cond = GEN6_COND_NZ;
- break;
- default:
- assert(!"invalid aos_set_on_cond() call");
- return;
- }
-
- /* note that for integer versions, all bits are set */
- switch (dst[0].type) {
- case TOY_TYPE_F:
- default:
- zero = tsrc_imm_f(0.0f);
- one = tsrc_imm_f(1.0f);
- break;
- case TOY_TYPE_D:
- zero = tsrc_imm_d(0);
- one = tsrc_imm_d(-1);
- break;
- case TOY_TYPE_UD:
- zero = tsrc_imm_ud(0);
- one = tsrc_imm_ud(~0);
- break;
- }
-
- tc_MOV(tc, dst[0], zero);
- tc_CMP(tc, tdst_null(), src[0], src[1], cond);
- inst = tc_MOV(tc, dst[0], one);
- inst->pred_ctrl = GEN6_PREDCTRL_NORMAL;
-}
-
-static void
-aos_compare(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- struct toy_inst *inst;
- struct toy_src zero;
-
- switch (tgsi_inst->Instruction.Opcode) {
- case TGSI_OPCODE_CMP:
- zero = tsrc_imm_f(0.0f);
- break;
- case TGSI_OPCODE_UCMP:
- zero = tsrc_imm_ud(0);
- break;
- default:
- assert(!"invalid aos_compare() call");
- return;
- }
-
- tc_CMP(tc, tdst_null(), src[0], zero, GEN6_COND_L);
- inst = tc_SEL(tc, dst[0], src[1], src[2], GEN6_COND_NONE);
- inst->pred_ctrl = GEN6_PREDCTRL_NORMAL;
-}
-
-static void
-aos_set_sign(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- struct toy_inst *inst;
- struct toy_src zero, one, neg_one;
-
- switch (tgsi_inst->Instruction.Opcode) {
- case TGSI_OPCODE_SSG:
- zero = tsrc_imm_f(0.0f);
- one = tsrc_imm_f(1.0f);
- neg_one = tsrc_imm_f(-1.0f);
- break;
- case TGSI_OPCODE_ISSG:
- zero = tsrc_imm_d(0);
- one = tsrc_imm_d(1);
- neg_one = tsrc_imm_d(-1);
- break;
- default:
- assert(!"invalid aos_set_sign() call");
- return;
- }
-
- tc_MOV(tc, dst[0], zero);
-
- tc_CMP(tc, tdst_null(), src[0], zero, GEN6_COND_G);
- inst = tc_MOV(tc, dst[0], one);
- inst->pred_ctrl = GEN6_PREDCTRL_NORMAL;
-
- tc_CMP(tc, tdst_null(), src[0], zero, GEN6_COND_L);
- inst = tc_MOV(tc, dst[0], neg_one);
- inst->pred_ctrl = GEN6_PREDCTRL_NORMAL;
-}
-
-static void
-aos_tex(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- struct toy_inst *inst;
- enum toy_opcode opcode;
- int i;
-
- switch (tgsi_inst->Instruction.Opcode) {
- case TGSI_OPCODE_TEX:
- opcode = TOY_OPCODE_TGSI_TEX;
- break;
- case TGSI_OPCODE_TXD:
- opcode = TOY_OPCODE_TGSI_TXD;
- break;
- case TGSI_OPCODE_TXP:
- opcode = TOY_OPCODE_TGSI_TXP;
- break;
- case TGSI_OPCODE_TXB:
- opcode = TOY_OPCODE_TGSI_TXB;
- break;
- case TGSI_OPCODE_TXL:
- opcode = TOY_OPCODE_TGSI_TXL;
- break;
- case TGSI_OPCODE_TXF:
- opcode = TOY_OPCODE_TGSI_TXF;
- break;
- case TGSI_OPCODE_TXQ:
- opcode = TOY_OPCODE_TGSI_TXQ;
- break;
- case TGSI_OPCODE_TXQ_LZ:
- opcode = TOY_OPCODE_TGSI_TXQ_LZ;
- break;
- case TGSI_OPCODE_TEX2:
- opcode = TOY_OPCODE_TGSI_TEX2;
- break;
- case TGSI_OPCODE_TXB2:
- opcode = TOY_OPCODE_TGSI_TXB2;
- break;
- case TGSI_OPCODE_TXL2:
- opcode = TOY_OPCODE_TGSI_TXL2;
- break;
- default:
- assert(!"unsupported texturing opcode");
- return;
- break;
- }
-
- assert(tgsi_inst->Instruction.Texture);
-
- inst = tc_add(tc);
- inst->opcode = opcode;
- inst->tex.target = tgsi_inst->Texture.Texture;
-
- assert(tgsi_inst->Instruction.NumSrcRegs <= ARRAY_SIZE(inst->src));
- assert(tgsi_inst->Instruction.NumDstRegs == 1);
-
- inst->dst = dst[0];
- for (i = 0; i < tgsi_inst->Instruction.NumSrcRegs; i++)
- inst->src[i] = src[i];
-
- for (i = 0; i < tgsi_inst->Texture.NumOffsets; i++)
- tc_fail(tc, "texelFetchOffset unsupported");
-}
-
-static void
-aos_sample(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- struct toy_inst *inst;
- enum toy_opcode opcode;
- int i;
-
- assert(!"sampling untested");
-
- switch (tgsi_inst->Instruction.Opcode) {
- case TGSI_OPCODE_SAMPLE:
- opcode = TOY_OPCODE_TGSI_SAMPLE;
- break;
- case TGSI_OPCODE_SAMPLE_I:
- opcode = TOY_OPCODE_TGSI_SAMPLE_I;
- break;
- case TGSI_OPCODE_SAMPLE_I_MS:
- opcode = TOY_OPCODE_TGSI_SAMPLE_I_MS;
- break;
- case TGSI_OPCODE_SAMPLE_B:
- opcode = TOY_OPCODE_TGSI_SAMPLE_B;
- break;
- case TGSI_OPCODE_SAMPLE_C:
- opcode = TOY_OPCODE_TGSI_SAMPLE_C;
- break;
- case TGSI_OPCODE_SAMPLE_C_LZ:
- opcode = TOY_OPCODE_TGSI_SAMPLE_C_LZ;
- break;
- case TGSI_OPCODE_SAMPLE_D:
- opcode = TOY_OPCODE_TGSI_SAMPLE_D;
- break;
- case TGSI_OPCODE_SAMPLE_L:
- opcode = TOY_OPCODE_TGSI_SAMPLE_L;
- break;
- case TGSI_OPCODE_GATHER4:
- opcode = TOY_OPCODE_TGSI_GATHER4;
- break;
- case TGSI_OPCODE_SVIEWINFO:
- opcode = TOY_OPCODE_TGSI_SVIEWINFO;
- break;
- case TGSI_OPCODE_SAMPLE_POS:
- opcode = TOY_OPCODE_TGSI_SAMPLE_POS;
- break;
- case TGSI_OPCODE_SAMPLE_INFO:
- opcode = TOY_OPCODE_TGSI_SAMPLE_INFO;
- break;
- default:
- assert(!"unsupported sampling opcode");
- return;
- break;
- }
-
- inst = tc_add(tc);
- inst->opcode = opcode;
-
- assert(tgsi_inst->Instruction.NumSrcRegs <= ARRAY_SIZE(inst->src));
- assert(tgsi_inst->Instruction.NumDstRegs == 1);
-
- inst->dst = dst[0];
- for (i = 0; i < tgsi_inst->Instruction.NumSrcRegs; i++)
- inst->src[i] = src[i];
-}
-
-static void
-aos_LIT(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- struct toy_inst *inst;
-
- tc_MOV(tc, tdst_writemask(dst[0], TOY_WRITEMASK_XW), tsrc_imm_f(1.0f));
-
- if (!(dst[0].writemask & TOY_WRITEMASK_YZ))
- return;
-
- tc_MOV(tc, tdst_writemask(dst[0], TOY_WRITEMASK_YZ), tsrc_imm_f(0.0f));
-
- tc_CMP(tc, tdst_null(),
- tsrc_swizzle1(src[0], TOY_SWIZZLE_X),
- tsrc_imm_f(0.0f),
- GEN6_COND_G);
-
- inst = tc_MOV(tc,
- tdst_writemask(dst[0], TOY_WRITEMASK_Y),
- tsrc_swizzle1(src[0], TOY_SWIZZLE_X));
- inst->pred_ctrl = GEN6_PREDCTRL_NORMAL;
-
- /* clamp W to (-128, 128)? */
- inst = tc_POW(tc,
- tdst_writemask(dst[0], TOY_WRITEMASK_Z),
- tsrc_swizzle1(src[0], TOY_SWIZZLE_Y),
- tsrc_swizzle1(src[0], TOY_SWIZZLE_W));
- inst->pred_ctrl = GEN6_PREDCTRL_NORMAL;
-}
-
-static void
-aos_EXP(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- struct toy_src src0 = tsrc_swizzle1(src[0], TOY_SWIZZLE_X);
-
- if (dst[0].writemask & TOY_WRITEMASK_X) {
- struct toy_dst tmp =
- tdst_d(tdst_writemask(tc_alloc_tmp(tc), TOY_WRITEMASK_X));
-
- tc_RNDD(tc, tmp, src0);
-
- /* construct the floating point number manually */
- tc_ADD(tc, tmp, tsrc_from(tmp), tsrc_imm_d(127));
- tc_SHL(tc, tdst_d(tdst_writemask(dst[0], TOY_WRITEMASK_X)),
- tsrc_from(tmp), tsrc_imm_d(23));
- }
-
- tc_FRC(tc, tdst_writemask(dst[0], TOY_WRITEMASK_Y), src0);
- tc_EXP(tc, tdst_writemask(dst[0], TOY_WRITEMASK_Z), src0);
- tc_MOV(tc, tdst_writemask(dst[0], TOY_WRITEMASK_W), tsrc_imm_f(1.0f));
-}
-
-static void
-aos_LOG(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- struct toy_src src0 = tsrc_swizzle1(src[0], TOY_SWIZZLE_X);
-
- if (dst[0].writemask & TOY_WRITEMASK_XY) {
- struct toy_dst tmp;
-
- tmp = tdst_d(tdst_writemask(tc_alloc_tmp(tc), TOY_WRITEMASK_X));
-
- /* exponent */
- tc_SHR(tc, tmp, tsrc_absolute(tsrc_d(src0)), tsrc_imm_d(23));
- tc_ADD(tc, tdst_writemask(dst[0], TOY_WRITEMASK_X),
- tsrc_from(tmp), tsrc_imm_d(-127));
-
- /* mantissa */
- tc_AND(tc, tmp, tsrc_d(src0), tsrc_imm_d((1 << 23) - 1));
- tc_OR(tc, tdst_writemask(tdst_d(dst[0]), TOY_WRITEMASK_Y),
- tsrc_from(tmp), tsrc_imm_d(127 << 23));
- }
-
- tc_LOG(tc, tdst_writemask(dst[0], TOY_WRITEMASK_Z), src0);
- tc_MOV(tc, tdst_writemask(dst[0], TOY_WRITEMASK_W), tsrc_imm_f(1.0f));
-}
-
-static void
-aos_DST(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- tc_MOV(tc, tdst_writemask(dst[0], TOY_WRITEMASK_X), tsrc_imm_f(1.0f));
- tc_MUL(tc, tdst_writemask(dst[0], TOY_WRITEMASK_Y), src[0], src[1]);
- tc_MOV(tc, tdst_writemask(dst[0], TOY_WRITEMASK_Z), src[0]);
- tc_MOV(tc, tdst_writemask(dst[0], TOY_WRITEMASK_W), src[1]);
-}
-
-static void
-aos_LRP(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- struct toy_dst tmp = tc_alloc_tmp(tc);
-
- tc_ADD(tc, tmp, tsrc_negate(src[0]), tsrc_imm_f(1.0f));
- tc_MUL(tc, tmp, tsrc_from(tmp), src[2]);
- tc_MAC(tc, dst[0], src[0], src[1], tsrc_from(tmp));
-}
-
-static void
-aos_DP2A(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- struct toy_dst tmp = tc_alloc_tmp(tc);
-
- assert(!"DP2A untested");
-
- tc_DP2(tc, tmp, src[0], src[1]);
- tc_ADD(tc, dst[0], tsrc_swizzle1(tsrc_from(tmp), TOY_SWIZZLE_X), src[2]);
-}
-
-static void
-aos_CLAMP(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- assert(!"CLAMP untested");
-
- tc_SEL(tc, dst[0], src[0], src[1], GEN6_COND_GE);
- tc_SEL(tc, dst[0], src[2], tsrc_from(dst[0]), GEN6_COND_L);
-}
-
-static void
-aos_XPD(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- struct toy_dst tmp = tc_alloc_tmp(tc);
-
- tc_MUL(tc, tdst_writemask(tmp, TOY_WRITEMASK_XYZ),
- tsrc_swizzle(src[0], TOY_SWIZZLE_Z, TOY_SWIZZLE_X,
- TOY_SWIZZLE_Y, TOY_SWIZZLE_W),
- tsrc_swizzle(src[1], TOY_SWIZZLE_Y, TOY_SWIZZLE_Z,
- TOY_SWIZZLE_X, TOY_SWIZZLE_W));
-
- tc_MAC(tc, tdst_writemask(dst[0], TOY_WRITEMASK_XYZ),
- tsrc_swizzle(src[0], TOY_SWIZZLE_Y, TOY_SWIZZLE_Z,
- TOY_SWIZZLE_X, TOY_SWIZZLE_W),
- tsrc_swizzle(src[1], TOY_SWIZZLE_Z, TOY_SWIZZLE_X,
- TOY_SWIZZLE_Y, TOY_SWIZZLE_W),
- tsrc_negate(tsrc_from(tmp)));
-
- tc_MOV(tc, tdst_writemask(dst[0], TOY_WRITEMASK_W),
- tsrc_imm_f(1.0f));
-}
-
-static void
-aos_PK2H(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- const struct toy_src h1 = tsrc_ud(tsrc_swizzle1(src[0], TOY_SWIZZLE_X));
- const struct toy_src h2 = tsrc_ud(tsrc_swizzle1(src[0], TOY_SWIZZLE_Y));
- struct toy_dst tmp = tdst_ud(tc_alloc_tmp(tc));
-
- assert(!"PK2H untested");
-
- tc_SHL(tc, tmp, h2, tsrc_imm_ud(16));
- tc_OR(tc, tdst_ud(dst[0]), h1, tsrc_from(tmp));
-}
-
-static void
-aos_UP2H(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- assert(!"UP2H untested");
-
- tc_AND(tc, tdst_writemask(tdst_ud(dst[0]), TOY_WRITEMASK_XZ),
- tsrc_ud(src[0]), tsrc_imm_ud(0xffff));
- tc_SHR(tc, tdst_writemask(tdst_ud(dst[0]), TOY_WRITEMASK_YW),
- tsrc_ud(src[0]), tsrc_imm_ud(16));
-}
-
-static void
-aos_SCS(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- assert(!"SCS untested");
-
- tc_add1(tc, TOY_OPCODE_COS,
- tdst_writemask(dst[0], TOY_WRITEMASK_X), src[0]);
-
- tc_add1(tc, TOY_OPCODE_SIN,
- tdst_writemask(dst[0], TOY_WRITEMASK_Y), src[0]);
-
- tc_MOV(tc, tdst_writemask(dst[0], TOY_WRITEMASK_Z), tsrc_imm_f(0.0f));
- tc_MOV(tc, tdst_writemask(dst[0], TOY_WRITEMASK_W), tsrc_imm_f(1.0f));
-}
-
-static void
-aos_DIV(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- struct toy_dst tmp = tc_alloc_tmp(tc);
-
- assert(!"DIV untested");
-
- tc_INV(tc, tmp, src[1]);
- tc_MUL(tc, dst[0], src[0], tsrc_from(tmp));
-}
-
-static void
-aos_BRK(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- tc_add0(tc, GEN6_OPCODE_BREAK);
-}
-
-static void
-aos_CEIL(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- struct toy_dst tmp = tc_alloc_tmp(tc);
-
- tc_RNDD(tc, tmp, tsrc_negate(src[0]));
- tc_MOV(tc, dst[0], tsrc_negate(tsrc_from(tmp)));
-}
-
-static void
-aos_SAD(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- struct toy_dst tmp = tc_alloc_tmp(tc);
-
- assert(!"SAD untested");
-
- tc_ADD(tc, tmp, src[0], tsrc_negate(src[1]));
- tc_ADD(tc, dst[0], tsrc_absolute(tsrc_from(tmp)), src[2]);
-}
-
-static void
-aos_CONT(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- tc_add0(tc, GEN6_OPCODE_CONT);
-}
-
-static void
-aos_BGNLOOP(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- struct toy_inst *inst;
-
- inst = tc_add0(tc, TOY_OPCODE_DO);
- /* this is just a marker */
- inst->marker = true;
-}
-
-static void
-aos_ENDLOOP(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- tc_add0(tc, GEN6_OPCODE_WHILE);
-}
-
-static void
-aos_unsupported(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src)
-{
- const char *name = tgsi_get_opcode_name(tgsi_inst->Instruction.Opcode);
-
- ilo_warn("unsupported TGSI opcode: TGSI_OPCODE_%s\n", name);
-
- tc_fail(tc, "unsupported TGSI instruction");
-}
-
-static const toy_tgsi_translate aos_translate_table[TGSI_OPCODE_LAST] = {
- [TGSI_OPCODE_ARL] = aos_simple,
- [TGSI_OPCODE_MOV] = aos_simple,
- [TGSI_OPCODE_LIT] = aos_LIT,
- [TGSI_OPCODE_RCP] = aos_simple,
- [TGSI_OPCODE_RSQ] = aos_simple,
- [TGSI_OPCODE_EXP] = aos_EXP,
- [TGSI_OPCODE_LOG] = aos_LOG,
- [TGSI_OPCODE_MUL] = aos_simple,
- [TGSI_OPCODE_ADD] = aos_simple,
- [TGSI_OPCODE_DP3] = aos_simple,
- [TGSI_OPCODE_DP4] = aos_simple,
- [TGSI_OPCODE_DST] = aos_DST,
- [TGSI_OPCODE_MIN] = aos_simple,
- [TGSI_OPCODE_MAX] = aos_simple,
- [TGSI_OPCODE_SLT] = aos_set_on_cond,
- [TGSI_OPCODE_SGE] = aos_set_on_cond,
- [TGSI_OPCODE_MAD] = aos_simple,
- [TGSI_OPCODE_LRP] = aos_LRP,
- [TGSI_OPCODE_SQRT] = aos_simple,
- [TGSI_OPCODE_DP2A] = aos_DP2A,
- [TGSI_OPCODE_FRC] = aos_simple,
- [TGSI_OPCODE_CLAMP] = aos_CLAMP,
- [TGSI_OPCODE_FLR] = aos_simple,
- [TGSI_OPCODE_ROUND] = aos_simple,
- [TGSI_OPCODE_EX2] = aos_simple,
- [TGSI_OPCODE_LG2] = aos_simple,
- [TGSI_OPCODE_POW] = aos_simple,
- [TGSI_OPCODE_XPD] = aos_XPD,
- [TGSI_OPCODE_DPH] = aos_simple,
- [TGSI_OPCODE_COS] = aos_simple,
- [TGSI_OPCODE_DDX] = aos_unsupported,
- [TGSI_OPCODE_DDY] = aos_unsupported,
- [TGSI_OPCODE_KILL] = aos_simple,
- [TGSI_OPCODE_PK2H] = aos_PK2H,
- [TGSI_OPCODE_PK2US] = aos_unsupported,
- [TGSI_OPCODE_PK4B] = aos_unsupported,
- [TGSI_OPCODE_PK4UB] = aos_unsupported,
- [TGSI_OPCODE_SEQ] = aos_set_on_cond,
- [TGSI_OPCODE_SGT] = aos_set_on_cond,
- [TGSI_OPCODE_SIN] = aos_simple,
- [TGSI_OPCODE_SLE] = aos_set_on_cond,
- [TGSI_OPCODE_SNE] = aos_set_on_cond,
- [TGSI_OPCODE_TEX] = aos_tex,
- [TGSI_OPCODE_TXD] = aos_tex,
- [TGSI_OPCODE_TXP] = aos_tex,
- [TGSI_OPCODE_UP2H] = aos_UP2H,
- [TGSI_OPCODE_UP2US] = aos_unsupported,
- [TGSI_OPCODE_UP4B] = aos_unsupported,
- [TGSI_OPCODE_UP4UB] = aos_unsupported,
- [TGSI_OPCODE_ARR] = aos_simple,
- [TGSI_OPCODE_CAL] = aos_unsupported,
- [TGSI_OPCODE_RET] = aos_unsupported,
- [TGSI_OPCODE_SSG] = aos_set_sign,
- [TGSI_OPCODE_CMP] = aos_compare,
- [TGSI_OPCODE_SCS] = aos_SCS,
- [TGSI_OPCODE_TXB] = aos_tex,
- [TGSI_OPCODE_DIV] = aos_DIV,
- [TGSI_OPCODE_DP2] = aos_simple,
- [TGSI_OPCODE_TXL] = aos_tex,
- [TGSI_OPCODE_BRK] = aos_BRK,
- [TGSI_OPCODE_IF] = aos_simple,
- [TGSI_OPCODE_UIF] = aos_simple,
- [TGSI_OPCODE_ELSE] = aos_simple,
- [TGSI_OPCODE_ENDIF] = aos_simple,
- [TGSI_OPCODE_PUSHA] = aos_unsupported,
- [TGSI_OPCODE_POPA] = aos_unsupported,
- [TGSI_OPCODE_CEIL] = aos_CEIL,
- [TGSI_OPCODE_I2F] = aos_simple,
- [TGSI_OPCODE_NOT] = aos_simple,
- [TGSI_OPCODE_TRUNC] = aos_simple,
- [TGSI_OPCODE_SHL] = aos_simple,
- [TGSI_OPCODE_AND] = aos_simple,
- [TGSI_OPCODE_OR] = aos_simple,
- [TGSI_OPCODE_MOD] = aos_simple,
- [TGSI_OPCODE_XOR] = aos_simple,
- [TGSI_OPCODE_SAD] = aos_SAD,
- [TGSI_OPCODE_TXF] = aos_tex,
- [TGSI_OPCODE_TXQ] = aos_tex,
- [TGSI_OPCODE_CONT] = aos_CONT,
- [TGSI_OPCODE_EMIT] = aos_simple,
- [TGSI_OPCODE_ENDPRIM] = aos_simple,
- [TGSI_OPCODE_BGNLOOP] = aos_BGNLOOP,
- [TGSI_OPCODE_BGNSUB] = aos_unsupported,
- [TGSI_OPCODE_ENDLOOP] = aos_ENDLOOP,
- [TGSI_OPCODE_ENDSUB] = aos_unsupported,
- [TGSI_OPCODE_TXQ_LZ] = aos_tex,
- [TGSI_OPCODE_NOP] = aos_simple,
- [TGSI_OPCODE_FSEQ] = aos_set_on_cond,
- [TGSI_OPCODE_FSGE] = aos_set_on_cond,
- [TGSI_OPCODE_FSLT] = aos_set_on_cond,
- [TGSI_OPCODE_FSNE] = aos_set_on_cond,
- [TGSI_OPCODE_CALLNZ] = aos_unsupported,
- [TGSI_OPCODE_BREAKC] = aos_unsupported,
- [TGSI_OPCODE_KILL_IF] = aos_simple,
- [TGSI_OPCODE_END] = aos_simple,
- [TGSI_OPCODE_F2I] = aos_simple,
- [TGSI_OPCODE_IDIV] = aos_simple,
- [TGSI_OPCODE_IMAX] = aos_simple,
- [TGSI_OPCODE_IMIN] = aos_simple,
- [TGSI_OPCODE_INEG] = aos_simple,
- [TGSI_OPCODE_ISGE] = aos_set_on_cond,
- [TGSI_OPCODE_ISHR] = aos_simple,
- [TGSI_OPCODE_ISLT] = aos_set_on_cond,
- [TGSI_OPCODE_F2U] = aos_simple,
- [TGSI_OPCODE_U2F] = aos_simple,
- [TGSI_OPCODE_UADD] = aos_simple,
- [TGSI_OPCODE_UDIV] = aos_simple,
- [TGSI_OPCODE_UMAD] = aos_simple,
- [TGSI_OPCODE_UMAX] = aos_simple,
- [TGSI_OPCODE_UMIN] = aos_simple,
- [TGSI_OPCODE_UMOD] = aos_simple,
- [TGSI_OPCODE_UMUL] = aos_simple,
- [TGSI_OPCODE_USEQ] = aos_set_on_cond,
- [TGSI_OPCODE_USGE] = aos_set_on_cond,
- [TGSI_OPCODE_USHR] = aos_simple,
- [TGSI_OPCODE_USLT] = aos_set_on_cond,
- [TGSI_OPCODE_USNE] = aos_set_on_cond,
- [TGSI_OPCODE_SWITCH] = aos_unsupported,
- [TGSI_OPCODE_CASE] = aos_unsupported,
- [TGSI_OPCODE_DEFAULT] = aos_unsupported,
- [TGSI_OPCODE_ENDSWITCH] = aos_unsupported,
- [TGSI_OPCODE_SAMPLE] = aos_sample,
- [TGSI_OPCODE_SAMPLE_I] = aos_sample,
- [TGSI_OPCODE_SAMPLE_I_MS] = aos_sample,
- [TGSI_OPCODE_SAMPLE_B] = aos_sample,
- [TGSI_OPCODE_SAMPLE_C] = aos_sample,
- [TGSI_OPCODE_SAMPLE_C_LZ] = aos_sample,
- [TGSI_OPCODE_SAMPLE_D] = aos_sample,
- [TGSI_OPCODE_SAMPLE_L] = aos_sample,
- [TGSI_OPCODE_GATHER4] = aos_sample,
- [TGSI_OPCODE_SVIEWINFO] = aos_sample,
- [TGSI_OPCODE_SAMPLE_POS] = aos_sample,
- [TGSI_OPCODE_SAMPLE_INFO] = aos_sample,
- [TGSI_OPCODE_UARL] = aos_simple,
- [TGSI_OPCODE_UCMP] = aos_compare,
- [TGSI_OPCODE_IABS] = aos_simple,
- [TGSI_OPCODE_ISSG] = aos_set_sign,
- [TGSI_OPCODE_LOAD] = aos_unsupported,
- [TGSI_OPCODE_STORE] = aos_unsupported,
- [TGSI_OPCODE_MFENCE] = aos_unsupported,
- [TGSI_OPCODE_LFENCE] = aos_unsupported,
- [TGSI_OPCODE_SFENCE] = aos_unsupported,
- [TGSI_OPCODE_BARRIER] = aos_unsupported,
- [TGSI_OPCODE_ATOMUADD] = aos_unsupported,
- [TGSI_OPCODE_ATOMXCHG] = aos_unsupported,
- [TGSI_OPCODE_ATOMCAS] = aos_unsupported,
- [TGSI_OPCODE_ATOMAND] = aos_unsupported,
- [TGSI_OPCODE_ATOMOR] = aos_unsupported,
- [TGSI_OPCODE_ATOMXOR] = aos_unsupported,
- [TGSI_OPCODE_ATOMUMIN] = aos_unsupported,
- [TGSI_OPCODE_ATOMUMAX] = aos_unsupported,
- [TGSI_OPCODE_ATOMIMIN] = aos_unsupported,
- [TGSI_OPCODE_ATOMIMAX] = aos_unsupported,
- [TGSI_OPCODE_TEX2] = aos_tex,
- [TGSI_OPCODE_TXB2] = aos_tex,
- [TGSI_OPCODE_TXL2] = aos_tex,
-};
-
-static void
-soa_passthrough(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst_,
- struct toy_src *src_)
-{
- const toy_tgsi_translate translate =
- aos_translate_table[tgsi_inst->Instruction.Opcode];
-
- translate(tc, tgsi_inst, dst_, src_);
-}
-
-static void
-soa_per_channel(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst_,
- struct toy_src *src_)
-{
- struct toy_dst dst[TGSI_FULL_MAX_DST_REGISTERS][4];
- struct toy_src src[TGSI_FULL_MAX_SRC_REGISTERS][4];
- int i, ch;
-
- for (i = 0; i < tgsi_inst->Instruction.NumDstRegs; i++)
- tdst_transpose(dst_[i], dst[i]);
- for (i = 0; i < tgsi_inst->Instruction.NumSrcRegs; i++)
- tsrc_transpose(src_[i], src[i]);
-
- /* emit the same instruction four times for the four channels */
- for (ch = 0; ch < 4; ch++) {
- struct toy_dst aos_dst[TGSI_FULL_MAX_DST_REGISTERS];
- struct toy_src aos_src[TGSI_FULL_MAX_SRC_REGISTERS];
-
- for (i = 0; i < tgsi_inst->Instruction.NumDstRegs; i++)
- aos_dst[i] = dst[i][ch];
- for (i = 0; i < tgsi_inst->Instruction.NumSrcRegs; i++)
- aos_src[i] = src[i][ch];
-
- aos_translate_table[tgsi_inst->Instruction.Opcode](tc,
- tgsi_inst, aos_dst, aos_src);
- }
-}
-
-static void
-soa_scalar_replicate(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst_,
- struct toy_src *src_)
-{
- struct toy_dst dst0[4], tmp;
- struct toy_src srcx[TGSI_FULL_MAX_SRC_REGISTERS];
- int opcode, i;
-
- assert(tgsi_inst->Instruction.NumDstRegs == 1);
-
- tdst_transpose(dst_[0], dst0);
- for (i = 0; i < tgsi_inst->Instruction.NumSrcRegs; i++) {
- struct toy_src tmp[4];
-
- tsrc_transpose(src_[i], tmp);
- /* only the X channels */
- srcx[i] = tmp[0];
- }
-
- tmp = tc_alloc_tmp(tc);
-
- opcode = aos_simple_opcode_map[tgsi_inst->Instruction.Opcode].opcode;
- assert(opcode);
-
- switch (tgsi_inst->Instruction.Opcode) {
- case TGSI_OPCODE_RCP:
- case TGSI_OPCODE_RSQ:
- case TGSI_OPCODE_SQRT:
- case TGSI_OPCODE_EX2:
- case TGSI_OPCODE_LG2:
- case TGSI_OPCODE_COS:
- case TGSI_OPCODE_SIN:
- tc_add1(tc, opcode, tmp, srcx[0]);
- break;
- case TGSI_OPCODE_POW:
- tc_add2(tc, opcode, tmp, srcx[0], srcx[1]);
- break;
- default:
- assert(!"invalid soa_scalar_replicate() call");
- return;
- }
-
- /* replicate the result */
- for (i = 0; i < 4; i++)
- tc_MOV(tc, dst0[i], tsrc_from(tmp));
-}
-
-static void
-soa_dot_product(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst_,
- struct toy_src *src_)
-{
- struct toy_dst dst0[4], tmp;
- struct toy_src src[TGSI_FULL_MAX_SRC_REGISTERS][4];
- int i;
-
- tdst_transpose(dst_[0], dst0);
- for (i = 0; i < tgsi_inst->Instruction.NumSrcRegs; i++)
- tsrc_transpose(src_[i], src[i]);
-
- tmp = tc_alloc_tmp(tc);
-
- switch (tgsi_inst->Instruction.Opcode) {
- case TGSI_OPCODE_DP2:
- tc_MUL(tc, tmp, src[0][1], src[1][1]);
- tc_MAC(tc, tmp, src[0][0], src[1][0], tsrc_from(tmp));
- break;
- case TGSI_OPCODE_DP2A:
- tc_MAC(tc, tmp, src[0][1], src[1][1], src[2][0]);
- tc_MAC(tc, tmp, src[0][0], src[1][0], tsrc_from(tmp));
- break;
- case TGSI_OPCODE_DP3:
- tc_MUL(tc, tmp, src[0][2], src[1][2]);
- tc_MAC(tc, tmp, src[0][1], src[1][1], tsrc_from(tmp));
- tc_MAC(tc, tmp, src[0][0], src[1][0], tsrc_from(tmp));
- break;
- case TGSI_OPCODE_DPH:
- tc_MAC(tc, tmp, src[0][2], src[1][2], src[1][3]);
- tc_MAC(tc, tmp, src[0][1], src[1][1], tsrc_from(tmp));
- tc_MAC(tc, tmp, src[0][0], src[1][0], tsrc_from(tmp));
- break;
- case TGSI_OPCODE_DP4:
- tc_MUL(tc, tmp, src[0][3], src[1][3]);
- tc_MAC(tc, tmp, src[0][2], src[1][2], tsrc_from(tmp));
- tc_MAC(tc, tmp, src[0][1], src[1][1], tsrc_from(tmp));
- tc_MAC(tc, tmp, src[0][0], src[1][0], tsrc_from(tmp));
- break;
- default:
- assert(!"invalid soa_dot_product() call");
- return;
- }
-
- for (i = 0; i < 4; i++)
- tc_MOV(tc, dst0[i], tsrc_from(tmp));
-}
-
-static void
-soa_partial_derivative(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst_,
- struct toy_src *src_)
-{
- if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_DDX)
- tc_add1(tc, TOY_OPCODE_DDX, dst_[0], src_[0]);
- else
- tc_add1(tc, TOY_OPCODE_DDY, dst_[0], src_[0]);
-}
-
-static void
-soa_if(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst_,
- struct toy_src *src_)
-{
- struct toy_src src0[4];
-
- assert(tsrc_is_swizzle1(src_[0]));
- tsrc_transpose(src_[0], src0);
-
- if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_IF)
- tc_IF(tc, tdst_null(), src0[0], tsrc_imm_f(0.0f), GEN6_COND_NZ);
- else
- tc_IF(tc, tdst_null(), src0[0], tsrc_imm_d(0), GEN6_COND_NZ);
-}
-
-static void
-soa_LIT(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst_,
- struct toy_src *src_)
-{
- struct toy_inst *inst;
- struct toy_dst dst0[4];
- struct toy_src src0[4];
-
- tdst_transpose(dst_[0], dst0);
- tsrc_transpose(src_[0], src0);
-
- tc_MOV(tc, dst0[0], tsrc_imm_f(1.0f));
- tc_MOV(tc, dst0[1], src0[0]);
- tc_POW(tc, dst0[2], src0[1], src0[3]);
- tc_MOV(tc, dst0[3], tsrc_imm_f(1.0f));
-
- /*
- * POW is calculated first because math with pred_ctrl is broken here.
- * But, why?
- */
- tc_CMP(tc, tdst_null(), src0[0], tsrc_imm_f(0.0f), GEN6_COND_L);
- inst = tc_MOV(tc, dst0[1], tsrc_imm_f(0.0f));
- inst->pred_ctrl = GEN6_PREDCTRL_NORMAL;
- inst = tc_MOV(tc, dst0[2], tsrc_imm_f(0.0f));
- inst->pred_ctrl = GEN6_PREDCTRL_NORMAL;
-}
-
-static void
-soa_EXP(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst_,
- struct toy_src *src_)
-{
- struct toy_dst dst0[4];
- struct toy_src src0[4];
-
- assert(!"SoA EXP untested");
-
- tdst_transpose(dst_[0], dst0);
- tsrc_transpose(src_[0], src0);
-
- if (!tdst_is_null(dst0[0])) {
- struct toy_dst tmp = tdst_d(tc_alloc_tmp(tc));
-
- tc_RNDD(tc, tmp, src0[0]);
-
- /* construct the floating point number manually */
- tc_ADD(tc, tmp, tsrc_from(tmp), tsrc_imm_d(127));
- tc_SHL(tc, tdst_d(dst0[0]), tsrc_from(tmp), tsrc_imm_d(23));
- }
-
- tc_FRC(tc, dst0[1], src0[0]);
- tc_EXP(tc, dst0[2], src0[0]);
- tc_MOV(tc, dst0[3], tsrc_imm_f(1.0f));
-}
-
-static void
-soa_LOG(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst_,
- struct toy_src *src_)
-{
- struct toy_dst dst0[4];
- struct toy_src src0[4];
-
- assert(!"SoA LOG untested");
-
- tdst_transpose(dst_[0], dst0);
- tsrc_transpose(src_[0], src0);
-
- if (dst_[0].writemask & TOY_WRITEMASK_XY) {
- struct toy_dst tmp = tdst_d(tc_alloc_tmp(tc));
-
- /* exponent */
- tc_SHR(tc, tmp, tsrc_absolute(tsrc_d(src0[0])), tsrc_imm_d(23));
- tc_ADD(tc, dst0[0], tsrc_from(tmp), tsrc_imm_d(-127));
-
- /* mantissa */
- tc_AND(tc, tmp, tsrc_d(src0[0]), tsrc_imm_d((1 << 23) - 1));
- tc_OR(tc, dst0[1], tsrc_from(tmp), tsrc_imm_d(127 << 23));
- }
-
- tc_LOG(tc, dst0[2], src0[0]);
- tc_MOV(tc, dst0[3], tsrc_imm_f(1.0f));
-}
-
-static void
-soa_DST(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst_,
- struct toy_src *src_)
-{
- struct toy_dst dst0[4];
- struct toy_src src[2][4];
-
- tdst_transpose(dst_[0], dst0);
- tsrc_transpose(src_[0], src[0]);
- tsrc_transpose(src_[1], src[1]);
-
- tc_MOV(tc, dst0[0], tsrc_imm_f(1.0f));
- tc_MUL(tc, dst0[1], src[0][1], src[1][1]);
- tc_MOV(tc, dst0[2], src[0][2]);
- tc_MOV(tc, dst0[3], src[1][3]);
-}
-
-static void
-soa_XPD(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst_,
- struct toy_src *src_)
-{
- struct toy_dst dst0[4];
- struct toy_src src[2][4];
-
- tdst_transpose(dst_[0], dst0);
- tsrc_transpose(src_[0], src[0]);
- tsrc_transpose(src_[1], src[1]);
-
- /* dst.x = src0.y * src1.z - src1.y * src0.z */
- tc_MUL(tc, dst0[0], src[0][2], src[1][1]);
- tc_MAC(tc, dst0[0], src[0][1], src[1][2], tsrc_negate(tsrc_from(dst0[0])));
-
- /* dst.y = src0.z * src1.x - src1.z * src0.x */
- tc_MUL(tc, dst0[1], src[0][0], src[1][2]);
- tc_MAC(tc, dst0[1], src[0][2], src[1][0], tsrc_negate(tsrc_from(dst0[1])));
-
- /* dst.z = src0.x * src1.y - src1.x * src0.y */
- tc_MUL(tc, dst0[2], src[0][1], src[1][0]);
- tc_MAC(tc, dst0[2], src[0][0], src[1][1], tsrc_negate(tsrc_from(dst0[2])));
-
- tc_MOV(tc, dst0[3], tsrc_imm_f(1.0f));
-}
-
-static void
-soa_PK2H(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst_,
- struct toy_src *src_)
-{
- struct toy_dst tmp = tdst_ud(tc_alloc_tmp(tc));
- struct toy_dst dst0[4];
- struct toy_src src0[4];
- int i;
-
- assert(!"SoA PK2H untested");
-
- tdst_transpose(dst_[0], dst0);
- tsrc_transpose(src_[0], src0);
-
- tc_SHL(tc, tmp, src0[1], tsrc_imm_ud(16));
- tc_OR(tc, tmp, src0[0], tsrc_from(tmp));
-
- for (i = 0; i < 4; i++)
- tc_MOV(tc, dst0[i], tsrc_from(tmp));
-}
-
-static void
-soa_UP2H(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst_,
- struct toy_src *src_)
-{
- struct toy_dst dst0[4];
- struct toy_src src0[4];
-
- assert(!"SoA UP2H untested");
-
- tdst_transpose(dst_[0], dst0);
- tsrc_transpose(src_[0], src0);
-
- tc_AND(tc, tdst_ud(dst0[0]), tsrc_ud(src0[0]), tsrc_imm_ud(0xffff));
- tc_SHR(tc, tdst_ud(dst0[1]), tsrc_ud(src0[1]), tsrc_imm_ud(16));
- tc_AND(tc, tdst_ud(dst0[2]), tsrc_ud(src0[2]), tsrc_imm_ud(0xffff));
- tc_SHR(tc, tdst_ud(dst0[3]), tsrc_ud(src0[3]), tsrc_imm_ud(16));
-
-}
-
-static void
-soa_SCS(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst_,
- struct toy_src *src_)
-{
- struct toy_dst dst0[4];
- struct toy_src src0[4];
-
- tdst_transpose(dst_[0], dst0);
- tsrc_transpose(src_[0], src0);
-
- tc_add1(tc, TOY_OPCODE_COS, dst0[0], src0[0]);
- tc_add1(tc, TOY_OPCODE_SIN, dst0[1], src0[0]);
- tc_MOV(tc, dst0[2], tsrc_imm_f(0.0f));
- tc_MOV(tc, dst0[3], tsrc_imm_f(1.0f));
-}
-
-static void
-soa_unsupported(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst_,
- struct toy_src *src_)
-{
- const struct tgsi_opcode_info *info =
- tgsi_get_opcode_info(tgsi_inst->Instruction.Opcode);
-
- ilo_warn("unsupported TGSI opcode in SoA form: TGSI_OPCODE_%s\n",
- info->mnemonic);
-
- tc_fail(tc, "unsupported TGSI instruction in SoA form");
-}
-
-static const toy_tgsi_translate soa_translate_table[TGSI_OPCODE_LAST] = {
- [TGSI_OPCODE_ARL] = soa_per_channel,
- [TGSI_OPCODE_MOV] = soa_per_channel,
- [TGSI_OPCODE_LIT] = soa_LIT,
- [TGSI_OPCODE_RCP] = soa_scalar_replicate,
- [TGSI_OPCODE_RSQ] = soa_scalar_replicate,
- [TGSI_OPCODE_EXP] = soa_EXP,
- [TGSI_OPCODE_LOG] = soa_LOG,
- [TGSI_OPCODE_MUL] = soa_per_channel,
- [TGSI_OPCODE_ADD] = soa_per_channel,
- [TGSI_OPCODE_DP3] = soa_dot_product,
- [TGSI_OPCODE_DP4] = soa_dot_product,
- [TGSI_OPCODE_DST] = soa_DST,
- [TGSI_OPCODE_MIN] = soa_per_channel,
- [TGSI_OPCODE_MAX] = soa_per_channel,
- [TGSI_OPCODE_SLT] = soa_per_channel,
- [TGSI_OPCODE_SGE] = soa_per_channel,
- [TGSI_OPCODE_MAD] = soa_per_channel,
- [TGSI_OPCODE_LRP] = soa_per_channel,
- [TGSI_OPCODE_SQRT] = soa_scalar_replicate,
- [TGSI_OPCODE_DP2A] = soa_dot_product,
- [TGSI_OPCODE_FRC] = soa_per_channel,
- [TGSI_OPCODE_CLAMP] = soa_per_channel,
- [TGSI_OPCODE_FLR] = soa_per_channel,
- [TGSI_OPCODE_ROUND] = soa_per_channel,
- [TGSI_OPCODE_EX2] = soa_scalar_replicate,
- [TGSI_OPCODE_LG2] = soa_scalar_replicate,
- [TGSI_OPCODE_POW] = soa_scalar_replicate,
- [TGSI_OPCODE_XPD] = soa_XPD,
- [TGSI_OPCODE_DPH] = soa_dot_product,
- [TGSI_OPCODE_COS] = soa_scalar_replicate,
- [TGSI_OPCODE_DDX] = soa_partial_derivative,
- [TGSI_OPCODE_DDY] = soa_partial_derivative,
- [TGSI_OPCODE_KILL] = soa_passthrough,
- [TGSI_OPCODE_PK2H] = soa_PK2H,
- [TGSI_OPCODE_PK2US] = soa_unsupported,
- [TGSI_OPCODE_PK4B] = soa_unsupported,
- [TGSI_OPCODE_PK4UB] = soa_unsupported,
- [TGSI_OPCODE_SEQ] = soa_per_channel,
- [TGSI_OPCODE_SGT] = soa_per_channel,
- [TGSI_OPCODE_SIN] = soa_scalar_replicate,
- [TGSI_OPCODE_SLE] = soa_per_channel,
- [TGSI_OPCODE_SNE] = soa_per_channel,
- [TGSI_OPCODE_TEX] = soa_passthrough,
- [TGSI_OPCODE_TXD] = soa_passthrough,
- [TGSI_OPCODE_TXP] = soa_passthrough,
- [TGSI_OPCODE_UP2H] = soa_UP2H,
- [TGSI_OPCODE_UP2US] = soa_unsupported,
- [TGSI_OPCODE_UP4B] = soa_unsupported,
- [TGSI_OPCODE_UP4UB] = soa_unsupported,
- [TGSI_OPCODE_ARR] = soa_per_channel,
- [TGSI_OPCODE_CAL] = soa_unsupported,
- [TGSI_OPCODE_RET] = soa_unsupported,
- [TGSI_OPCODE_SSG] = soa_per_channel,
- [TGSI_OPCODE_CMP] = soa_per_channel,
- [TGSI_OPCODE_SCS] = soa_SCS,
- [TGSI_OPCODE_TXB] = soa_passthrough,
- [TGSI_OPCODE_DIV] = soa_per_channel,
- [TGSI_OPCODE_DP2] = soa_dot_product,
- [TGSI_OPCODE_TXL] = soa_passthrough,
- [TGSI_OPCODE_BRK] = soa_passthrough,
- [TGSI_OPCODE_IF] = soa_if,
- [TGSI_OPCODE_UIF] = soa_if,
- [TGSI_OPCODE_ELSE] = soa_passthrough,
- [TGSI_OPCODE_ENDIF] = soa_passthrough,
- [TGSI_OPCODE_PUSHA] = soa_unsupported,
- [TGSI_OPCODE_POPA] = soa_unsupported,
- [TGSI_OPCODE_CEIL] = soa_per_channel,
- [TGSI_OPCODE_I2F] = soa_per_channel,
- [TGSI_OPCODE_NOT] = soa_per_channel,
- [TGSI_OPCODE_TRUNC] = soa_per_channel,
- [TGSI_OPCODE_SHL] = soa_per_channel,
- [TGSI_OPCODE_AND] = soa_per_channel,
- [TGSI_OPCODE_OR] = soa_per_channel,
- [TGSI_OPCODE_MOD] = soa_per_channel,
- [TGSI_OPCODE_XOR] = soa_per_channel,
- [TGSI_OPCODE_SAD] = soa_per_channel,
- [TGSI_OPCODE_TXF] = soa_passthrough,
- [TGSI_OPCODE_TXQ] = soa_passthrough,
- [TGSI_OPCODE_CONT] = soa_passthrough,
- [TGSI_OPCODE_EMIT] = soa_unsupported,
- [TGSI_OPCODE_ENDPRIM] = soa_unsupported,
- [TGSI_OPCODE_BGNLOOP] = soa_passthrough,
- [TGSI_OPCODE_BGNSUB] = soa_unsupported,
- [TGSI_OPCODE_ENDLOOP] = soa_passthrough,
- [TGSI_OPCODE_ENDSUB] = soa_unsupported,
- [TGSI_OPCODE_TXQ_LZ] = soa_passthrough,
- [TGSI_OPCODE_NOP] = soa_passthrough,
- [TGSI_OPCODE_FSEQ] = soa_per_channel,
- [TGSI_OPCODE_FSGE] = soa_per_channel,
- [TGSI_OPCODE_FSLT] = soa_per_channel,
- [TGSI_OPCODE_FSNE] = soa_per_channel,
- [TGSI_OPCODE_CALLNZ] = soa_unsupported,
- [TGSI_OPCODE_BREAKC] = soa_unsupported,
- [TGSI_OPCODE_KILL_IF] = soa_passthrough,
- [TGSI_OPCODE_END] = soa_passthrough,
- [TGSI_OPCODE_F2I] = soa_per_channel,
- [TGSI_OPCODE_IDIV] = soa_per_channel,
- [TGSI_OPCODE_IMAX] = soa_per_channel,
- [TGSI_OPCODE_IMIN] = soa_per_channel,
- [TGSI_OPCODE_INEG] = soa_per_channel,
- [TGSI_OPCODE_ISGE] = soa_per_channel,
- [TGSI_OPCODE_ISHR] = soa_per_channel,
- [TGSI_OPCODE_ISLT] = soa_per_channel,
- [TGSI_OPCODE_F2U] = soa_per_channel,
- [TGSI_OPCODE_U2F] = soa_per_channel,
- [TGSI_OPCODE_UADD] = soa_per_channel,
- [TGSI_OPCODE_UDIV] = soa_per_channel,
- [TGSI_OPCODE_UMAD] = soa_per_channel,
- [TGSI_OPCODE_UMAX] = soa_per_channel,
- [TGSI_OPCODE_UMIN] = soa_per_channel,
- [TGSI_OPCODE_UMOD] = soa_per_channel,
- [TGSI_OPCODE_UMUL] = soa_per_channel,
- [TGSI_OPCODE_USEQ] = soa_per_channel,
- [TGSI_OPCODE_USGE] = soa_per_channel,
- [TGSI_OPCODE_USHR] = soa_per_channel,
- [TGSI_OPCODE_USLT] = soa_per_channel,
- [TGSI_OPCODE_USNE] = soa_per_channel,
- [TGSI_OPCODE_SWITCH] = soa_unsupported,
- [TGSI_OPCODE_CASE] = soa_unsupported,
- [TGSI_OPCODE_DEFAULT] = soa_unsupported,
- [TGSI_OPCODE_ENDSWITCH] = soa_unsupported,
- [TGSI_OPCODE_SAMPLE] = soa_passthrough,
- [TGSI_OPCODE_SAMPLE_I] = soa_passthrough,
- [TGSI_OPCODE_SAMPLE_I_MS] = soa_passthrough,
- [TGSI_OPCODE_SAMPLE_B] = soa_passthrough,
- [TGSI_OPCODE_SAMPLE_C] = soa_passthrough,
- [TGSI_OPCODE_SAMPLE_C_LZ] = soa_passthrough,
- [TGSI_OPCODE_SAMPLE_D] = soa_passthrough,
- [TGSI_OPCODE_SAMPLE_L] = soa_passthrough,
- [TGSI_OPCODE_GATHER4] = soa_passthrough,
- [TGSI_OPCODE_SVIEWINFO] = soa_passthrough,
- [TGSI_OPCODE_SAMPLE_POS] = soa_passthrough,
- [TGSI_OPCODE_SAMPLE_INFO] = soa_passthrough,
- [TGSI_OPCODE_UARL] = soa_per_channel,
- [TGSI_OPCODE_UCMP] = soa_per_channel,
- [TGSI_OPCODE_IABS] = soa_per_channel,
- [TGSI_OPCODE_ISSG] = soa_per_channel,
- [TGSI_OPCODE_LOAD] = soa_unsupported,
- [TGSI_OPCODE_STORE] = soa_unsupported,
- [TGSI_OPCODE_MFENCE] = soa_unsupported,
- [TGSI_OPCODE_LFENCE] = soa_unsupported,
- [TGSI_OPCODE_SFENCE] = soa_unsupported,
- [TGSI_OPCODE_BARRIER] = soa_unsupported,
- [TGSI_OPCODE_ATOMUADD] = soa_unsupported,
- [TGSI_OPCODE_ATOMXCHG] = soa_unsupported,
- [TGSI_OPCODE_ATOMCAS] = soa_unsupported,
- [TGSI_OPCODE_ATOMAND] = soa_unsupported,
- [TGSI_OPCODE_ATOMOR] = soa_unsupported,
- [TGSI_OPCODE_ATOMXOR] = soa_unsupported,
- [TGSI_OPCODE_ATOMUMIN] = soa_unsupported,
- [TGSI_OPCODE_ATOMUMAX] = soa_unsupported,
- [TGSI_OPCODE_ATOMIMIN] = soa_unsupported,
- [TGSI_OPCODE_ATOMIMAX] = soa_unsupported,
- [TGSI_OPCODE_TEX2] = soa_passthrough,
- [TGSI_OPCODE_TXB2] = soa_passthrough,
- [TGSI_OPCODE_TXL2] = soa_passthrough,
-};
-
-static bool
-ra_dst_is_indirect(const struct tgsi_full_dst_register *d)
-{
- return (d->Register.Indirect ||
- (d->Register.Dimension && d->Dimension.Indirect));
-}
-
-static int
-ra_dst_index(const struct tgsi_full_dst_register *d)
-{
- assert(!d->Register.Indirect);
- return d->Register.Index;
-}
-
-static int
-ra_dst_dimension(const struct tgsi_full_dst_register *d)
-{
- if (d->Register.Dimension) {
- assert(!d->Dimension.Indirect);
- return d->Dimension.Index;
- }
- else {
- return 0;
- }
-}
-
-static bool
-ra_is_src_indirect(const struct tgsi_full_src_register *s)
-{
- return (s->Register.Indirect ||
- (s->Register.Dimension && s->Dimension.Indirect));
-}
-
-static int
-ra_src_index(const struct tgsi_full_src_register *s)
-{
- assert(!s->Register.Indirect);
- return s->Register.Index;
-}
-
-static int
-ra_src_dimension(const struct tgsi_full_src_register *s)
-{
- if (s->Register.Dimension) {
- assert(!s->Dimension.Indirect);
- return s->Dimension.Index;
- }
- else {
- return 0;
- }
-}
-
-/**
- * Infer the type of either the sources or the destination.
- */
-static enum toy_type
-ra_infer_opcode_type(int tgsi_opcode, bool is_dst)
-{
- enum tgsi_opcode_type type;
-
- if (is_dst)
- type = tgsi_opcode_infer_dst_type(tgsi_opcode);
- else
- type = tgsi_opcode_infer_src_type(tgsi_opcode);
-
- switch (type) {
- case TGSI_TYPE_UNSIGNED:
- return TOY_TYPE_UD;
- case TGSI_TYPE_SIGNED:
- return TOY_TYPE_D;
- case TGSI_TYPE_FLOAT:
- return TOY_TYPE_F;
- case TGSI_TYPE_UNTYPED:
- case TGSI_TYPE_VOID:
- case TGSI_TYPE_DOUBLE:
- default:
- assert(!"unsupported TGSI type");
- return TOY_TYPE_UD;
- }
-}
-
-/**
- * Return the type of an operand of the specified instruction.
- */
-static enum toy_type
-ra_get_type(struct toy_tgsi *tgsi, const struct tgsi_full_instruction *tgsi_inst,
- int operand, bool is_dst)
-{
- enum toy_type type;
- enum tgsi_file_type file;
-
- /* we need to look at both src and dst for MOV */
- /* XXX it should not be this complex */
- if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_MOV) {
- const enum tgsi_file_type dst_file = tgsi_inst->Dst[0].Register.File;
- const enum tgsi_file_type src_file = tgsi_inst->Src[0].Register.File;
-
- if (dst_file == TGSI_FILE_ADDRESS || src_file == TGSI_FILE_ADDRESS) {
- type = TOY_TYPE_D;
- }
- else if (src_file == TGSI_FILE_IMMEDIATE &&
- !tgsi_inst->Src[0].Register.Indirect) {
- const int src_idx = tgsi_inst->Src[0].Register.Index;
- type = tgsi->imm_data.types[src_idx];
- }
- else {
- /* this is the best we can do */
- type = TOY_TYPE_F;
- }
-
- return type;
- }
- else if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_UCMP) {
- if (!is_dst && operand == 0)
- type = TOY_TYPE_UD;
- else
- type = TOY_TYPE_F;
-
- return type;
- }
-
- type = ra_infer_opcode_type(tgsi_inst->Instruction.Opcode, is_dst);
-
- /* fix the type */
- file = (is_dst) ?
- tgsi_inst->Dst[operand].Register.File :
- tgsi_inst->Src[operand].Register.File;
- switch (file) {
- case TGSI_FILE_SAMPLER:
- case TGSI_FILE_IMAGE:
- case TGSI_FILE_SAMPLER_VIEW:
- type = TOY_TYPE_D;
- break;
- case TGSI_FILE_ADDRESS:
- assert(type == TOY_TYPE_D);
- break;
- default:
- break;
- }
-
- return type;
-}
-
-/**
- * Allocate a VRF register.
- */
-static int
-ra_alloc_reg(struct toy_tgsi *tgsi, enum tgsi_file_type file)
-{
- const int count = (tgsi->aos) ? 1 : 4;
- return tc_alloc_vrf(tgsi->tc, count);
-}
-
-/**
- * Construct the key for VRF mapping look-up.
- */
-static void *
-ra_get_map_key(enum tgsi_file_type file, unsigned dim, unsigned index)
-{
- intptr_t key;
-
- /* this is ugly... */
- assert(file < 1 << 4);
- assert(dim < 1 << 12);
- assert(index < 1 << 16);
- key = (file << 28) | (dim << 16) | index;
-
- return intptr_to_pointer(key);
-}
-
-/**
- * Map a TGSI register to a VRF register.
- */
-static int
-ra_map_reg(struct toy_tgsi *tgsi, enum tgsi_file_type file,
- int dim, int index, bool *is_new)
-{
- void *key, *val;
- intptr_t vrf;
-
- key = ra_get_map_key(file, dim, index);
-
- /*
- * because we allocate vrf from 1 and on, val is never NULL as long as the
- * key exists
- */
- val = util_hash_table_get(tgsi->reg_mapping, key);
- if (val) {
- vrf = pointer_to_intptr(val);
-
- if (is_new)
- *is_new = false;
- }
- else {
- vrf = (intptr_t) ra_alloc_reg(tgsi, file);
-
- /* add to the mapping */
- val = intptr_to_pointer(vrf);
- util_hash_table_set(tgsi->reg_mapping, key, val);
-
- if (is_new)
- *is_new = true;
- }
-
- return (int) vrf;
-}
-
-/**
- * Return true if the destination aliases any of the sources.
- */
-static bool
-ra_dst_is_aliasing(const struct tgsi_full_instruction *tgsi_inst, int dst_index)
-{
- const struct tgsi_full_dst_register *d = &tgsi_inst->Dst[dst_index];
- int i;
-
- /* we need a scratch register for indirect dst anyway */
- if (ra_dst_is_indirect(d))
- return true;
-
- for (i = 0; i < tgsi_inst->Instruction.NumSrcRegs; i++) {
- const struct tgsi_full_src_register *s = &tgsi_inst->Src[i];
-
- if (s->Register.File != d->Register.File)
- continue;
-
- /*
- * we can go on to check dimension and index respectively, but
- * keep it simple for now
- */
- if (ra_is_src_indirect(s))
- return true;
- if (ra_src_dimension(s) == ra_dst_dimension(d) &&
- ra_src_index(s) == ra_dst_index(d))
- return true;
- }
-
- return false;
-}
-
-/**
- * Return the toy register for a TGSI destination operand.
- */
-static struct toy_dst
-ra_get_dst(struct toy_tgsi *tgsi,
- const struct tgsi_full_instruction *tgsi_inst, int dst_index,
- bool *is_scratch)
-{
- const struct tgsi_full_dst_register *d = &tgsi_inst->Dst[dst_index];
- bool need_vrf = false;
- struct toy_dst dst;
-
- switch (d->Register.File) {
- case TGSI_FILE_NULL:
- dst = tdst_null();
- break;
- case TGSI_FILE_OUTPUT:
- case TGSI_FILE_TEMPORARY:
- case TGSI_FILE_ADDRESS:
- case TGSI_FILE_PREDICATE:
- need_vrf = true;
- break;
- default:
- assert(!"unhandled dst file");
- dst = tdst_null();
- break;
- }
-
- if (need_vrf) {
- /* XXX we do not always need a scratch given the conditions... */
- const bool need_scratch =
- (ra_dst_is_indirect(d) || ra_dst_is_aliasing(tgsi_inst, dst_index) ||
- tgsi_inst->Instruction.Saturate);
- const enum toy_type type = ra_get_type(tgsi, tgsi_inst, dst_index, true);
- int vrf;
-
- if (need_scratch) {
- vrf = ra_alloc_reg(tgsi, d->Register.File);
- }
- else {
- vrf = ra_map_reg(tgsi, d->Register.File,
- ra_dst_dimension(d), ra_dst_index(d), NULL);
- }
-
- if (is_scratch)
- *is_scratch = need_scratch;
-
- dst = tdst_full(TOY_FILE_VRF, type, TOY_RECT_LINEAR,
- false, 0, d->Register.WriteMask, vrf * TOY_REG_WIDTH);
- }
-
- return dst;
-}
-
-static struct toy_src
-ra_get_src_for_vrf(const struct tgsi_full_src_register *s,
- enum toy_type type, int vrf)
-{
- return tsrc_full(TOY_FILE_VRF, type, TOY_RECT_LINEAR,
- false, 0,
- s->Register.SwizzleX, s->Register.SwizzleY,
- s->Register.SwizzleZ, s->Register.SwizzleW,
- s->Register.Absolute, s->Register.Negate,
- vrf * TOY_REG_WIDTH);
-}
-
-static int
-init_tgsi_reg(struct toy_tgsi *tgsi, struct toy_inst *inst,
- enum tgsi_file_type file, int index,
- const struct tgsi_ind_register *indirect,
- const struct tgsi_dimension *dimension,
- const struct tgsi_ind_register *dim_indirect)
-{
- struct toy_src src;
- int num_src = 0;
-
- /* src[0]: TGSI file */
- inst->src[num_src++] = tsrc_imm_d(file);
-
- /* src[1]: TGSI dimension */
- inst->src[num_src++] = tsrc_imm_d((dimension) ? dimension->Index : 0);
-
- /* src[2]: TGSI dimension indirection */
- if (dim_indirect) {
- const int vrf = ra_map_reg(tgsi, dim_indirect->File, 0,
- dim_indirect->Index, NULL);
-
- src = tsrc(TOY_FILE_VRF, vrf, 0);
- src = tsrc_swizzle1(tsrc_d(src), indirect->Swizzle);
- }
- else {
- src = tsrc_imm_d(0);
- }
-
- inst->src[num_src++] = src;
-
- /* src[3]: TGSI index */
- inst->src[num_src++] = tsrc_imm_d(index);
-
- /* src[4]: TGSI index indirection */
- if (indirect) {
- const int vrf = ra_map_reg(tgsi, indirect->File, 0,
- indirect->Index, NULL);
-
- src = tsrc(TOY_FILE_VRF, vrf, 0);
- src = tsrc_swizzle1(tsrc_d(src), indirect->Swizzle);
- }
- else {
- src = tsrc_imm_d(0);
- }
-
- inst->src[num_src++] = src;
-
- return num_src;
-}
-
-static struct toy_src
-ra_get_src_indirect(struct toy_tgsi *tgsi,
- const struct tgsi_full_instruction *tgsi_inst,
- int src_index)
-{
- const struct tgsi_full_src_register *s = &tgsi_inst->Src[src_index];
- bool need_vrf = false, is_resource = false;
- struct toy_src src;
-
- switch (s->Register.File) {
- case TGSI_FILE_NULL:
- src = tsrc_null();
- break;
- case TGSI_FILE_SAMPLER:
- case TGSI_FILE_IMAGE:
- case TGSI_FILE_SAMPLER_VIEW:
- is_resource = true;
- /* fall through */
- case TGSI_FILE_CONSTANT:
- case TGSI_FILE_INPUT:
- case TGSI_FILE_SYSTEM_VALUE:
- case TGSI_FILE_TEMPORARY:
- case TGSI_FILE_ADDRESS:
- case TGSI_FILE_IMMEDIATE:
- case TGSI_FILE_PREDICATE:
- need_vrf = true;
- break;
- default:
- assert(!"unhandled src file");
- src = tsrc_null();
- break;
- }
-
- if (need_vrf) {
- const enum toy_type type = ra_get_type(tgsi, tgsi_inst, src_index, false);
- int vrf;
-
- if (is_resource) {
- assert(!s->Register.Dimension);
- assert(s->Register.Indirect);
-
- vrf = ra_map_reg(tgsi, s->Indirect.File, 0, s->Indirect.Index, NULL);
- }
- else {
- vrf = ra_alloc_reg(tgsi, s->Register.File);
- }
-
- src = ra_get_src_for_vrf(s, type, vrf);
-
- /* emit indirect fetch */
- if (!is_resource) {
- struct toy_inst *inst;
-
- inst = tc_add(tgsi->tc);
- inst->opcode = TOY_OPCODE_TGSI_INDIRECT_FETCH;
- inst->dst = tdst_from(src);
- inst->dst.writemask = TOY_WRITEMASK_XYZW;
-
- init_tgsi_reg(tgsi, inst, s->Register.File, s->Register.Index,
- (s->Register.Indirect) ? &s->Indirect : NULL,
- (s->Register.Dimension) ? &s->Dimension : NULL,
- (s->Dimension.Indirect) ? &s->DimIndirect : NULL);
- }
- }
-
- return src;
-}
-
-/**
- * Return the toy register for a TGSI source operand.
- */
-static struct toy_src
-ra_get_src(struct toy_tgsi *tgsi,
- const struct tgsi_full_instruction *tgsi_inst,
- int src_index)
-{
- const struct tgsi_full_src_register *s = &tgsi_inst->Src[src_index];
- bool need_vrf = false;
- struct toy_src src;
-
- if (ra_is_src_indirect(s))
- return ra_get_src_indirect(tgsi, tgsi_inst, src_index);
-
- switch (s->Register.File) {
- case TGSI_FILE_NULL:
- src = tsrc_null();
- break;
- case TGSI_FILE_CONSTANT:
- case TGSI_FILE_INPUT:
- case TGSI_FILE_SYSTEM_VALUE:
- need_vrf = true;
- break;
- case TGSI_FILE_TEMPORARY:
- case TGSI_FILE_ADDRESS:
- case TGSI_FILE_PREDICATE:
- need_vrf = true;
- break;
- case TGSI_FILE_SAMPLER:
- case TGSI_FILE_IMAGE:
- case TGSI_FILE_SAMPLER_VIEW:
- assert(!s->Register.Dimension);
- src = tsrc_imm_d(s->Register.Index);
- break;
- case TGSI_FILE_IMMEDIATE:
- {
- const uint32_t *imm;
- enum toy_type imm_type;
- bool is_scalar;
-
- imm = toy_tgsi_get_imm(tgsi, s->Register.Index, &imm_type);
-
- is_scalar =
- (imm[s->Register.SwizzleX] == imm[s->Register.SwizzleY] &&
- imm[s->Register.SwizzleX] == imm[s->Register.SwizzleZ] &&
- imm[s->Register.SwizzleX] == imm[s->Register.SwizzleW]);
-
- if (is_scalar) {
- const enum toy_type type =
- ra_get_type(tgsi, tgsi_inst, src_index, false);
-
- /* ignore imm_type */
- src = tsrc_imm_ud(imm[s->Register.SwizzleX]);
- src.type = type;
- src.absolute = s->Register.Absolute;
- src.negate = s->Register.Negate;
- }
- else {
- need_vrf = true;
- }
- }
- break;
- default:
- assert(!"unhandled src file");
- src = tsrc_null();
- break;
- }
-
- if (need_vrf) {
- const enum toy_type type = ra_get_type(tgsi, tgsi_inst, src_index, false);
- bool is_new;
- int vrf;
-
- vrf = ra_map_reg(tgsi, s->Register.File,
- ra_src_dimension(s), ra_src_index(s), &is_new);
-
- src = ra_get_src_for_vrf(s, type, vrf);
-
- if (is_new) {
- switch (s->Register.File) {
- case TGSI_FILE_TEMPORARY:
- case TGSI_FILE_ADDRESS:
- case TGSI_FILE_PREDICATE:
- {
- struct toy_dst dst = tdst_from(src);
- dst.writemask = TOY_WRITEMASK_XYZW;
-
- /* always initialize registers before use */
- if (tgsi->aos) {
- tc_MOV(tgsi->tc, dst, tsrc_type(tsrc_imm_d(0), type));
- }
- else {
- struct toy_dst tdst[4];
- int i;
-
- tdst_transpose(dst, tdst);
-
- for (i = 0; i < 4; i++) {
- tc_MOV(tgsi->tc, tdst[i],
- tsrc_type(tsrc_imm_d(0), type));
- }
- }
- }
- break;
- default:
- break;
- }
- }
-
- }
-
- return src;
-}
-
-static void
-parse_instruction(struct toy_tgsi *tgsi,
- const struct tgsi_full_instruction *tgsi_inst)
-{
- struct toy_dst dst[TGSI_FULL_MAX_DST_REGISTERS];
- struct toy_src src[TGSI_FULL_MAX_SRC_REGISTERS];
- bool dst_is_scratch[TGSI_FULL_MAX_DST_REGISTERS];
- toy_tgsi_translate translate;
- int i;
-
- /* convert TGSI registers to toy registers */
- for (i = 0; i < tgsi_inst->Instruction.NumSrcRegs; i++)
- src[i] = ra_get_src(tgsi, tgsi_inst, i);
- for (i = 0; i < tgsi_inst->Instruction.NumDstRegs; i++)
- dst[i] = ra_get_dst(tgsi, tgsi_inst, i, &dst_is_scratch[i]);
-
- /* translate the instruction */
- translate = tgsi->translate_table[tgsi_inst->Instruction.Opcode];
- if (!translate) {
- if (tgsi->translate_table == soa_translate_table)
- soa_unsupported(tgsi->tc, tgsi_inst, dst, src);
- else
- aos_unsupported(tgsi->tc, tgsi_inst, dst, src);
- }
- translate(tgsi->tc, tgsi_inst, dst, src);
-
- /* write the result to the real destinations if needed */
- for (i = 0; i < tgsi_inst->Instruction.NumDstRegs; i++) {
- const struct tgsi_full_dst_register *d = &tgsi_inst->Dst[i];
-
- if (!dst_is_scratch[i])
- continue;
-
- tgsi->tc->templ.saturate = tgsi_inst->Instruction.Saturate;
-
- /* emit indirect store */
- if (ra_dst_is_indirect(d)) {
- struct toy_inst *inst;
-
- inst = tc_add(tgsi->tc);
- inst->opcode = TOY_OPCODE_TGSI_INDIRECT_STORE;
- inst->dst = dst[i];
-
- init_tgsi_reg(tgsi, inst, d->Register.File, d->Register.Index,
- (d->Register.Indirect) ? &d->Indirect : NULL,
- (d->Register.Dimension) ? &d->Dimension : NULL,
- (d->Dimension.Indirect) ? &d->DimIndirect : NULL);
- }
- else {
- const enum toy_type type = ra_get_type(tgsi, tgsi_inst, i, true);
- struct toy_dst real_dst;
- int vrf;
-
- vrf = ra_map_reg(tgsi, d->Register.File,
- ra_dst_dimension(d), ra_dst_index(d), NULL);
- real_dst = tdst_full(TOY_FILE_VRF, type, TOY_RECT_LINEAR,
- false, 0, d->Register.WriteMask, vrf * TOY_REG_WIDTH);
-
- if (tgsi->aos) {
- tc_MOV(tgsi->tc, real_dst, tsrc_from(dst[i]));
- }
- else {
- struct toy_dst tdst[4];
- struct toy_src tsrc[4];
- int j;
-
- tdst_transpose(real_dst, tdst);
- tsrc_transpose(tsrc_from(dst[i]), tsrc);
-
- for (j = 0; j < 4; j++)
- tc_MOV(tgsi->tc, tdst[j], tsrc[j]);
- }
- }
-
- tgsi->tc->templ.saturate = false;
- }
-
- switch (tgsi_inst->Instruction.Opcode) {
- case TGSI_OPCODE_KILL_IF:
- case TGSI_OPCODE_KILL:
- tgsi->uses_kill = true;
- break;
- }
-
- for (i = 0; i < tgsi_inst->Instruction.NumSrcRegs; i++) {
- const struct tgsi_full_src_register *s = &tgsi_inst->Src[i];
- if (s->Register.File == TGSI_FILE_CONSTANT && s->Register.Indirect)
- tgsi->const_indirect = true;
- }
-
- /* remember channels written */
- for (i = 0; i < tgsi_inst->Instruction.NumDstRegs; i++) {
- const struct tgsi_full_dst_register *d = &tgsi_inst->Dst[i];
-
- if (d->Register.File != TGSI_FILE_OUTPUT)
- continue;
- for (i = 0; i < tgsi->num_outputs; i++) {
- if (tgsi->outputs[i].index == d->Register.Index) {
- tgsi->outputs[i].undefined_mask &= ~d->Register.WriteMask;
- break;
- }
- }
- }
-}
-
-static void
-decl_add_in(struct toy_tgsi *tgsi, const struct tgsi_full_declaration *decl)
-{
- static const struct tgsi_declaration_interp default_interp = {
- TGSI_INTERPOLATE_PERSPECTIVE, false, 0,
- };
- const struct tgsi_declaration_interp *interp =
- (decl->Declaration.Interpolate) ? &decl->Interp: &default_interp;
- int index;
-
- if (decl->Range.Last >= ARRAY_SIZE(tgsi->inputs)) {
- assert(!"invalid IN");
- return;
- }
-
- for (index = decl->Range.First; index <= decl->Range.Last; index++) {
- const int slot = tgsi->num_inputs++;
-
- tgsi->inputs[slot].index = index;
- tgsi->inputs[slot].usage_mask = decl->Declaration.UsageMask;
- if (decl->Declaration.Semantic) {
- tgsi->inputs[slot].semantic_name = decl->Semantic.Name;
- tgsi->inputs[slot].semantic_index = decl->Semantic.Index;
- }
- else {
- tgsi->inputs[slot].semantic_name = TGSI_SEMANTIC_GENERIC;
- tgsi->inputs[slot].semantic_index = index;
- }
- tgsi->inputs[slot].interp = interp->Interpolate;
- tgsi->inputs[slot].centroid = interp->Location == TGSI_INTERPOLATE_LOC_CENTROID;
- }
-}
-
-static void
-decl_add_out(struct toy_tgsi *tgsi, const struct tgsi_full_declaration *decl)
-{
- int index;
-
- if (decl->Range.Last >= ARRAY_SIZE(tgsi->outputs)) {
- assert(!"invalid OUT");
- return;
- }
-
- assert(decl->Declaration.Semantic);
-
- for (index = decl->Range.First; index <= decl->Range.Last; index++) {
- const int slot = tgsi->num_outputs++;
-
- tgsi->outputs[slot].index = index;
- tgsi->outputs[slot].undefined_mask = TOY_WRITEMASK_XYZW;
- tgsi->outputs[slot].usage_mask = decl->Declaration.UsageMask;
- tgsi->outputs[slot].semantic_name = decl->Semantic.Name;
- tgsi->outputs[slot].semantic_index = decl->Semantic.Index;
- }
-}
-
-static void
-decl_add_sv(struct toy_tgsi *tgsi, const struct tgsi_full_declaration *decl)
-{
- int index;
-
- if (decl->Range.Last >= ARRAY_SIZE(tgsi->system_values)) {
- assert(!"invalid SV");
- return;
- }
-
- for (index = decl->Range.First; index <= decl->Range.Last; index++) {
- const int slot = tgsi->num_system_values++;
-
- tgsi->system_values[slot].index = index;
- if (decl->Declaration.Semantic) {
- tgsi->system_values[slot].semantic_name = decl->Semantic.Name;
- tgsi->system_values[slot].semantic_index = decl->Semantic.Index;
- }
- else {
- tgsi->system_values[slot].semantic_name = TGSI_SEMANTIC_GENERIC;
- tgsi->system_values[slot].semantic_index = index;
- }
- }
-}
-
-/**
- * Emit an instruction to fetch the value of a TGSI register.
- */
-static void
-fetch_source(struct toy_tgsi *tgsi, enum tgsi_file_type file, int dim, int idx)
-{
- struct toy_dst dst;
- int vrf;
- enum toy_opcode opcode;
- enum toy_type type = TOY_TYPE_F;
-
- switch (file) {
- case TGSI_FILE_INPUT:
- opcode = TOY_OPCODE_TGSI_IN;
- break;
- case TGSI_FILE_CONSTANT:
- opcode = TOY_OPCODE_TGSI_CONST;
- break;
- case TGSI_FILE_SYSTEM_VALUE:
- opcode = TOY_OPCODE_TGSI_SV;
- break;
- case TGSI_FILE_IMMEDIATE:
- opcode = TOY_OPCODE_TGSI_IMM;
- toy_tgsi_get_imm(tgsi, idx, &type);
- break;
- default:
- /* no need to fetch */
- return;
- break;
- }
-
- vrf = ra_map_reg(tgsi, file, dim, idx, NULL);
- dst = tdst(TOY_FILE_VRF, vrf, 0);
- dst = tdst_type(dst, type);
-
- tc_add2(tgsi->tc, opcode, dst, tsrc_imm_d(dim), tsrc_imm_d(idx));
-}
-
-static void
-parse_declaration(struct toy_tgsi *tgsi,
- const struct tgsi_full_declaration *decl)
-{
- int i;
-
- switch (decl->Declaration.File) {
- case TGSI_FILE_INPUT:
- decl_add_in(tgsi, decl);
- break;
- case TGSI_FILE_OUTPUT:
- decl_add_out(tgsi, decl);
- break;
- case TGSI_FILE_SYSTEM_VALUE:
- decl_add_sv(tgsi, decl);
- break;
- case TGSI_FILE_IMMEDIATE:
- /* immediates should be declared with TGSI_TOKEN_TYPE_IMMEDIATE */
- assert(!"unexpected immediate declaration");
- break;
- case TGSI_FILE_CONSTANT:
- if (tgsi->const_count <= decl->Range.Last)
- tgsi->const_count = decl->Range.Last + 1;
- break;
- case TGSI_FILE_NULL:
- case TGSI_FILE_TEMPORARY:
- case TGSI_FILE_SAMPLER:
- case TGSI_FILE_PREDICATE:
- case TGSI_FILE_ADDRESS:
- case TGSI_FILE_IMAGE:
- case TGSI_FILE_SAMPLER_VIEW:
- /* nothing to do */
- break;
- default:
- assert(!"unhandled TGSI file");
- break;
- }
-
- /* fetch the registers now */
- for (i = decl->Range.First; i <= decl->Range.Last; i++) {
- const int dim = (decl->Declaration.Dimension) ? decl->Dim.Index2D : 0;
- fetch_source(tgsi, decl->Declaration.File, dim, i);
- }
-}
-
-static int
-add_imm(struct toy_tgsi *tgsi, enum toy_type type, const uint32_t *buf)
-{
- /* reallocate the buffer if necessary */
- if (tgsi->imm_data.cur >= tgsi->imm_data.size) {
- const int cur_size = tgsi->imm_data.size;
- int new_size;
- enum toy_type *new_types;
- uint32_t (*new_buf)[4];
-
- new_size = (cur_size) ? cur_size << 1 : 16;
- while (new_size <= tgsi->imm_data.cur)
- new_size <<= 1;
-
- new_buf = REALLOC(tgsi->imm_data.buf,
- cur_size * sizeof(new_buf[0]),
- new_size * sizeof(new_buf[0]));
- new_types = REALLOC(tgsi->imm_data.types,
- cur_size * sizeof(new_types[0]),
- new_size * sizeof(new_types[0]));
- if (!new_buf || !new_types) {
- FREE(new_buf);
- FREE(new_types);
- return -1;
- }
-
- tgsi->imm_data.buf = new_buf;
- tgsi->imm_data.types = new_types;
- tgsi->imm_data.size = new_size;
- }
-
- tgsi->imm_data.types[tgsi->imm_data.cur] = type;
- memcpy(&tgsi->imm_data.buf[tgsi->imm_data.cur],
- buf, sizeof(tgsi->imm_data.buf[0]));
-
- return tgsi->imm_data.cur++;
-}
-
-static void
-parse_immediate(struct toy_tgsi *tgsi, const struct tgsi_full_immediate *imm)
-{
- enum toy_type type;
- uint32_t imm_buf[4];
- int idx;
-
- switch (imm->Immediate.DataType) {
- case TGSI_IMM_FLOAT32:
- type = TOY_TYPE_F;
- imm_buf[0] = fui(imm->u[0].Float);
- imm_buf[1] = fui(imm->u[1].Float);
- imm_buf[2] = fui(imm->u[2].Float);
- imm_buf[3] = fui(imm->u[3].Float);
- break;
- case TGSI_IMM_INT32:
- type = TOY_TYPE_D;
- imm_buf[0] = (uint32_t) imm->u[0].Int;
- imm_buf[1] = (uint32_t) imm->u[1].Int;
- imm_buf[2] = (uint32_t) imm->u[2].Int;
- imm_buf[3] = (uint32_t) imm->u[3].Int;
- break;
- case TGSI_IMM_UINT32:
- type = TOY_TYPE_UD;
- imm_buf[0] = imm->u[0].Uint;
- imm_buf[1] = imm->u[1].Uint;
- imm_buf[2] = imm->u[2].Uint;
- imm_buf[3] = imm->u[3].Uint;
- break;
- default:
- assert(!"unhandled TGSI imm type");
- type = TOY_TYPE_F;
- memset(imm_buf, 0, sizeof(imm_buf));
- break;
- }
-
- idx = add_imm(tgsi, type, imm_buf);
- if (idx >= 0)
- fetch_source(tgsi, TGSI_FILE_IMMEDIATE, 0, idx);
- else
- tc_fail(tgsi->tc, "failed to add TGSI imm");
-}
-
-static void
-parse_property(struct toy_tgsi *tgsi, const struct tgsi_full_property *prop)
-{
- switch (prop->Property.PropertyName) {
- case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
- tgsi->props.vs_prohibit_ucps = prop->u[0].Data;
- break;
- case TGSI_PROPERTY_FS_COORD_ORIGIN:
- tgsi->props.fs_coord_origin = prop->u[0].Data;
- break;
- case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
- tgsi->props.fs_coord_pixel_center = prop->u[0].Data;
- break;
- case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
- tgsi->props.fs_color0_writes_all_cbufs = prop->u[0].Data;
- break;
- case TGSI_PROPERTY_FS_DEPTH_LAYOUT:
- tgsi->props.fs_depth_layout = prop->u[0].Data;
- break;
- case TGSI_PROPERTY_GS_INPUT_PRIM:
- tgsi->props.gs_input_prim = prop->u[0].Data;
- break;
- case TGSI_PROPERTY_GS_OUTPUT_PRIM:
- tgsi->props.gs_output_prim = prop->u[0].Data;
- break;
- case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
- tgsi->props.gs_max_output_vertices = prop->u[0].Data;
- break;
- default:
- assert(!"unhandled TGSI property");
- break;
- }
-}
-
-static void
-parse_token(struct toy_tgsi *tgsi, const union tgsi_full_token *token)
-{
- switch (token->Token.Type) {
- case TGSI_TOKEN_TYPE_DECLARATION:
- parse_declaration(tgsi, &token->FullDeclaration);
- break;
- case TGSI_TOKEN_TYPE_IMMEDIATE:
- parse_immediate(tgsi, &token->FullImmediate);
- break;
- case TGSI_TOKEN_TYPE_INSTRUCTION:
- parse_instruction(tgsi, &token->FullInstruction);
- break;
- case TGSI_TOKEN_TYPE_PROPERTY:
- parse_property(tgsi, &token->FullProperty);
- break;
- default:
- assert(!"unhandled TGSI token type");
- break;
- }
-}
-
-static enum pipe_error
-dump_reg_mapping(void *key, void *val, void *data)
-{
- int tgsi_file, tgsi_dim, tgsi_index;
- uint32_t sig, vrf;
-
- sig = (uint32_t) pointer_to_intptr(key);
- vrf = (uint32_t) pointer_to_intptr(val);
-
- /* see ra_get_map_key() */
- tgsi_file = (sig >> 28) & 0xf;
- tgsi_dim = (sig >> 16) & 0xfff;
- tgsi_index = (sig >> 0) & 0xffff;
-
- if (tgsi_dim) {
- ilo_printf(" v%d:\t%s[%d][%d]\n", vrf,
- tgsi_file_name(tgsi_file), tgsi_dim, tgsi_index);
- }
- else {
- ilo_printf(" v%d:\t%s[%d]\n", vrf,
- tgsi_file_name(tgsi_file), tgsi_index);
- }
-
- return PIPE_OK;
-}
-
-/**
- * Dump the TGSI translator, currently only the register mapping.
- */
-void
-toy_tgsi_dump(const struct toy_tgsi *tgsi)
-{
- util_hash_table_foreach(tgsi->reg_mapping, dump_reg_mapping, NULL);
-}
-
-/**
- * Clean up the TGSI translator.
- */
-void
-toy_tgsi_cleanup(struct toy_tgsi *tgsi)
-{
- FREE(tgsi->imm_data.buf);
- FREE(tgsi->imm_data.types);
-
- util_hash_table_destroy(tgsi->reg_mapping);
-}
-
-static unsigned
-reg_mapping_hash(void *key)
-{
- return (unsigned) pointer_to_intptr(key);
-}
-
-static int
-reg_mapping_compare(void *key1, void *key2)
-{
- return (key1 != key2);
-}
-
-/**
- * Initialize the TGSI translator.
- */
-static bool
-init_tgsi(struct toy_tgsi *tgsi, struct toy_compiler *tc, bool aos)
-{
- memset(tgsi, 0, sizeof(*tgsi));
-
- tgsi->tc = tc;
- tgsi->aos = aos;
- tgsi->translate_table = (aos) ? aos_translate_table : soa_translate_table;
-
- /* create a mapping of TGSI registers to VRF reigsters */
- tgsi->reg_mapping =
- util_hash_table_create(reg_mapping_hash, reg_mapping_compare);
-
- return (tgsi->reg_mapping != NULL);
-}
-
-/**
- * Translate TGSI tokens into toy instructions.
- */
-void
-toy_compiler_translate_tgsi(struct toy_compiler *tc,
- const struct tgsi_token *tokens, bool aos,
- struct toy_tgsi *tgsi)
-{
- struct tgsi_parse_context parse;
-
- if (!init_tgsi(tgsi, tc, aos)) {
- tc_fail(tc, "failed to initialize TGSI translator");
- return;
- }
-
- tgsi_parse_init(&parse, tokens);
- while (!tgsi_parse_end_of_tokens(&parse)) {
- tgsi_parse_token(&parse);
- parse_token(tgsi, &parse.FullToken);
- }
- tgsi_parse_free(&parse);
-}
-
-/**
- * Map the TGSI register to VRF register.
- */
-int
-toy_tgsi_get_vrf(const struct toy_tgsi *tgsi,
- enum tgsi_file_type file, int dimension, int index)
-{
- void *key, *val;
-
- key = ra_get_map_key(file, dimension, index);
-
- val = util_hash_table_get(tgsi->reg_mapping, key);
-
- return (val) ? pointer_to_intptr(val) : -1;
-}
+++ /dev/null
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef TOY_TGSI_H
-#define TOY_TGSI_H
-
-#include "pipe/p_state.h"
-#include "pipe/p_shader_tokens.h"
-#include "toy_compiler.h"
-
-struct tgsi_token;
-struct tgsi_full_instruction;
-struct util_hash_table;
-
-typedef void (*toy_tgsi_translate)(struct toy_compiler *tc,
- const struct tgsi_full_instruction *tgsi_inst,
- struct toy_dst *dst,
- struct toy_src *src);
-
-struct toy_tgsi {
- struct toy_compiler *tc;
- bool aos;
- const toy_tgsi_translate *translate_table;
-
- struct util_hash_table *reg_mapping;
-
- struct {
- bool vs_prohibit_ucps;
- int fs_coord_origin;
- int fs_coord_pixel_center;
- bool fs_color0_writes_all_cbufs;
- int fs_depth_layout;
- int gs_input_prim;
- int gs_output_prim;
- int gs_max_output_vertices;
- } props;
-
- struct {
- enum toy_type *types;
- uint32_t (*buf)[4];
- int cur, size;
- } imm_data;
-
- struct {
- int index:16;
- unsigned usage_mask:4; /* TGSI_WRITEMASK_x */
- unsigned semantic_name:8; /* TGSI_SEMANTIC_x */
- unsigned semantic_index:8;
- unsigned interp:4; /* TGSI_INTERPOLATE_x */
- unsigned centroid:1;
- } inputs[PIPE_MAX_SHADER_INPUTS];
- int num_inputs;
-
- struct {
- int index:16;
- unsigned undefined_mask:4;
- unsigned usage_mask:4; /* TGSI_WRITEMASK_x */
- unsigned semantic_name:8; /* TGSI_SEMANTIC_x */
- unsigned semantic_index:8;
- } outputs[PIPE_MAX_SHADER_OUTPUTS];
- int num_outputs;
-
- struct {
- int index:16;
- unsigned semantic_name:8; /* TGSI_SEMANTIC_x */
- unsigned semantic_index:8;
- } system_values[8];
- int num_system_values;
-
- int const_count;
- bool const_indirect;
-
- bool uses_kill;
-};
-
-/**
- * Find the slot of the TGSI input.
- */
-static inline int
-toy_tgsi_find_input(const struct toy_tgsi *tgsi, int index)
-{
- int slot;
-
- for (slot = 0; slot < tgsi->num_inputs; slot++) {
- if (tgsi->inputs[slot].index == index)
- return slot;
- }
-
- return -1;
-}
-
-/**
- * Find the slot of the TGSI system value.
- */
-static inline int
-toy_tgsi_find_system_value(const struct toy_tgsi *tgsi, int index)
-{
- int slot;
-
- for (slot = 0; slot < tgsi->num_system_values; slot++) {
- if (tgsi->system_values[slot].index == index)
- return slot;
- }
-
- return -1;
-}
-
-/**
- * Return the immediate data of the TGSI immediate.
- */
-static inline const uint32_t *
-toy_tgsi_get_imm(const struct toy_tgsi *tgsi, unsigned index,
- enum toy_type *type)
-{
- const uint32_t *imm;
-
- if (index >= tgsi->imm_data.cur)
- return NULL;
-
- imm = tgsi->imm_data.buf[index];
- if (type)
- *type = tgsi->imm_data.types[index];
-
- return imm;
-}
-
-void
-toy_compiler_translate_tgsi(struct toy_compiler *tc,
- const struct tgsi_token *tokens, bool aos,
- struct toy_tgsi *tgsi);
-
-void
-toy_tgsi_cleanup(struct toy_tgsi *tgsi);
-
-int
-toy_tgsi_get_vrf(const struct toy_tgsi *tgsi,
- enum tgsi_file_type file, int dimension, int index);
-
-void
-toy_tgsi_dump(const struct toy_tgsi *tgsi);
-
-#endif /* TOY_TGSI_H */
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