record commands for building ECP5

diff --git a/src/soc/litex/florent/README.txt b/src/soc/litex/florent/README.txt
index 71d55183342b033d46f638442a9b2afa2029d8aa..2cab663850af1c530d852f948bf79e5795bb7e2a 100644 (file)
--- a/src/soc/litex/florent/README.txt
+++ b/src/soc/litex/florent/README.txt
@@ -1,4 +1,11 @@
+# sim openocd test
+
 create verilog file "python issuer_verilog libresoc.v"
 copy to libresoc/ directory
 terminal 1: ./sim.py
 terminal 2: openocd -f openocd.cfg -c init -c 'svf idcode_test2.svf'
+
+# ecp5 build
+
+./versa_ecp5.py --sys-clk-freq=55e6 --build
+./versa_ecp5.py --sys-clk-freq=55e6 --load

diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index 9da9d180a23c45448ddd1d1628549e1eb88791a6..4279effcffe2fbf15f877e9b2a1b76beab248dac 100755 (executable)
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -521,6 +521,8 @@ class LibreSoCSim(SoCCore):
         if not debug:
             return
 
+        jtag_en = ('jtag' in variant) or variant == 'ls180'
+
         # setup running of DMI FSM
         dmi_addr = Signal(4)
         dmi_din = Signal(64)

diff --git a/src/soc/litex/florent/versa_ecp5.py b/src/soc/litex/florent/versa_ecp5.py
index d2e157d79ed687bb8287f2d69beac6c90c69979c..55787f25094f1b97a33a888e90a4f4dfd34dfa99 100755 (executable)
--- a/src/soc/litex/florent/versa_ecp5.py
+++ b/src/soc/litex/florent/versa_ecp5.py
@@ -26,6 +26,7 @@ class TestSoC(BaseSoC):
         BaseSoC.__init__(self, sys_clk_freq,
             cpu_type = "external",
             cpu_cls  = LibreSoC,
+            cpu_variant = "standardjtag",
             #cpu_cls  = Microwatt,
             device        = "LFE5UM",
             **kwargs)