from nmigen import Signal, Const
-from nmutil.dynamicpipe import SimpleHandshakeRedir
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.fu.pipe_data import IntegerData
+from soc.fu.pipe_data import IntegerData, CommonPipeSpec
from ieee754.fpcommon.getop import FPPipeContext
from soc.decoder.power_decoder2 import Data
self.xer_ov.eq(i.xer_ov), self.xer_so.eq(i.xer_so)]
-class ALUPipeSpec:
+class ALUPipeSpec(CommonPipeSpec):
regspec = (ALUInputData.regspec, ALUOutputData.regspec)
opsubsetkls = CompALUOpSubset
- def __init__(self, id_wid, op_wid):
- self.pipekls = SimpleHandshakeRedir
- self.id_wid = id_wid
- self.op_wid = op_wid
- self.opkls = lambda _: self.opsubsetkls(name="op")
- self.stage = None
self.sprs = sprs
self.name = name
-def get_rec_width(rec):
- recwidth = 0
- # Setup random inputs for dut.op
- for p in rec.ports():
- width = p.width
- recwidth += width
- return recwidth
def set_alu_inputs(alu, dec2, sim):
# TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
self.run_tst_program(Program(lst), initial_regs, {})
def test_ilang(self):
- rec = ALUPipeSpec.opsubsetkls()
-
- pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec = ALUPipeSpec(id_wid=2)
alu = ALUBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("alu_pipeline.il", "w") as f:
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- rec = ALUPipeSpec.opsubsetkls()
-
- pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec = ALUPipeSpec(id_wid=2)
m.submodules.alu = alu = ALUBasePipe(pspec)
comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
from nmigen import Signal, Const
from ieee754.fpcommon.getop import FPPipeContext
from soc.decoder.power_decoder2 import Data
-from soc.fu.pipe_data import IntegerData
-from nmutil.dynamicpipe import SimpleHandshakeRedir
+from soc.fu.pipe_data import IntegerData, CommonPipeSpec
from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
# TODO: replace CompALUOpSubset with CompBranchOpSubset
-class BranchPipeSpec:
+class BranchPipeSpec(CommonPipeSpec):
regspec = (BranchInputData.regspec, BranchOutputData.regspec)
opsubsetkls = CompALUOpSubset
- def __init__(self, id_wid, op_wid):
- self.id_wid = id_wid
- self.op_wid = op_wid
- self.opkls = lambda _: self.opsubsetkls(name="op")
- self.stage = None
- self.pipekls = SimpleHandshakeRedir
from soc.simulator.program import Program
from soc.decoder.isa.all import ISA
-
from soc.fu.branch.pipeline import BranchBasePipe
from soc.fu.branch.pipe_data import BranchPipeSpec
import random
initial_cr=cr)
def test_ilang(self):
- rec = BranchPipeSpec.opsubsetkls()
-
- pspec = BranchPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec = BranchPipeSpec(id_wid=2)
alu = BranchBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("branch_pipeline.il", "w") as f:
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- rec = BranchPipeSpec.opsubsetkls()
-
- pspec = BranchPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec = BranchPipeSpec(id_wid=2)
m.submodules.branch = branch = BranchBasePipe(pspec)
comb += branch.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
from nmigen import Signal, Const
from ieee754.fpcommon.getop import FPPipeContext
-from soc.fu.pipe_data import IntegerData
-from nmutil.dynamicpipe import SimpleHandshakeRedir
+from soc.fu.pipe_data import IntegerData, CommonPipeSpec
from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
self.cr.eq(i.cr)]
# TODO: replace CompALUOpSubset with CompCROpSubset
-class CRPipeSpec:
+class CRPipeSpec(CommonPipeSpec):
regspec = (CRInputData.regspec, CROutputData.regspec)
opsubsetkls = CompALUOpSubset
- def __init__(self, id_wid, op_wid):
- self.id_wid = id_wid
- self.op_wid = op_wid
- self.opkls = lambda _: self.opsubsetkls(name="op")
- self.stage = None
- self.pipekls = SimpleHandshakeRedir
self.name = name
self.cr = cr
-def get_rec_width(rec):
- recwidth = 0
- # Setup random inputs for dut.op
- for p in rec.ports():
- width = p.width
- recwidth += width
- return recwidth
-
# This test bench is a bit different than is usual. Initially when I
# was writing it, I had all of the tests call a function to create a
def test_ilang(self):
- rec = CRPipeSpec.opsubsetkls()
-
- pspec = CRPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec = CRPipeSpec(id_wid=2)
alu = CRBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("cr_pipeline.il", "w") as f:
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- rec = CRPipeSpec.opsubsetkls()
-
- pspec = CRPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec = CRPipeSpec(id_wid=2)
m.submodules.alu = alu = CRBasePipe(pspec)
comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
from nmigen import Signal, Const
from ieee754.fpcommon.getop import FPPipeContext
from soc.fu.pipe_data import IntegerData
-from soc.fu.alu.pipe_data import ALUOutputData
-from nmutil.dynamicpipe import SimpleHandshakeRedir
+from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec
from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
# TODO: replace CompALUOpSubset with CompLogicalOpSubset
-class LogicalPipeSpec:
+class LogicalPipeSpec(CommonPipeSpec):
regspec = (LogicalInputData.regspec, ALUOutputData.regspec)
opsubsetkls = CompALUOpSubset
- def __init__(self, id_wid, op_wid):
- self.id_wid = id_wid
- self.op_wid = op_wid
- self.opkls = lambda _: self.opsubsetkls(name="op")
- self.stage = None
- self.pipekls = SimpleHandshakeRedir
self.name = name
-def get_rec_width(rec):
- recwidth = 0
- # Setup random inputs for dut.op
- for p in rec.ports():
- width = p.width
- recwidth += width
- return recwidth
-
-
def set_alu_inputs(alu, dec2, sim):
# TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
# detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
self.run_tst_program(Program(lst), initial_regs)
def test_ilang(self):
- rec = LogicalPipeSpec.opsubsetkls()
-
- pspec = LogicalPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec = LogicalPipeSpec(id_wid=2)
alu = LogicalBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("logical_pipeline.il", "w") as f:
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- rec = LogicalPipeSpec.opsubsetkls()
-
- pspec = LogicalPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec = LogicalPipeSpec(id_wid=2)
m.submodules.alu = alu = LogicalBasePipe(pspec)
comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
from ieee754.fpcommon.getop import FPPipeContext
+from nmutil.dynamicpipe import SimpleHandshakeRedir
class IntegerData:
def ports(self):
return self.ctx.ports()
+
+# hmmm there has to be a better way than this
+def get_rec_width(rec):
+ recwidth = 0
+ # Setup random inputs for dut.op
+ for p in rec.ports():
+ width = p.width
+ recwidth += width
+ return recwidth
+
+
+class CommonPipeSpec:
+ def __init__(self, id_wid):
+ self.pipekls = SimpleHandshakeRedir
+ self.id_wid = id_wid
+ self.opkls = lambda _: self.opsubsetkls(name="op")
+ self.op_wid = get_rec_width(self.opkls(None)) # hmm..
+ self.stage = None
from nmutil.dynamicpipe import SimpleHandshakeRedir
from soc.fu.alu.alu_input_record import CompALUOpSubset
from ieee754.fpcommon.getop import FPPipeContext
-from soc.fu.pipe_data import IntegerData
+from soc.fu.pipe_data import IntegerData, CommonPipeSpec
from soc.fu.alu.pipe_data import ALUOutputData
from nmutil.dynamicpipe import SimpleHandshakeRedir
# TODO: replace CompALUOpSubset with CompShiftRotOpSubset
-class ShiftRotPipeSpec:
+class ShiftRotPipeSpec(CommonPipeSpec):
regspec = (ShiftRotInputData.regspec, ALUOutputData.regspec)
opsubsetkls = CompALUOpSubset
- def __init__(self, id_wid, op_wid):
- self.id_wid = id_wid
- self.op_wid = op_wid
- self.opkls = lambda _: self.opsubsetkls(name="op")
- self.stage = None
- self.pipekls = SimpleHandshakeRedir
self.run_tst_program(Program(lst), initial_regs)
def test_ilang(self):
- rec = ShiftRotPipeSpec.opsubsetkls()
-
- pspec = ShiftRotPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec = ShiftRotPipeSpec(id_wid=2)
alu = ShiftRotBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("pipeline.il", "w") as f:
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- rec = ShiftRotPipeSpec.opsubsetkls()
-
- pspec = ShiftRotPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec = ShiftRotPipeSpec(id_wid=2)
m.submodules.alu = alu = ShiftRotBasePipe(pspec)
comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)