too much debug info going past, so add the test registers to the

failed log message

diff --git a/src/soc/fu/div/test/runner.py b/src/soc/fu/div/test/runner.py
index e822e41cb590b6d7379626c49b23126dfc090a0c..5404c773e94dd4e4f339508b33af8553966b6692 100644 (file)
--- a/src/soc/fu/div/test/runner.py
+++ b/src/soc/fu/div/test/runner.py
@@ -190,6 +190,7 @@ class DivRunner(unittest.TestCase):
                         # XXX print("time:", sim._state.timeline.now)
                         msg = "%s: %s" % (self.div_pipe_kind.name, code)
                         msg += " %s" % (repr(prog.assembly))
+                        msg += " %s" % (repr(test.regs))
                         yield from self.check_alu_outputs(alu, pdecode2,
                                                           isa_sim, msg)