Remove extra yield from test case.

Seems pysim is correct, after all. There seems to be some
strange interaction between cxxrtl and python.

diff --git a/src/soc/experiment/alu_fsm.py b/src/soc/experiment/alu_fsm.py
index b3ab5b175a1edd9128d3cbd9db29c1e634e7a1ab..f3b6726434bc8c7a19083bbe9c631d395e52bd80 100644 (file)
--- a/src/soc/experiment/alu_fsm.py
+++ b/src/soc/experiment/alu_fsm.py
@@ -240,9 +240,6 @@ def test_shifter():
             yield
         # read result
         result = yield dut.n.data_o.data
-
-        # must leave ready_i valid for 1 cycle, ready_i to register for 1 cycle
-        yield
         # negate n.ready_i
         yield dut.n.ready_i.eq(0)
         # check result