# set up registers, instruction memory, data memory, PC, SPRs, MSR
self.svp64rm = SVP64RM()
- self.svstate = SVP64State(initial_svstate)
+ if isinstance(initial_svstate, int):
+ initial_svstate = SVP64State(initial_svstate)
+ self.svstate = initial_svstate
self.gpr = GPR(decoder2, self, self.svstate, regfile)
self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
def __init__(self, num):
self.num = num
-def run_tst(generator, initial_regs, initial_sprs={}):
+def run_tst(generator, initial_regs, initial_sprs=None, svstate=0):
+ if initial_sprs is None:
+ initial_sprs = {}
m = Module()
comb = m.d.comb
instruction = Signal(32)
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
simulator = ISA(pdecode2, initial_regs, initial_sprs, 0,
initial_insns=gen, respect_pc=True,
+ initial_svstate=svstate,
disassembly=insncode,
bigendian=0)
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
from soc.decoder.power_decoder import (create_pdecode)
from soc.decoder.power_decoder2 import (PowerDecode2)
from soc.simulator.program import Program
-from soc.decoder.isa.caller import ISACaller, inject
+from soc.decoder.isa.caller import ISACaller, SVP64State
from soc.decoder.selectable_int import SelectableInt
from soc.decoder.orderedset import OrderedSet
from soc.decoder.isa.all import ISA
initial_regs = [0] * 32
initial_regs[3] = 0x1234
initial_regs[2] = 0x4321
+ svstate = SVP64State()
+ svstate.vl[0:-1] = 2 # VL
+ svstate.maxvl[0:-1] = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.spr.asint()))
with Program(lst, bigendian=False) as program:
- sim = self.run_tst_program(program, initial_regs)
+ sim = self.run_tst_program(program, initial_regs, svstate)
self.assertEqual(sim.gpr(1), SelectableInt(0x5555, 64))
- def run_tst_program(self, prog, initial_regs=[0] * 32):
- simulator = run_tst(prog, initial_regs)
+ def run_tst_program(self, prog, initial_regs=[0] * 32,
+ svstate=None):
+ simulator = run_tst(prog, initial_regs, svstate=svstate)
simulator.gpr.dump()
return simulator