info->has_2d_tiling = true;
info->has_read_registers_query = true;
info->has_scheduled_fence_dependency = info->drm_minor >= 28;
+ info->mid_command_buffer_preemption_enabled =
+ amdinfo->ids_flags & AMDGPU_IDS_FLAGS_PREEMPTION;
info->pa_sc_tile_steering_override = device_info.pa_sc_tile_steering_override;
info->num_render_backends = amdinfo->rb_pipes;
printf(" has_read_registers_query = %u\n", info->has_read_registers_query);
printf(" has_gds_ordered_append = %u\n", info->has_gds_ordered_append);
printf(" has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency);
+ printf(" mid_command_buffer_preemption_enabled = %u\n", info->mid_command_buffer_preemption_enabled);
printf("Shader core info:\n");
printf(" max_shader_clock = %i\n", info->max_shader_clock);
bool has_read_registers_query;
bool has_gds_ordered_append;
bool has_scheduled_fence_dependency;
+ /* Whether SR-IOV is enabled or amdgpu.mcbp=1 was set on the kernel command line. */
+ bool mid_command_buffer_preemption_enabled;
/* Shader cores. */
uint32_t cu_mask[4][2];
void si_init_cp_reg_shadowing(struct si_context *sctx)
{
- if (sctx->screen->debug_flags & DBG(SHADOW_REGS)) {
+ if (sctx->screen->info.mid_command_buffer_preemption_enabled ||
+ sctx->screen->debug_flags & DBG(SHADOW_REGS)) {
sctx->shadowed_regs =
si_aligned_buffer_create(sctx->b.screen,
SI_RESOURCE_FLAG_UNMAPPABLE,